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lt6556 1 6556f lt6556 v + v r ina g ina b ina r inb g inb b inb 75 75 75 75 75 75 v ref 6556 ta01 agnd enable dgnd 1k r out 1k g out 1k b out 1 1 1 select a/b time (ns) output (v) 1.51.0 0.5 0 ?.5?.0 ?.5 4 8 12 16 6556 ta02 20 20 6 10 14 18 v in = 2v p-p v s = 5v r l = 1k t a = 25 c 750mhz gain of 1 triple 2:1video multiplexer the lt ? 6556 is a high speed triple 2:1 video multiplexer with an internally ? xed gain of 1. the individual buffers are optimized for performance with a 1k load and feature a 2v p-p C3db bandwidth of 450mhz, making them ideal for driving very high resolution video signals. separate power supply pins for each ampli? er boost channel separation to 72db, allowing the lt6556 to excel in many high speed applications. while the performance of the lt6556 is optimized for dual supply operation, it can also be operated with a single sup- ply as low as 4.5v. using dual 5v supplies, each ampli? er draws only 9.5ma. when disabled, the ampli? ers draw less than 330a and the outputs become high impedance. for applications requiring a ? xed gain of 2, refer to the lt6555 datasheet. the lt6556 is available in 24-lead ssop and ultra-compact 24-lead qfn packages. rgb buffers uxga video multiplexing lcd projectors 750mhz C3db small signal bandwidth 450mhz C3db 2v p-p large-signal bandwidth 120mhz 0.1db bandwidth high slew rate: 2100v/s fixed gain of 1; no external resistors required 72db channel separation at 10mhz 52db channel separation at 100mhz C84dbc 2nd harmonic distortion at 10mhz, 2v p-p C87dbc 3rd harmonic distortion at 10mhz, 2v p-p low supply current: 9.5ma per ampli? er 6.5ns 0.1% settling time for 2v step i ss 330a per ampli? er when disabled differential gain of 0.033%, differential phase of 0.022 wide supply range: 2.25v (4.5v) to 6v (12v) available in 24-lead ssop and 24-lead qfn packages rgb multiplexer and line driver applicatio s u features descriptio u typical applicatio u , ltc and lt are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. large-signal transient response downloaded from: http:///
lt6556 2 6556f total supply voltage (v + to v C ) .............................12.6v input current (note 2) .........................................10ma output current (continuous) ..............................70ma ? e ? n to dgnd voltage (note 2) ..................................5.5v sel to dgnd voltage (note 2) ....................................8v output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4) ... C40c to 85c speci? ed temperature range (note 5) .... C40c to 85c (note 1) the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, r l = 1k, c l = 1.5pf, v ? e ? n = 0.4v, v agnd , v dgnd , v vref = 0v. symbol parameter conditions min typ max units v os offset voltage v in = 0v, v os = v out 18 67 75 mv mv i in input current 12 45 a r in input resistance v in = ?v 100 500 k c in input capacitance f = 100khz 1p f psrr power supply rejection ratio v s = ?.25v to ?v (note 6) 51 62 db electrical characteristics absolute axi u rati gs w ww u package/order i for atio uu w junction temperature ssop ................................................................ 150c qfn ................................................................... 125c storage temperature range ssop ................................................. C65c to 150c qfn .................................................... C65c to 125c soldering temperature (10 sec) ............................ 300c 12 3 4 5 6 7 8 9 1011 12 top view gn package 24-lead plastic ssop 2423 22 21 20 19 18 17 16 15 14 13 in1a dgnd in2a v ref in3a agnd1 in1b agnd2 in2b agnd3 in3b v v + ensel a/b v + out1v out2v + out3v v + v + g = +1 g = +1 g = +1 t jmax = 150c, ja = 90c/w 24 23 22 21 20 19 7 8 9 top view 25 uf package 24-lead (4mm 4mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 v ref in3a agnd1 v in1b agnd2 v + out1v out2v + out3 in2adgnd in1a v + ensel a/b in2b agnd3 in3b v + v + v t jmax = 125c, ja = 37c/w, jc = 2.6c/w exposed pad (pin 25) is v C must be soldered to pcb order part number gn part marking order part number uf part marking* lt6556cgn lt6556ign lt6556cgn lt6556ign lt6556cuf lt6556iuf 6556 order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. downloaded from: http:///
lt6556 3 6556f note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired.note 2: this parameter is guaranteed to meet speci? ed performance through design and characterization. it is not production tested.note 3: as long as output current and junction temperature are kept below the absolute maximum ratings, no damage to the part will occur. depending on the supply voltage, a heat sink may be required. note 4: the lt6556c is guaranteed functional over the operating temperature range of C40c to 85c.note 5: the lt6556c is guaranteed to meet speci? ed performance from 0c to 70c. the lt6556c is designed, characterized and expected to meet speci? ed performance from C40c and 85c but is not tested or qa sampled at these temperatures. the lt6556i is guaranteed to meet speci? ed performance from C40c to 85c. note 6: in order to follow the constraints for 4.5v operation for psrr and i psrr testing at 2.25v, the dgnd pin is set to v C , the ? e ? n pin is set the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v s = 5v, r l = 1k, c l = 1.5pf, v en = 0.4v, v agnd , v dgnd , v vref = 0v. electrical characteristics symbol parameter conditions min typ max units i psrr input current power supply rejection v s = ?.25v to ?v (note 6) 1 3 ?/v a v err gain error v out = v ref = ?v, nominal gain 1v/v 2.8 1.15 0 % a v match gain matching any one channel to another 0.05 % v out output voltage swing (note 7) 3.65 3.85 v i s supply current, per ampli er r l = 9.5 13 14.5 mama supply current, disabled, per ampli er v ? e ? n = 4v, r l = v ? e ? n = open, r l = 4742 330330 aa i ? e ? n enable pin current v ? e ? n = 0.4v v ? e ? n = 4v 200 75 95 21 aa i sel select pin current v sel = 0.4v v sel = 4v 50 50 5 1 aa i sc output short-circuit current r l = 0 , v in = ?v, v ref = ?v 50 105 ma sr slew rate ?v on ?.2v output step (note 8) 1200 2100 v/? ?db bw small-signal ?db bandwidth v out = 200mv p-p 750 mhz 0.1db bw gain flatness ?.1db bandwidth v out = 200mv p-p 120 mhz fpbw full power bandwidth 2v v out = 2v p-p (note 9) 190 335 mhz full power bandwidth 4v v out = 4v p-p (note 9) 175 mhz all-hostile crosstalk f = 10mhz, v in = 2v p-p f = 100mhz, v in = 2v p-p 72 52 dbdb selected channel to unselected channel crosstalk f = 10mhz, v in = 2v p-p f = 100mhz, v in = 2v p-p 85 64 dbdb channel select output transient ina = inb = 0v 200 mv p-p channel-to-channel select time ina = ?v, inb = 1v from 50% sel to v out = 0v 8n s t s settling time 0.1% of v final , v step = 2v 6.5 ns t r , t f small-signal rise and fall time 10% to 90%, v out = 200mv p-p 500 ps dg differential gain (note 10) 0.056 % dp differential phase (note 10) 0.028 deg hd2 2nd harmonic distortion f = 10mhz, v out = 2v p-p ?4 dbc hd3 3rd harmonic distortion f = 10mhz, v out = 2v p-p ?7 dbc to v C + 0.4v, and the sel pin is set to either v C + 0.4v or v C + 4v. at 6v and all other cases, dgnd is set to ground and the ? e ? n and sel pins are referenced from it.note 7: the v ref pin is set to 3v when testing positive swing and C3v when testing negative swing to ensure that the internal input clamps do not limit the output swing. note 8: slew rate is 100% production tested using both inputs of channel 2. slew rates of channels 1 and 3 are guaranteed through design and characterization. note 9: full power bandwidth is calculated from the slew rate: fpbw = sr/( ? v p-p ) note 10: differential gain and phase are measured using a tektronix tsg120yc/ntsc signal generator and a tektronix 1780r video measurement set. the resolution of this equipment is better than 0.05% and 0.05. nine identical ampli? er stages were cascaded giving an effective resolution of better than 0.0056% and 0.0056. downloaded from: http:///
lt6556 4 6556f temperature ( c) ?5 input bias current ( a) ?0 ?5 ?0 105 6556 g05 ?5 ?0 ?0 ?5 25 65 ?5 125 5 45 85 ?5 0 ? v s = 5v v in = 1.5v v in = ?.5v v in = 0v en pin voltage (v) supply current (ma) 6556 g03 1210 86 4 2 0 0 1.0 2.0 2.5 0.5 1.5 3.0 3.5 4.0 v s = 5v r l = v in = 0v t a = ?5 c t a = 125 c t a = 25 c total supply voltage (v) 04 6556 g02 1 2 3 56789101112 supply current (ma) 1210 86 4 2 0 v s = 5v v en , v in , v dgnd , v sel = 0v t a = 25 c temperature ( c) ?5 supply current (ma) ?5 25 45 125 6556 g01 ?5 5 65 85 105 1210 86 4 2 0 v s = 5v r l = v in = 0v v en = 0v v en = 4v v en = 0.4v sink current (ma) 0 output voltage (v) ? ? 0 80 6556 g09 ? ? ? 10 20 30 40 50 60 70 90 100 v s = 5v v in = ?v v vref = ?v t a = 125 c t a = 25 c t a = 55 c source current (ma) 0 output voltage (v) 3 4 5 80 6556 g08 2 1 0 10 20 30 40 50 60 70 90 100 v s = 5v v in = 4v v vref = 3v t a = 125 c t a = 25 c t a = 55 c temperature ( c) ?5 0 offset voltage (mv) 10 20 ?5 25 45 125 6556 g04 5 ?5 5 65 85 105 15 25 v s = 5v v in = 0v v ref pin voltage (v) ? output voltage (v) 0 2 2 6556 g07 ?? ? ? 0 1 ?.5 ?.5 0.5 1.5 54 ? 1 ? 3 v s = 5v r l = 1k high swing low swing t a = 125 c t a = 125 c t a = 25 c t a = 55 c t a = 55 c t a = 25 c en pin voltage (v) 0 en pin current ( a) 0 ?0?0 ?0 ?0 ?00?20 ?40 6556 g06 2 5 1 34 v s = 5v v dgnd = 0v t a = ?5 c t a = 25 c t a = 125 c supply current per ampli? er vs temperature supply current per ampli? er vs supply voltage supply current per ampli? er vs ? e ? n pin voltage offset voltage vs temperature input bias current vs temperature ? e ? n pin current vs ? e ? n pin voltage maximum output voltage swing vs v ref pin voltage output voltage swing vs i load (output high) output voltage swing vs i load (output low) typical perfor a ce characteristics uw downloaded from: http:///
lt6556 5 6556f frequency (mhz) ?0 amplitude (db) ?0 0 ?00 ?0 ?0 0.1 10 100 1000 6556 g16 ?20 1 v s = 5v v out = 2v p-p r l = 1k t a = 25 c drive in a; select in b drive in b;select in a frequency (mhz) ?0 amplitude (db) ?0 0 ?00 ?0 ?0 0.1 10 100 1000 6556 g17 ?20 1 v s = 5v v out = 2v p-p r l = 1k t a = 25 c worst adjacent all channelsdriven frequency (mhz) ? amplitude (db) 0 3 6 0.1 10 100 1000 6555 g15 ? 1 9 v s = 5v v out = 200mv p-p r l = 1k t a = 25 c c l = 15pf c l = 0pf c l = 6.8pf c l = 3.3pf c l = 10pf frequency (mhz) ? gain (db) ? ? 1 32 0.1 10 100 1000 6556 g13 ? 1 0 ?? v s = 5v r l = 1k t a = 25 c v out = 2v p-p v out = 4v p-p v out = 200mv p-p frequency (mhz) ?.05 gain (db) 0.05 0.15 ?.10 0 0.10 0.1 10 100 1000 6556 g14 ?.15 1 in3b in2b in3a v s = 5v v out = 200mv p-p r l = 1k t a = 25 c in1a in1b in2a frequency (mhz) ?00 distortion (dbc) ?0 ?0 ?0 ?0 0.01 1 10 100 6556 g18 ?20 0.1 0 ?10 ?0 ?0 ?0 ?0 ?0 v s = 5v v out = 2v p-p r l = 1k t a = 25 c hd2 hd3 frequency (mhz) 20 rejection ratio (db) 40 7010 30 50 60 0.001 0.1 1 10 100 6556 g12 0 0.01 psrr ?srr +psrr v s = 5v t a = 25 c frequency (khz) input noise (nv/ hz or pa/ hz) 0.001 0.01 1 10 100 0.1 1000 100 10 1 i n v s = 5v t a = 25 c e n 6556 g10 6556 g11 frequency (mhz) input impedance (k ) 0.01 0.1 10 100 1000 1 1000 100 10 1 0.1 v s = 5v v in = 0v t a = 25 c input noise spectral density input impedance vs frequency psrr vs frequency frequency response vs output amplitude gain flatness vs frequency frequency response with capacitive loads crosstalk vs frequency crosstalk vs frequency harmonic distortion vs frequency typical perfor a ce characteristics uw downloaded from: http:///
lt6556 6 6556f time (ns) 0 sel a/b (v) 42 1 3 5 20 40 60 80 6556 g26 100 10 03 05 07 09 0 v s = 5v r l = 1k ina = inb = 0vt a = 25 c output (v) ?.05 0.05 0.15?.10 0 0.10 frequency (mhz) 0.01 0.1 output impedance ( ) 100 1000000 0.1 1 10 100 1000 6556 g19 1 10000 1000 10 100000 disabled v en = 4v enabled v en = o.4v v s = 5v t a = 25 c time (ns) 0 sel a/b (v) output (v) 42 1 3 5 0?.5 1.51.0 0.5 ?.5 ?.0 20 40 60 80 6556 g27 100 10 03 05 07 09 0 v s = 5v r l = 1k inb = 300mhz, 2v p-p sine t a = 25 c ina = 0v gain error?etween channels (%) ?.1 percent of units (%) 25 30 35 40 0.1 6556 g25 15 0 ?.075 0.025 ?.05 0 0.025 0.05 0.075 20 10 5 v s = 5v v out = 2v r l = 1k t a = 25 c gain error?ndividual channel (%) ?.3 percent of units (%) 25 30 35 ?90 6556 g24 15 0 ?.25 1.15 ?.2 1.1 ?.05 ?.0 ?95 20 10 5 v s = 5v v out = 2v r l = 1k t a = 25 c time (ns) 0 output (v) 2.52.0 1.5 1.0 0.5 0 0.5 1.5 2.5 1.0 2.0 16 6556 g23 4 8 12 20 14 2 6 10 18 v in = 4v p-p v s = 5v r l = 1k t a = 25 c time (ns) ?.2 output (v) 0.2 0.5 0.9 0 0.4 0.7 ?.1 0.3 0.60.1 0.8 4 8 12 16 6556 g22 20 2 0 6 10 14 18 v in = 700mv p-p v s = 5v r l = 1k t a = 25 c time (ns) 0 output (v) ?.10 0 0.10 0.200.15 16 6556 g21 ?.20 ?.15 ?.05 0.05 4 8 12 21 8 6 10 14 20 v in = 200mv p-p v s = 5v r l = 1k t a = 25 c 6556 g20 capacitive load (pf) 1 output series resistance ( ) 3530 25 20 15 10 50 10 100 1000 v out = 2v p? v s = 5v r l = 1k t a = 25 c ac peaking >3db output impedance vs frequency maximum capacitive load vs output series resistor small-signal transient response video amplitude transient response large-signal transient response gain error distribution gain error matching distribution channel switching transient channel switching transient typical perfor a ce characteristics uw downloaded from: http:///
lt6556 7 6556f pi fu ctio s uuu in1a (pin 1): channel 1 input a. this pin has a nominal impedance of 500k and does not have any internal termination resistor. dgnd (pin 2): digital ground reference for enable pin. this pin is normally connected to ground.in2a (pin 3): channel 2 input a. this pin has a nominal impedance of 500k and does not have any internal termination resistor. vref (pin 4): voltage reference for input clamping. this is the tap to an internal voltage divider that de? nes mid- supply. it is normally connected to ground in dual supply, dc coupled applications. in3a (pin 5): channel 3 input a. this pin has a nominal impedance of 500k and does not have any internal termination resistor. agnd (pin 6): analog ground for isolation between in3a and in1b. agnd pins have esd protection and should not be connected to potentials outside the power supply range. in1b (pin 7): channel 1 input b. this pin has a nominal impedance of 500k and does not have any internal termination resistor. agnd (pin 8): analog ground for isolation between in1b and in2b. agnd pins have esd protection and should not be connected to potentials outside the power supply range. in2b (pin 9): channel 2 input b. this pin has a nominal impedance of 500k and does not have any internal termination resistor. agnd (pin 10): analog ground for isolation between in2b and in3b. agnd pins have esd protection and should not be connected to potentials outside the power supply range. in3b (pin 11): channel 3 input b. this pin has a nominal impedance of 500k and does not have any internal termination resistor. vC (pin 12): negative supply voltage. v C pins are not in- ternally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. v+ (pins 13, 14, 24): positive supply voltage. v + pins are not internally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. vC (pin 15): negative supply voltage for channel 3 output stage. v C pins are not internally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. out3 (pin 16): channel 3 output. it is the buffered output of the selected channel 3 input.v+ (pin 17): positive supply voltage for channels 2 and 3 output stages. v + pins are not internally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. out2 (pin 18): channel 2 output. it is the buffered output of the selected channel 2 input.vC (pin 19): negative supply voltage for channels 1 and 2 output stages. v C pins are not internally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. out1 (pin 20): channel 1 output. it is the buffered output of the selected channel 1 input. v+ (pin 21): positive supply voltage for channel 1 output stage. v + pins are not internally connected to each other and must all be connected externally. proper supply bypassing is necessary for best performance. see the applications information section. sel ? a/b (pin 22): select pin. this high impedance pin selects which set of inputs are sent to the output pins. when the pin is pulled low, the a inputs are selected. when the pin is pulled high, the b inputs are selected. ? e ? n (pin 23): enable control pin. an internal pull-up resistor of 46k de? nes the pins impedance and will turn the part off if the pin is unconnected. when the pin is pulled low, the ampli? ers are enabled. exposed pad (pin 25, qfn only): the exposed pad is v C and must be soldered to the pcb. it is internally con- nected to the qfn pin 4, v C . (gn24 package) downloaded from: http:///
lt6556 8 6556f applicatio s i for atio wu u u power supplies the lt6556 is optimized for 5v supplies but can be op- erated on as little as 2.25v or a single 4.5v supply and as much as 6v or a single 12v supply. internally, each supply is independent to improve channel isolation. do not leave any supply pins disconnected or the part may not function correctly! enable/shutdown the lt6556 has a shutdown mode controlled by the ? e ? n pin and referenced to the dgnd pin. if the ampli? er will be enabled at all times, the ? e ? n pin can be connected directly to dgnd. if the enable function is desired, either driving the pin above 2v or allowing the internal 46k pull-up resistor to pull the ? e ? n pin to the top rail will disable the ampli? er. when disabled, the output will become very high impedance. supply current into the ampli? er in the disabled state will be: i vv k vv k s en =+ + + 46 80 it is important that the following constraints on the dgnd, ? e ? n and sel pins are always followed: v + C v dgnd 4.5v -0.5v v ? e ? n C v dgnd 5.5v v sel C v dgnd 8v in dual supply cases where v + is less than 4.5v, dgnd should be connected to a potential below ground, such as v C . since the ?e ?n and sel pins are referenced to dgnd, they may need to be pulled below ground in those cases. however, in order to protect the internal enable circuitry, the ?e ?n pin should not be forced more than 0.5v below dgnd. in single supply applications above 5.5v, an additional resistor may be needed from the ? e ? n pin to dgnd if the pin is ever allowed to ? oat. for example, on a 12v single supply, a 33k resistor would protect the pin from ? oating too high while still allowing the internal pull-up resistor to disable the part. on dual 2.25v supplies, connecting the dgnd pin to v C is the only way of ensuring that v + C v dgnd 4.5v. the enable/disable times of the lt6556 are fast when driven with a logic input. turn on (from 50% ? e ? n input to 50% output) typically occurs in less than 50ns. turn off is slower, but is typically below 500ns. channel select the sel pin uses the same internal threshold as the ? e ? n pin and is also referenced to dgnd. when the pin is logic low, the channel a inputs are passed to the output. when the pin is logic high, the channel b inputs are passed to the output. the pin should not be ? oated but can be tied to dgnd to force the outputs to always be channel a or to v + (when less than 8v) to force the outputs to always be channel b. truth table sel ? a/b ? e ? n out 0 0 in a 1 0 in b x 1 off input considerations the lt6556 uses input clamps referenced to the v ref pin to prevent damage to the input stage on the unselected channel. three transistors in series limit the input voltage to within three diode drops () from v ref . v ref is nominally set to half of the sum of the supplies by the 40k resistors. a simpli? ed schematic is shown in figure 1. v ref 40k40k 6556 f01 v + v in figure 1. simpli? ed schematic of v ref pin and input clamping downloaded from: http:///
lt6556 9 6556f to improve clamping, the pins dc impedance should be minimized by connecting the v ref pin directly to ground in the symmetric dual supply case with a common mode voltage of 0v. if the common mode voltage is not centered at ground or the input voltage exceeds plus or minus three diodes from ground, an external resistor to either supply can be added to shift the v ref voltage to the desired level. the only way to cover the full input voltage range of v C + 1v to v + C 1v is to shift v ref up or down. the v ref pin can also be directly driven with a dc source. figure 2 shows the effect of the clamp on input current when sweeping input voltage with various v ref pin volt- ages. bypassing the v ref pin is not necessary. input voltage (v) ? input current ( a) 0 100 4 6556 f02 ?00?50 ?00 ? 0 2 ? ? 1 3 250200 ?0 50 ?50 150 t a = 25 c v s = 5v v ref = 2v v ref = 1v v ref = 0v v ref = ?v v ref = ?v the inputs can be driven beyond the point at which the output clips so long as input currents are limited to less than 10ma. continuing to drive the input beyond the output limit can result in increased current drive and slightly increased swing, but will also increase supply current and may result in delays in transient response at larger levels of overdrive. layout and groundingit is imperative that care is taken in pcb layout in order to bene? t from the very high speed and very low crosstalk of the lt6556. separate power and ground planes are highly recommended and trace lengths should be kept as short as possible. if input traces must be run over a distance of several centimeters, they should use a controlled imped- ance with either series or shunt terminations (nominally 50 or 75 ) to maintain signal ? delity. care should be taken to minimize capacitance on the lt6556s output traces by increasing spacing between traces and adjacent metal and by eliminating metal planes in underlying layers. to drive cable or traces longer than several centimeters, using the lt6555 with its ? xed gain of+2 in conjunction with series and load termination resis-tors may provide better results. a plot of ac performance driving a 1k load with various trace lengths is shown in figure 3. all data is from a 4-layer board with 2oz copper, 18mil of board layer thickness to the ground plane, a trace width of 12mils and spacing to adjacent metal of 18mils. the 0.2cm output trace places the 1k resistor as close to the part as possible, while the other curves show the load resistor consecutively further away. the worst case, 4cm, trace has almost 10pf of parasitic capacitance. frequency (mhz) 0.1 amplitude (db) 64 2 0 ? ?? 1 10 100 1000 6556 f03 4cm trace 0.2cm trace 2cm trace v s = 5v v out = 200mv p-p r l = 1k t a = 25 c figure 3. response vs output trace length applicatio s i for atio wu u u figure 2. input current vs input voltage at different v ref voltages downloaded from: http:///
lt6556 10 6556f applicatio s i for atio wu u u in order to counteract any peaking in the frequency re-sponse from driving a capacitive load, a series resistance can be inserted in the line at the output of the part to ? at- ten the response. figure 4 shows the frequency response with the same 4cm trace from figure 3, now with a 10 series resistor inserted near the output pin of the ampli- ? er. note that using a 10 series resistor with a 1k load only decreases the output amplitude by 0.1db or 1% and has a minimal effect on the bandwidth of the system. see the graph labeled maximum capacitive load vs output series resistor in the typical performance characteristics section for more information. frequency (mhz) 0.1 amplitude (db) 64 2 0 ? ?? 1 10 100 1000 6556 f04 4cm trace 4cm trace r s, out = 10 v s = 5v v out = 200mv p-p r l = 1k t a = 25 c figure 4. response vs series output resistance while the agnd pins on the lt6556 are not connected to the ampli? er circuitry, tying them to ground or another quiet node signi? cantly increases channel isolation and is always recommended. the agnd pins do have esd protection and therefore should not be connected to potentials outside the power supply range. low esl/esr bypass capacitors should be placed as close to the positive and negative supply pins as possible. one 4700pf ceramic capacitor is recommended for both v + and v C supply busses. additional 470pf ceramic capacitors with minimal trace length on each supply pin will further improve ac and transient response as well as channel isolation. for high current drive and large-signal transient applications, additional 1f to 10f tantalums should be added on each supply. the smallest value capacitors should be placed closest to the package. to maintain the lt6556s channel isolation, it is bene? cial to shield parallel input and parallel output traces using a ground plane or power supply traces. vias between top- side and backside metal may be required to maintain a low inductance ground near the part where numerous traces converge. see figures 7 and 8 for photos of an optimized layout. single supply operation figure 5 illustrates how to use the lt6556 with a single supply ranging from 4.5v to 12v. since the output range is comparable to the input range, the dc bias point at the input can be set anywhere between the supplies that will prevent the ac-coupled signal from running into the output range limits. as shown, the dc input level is mid-supply. the only additional power dissipation in the single supply con? guration is through the resistor bias string at the input and through any load resistance at the output. in many cases, the output can be used to directly drive other single supply devices without additional coupling and without any resistive load. 1/3 lt6556 5k 5k agnd in v in 22 f out v + v 4.5v to 12v 6556 f05 figure 5. single supply con? guration, one channel shown input expansionin applications with more than two inputs per channel, multiple lt6556s can be connected directly together at the outputs. logic circuitry can be used to drive the ? e ? n pins of each lt6556 to ensure that only one set of channels is buffered at a time. see figure 9 for a schematic. since the output impedance of a disabled lt6556 is high, adding additional channels will not resistively load an downloaded from: http:///
lt6556 11 6556f applicatio s i for atio wu u u enabled output. however, since the disabled lt6556 and its traces have around 6pf of capacitance, it may be desirable to resistively isolate the outputs of each channel to maintain ? at frequency response as shown in the graph labeled maximum capacitive load vs output series resistor in the typical performance characteristics section. esd protection the lt6556 has reverse-biased esd protection diodes on all pins. if any pins are forced a diode drop above the positive supply or a diode drop below the negative supply, large currents may ? ow through these diodes. if the current is kept below 10ma, no damage to the devices will occur. typical applicatio u rgb multiplexer demo boardthe dc892a demo board illustrates optimal routing, bypassing and termination using the lt6556 as an rgb video multiplexer. the schematic is shown in figure 6. all inputs and outputs are routed to have a characteristic impedance of 75 and 75 input shunt and output series terminations are connected as close to the part as pos-sible. the board is fabricated with four layers with internal ground and power planes. while the 75 back termination resistors at the outputs of the lt6556 minimize signal re? ections in the output traces and isolate the part from any capacitive loading in those traces, they also contribute to gain error if the out- put is not terminated with high impedance. for example, if the output is terminated with a 1k load, the 75 back termination will cause a 7% gain error. decreasing the value of the back termination resistors will decrease the signal attenuation but may compromise the ac response. however, connecting the lt6556 output pins to the output traces on the dc892a board without some series resistance is not recommended; 10 to 20 is generally suf? cient. figures 7 and 8 show the top and bottom side board layout and placement. figure 6. demo board schematic 5 in1a 43 2 5 in2a 43 2 5 in3a 43 2 5 in1b 43 2 5 in2b 43 2 5 in3b 43 2 in1b agnd1 in3a v ref v ref in2a dgnd dgnd in1aagnd2 67 8 9 4 5 3 2 1 24 23 22 1413 12 11 10 15 16 17 18 19 20 21 v + out2 v out1 in3b agnd3 in2bv v + v + v out3 v + sel en v + u1 lt6556cuf ext gnd 1 3 2 jp5 v ref jp12 bnc 6 dgnd 11 1 1 1 1 l1l1 l1 l1 l1 l1 z = 75z = 75 z = 75 z = 75 z = 75 z = 75 jp13jp14 jp5jp6 jp7 j3 banana jack float agnd 1 3 2 jp2 dgnd ext enable 1 3 2 jp1 control 1 3 v cc sel a/b ab dgnd 2 jp4 sel r7 20k j1 50 bnc en 5432 1 r1075 r1175 r1275 r475 r575 r675 2 dual note: 470pf bypass capacitors located as close to pins as possible single agnd jp3 supply 3 1 e1 en e4 sel a/b e2 dgnd e5 v ref e3 agnd r850 opt z = 50 z = 50 en 5 out1 j9 1l2 l2l2 z = 75 r1 75 r2 75 r3 75 z = 75z = 75 11 j10j11 j4 banana jack v ee 6556 f06 43 2 5 out2 43 2 5 out3 v ee ?.3v to ?v 43 2 c14700pf c104700pf c70.33 f 10v c2470pf c3470pf c410 f 16v1206 c910 f 16v1206 j2 banana jack v cc v cc 3.3v to 5v c54700pf c6470pf c80.33 f 10v bnc 3 5432 1 r950 opt j8 50 bnc sel a/b v 25 downloaded from: http:///
lt6556 12 6556f typical applicatio u figure 7. demo board topside (ic removed for clarity) figure 8. demo board bottom side downloaded from: http:///
lt6556 13 6556f sche atic w w si plified 360 100 770 1k v + v + v + v v v ina en dgnd v v + sel to otherinput stages v ref v ref 40k 40k 100 inb v ref v ref select 46k bias to otheroutput stages v + out 6556 ss v 360 (one channel shown) downloaded from: http:///
lt6556 14 6556f package descriptio u .337 ?.344* (8.560 ?8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 1617 18 19 20 21 22 23 24 15 14 13 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .0075 ?.0098 (0.19 ?0.25) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note:1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) downloaded from: http:///
lt6556 15 6556f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. package descriptio u 4.00 0.10 (4 sides) note:1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?o be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 24 23 12 bottom view?xposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ?0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notchr = 0.20 typ or 0.35 45 chamfer uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) downloaded from: http:///
lt6556 16 6556f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt/tp 0805 500 printed in usa part number description comments lt1203 150mhz single 2:1 multiplexer single spdt video switch lt1399 300mhz triple current feedback ampli? er 0.1db gain flatness to 150mhz, shutdown lt1675 250mhz triple rgb multiplexer 100mhz pixel switching, 1100v/s slew rate, 16-lead ssop lt6550/lt6551 3.3v triple and quad video buffers 110mhz gain of 2 buffers in ms package lt6553 650mhz gain of 2 triple video ampli? er same pinout as the lt6554 but optimized for driving 75 cables lt6554 650mhz gain of 1 triple video ampli? er performance similar to the lt6556 with one set of inputs, 16-lead ssop lt6555 650mhz gain of 2 triple video multiplexer same pinout as the lt6556 but optimized for driving 75 cables related parts typical applicatio u 1 lt6556 #1 v + in1a red 1 green 1 blue 1 red 2 green 2 blue 2 75 75 in1b 1 in2a 75 75 75 75 in2b 1 in3ain3b sel out3 out2 out1 ?v g out agndout1 out2 en 5v dgnd v v ref 1 lt6556 #2 v + in1a red 3 green 3 blue 3 red 4 green 4 blue 4 sel0sel1 75 75 in1b 1 in2a 75 75 75 75 in2b 1 in3ain3b sel out3 ?v agnd en 5v dgnd 6556 f09 v v ref r out b out nc7sz14 sel1 00 1 1 sel0 01 0 1 output 12 3 4 figure 9. 4:1 rgb multiplexer downloaded from: http:///

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