DS782 october 19, 2011 www.xilinx.com 1 product specification ? copyright 2009?2011 xilinx, inc. xilinx, the xilinx logo, artix, ise, kintex, spartan, virtex, zynq, and other designated bra nds included herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the xilinx chipscope? pro ibert core for spartan?-6 gtp transceivers is customizable and can be used to evaluate and monitor spartan-6 gtp transceivers. the design includes pattern generators and checkers implemented in fpga logic, and access to the ports and the drp attributes of the transceivers. communication logic is also included to allow the design to be run-time, and is accessible through jtag pins. the ibert core is a self-contained design; when generated, it runs through the entire implementation flow, including bitstream generation. features ? provides a communication path between the chipscope pro analyzer software and the ibert core. ? has a user-selectable number of spartan-6 gtp transceivers. ? each transceiver can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width. ? requires a system clock that can be sourced from a pin or one of the enabled serial transceivers. chipscope integrated bit error ratio test (ibert) for spartan-6 gtp (v2.02a) DS782 october 19, 2011 product specification logicore ip facts table core specifics supported device family (1) 1. including the variants of this fpga device. spartan-6 supported user interfaces n/a resources (2) 2. for single-serial transceiver design with 20-bit fpga logic width. frequency configuration luts ffs i/o block rams max. freq config1 5921 9750 18 0 139.567 mhz provided with core documentation product specification user guide design files netlist example design n/a te s t b e n c h n/a constraints file n/a simulation model not provided tested design tools design entry tools xilinx core generator? tool simulation not provided synthesis tools not provided support provided by xilinx @ www.xilinx.com/support
DS782 october 19, 2011 www.xilinx.com 2 product specification chipscope ibert for spartan-6 gtp applications the ibert core is designed to be used in any application that requires verification or evaluation of spartan-6 gtp transceivers. functional description the ibert core provides a broad-based physical medium attachment (pma) evaluation and demonstration platform for spartan-6 gtp transceive rs. parameterizable to use differen t serial transceivers and clocking topologies, the ibert core can also be customized to use different line rates, reference clock rates, and fpga logic widths. data pattern generators and checkers are included for each serial transceiver desired, giving a variety of different prbs and clock patterns to be sent over the channe ls. in addition, the configurat ion and tuning of the serial transceivers is accessible though logic that communicates to the drp port of the serial transceiver, in order to change attribute settings, as well as registers that control the values on the ports. at run time, the chipscope analyzer tool communicates to the ibert core through jtag, using the xi linx cables and proprietary logic that is part of the ibert core. serial transceiver features ibert is designed for pma evaluation and demonstration. all the major pma features of the serial transceiver are supported and controllable in ibert, including: ? transmit (tx) pre-emph asis and post-emphasis ? tx differential swing ? receive (rx) equalization ? phase-locked loop (pll) divider settings some of the physical coding sublayer (pcs) features offered by the transc eiver are outside the scope of ibert, including ? clock correction ? channel bonding ? 8b/10b, 64b/66b, or 64b/67b encoding ? tx or rx buffer bypass generating the core using the xilinx core generator? software, you can defi ne and generate a customized ibert core for spartan-6 fpga gtp transceivers. when all the ibert parameters have been chosen, a full design is generated, including a bitstream. the ibert core cannot be included in your design ; it can only be generated in its own stand-alone design. the ise tools are invoked by the core generator tool to gene rate a bitstream file (.bit) rather than a design netlist file (.ngc or .edn). 1. in the debug & verification > chipscope pro ip category of core generator, select ibert spartan6 gtp (chipscope pro - ibert) core. 2. then click customize in the right side of the window.
DS782 october 19, 2011 www.xilinx.com 3 product specification chipscope ibert for spartan-6 gtp general ibert options the first screen in the core generator tool is used to set up general ibert options, described in the following sections. choosing the component name the component name can be any combination of alpha- numeric characters, including the underscore symbol. however, the underscore symbol cannot be the first character in the component name. selecting the number of line rates (protocols) the ibert core can have multiple mgts, which do not ha ve to operate at the same line rate, or use the same reference clock. choose the number of distinct line rate/r eference clock rate combinations needed from the number of line rates (protocols) dialog. choosing the line rate settings for each line rate setting desired, choose between a custom setting (?start from scratch?) or a pre-defined protocol setting from the protocol combo box. if a named protocol is chosen, the fields for max rate, data width, and refclk are automatically filled in according to the protoc ol. if specifying a custom protocol, type in the values desired. selecting the gtpa1_duals and reference clocks after selecting the protocol options for the ibert core, click next to view the gtpa1_duals. select gtxs and reference clocks for line rate 1. af ter line rate 1 is complete, click next to access line rate 2, etc. until all the line rates are completed. choosing gtpa1_duals each available gtpa1_dual (also referred to as ?dual? is listed with its location and a checkbox next to it. you cannot select a single transceiver within the dual: both transceivers must be used. if the checkbox is greyed out, the transceiver is already configured wi th a different line rate. check the duals that will use the given line rate. although both duals must be configured at the same line rate at generate time, that can be altered at runtime. choosing refclk sources from the gtp1 refclk source combo box, choose the reference clock for each transceiver. one reference clock is available from the dual, and reference clocks are also available from neighboring duals. see the spartan-6 fpga gtp transceivers user guide for more information on the clocking topology. enabling rxrecclk probes after selecting the gtp transceivers and refclk option s for the ibert core for all the line rates, click next to view the rxrecclk probe options. for each of the gtp transceivers used, it is possible to drive the rxrecclk (recovered clock) out to a pin for use in external measurement. to enable this, check the enab le checkbox next to the desired recovered clock. then specify the pin location in the location text field, and choose the i/o standard from the io standard combo box. for differential standards, specify the p pin location. choosing the system clock source after selecting the rxrecclk probing options, cl ick next to view the system clock options.
DS782 october 19, 2011 www.xilinx.com 4 product specification chipscope ibert for spartan-6 gtp ibert needs a clock for the internal communication logic. this can come from an external pin, or from the txoutclk of one of the gtp transceivers enabled in the ibert design. to use a clock from a pin, enable the use external clock source radio button, type the frequency in the frequency field, type the pin location in the pin location field, and choose the pin input standard. for differential standards, specify the p pin location. to specify an internal clock, disable the use external cl ock source radio button in the first panel. in the system clock source panel, specify the gtp transceiver in the gtp dual source combo box. generating the design after entering the ibert core parameters, click next to view the ibert design summary. this includes the gtp transceivers used, system clock, and the details of the global clock resources. to generate the design, click generate . pattern generation and checking each serial transceiver enabled in the ibert design has both a pattern generator and a pattern checker. the pattern generator sends data out through the transmitter. the patte rn checker takes the data coming in through the receiver and checks it against an internally ge nerated pattern. ibert offers prbs 7-bit, prbs 15-bit, prbs 23-bit, prbs31-bit, clk 2x (101010...) and clk 10x(1111111111 0000000000...) patterns. these patterns are optimized for the fpga logic width chosen, and are selectable at run time. the tx pattern and rx pattern are individually selectable. the pattern checker logic also generates a ?link? signal that displays in the analyzer software. the channel is linked when there are five consecutive cycles of data with no er rors. the incoming data is co mpared against a pattern that is generated internally. when the checker receives five cons ecutive cycles of data with errors, it removes the channel link. internal counters a ccumulate the number of words and error received. drp and ports access ibert also provides flexibility to change serial transceive r ports and attributes. drp interface logic is included that allows the run-time software to monitor and change any attr ibute in any of the serial transceivers included in the ibert core. readable and writable (when applicable) regist ers are also included that are connected to the various ports of the serial transceiver. all are accessible at run time using the chipscope analyzer tool. system clock the ibert core requires a free-running system clock to clock the communication and ot her logic included in the ibert core. this clock can be chosen at generation time to come from an fpga pin, or be driven from the txoutclk port of one of the serial transceivers in the core. if the system clock is running faster than 150 mhz, it is divided down internally using an dcm to satisfy timing constraints. interface ports the input/output (i/o) signals of the ibert core consist on ly of the serial transceiver reference clocks, the serial transceiver transmit and receive pi ns, and a system clock (optional). ta bl e 1 : interface ports port name direction description sysclk in design clock that clocks all communication logic. this port is optional, because you can select an internal serial transceiver clock at generation time to perform this function. txn[n-1:0], txp[n-1:0] out transmit differential pairs for each of the n serial transceivers used.
DS782 october 19, 2011 www.xilinx.com 5 product specification chipscope ibert for spartan-6 gtp restrictions only one ibert core can be generated for a device, and the ibert core will constitute the entire design. the ibert core cannot be merged in with user logic. verification xilinx has verified the ibert core in a proprietary test environment, using an internally developed bus functional model. references ? more information on the chipscope pro software and cores is available in the software and cores user guide , located at http://www.xilinx.com/documentation . ? information about hardware debugging using chipscope pro in edk is available in the platform studio 11 online help, located at http://www.xilinx.com/documentation . ? information about hardware debugging using chipscope pro in system generator for dsp is available in the xilinx system generator for dsp user guide , located at http://www.xilinx.com/documentation . support xilinx provides technical support for this logicore? ip product when used as described in the product documentation. xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that are not defined in the documentation, if customized be yond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . ordering information the ibert core is provided under the integrated software environment (ise?) design suite end-user license agreement and can be generated using the xilinx core generator system 11 or higher. the core generator system is shipped with xilinx ise design suite development software. contact your local xilinx sales representative for pricing and availability of additional xilinx logicore modules and software. information about additional xilinx logicore modules is available on the xilinx ip center . rxn[n-1:0], rxp[n-1:0] out receive differential pa irs for each of the n serial transceivers used. mgtrefclk_p[m-1:0], mgtrefclk_n[m-1:0] in serial transceiver reference clocks used. not necessarily m = n because some serial transceivers can share clock inputs. ta bl e 1 : interface ports (cont?d) port name direction description
DS782 october 19, 2011 www.xilinx.com 6 product specification chipscope ibert for spartan-6 gtp list of acronyms revision history the following table sumarizes the ch ange history for this document: notice of disclaimer the information disclosed to you hereunder (the ?materials?) is provided solely for the selectio n and use of xilinx products. t o the maximum extent permitted by applicable law: (1) materials are made availa ble ?as is? and with al l faults, xilinx hereby disclaims all warranties and conditions, express, implied, or statutory, including but not limited to warranties of merchantability, non-infringement, or fitness for any particular purpose; and (2) xilinx shall not be liable (whether in contra ct or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature relate d to, arising under, or in connection with, the materials (includ ing your use of the materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffer ed as a result of any action br ought by a third party) even if such damage or loss was reasonably foreseeable or xilinx had b een advised of the possibility of the same. xilinx assumes no obligation to correct any errors contained in the materials or to notify you of updates to the materials or to product specifications. you may not reproduce, mo dify, distribute, or publicly display th e materials without prior written consent. certain products are subject to the terms and conditions of the limited warranties which can be viewed at ta bl e 2 : list of acronyms acronym definition drp dynamic reconfiguration port ff flip-flop fpga field programmable gate array i/o input/output ibert integrated bit error radio tester ip intellectual property ise integrated software environment jtag joint test action group lut lookup table pcs physical coding sublayer pll phase-locked loop pma physical medium attachment prbs pseudorandom binary sequence ram random access memory rx receive tx transmit xst xilinx synthesis technology date version description of revisions 09/16/2009 1.0 release 11.3 (initial xilinx release). 10/19/2011 2.0 ? updated to 2.02.a core version and 13.3 xilinx tools. ? added new section for generating the ibert core. ? added list of acronyms. ? updated notice of disclaimer and copyright notice. ? replaced ?mgt? with ?serial transceiver?
DS782 october 19, 2011 www.xilinx.com 7 product specification chipscope ibert for spartan-6 gtp http://www.xilinx.com/warranty.htm ; ip cores may be subject to warranty and suppo rt terms contained in a license issued to you by xilinx. xilinx products are not desi gned or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability fo r use of xilinx products in critical applications: http://www.xilinx.com/warranty.htm#critapps .
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