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may 2014 altera corporation ? 2014 altera corporation. all rights reserved. altera , arria, cyclone, enpirion, hardcopy, max, megacore, nios, quartus and stratix words and logos are trademarks of altera corporation and registered in the u.s. patent and trademark office and in other countries. al l other words and logos identified as tradem arks or service marks are the property o f their respective holders as described at www.altera.com/common/legal.html . altera warrants performance of its semiconductor products to current specifications in accord ance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liabilit y arising out of the application or use of any information, product, or service desc ribed herein except as expressly agreed to in writing by altera. altera customers a re advised to obtain the latest version of de vice specifications before relying on any published information and before placing or ders for products or services. 101 innovation drive san jose, ca 95134 www.altera.com subscribe iso 9001:2008 registered ES1022SI datasheet the ES1022SI ic pr ovides four delay adjustable sequenced outputs while monitoring an input voltage all with a minimum of external components. high performance dsp, fpga, p and various sub- systems require input power sequencing for proper functionality at initial power up and the ES1022SI provides this function whil e monitoring the distributed voltage for over and undervoltage compliance. this ic operates over the +3.3v to +24v nominal voltage range. it has a user adjustable time from uv and ov voltage compliance to sequen cing start via an external capacitor when in auto start mode and adjustable time delay to subsequent en output signal via external resistors. additionally, the ES1022SI pr ovides i/o for sequencing on and off operation (seq_en) and for voltage window compliance reporting (fault) over the +3.3v to +24v nominal voltage range. easily daisy chained for more than 4 sequenced signals. altogether, the ES1022SI provides these adjustable features with a minimum of external bom. see figure 1 for typical implementation. features ? adjustable delay to subsequent en signal ? adjustable delay to sequence auto start ? adjustable distribute d voltage monitoring ? under and overvoltage adjustable delay to auto start sequence ? i/o options: en and seq_en ? voltage compliance fault output ? pb-free plus anneal available (rohs compliant) applications ? power supply sequencing ? system timing function figure 1. ES1022SI implementation en_a uv ov vin fault seq_en en_b en_c en_d 3.3-24v dc/dc en dc/dc en dc/dc en dc/dc en vo1 vo2 vo3 v04 ru rm rl gnd tdly_ab tdly_bc tdly_cd time enpirion ? power datasheet ES1022SI adjustable quad sequencer 10037 may 28, 2014 rev a
page 2 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation ordering information part number (note 1) part marking temp. range (c) package (pb-free) pkg. dwg. # ES1022SI* ES1022SI -40 to +85 14 ld soic m14.15 evb-ES1022SI evaluation platform *add ?-t? suffix for tape and reel. please refer to packing and marking information: www.alter a.com/support/reliability/packing /rel- packing-and-marking.html notes: 1. altera enpirion pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. altera enpir ion pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std -020. 10037 may 28, 2014 rev a
page 3 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation pinout ES1022SI (14 ld soic) top view pin descriptions pin number pin name function description 1 en_d en output d. active high open drain se quenced output. sequenced on af ter en_c and first output to sequence off. pulls low with v in < 1v. 2 en_c en output c. active high open drain sequenced output. sequenced on after en_b and sequenced off after en_d. pulls low with v in < 1v. 3 en_b en output b. active high open drain sequenced output. sequenced on after en_a and sequenced off after en_c. pulls low with v in < 1v. 4 en_a en output a. active high open drain se quenced output. sequenced on after ctime period and sequenced off after en_b. pulls low with v in < 1v. 5 ov the voltage on this pin must be under its 1.22v vth or the four en outputs will be immediately pulled down. 6 uv the voltage on this pin must be over its 1.22v vth or the four en outputs will be immediately pulled down. 7 gnd ic ground. 8 fault the v in voltage when not within the desired uv to ov window will cause fault to be released to be pulled high to a voltage equal to or less than v in via an external resistor. 9 seq_en this pin provides a sequence on signal input with a high input. internally pulled high to ~2.4v. 10 time this pin provides a 2.6a current output so that an adjustable v in valid to sequencing on and off start delay period is created with a capacitor to ground. 11 tdly_ab a resistor connected from this pin to ground determines the time delay from en _a being active to en _b being active on turn- on and also going inactive on turn-off via the seq_en input. 12 tdly_bc a resistor connected from this pin to ground determines the time delay from en _b being active to en _c being active on turn- on and also going inactive on turn-off via the seq_en input. 13 tdly_cd a resistor connected from this pi n to ground determines the time delay from en _c being active to en _d being active on turn- on and also going inactive on turn-off via the seq_en input. 14 v in ic bias pin nominally 3.3v to 24v this pin requires a 1 f decoupling capacito r close to ic pin. en_d en_c en_b en_a 1 2 3 4 5 vin tdly_cd tdly_bc tdly_ab 6 7 8 9 14 time seq_en fault ov uv gnd 13 12 11 10 10037 may 28, 2014 rev a
page 4 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation absolute maximum ratings thermal information v in , en, fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27v, to -0.3v time, tdly_ab, tdly_bc, tdly_cd, uv, ov .+6v, to -0.3v seq_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v in +0.3v, to -0.3v en output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range (nominal) . . . . . . . . . . . . . . 3.3v to 24v thermal resistance (typical, note 2) . . . . . . . . . . . ja (c/w) 14 ld soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 maximum junction temperature (plastic package) +125c maximum storage temperature range . . . . . . -65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . +300c (soic lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicate d in the operational sections of this specification is not impl ied. note: 2. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. electrical specifications nominal v in = 3.3v to +24v, t a = t j = -40 c to+85c, unless otherwise specified. parameter symbol test conditions min typ max unit uv and ov inputs uv/ov rising threshold v uvrvth 1.16 1.21 1.28 v uv/ov falling threshold v uvfvth 1.06 1.10 1.18 v uv/ov hysteresis v uvhys v uvrvth - v uvfvth -104-mv uv/ov input current i uv -10-na time, en outputs time pin charging current i time -2.6- a time pin threshold v time_vth 1.9 2.0 2.25 v time from v in valid to en_a t vinseqpd seq_en = high, c time = open - 30 - s t vinseqpd_10 seq_en = high, c time = 10nf - 7.7 - ms t vinseqpd500 seq_en = high, c time = 500nf - 435 - ms time from v in invalid to shutdown t shutdown uv or ov to simult aneous shutdown - - 1 s en output resistance r en i en = 1ma -100- en output low vol i en = 1ma -0.1- v en pull-down current i pulld en = 1v 10 15 - ma delay to subsequent en turn-on/off t del_120 r tx = 120k 155 195 240 ms t del_3 r tx = 3k 3.5 4.7 6 ms t del_0 r tx = 0 -0.5-ms sequence en and fault i/o v in valid to fault low t fltl 15 30 50 s v in invalid to fault high t flth -0.5- s fault pull-down current fault = 1v 10 15 - ma seq_en pull-up voltage v seq seq_en open - 2.4 - v seq_en low threshold voltage vil seq_en --0.3v seq_en high threshold voltage vih seq_en 1.2 - - v delay to en_a deasserted t seq_en_ena seq_en low to en_a low - 0.2 1 s 10037 may 28, 2014 rev a
page 5 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation functional block diagram functional description ES1022SI provides four delay adjustable se quenced outputs while monitoring a sing le distributed volt age in the nominal range of 3.3v to 24v for both under and overvoltage. only when the voltage is in compliance w ill the ES1022SI initiate the pre-programmed a-b-c-d sequence of the en outputs. although this ic has a bias range of 3.3v to 24v it can monitor any voltage >1.22v via the external divider if a suitable bias voltage is otherwise provided. during initial bias voltage (v in ) application the ES1022SI en outputs are held low once v in =1v. once v in > the v bias power on reset threshold (por) of 2.8v, v in is constantly monitored for compliance via the input voltage resistor divider and the voltages on the uv and ov pins and reported by the fault output. inte rnally, voltage regulators generate 3.5v and 1.17v 5% voltage rails for internal usage once v in > por. once uv > 1.22v and with the seq_en pin high or open, the auto sequence of the four en outputs begins as the time pin charges its external capacitor with a 2.6a current source. the voltage on time is compar ed to the internal reference (v time_vth ) comparator input and when greater than v time_vth the en_a is released to go high via an external pull-u p resistor or a pull-up in a dc/dc convertor en input, for example. the time delay generated by the extern al capacitor is to assure continued voltage compliance within the programmed limits, as during this time any ov or uv condition will halt the start-up process. time cap is discharged once v time_vth is met. bias ic supply current i vin_3.3v v in = 3.3v - 191 - a i vin_12v v in = 12v - 246 400 a i vin_24v v in = 24v - 286 - a v in power on reset v in_por v in low to high - 2.3 2.8 v electrical specifications nominal v in = 3.3v to +24v, t a = t j = -40 c to+85c, unless otherwise specified. (continued) parameter symbol test conditions min typ max unit vin voltage 1.17v internal voltage regulator vin (2.8v min - 27v max) 2.0v vin por 3.5v logic vin programmable delay timer v time_vth 2.6 a vin tdly_ab tdly_bc tdly_cd en_a en_b en_c en_d time gnd fault seq_en uv ov + - - + eo vref 30 s reference 10037 may 28, 2014 rev a
page 6 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation once en_a is active (released high on the ES1022SI) a counte r is started and using the resi stor on tdly_ab as a timing component a delay is generated before en_b is activated. at this time, the counter is restarted using the resistor on tdly_bc as its timing component for a separate timed delay until en_ c is activated. this process is repeated for the resistor on tdly_cd to complete the a-b- c-d sequencing order of the en outputs. at any time during sequencing if an ov or uv event is registered, a ll four en outputs will immediately re turn to their low reset state. c time is immediately discharged after initial ramp up thus waiting for subsequent voltage complianc e to restart. once sequencing is complete, any subsequently registered uv or ov event will trigger an immediate and simultaneous reset of all en outputs. on the ES1022SI, enabling of on or off sequencing can also be signaled via the seq_en input pin once voltage compliance is met. initially, the seq_en pin should be held lo w and released when sequence start is desired. seq_en is internally pulled high and sequencing is enabled unless it is pulled low. the on sequence of the en outputs is as previously described. the off sequence is d off, then c off, th en b off and finally a off. once seq_en is signaled low, the time cap is charged to 2v once again. once this vth is reached, en_d transi tions to its reset state and ctim is discharged. a delay and subsequent sequence off is then dete rmined by tdly_cd resistor to en_c. likewise, a delay to en_b and then en_a turn-off is determined by tdly_bc and tdly_ab resistor values respectively. the fault signal is always valid at operational voltages an d can be used as justification for seq_en release or even controlled with an rc timer for sequence on. programming the under and overvoltage limits when choosing resistors for the divider remember to keep the current through the string bounded by power loss at the top end and noise immunity at the bottom end. for most applications, total divider resistance in the 10k to1000k range is advisable with high prec ision resistors being used to reduce monitoring er ror. although for the es 1022si, two dividers of two resistors each can be employed to separate ly monitor the ov and uv levels for the v in voltage. we will discuss using a single three resistor string for monitoring the v in voltage, referencing figure 1. in the three resistor divider string with ru (upper), rm (middle) and rl (lower), the ratios of each in combination to the other two is balanced to achieve the desired uv and ov trip levels. alth ough this ic has a bias range of 3.3v to 24v, it can monitor any voltage >1.22v. the ratio of the desired overvoltage trip point to the internal reference is equal to the ratio of the two upper resistors to t he lowest (gnd connected) resistor. the ratio of the desired undervoltage trip point to the internal reference voltage is equal to the ratio of the uppermost (voltage connected) resistor to the lower two resistors. these assumptions are true fo r both rising (turn-on) or falling (shutdown) voltages. the following is a practical example worked out. for detail ed equations on how to perform this operation for a given supply requirement please see the next section. 1. determine if turn-on or shutdown limits are preferred. in th is example, we will determine the resistor values based on the shutdown limits. 2. establish lower and upper trip level: 12v 10% or 13.2v (ov) and 10.8v (uv) 3. establish total resistor string value: 100k , ir = divider current 4. (rm+rl) x ir = 1.1v @ uv and rl x ir = 1.2v @ ov 5. rm+rl = 1.1v/ir @ uv = rm+rl = 1.1v/(10.8v/100k ) = 10.370k 6. rl = 1.2v/ir @ ov = rl = 1.2v/(13.2v/100k ) = 9.242k 7. rm = 10.370k - 9.242k = 1.128k 8. ru = 100k - 10.370k = 89.630k 9. choose standard value resistors that most closely approximate these ideal va lues. choosing a different total divider resistance value may yield a more ideal ratio with available resistor?s values . in our example, with the closes t standard values of ru = 90.9k , rm = 1.13k and rl = 9.31k , the nominal uv falling and ov rising will be at 10.9v and 13.3v respectively. programming the en output delays the delay timing between the four sequenced en outputs ar e programmed with four external passive components. the delay from seq_en being valid to en_a is determined by the value of the capacitor on the time pin to gnd. the external time pin capacitor is charge d with a 2.6a current source. once the volt age on time is charged up to the internal 10037 may 28, 2014 rev a
page 7 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation reference voltage, (v time_vth ) the en_a output is released out of its reset st ate. the capacitor value for a desired delay (10%) to en_a once v in and seq_en where applicable has been satisfied is determined by: c time = t vinseqpd /770k once en_a reaches v time_vth , the time pin is pulled low in preparation for a sequenced off signal via seq_en. at this time, the sequencing of the subs equent outputs is started. en_b is released out of reset after a programmable time, then en_c, then en_d, all with their own programmed delay times. the subsequent delay times are programme d with a single external resistor fo r each en output providing maximum flexibility to the designer through the ch oice of the resistor value connected fr om tdly_ab, tdly_bc and tdly_cd pins to gnd. the resistor values determine the charge and discha rge rate of an internal capacitor comprising an rc time constant for an oscillator wh ose output is fed into a counter generating the timing delay to en output sequencing. the r tx value for a given delay time is defined as: r tx = t del /1667nf an advanced tutorial on setting uv and ov levels this section discusses in additional detail the nuances of se tting the uv and ov levels, providing more insight into the ES1022SI than the earlier text. the following equation set can alternatively be used to work out ideal values for a 3 resistor divider string of ru, rm and rl. these equations assume that v ref is the center point between v uvrvth and v uvfvth (i.e. (v uvrvth + v uvfvth )/2 = 1.17v), iload is the load current in the resistor string (i.e. v in /(ru + rm + rl)), v in is the nominal input voltage and vtol is the acceptable voltage tolerance, such that the uv an d ov thresholds are centered at v in vtol. the actual acceptable voltage window will also be affected by the hysteresis at the uv and ov pins. this hysteresis is amplif ied by the resistor string such that the hysteresis at the top of the string is: vhys = v uvhys x v out /v ref this means that the v in vtol thresholds will exhibit hyst eresis resulting in thresholds of v in + vtol vhys/2 and v in - vtol vhys/2. there is a window between the v in rising uv threshold and the v in falling ov threshold where the input level is guaranteed not to be detected as a fault. this window exists between the limits v in (vtol - vhys/2). there is an extension of this window in each direction up to v in (vtol + vhys/2), where the voltage may or may not be detected as a fault, depending on the direction from which it is approached. these two equations may be used to determine the required value of vtol for a given system. for example, if v in is 12v, vhys = (0.1 x 12)/1.17 = 1.03v. if v in must remain within 12v 1.5v, vtol = 1.5 - 1.03/2 = 0.99v. this will give a window of 12 0.48v where the system is guaranteed not to be in fault and a limit of 12 1.5v beyond which the system is guar anteed to be in fault. it is wise to check both these voltages, for if the latter is made to tight, the former will ceas e to exist. this point comes w hen vtol < vhys/2 and results from the fact th at the acceptable window for the ov pin no longer aligns with the acceptable window for the uv pin. in this case, the application will have to be changed such that uv and ov are provided separate resistor strings. in this case, the uv and ov thresholds can be individually controlled by adjusting the relevant divider. the previous example will give voltage thresholds of: with v in rising uvr = v in - vtol + vhys/2 = 11.5v and ovr = v in + vtol + vhys/2 = 13.5v with v in falling ovf = v in + vtol - vhys/2 = 12.5v and uvf = v in - vtol - vhys/2 = 10.5v. so with a single three resi stor string, the resistor values can be calculated as: rl = (v ref /iload) (1 - vtol/v in ) rm = 2(v ref x vtol)/(v in x iload) ru = 1/iload x (v in - v ref (1+vtol/v in )) 10037 may 28, 2014 rev a
page 8 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation for the above example, with vtol = 0.99v, assuming a 100a iload at v in = 12v: rl = 10.7k rm = 1.9k ru = 107.3k typical performance curves figure 4. uv/ov rising threshold figure 5. v in current figure 2. ES1022SI operational diagram en outputs abcd fault a b cd seq_en time figure 3. ES1022SI fault operational diagram undervoltage overvoltage monitored voltage fault output t flth limit limit ramping up and down t flth t fltl t fltl page 9 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation applications usage using the evb-ES1022SI platform the evb-ES1022SI platform is the primary evaluation board for this family of sequencers. see figure 15 for photograph and schematic. the evaluation board is shipped wi th an ES1022SI mounted in the left position and with the other device variants loos e packed. in the following disc ussion, test points names are bold on initial occurrence for identification. the v in test point is the chip bias and ca n be biased from 3.3v to 24v. the vhi test point is for the en and fault pull-up voltage which are limited to a maximum of 24v independent of v in . the uv/ov resistor di vider is set so that a nominal 12v on the vmonitor test point is compliant and with a rising ov set at 13.2v and a falling uv set at 10.7v. these three test points (v in ,vhi and vmonitor) are brought out se parately for maximum flexibility in evaluation. vmonitor ramping up and down through the uv and ov levels will result in the fault output signaling the out of bound conditions by being released to pull high to the vhi voltage as shown in figures 6 and 7. once the voltage monitoring fault is resolved and where applicable, the seq_en is satisfied, sequencing of the en_x outputs begins. when sequence enabled the en_a , en_b , en_c and lastly en_d are asserted in that order and when seq_en is disabled the order is reversed. see fi gures 8 and 9 demonstrating the sequenced enabling and disabling of the en outputs. the timing between en outputs is set by the resistor values on the tdly_ab, tdly_bc, tdly_cd pins as shown. figure 10 il lustrates the timing from either se q_en and/or vmonit or being valid to en_a being asserted with a 10nf time capacitor. figure 11 shows that en_x outputs are pulled low even before v in = 1v. this is critical to ensure that a false en is not si gnaled. figure 12 shows the time from seq_en transition with the voltage ramping across the time capa citor to time vth being met. this result s in the immediate pull down of the time pin and simultan eous en_a enabling. figure 6. vmonitor rising to fault figure 7. vmonitor falling to fault fault output vmon rising vmon > uv vmon > ov level level vmon falling vmon > ov vmon > uv level level fault output 10037 may 28, 2014 rev a
page 10 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation figure 8. en_x to en_x enabling figure 9. en_x to en_x disabling figure 10. v in /seq_en valid to en_a figure 11. en as v in rises figure 12. seq_en to en_a figure 13. ov and uv transient immunity r tdly_cd = 120k delay = 196ms r tdly_bc = 51k r tdly_ab = 3k delay = 5ms delay = 86ms r tdly_cd = 120k delay = 196ms r tdly_ab = 3k delay = 5ms r tdly_bc = 51k delay = 86ms c time = 10nf delay = 8.5ms 1v/div 10ms/div v in rising en outputs tracks v in to < 0.8v en_a time seq_en 0.5v/div 8s/div fault = low vmonitor ov vmonitor uv 10037 may 28, 2014 rev a
page 11 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation application recommendations best practices v in decoupling is required, a 1 f capacitor is recommended. coupling from the en_x pins to the sens itive uv and ov pins can cause false ov/uv events to be detected. this is relevant due to the en_a and ov pins being adjacent. this coupling can be reduced by adding a ground trace between uv and the en/fault si gnals, as shown in figure 14. the pcb traces on ov and uv should be kept as small as practical and the en_x and fault traces should ideally not be routed under/over the ov/uv traces on different pcb layers unless there is a ground or power plane in between. other methods that can be used to eliminate this issue are by reducing the value of the resis tors in the network connected to uv and ov (r2, r3, r5 in figure 15) or by adding small decoupling capacitors to ov and uv (c2 and c7 in figure 15). both these me thods act to reduce the ac impedance at the nodes, although the latte r method acts to filter the signals whic h will also cause an increase in the time that a uv/ov fault takes to be detected . when the ES1022SI is implemented on a hot swappable card that is plugged into an al ways powered passive back plane an rc filter is required on the v in pin to prevent a high dv/dt transi ent. with the already existing 1 f decoupling capacitor the addition of a small series r (>50 ) to provide a time constant >50 s is all that is necessary. figure 14. layout detail of gnd between pins 4 and 5 pin 4 pin 5 gnd 10037 may 28, 2014 rev a
page 12 enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation . table 1. evb-ES1022SI left channel component listing component designator component function component description u1 ES1022SI, quad under/overvoltage sequencer altera enpirion, ES1022SI, quad under/overvoltage sequencer r3 uv resistor for divider string 1.1k 1%, 0603 r2 vmonitor resistor for divider string 88.7k 1%, 0603 r5 ov resistor for divider string 9.1k 1%, 0603 c1 c time sets delay from sequence start to first en 0.01 f, 0603 r1 r tdly_cd sets delay from third to fourth en 120k 1%, 0603 r9 r tdly_ab sets delay from first to second en 3.01k 1%, 0603 r7 r tdly_bc sets delay from second to third en 51k 1%, 0603 r4, r6, r8, r10, r11 en_x and fault pull-up resistors 4k 10%, 0402 c3 decoupling capacitor 1 f, 0603 figure 15. evb-ES1022SI photograph and schematic of left channel timing components resistors uv/ov set resistors pull-up en_a en_b en_c en_d ES1022SI tdly_cd tdly_bc tdly_ab 10037 may 28, 2014 rev a
page 13 enpirion power datasheet es102 2si adjustable quad sequencer may 2014 altera corporation revision history the table lists the revision history for this document. date revision change may, 2014 1.0 initial release. 10037 may 28, 2014 rev a
enpirion power datasheet ES1022SI adjustable quad sequencer may 2014 altera corporation page 14 small outline plastic packages (soic) notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publica- tion number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shal l not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0. 36mm (0.014 inch) or greater above the seating plane, shall not exceed a m aximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. co nverted inch dimensions are not nec- essarily exact. index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m m14.15 (jedec ms-012-ab issue c) 14 lead narrow body sm all outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.3367 0.3444 8.55 8.75 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n14 147 a 0 o 8 o 0 o 8 o - rev. 0 12/93 10037 may 28, 2014 rev a

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