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description the 78q2123 and 78q2133, microphy tm , are the smallest 10base-t/100base-tx fast ethernet transceivers in the market. they include integrated mii, endecs, scrambler/descrambler, dual-speed clock recovery, and full-featured auto-negotiation functions. the transmitter includes an on-chip pulse- shaper and a low-power line driver. the receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery. the transceiver interfaces to category-5 unshielded twisted pair (cat-5 utp) cabling for 100base-tx applications, and category-3 unshielded twisted pair (cat-3 utp) for 10base-t applications. the mdi is connected to the line media via dual 1:1 isolation transformers. no external filter is required. interface to the mac is accomplished through an ieee-802.3 compliant media independent interface (mii). the 78q2123/78q2133 are intended to serve the embedded ethernet market, tailored specifically to the needs of game consoles, broadband modems, printers, set top boxes and audio/visual equipment. it is designed for low-power consumption and operates from a single 3.3v supply. the 78q2123 is rated for commercial temperature range and the 78q2133 is rated for industrial temperature range. features x smallest 10/100 phy available x 10base-t/100base-tx ieee-802.3 compliant tx and rx functions requiring a dual 1:1 isolation transformer interface to the line x integrated mii, 10base-t/100base-tx endec, 100base-tx scrambler/descrambler, and full-featured auto-negotiation function x full duplex operation capable x automatic mdi/mdi-x cross over correction x register-programmable transmit amplitude x automatic polarity correction during auto- negotiation and 10base-t signal reception x power-saving and power-down modes including transmitter disable x 2 programmable led indicators (link and activity by default) x user programmable interrupt pin x packages: 32-qfn (5x5 mm) and 32-tqfn (5x5mm) x low power (~290mw) x single 3.3 v r 0.3v supply x 78q2123 rated for 0c to 70c operation x 78q2133 rated for -40c to 85c operation rxc txc rxd txd smi mii 100m 10m scrambler, parallel/serial parallel/serial, manchester encoder mrz/nrzi mlt3 encoder tx clk gen auto auto mdi-x mux tx/rxrx/tx carrier sense, collision detect clk recovery 10m 100m adaptive eq, baseline wander correct, mlt3 decode, nrzi/nrz clock reference leds clkin 25mhz link act rev. 2.0 1 data sheet 78q2123/78q2133 microphy ? 10/100base-tx transceiver simplifyingsystemintegration tm pulse shaper and filter manchester decoder, parallel/serial mii registers serial/parallel descrambler, 5b/4b decoder downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 table of contents 1 functional description .......................................................................................................................... 5 1.1 general ............................................................................................................................... ............ 5 1.1.1 power management............................................................................................................ 5 1.1.2 analog biasing and supply regulation ................................................................................ 5 1.1.3 clock selection.................................................................................................................... 5 1.1.4 transmit clock generation .................................................................................................. 5 1.1.5 receive signal qualification................................................................................................ 6 1.1.6 receive clock recovery ..................................................................................................... 6 1.2 100base-tx o peration........................................................................................................... 6 1.2.1 100base-tx transmit........................................................................................................ 6 1.2.2 100base-tx receive......................................................................................................... 6 1.2.3 pcs bypass mode (auto-negotiate must be off) ................................................................. 6 1.3 10base-t operation ............................................................................................................. .. 7 1.3.1 10base-t transmit ............................................................................................................ 7 1.3.2 10base-t receive ............................................................................................................. 7 1.3.3 polarity correction............................................................................................................... 7 1.3.4 sqe test .......................................................................................................................... 7 1.3.5 natural loopback ................................................................................................................ 7 1.3.6 repeater mode ................................................................................................................... 7 1.4 auto-negotiation ............................................................................................................................ 8 1.5 media independent interface ......................................................................................................... 9 1.5.1 mii transmit and receive operation................................................................................... 9 1.5.2 station management interface ............................................................................................ 9 1.6 additionalfeatures ......................................................................................................................10 1.6.1 led indicators.................................................................................................................. .10 1.6.2 interrupt pin................................................................................................................... ....10 1.6.3 automatic mdi/ mdi-x configuration ................................................................................10 2 pin description.....................................................................................................................................11 2.1 legend ............................................................................................................................... ...........11 2.2 mii (media independent interface) ..............................................................................................11 2.3 control and status .......................................................................................................................12 2.4 mdi (media dependent interface) ...............................................................................................12 2.5 oscillator/clock ............................................................................................................................12 2.6 power supply and ground ...........................................................................................................12 2.7 led signals (programmability is secondary requirement) ......................................................13 3 register description .......................................................................................................... .................14 3.1 mr0: control register .................................................................................................................15 3.2 mr1: status register ...................................................................................................................16 3.3 mr2: phy identifier register 1 ...................................................................................................17 3.4 mr3: phy identifier register 2 ...................................................................................................17 3.5 mr4: auto-negotiation advertisement register .........................................................................17 3.6 mr5: auto-negotiation link partner ability register ................................................................18 3.7 mr6: auto-negotiation expansion register ...............................................................................18 3.8 mr16: vendor specific register .................................................................................................18 3.9 mr17: interrupt control/status register .....................................................................................20 3.10 mr18: diagnostic register ..........................................................................................................21 3.11 mr19: transceiver control .........................................................................................................21 3.12 mr20: reserved ..........................................................................................................................21 3.13 mr21: reserved ..........................................................................................................................21 3.14 mr22: reserved ..........................................................................................................................21 3.15 mr23: led configuration register .............................................................................................22 3.16 mr24: mdi/mdix control register .............................................................................................22 2 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4 electrical specifications ....................................................................................................... ...............23 4.1 absolute maximum ratings .........................................................................................................23 4.2 recommended operatingconditions .........................................................................................23 4.3 dccharacteristics .......................................................................................................................23 4.4 digital i/o characteristics ............................................................................................................24 4.5 digital timing characteristics ......................................................................................................25 4.5.2 mii transmit interface .......................................................................................................25 4.5.3 mii receive interface.........................................................................................................26 4.6 mdio interface input timing ........................................................................................................26 4.6.1 mdio interface output timing ..........................................................................................27 4.6.2 mdio interface output timing ..........................................................................................28 4.6.3 100base-tx system timing ............................................................................................29 4.6.4 10base-t system timing.................................................................................................29 4.7 analog electrical characteristics .................................................................................................30 4.7.1 100base-tx transmitter..................................................................................................30 4.7.2 100base-tx transmitter (informative).............................................................................30 4.7.3 100base-tx receiver......................................................................................................30 4.7.4 10base-t transmitter ......................................................................................................31 4.7.5 10base-t transmitter (informative) .................................................................................31 4.7.6 10base-t receiver ..........................................................................................................31 4.8 isolation tr ansformers .......................................................................................................... .......33 4.9 referencecrystal .........................................................................................................................33 4.9.1 external xtlp oscillator characteristics...........................................................................34 5 package pin d esignati ons ......................................................................................................... .........35 6 package information ............................................................................................................. ...............36 7 ordering info rmation ........................................................................................................... ................36 revision history ................................................................................................................ ...........................37 3 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 figures figure 1: rst pulse duration ....................................................................................................... ....................25 figure 2: transmit inputs to the 78q2123/78q2133 ........................................................................................25 figure 3: receive outputs from the 78q2123/78q2133 .................................................................................2 6 figure 4: mdio as an input to the 78q2123/78q2133 ....................................................................................26 figure 5: mdio as an output to the 78q2123/78q2133............................................................................. 27 figure 6: mdio interface output timing............................................................................................. ......... 28 figure 7: application diagram for 78q2123/78q2133 ................................................................................... ..32 figure 8: external xtlp oscillator characteristics ...................................................................................... 34 figure 9: package pin designations................................................................................................. ................35 4 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 1 functional description 1.1 general 1.1.1 power management the 78q2123 and 78q2133 have three power saving modes: x chip power-down x receive power management x transmit high impedance mode chip power-down is activated by setting the pwrdn bit in mii register mr0.11. when t he chip is in power-down mode, all on-chip circuitry is shut off, and the device consumes minimum pow er. while in the power-down state, the 78q2123/78q2133 still respond to m anagement transactions. receive power management (rxcc mode) is activated by setting the rxcc bit in mii reg ister mr16.0. in this mode of operation, the adaptive equalizer, the clock recovery phase lock loop (p ll), and all other receive circuitry will be powered down when no valid mlt-3 signal is pres ent at the utp receive line interface. as soon as a valid signal is detected, all circuits will automatically be powere d up to resume normal operation. during this mode of operation, rx_clk will be inactiv e when there is no data being received. note that the rxcc mode is not supported during 10 base-t operation. transmit high impedance mode is activated by setting the txhim bit in mii register mr 16.12. in this mode of operation, the transmit utp drivers are in a high impedance state a nd tx_clk is tri-stated. a weak internal pull-up is enabled on tx_clk. the receive circuitry remains fully opera tional. the default state of mr16.12 is a logic low for disabling the transmit high impedance mode. only a reset condition will automatically clear mr16.12. the transmitter is fully functional when mr16.12 is clear ed. this feature is useful when configuring a system for wake-on lan (when the 78q2123/78q2133 a re coupled with a wake-on lan capable mac). 1.1.2 analog biasing and supply regulation the 78q2123/78q2133 require no external component to generate on-chip bias voltages and currents. high accuracy is maintained through a closed-loop trimmed biasing network. on-chip digital logic runs off an internal voltage regulator. hence only a single 3.3v ( r 0.3v) supply is required to power-up the device. the on-chip regulator is not affected by the pow er-down mode. 1.1.3 clock selection the 78q2123/78q2133 have an on-chip crystal oscillator which can also be driven by an ext ernal oscillator. in this mode of operation, a 25 mhz crystal should be connected between the xtlp an d xtln pins. alternatively, an external 25 mhz clock input can be connected to the xtlp pin. in th is mode of operation, a crystal is not required and the xtln pin must be tied to ground. 1.1.4 transmit clock generation the transmitter uses an on-chip frequency synthesizer to generate the transmit clock. in 100base-tx operation, the synthesizer multiplies the reference clock by 5 to obtain the internal 125 mhz seri al transmit clock. in 10base-t mode, it generates an internal 20mhz transmit clock by multiplying the reference 25 mhz clock by 4/5. the synthesizer references either the local 25 mhz crystal oscillator, or the externally applied clock, depending on the selected mode of operation. 5 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 1.1.5 receive signal qualification the integrated signal qualifier has separate squelch and unsquelch thresholds. it also includes a bu ilt-in timer to ensure fast and accurate signal detection and line noise rejection. upo n detection of two or more valid 10base-t or 100base-tx pulses on the line receive port, signal detect is indica ted. the signal detect threshold is then lowered by about 40%. all adaptive circuits are released from their initial states and allowed to lock onto the incoming data. in 100base-tx operation, signal detect is de-asserted whe n no signal is presented for a period of about 1.2 s. in 10base-t operation, signal detect is de-asserted whenever no manchester data is received. in either case, the signal detect threshold will return to the squelched level whenever the signal detect indication is de-asserted. si gnal detect is also used to control the operation of the clock/data recovery circuit to assure fast acquisition. 1.1.6 receive clock recovery in 100base-tx mode, the 125 mhz receive clock is extracted using a digital dll-based loo p. when no receive signal is present, the cdr is directed to lock onto the 1 25 mhz transmit serial clock. when signal detect is asserted, the cdr will use the received mlt-3 signal as the clock reference. the recovered clock is used to re-time the data signal and for conversion of the data to nrz format. in 1 0base-t mode, the 20 mhz receive clock is recovered digitally from the manchester data using a dll locked to the reference clock. when manchester-coded preambles are detected, t he cdr immediately re-aligns the phase of the clock to synchronize with the inco ming data. hence clock acquisition is fast and immediate. 1.2 100base-tx operation 1.2.1 100base-tx transmit the 78q2123/78q2133 contain all of the necessary circuitry to convert the transmi t mii signaling from a mac to an ieee-802.3 compliant data-stream driving cat-5 utp cabling. the internal pcs interface maps 4 bit nibbles from the mii to 5 bit code groups as defined in table 24 -1 of ieee-802.3. these 5 bit code groups are then scrambled and converted to a serial stream before being sent to the mlt-3 pulse shaping circuitry and line driver. the pulse-shaper uses current m odulation to pr oduce the desired output waveform. controlled rise/fall time in the mlt-3 signal is achieved using an accur ately controlled voltage ramp generator. the line driver requires an external 1:1 isolation transformer to in terface with the line media. the center-tap of the primary side of the transformer must be connecte d to the vcc supply (3.3v r 0. 3v). 1.2.2 100base-tx receive the 78q2123/78q2133 receive a 125mbaud mlt-3 signal through a 1:1 transformer. the si gnal then goes through a combination of adaptive offset adjustment (baseline w ander correction) and adaptive equalization. the effect of these circuits is to sense the amount of dispersi on and attenuation caused by the cable and transformer, and restore the received pulses to logic levels. th e amount of gain and equalization applied to the pulses varies with the detected attenuation and dispersion an d, therefore, with the length of the cable. the 78q2123/78q2133 can compensate for cable loss of up to 10db at 16 mhz. this loss is represented as test_chan_5 in annex a of the ansi x3.263:199x. the equalized ml t-3 data signal is bi-directionally sliced and the resulting nrzi bit-stream is presented to the cdr where it is re-timed and decoded to nrz format. the re-timed serial data passes through a seria l-to-parallel converter, then descrambled and aligned into 5 bit code groups. the re ceive pcs interface maps these code groups to 4 bit data for the mii as outlined in table 24-1 in clause 24 of ieee-802.3. 1.2.3 pcs bypass mode (auto-negotiate must be off) the pcs bypass mode is entered by setting register bit mr 16.1. in this mode t he 78q2123/78q2133 accept scrambled 5 bit code words at the tx_er and txd[3:0] pins, tx_er be ing the msb of the data input. the 5 bit code groups are converted to mlt-3 signal for transmis sion. 6 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet the received mlt-3 signal is converted to 5 bit nrz code groups and output from the rx_er and rxd[3:0] pins, rx_er being the msb of the data output. the rx_dv and tx_en pins are unused in pcs bypass mode. 1.3 10base-t operation 1.3.1 10base-t transmit the 78q2123/78q2133 take 4-bit parallel nrz data via the mii interface and passes it through a pa rallel to serial converter. the data is then passed through a manchester encoder, pre- emphasis pulse-shaper, media filter, and finally to the twisted-pair line driver. the pulse-shaper and fi lter ensure the output waveforms meet the voltage template and spectral content requirements detailed in cl ause 14 of ieee-802.3. interface to the twisted-pair media is through a center-tapped 1:1 transfo rmer. no external filtering is required. during auto-negotiation and 10base-t idle periods, link pulses are tr ansmitted. the 78q2123/78q2133 employ an onboard timer to prevent the mac from capturing a netw ork through excessively long transmissions. when this timer expires, the chip enter s the jabber state and transmission is halted. the jabber state is exited after the mii goes idle for 500 r 250 ms. 1.3.2 10base-t receive the 78q2123/78q2133 receive manchester-encoded 10base-t data through the twisted pair inputs a nd re-establishes logic levels through a slicer with a smart squelch function. the slicer automatically adjusts its level after detection of valid data with the appropriate levels. data is passed on to the cdr where the clock is recovered, and the data is re-timed and decoded. from there, data e nters the serial-to-parallel converter for transmission to the mac via the media independent interface. interface t o the twisted-pair media is through an external 1:1 transformer. polarity information is detected and corrected within internal circuitry. 1.3.3 polarity correction the 78q2123/78q2133 are capable of either automatic or manual polarity reversal for 10base-t and auto-negotiation functions. register bits mr16.5 and mr16.4 control this f eature. the default is automatic mode where mr16.5 is low and mr16.4 indicates if the detection circuitry has inv erted the input signal. to enter manual mode, mr16.5 should be set high and mr16.4 will then con trol the si gnal polarity. 1.3.4 sqe test the 78q2123/78q2133 support the signal quality error (sqe) function detailed in ieee-802.3. at an interval of 1 p s after each negative transition of the tx_en pin in 10 base-t mode, the col pin will go high for a period of 1 p s. sqe is not signaled during transmission after collision is detected. sqe is automatically disabled when repeater mode is enabled. this function can be disabled through regi ster bit mr16.11. 1.3.5 natural loopback when enabled, whenever the 78q2123/78q2133 are transmitting and not receivi ng on the twisted pair media (10base-t half duplex mode), data on the txd3-0 pins are lo oped back onto the rxd3-0 pins. during a collision, data from the rxi pins is routed to the rxd3-0 pins. the natural loo pback function is enabled through register bit mr16.10. this feature is off by default. 1.3.6 repeater mode when register bit mr16.15 is set, the 78q2123/78q2133 are placed in repeater mode. in t his m ode, full duplex operation is prohibited, crs responds only to receive activity and, in 10 base-t mode, the sqe test function is disabled. 7 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 1.4 auto-negotiation the 78q2123/78q2133 support the auto-negotiation functions of clause 28 of ieee-802.3 for 10/100 mbps operation over c opper wiring. this function can be enabled via register settings. the auto-negotiation function defaults to on and bit mr0.12 (anegen) is hig h after reset. software can disable the auto-negotiation function by writing to bit mr0.12. the contents of register mr4 are sent to the 78q2123/78q2133s link partner during auto-negotiation via fast link pulse coding. the default values of the auto-negotiation registers are set as follows: register.bits function default value 0.13 speed select 1 (100 base tx) 0.12 an enable 1 (enabled) 0.8 duplex 1 (full duplex) 4.8/1.14 100base-tx full duplex 1 4.7/1.13 100 base-tx 1 4.6/1.12 10 base-t full duplex 1 4.5/1.11 10 base-t 1 these default values can be changed by writing different values to the regist ers, then restarting auto-negotiation. with auto-negotiation enabled, the 78q2123/78q2133 will start sending fast link pulses at pow er on, loss of link or upon a command to restart. at the same time, it will look for either 10base-t id le, 100base-tx idle, or fast link pulses from its link partner. if either idle pattern is detec ted, the 78q2123/78q2133 configure themselves in half-duplex mode at the appropriate speed. if it detects fast link pulses, it decodes and analyzes the link code transmitted by the link partner. whe n three identical link code words are received (ignoring the acknowl edge bit) the link code word is stored in register mr5. upon receiving three more identical link code words, with the acknowledge bit set, the 78q2123/78q2133 configure themselves to the highest priority technology common to the two link partners. the t echnology priorities are, in descending order: 100base-tx, full duplex 100base-tx, half duplex 10base-t, full duplex 10base-t, half duplex once auto-negotiation is complete, register bits mr18.11:10 will refl ect the actual speed and duplex that was chosen. if aut o-negotiation fails to establish a link for any reason, register bit mr18.12 will reflect this and auto negotiation will restart from the beginning. writing a 1 to bit mr0.9 (raneg) will also c ause auto-negotiation to restart. 8 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 1.5 media independent interface 1.5.1 mii transmit and receive operation the mii interface on the 78q2123/78q2133 provide independent transmit and recei ve paths for both 10mb/s and 100mb/s data rates as described in clause 22 of the ieee-802.3 standard. the transmit clock, tx_clk, provides the timing reference for the transfer of tx_e n, txd3-0, and tx_er signals from the mac to the 78q 2123/78q2133. txd3-0 is captured on the rising edge of tx_clk when tx_en is asserted. tx_er is also captured on the rising edge of t x_clk and is asserted by the mac to request that an error code group is to be transmitted. th e assertion of tx_er is ignored when the 78q2123/78q2133 are operating in 10base-t mode. the receive clock, rx_clk, provides the timing reference to transfer rx_ dv, rxd3-0, and rx_er signals from the 78q2123/78q2133 to the mac. rx_dv transitions synchronousl y with respect to rx_clk and is asserted when the 78q2123/78q2133 are presenting valid dat a on rxd3-0. rx_er is asserted and is synchronous to rx_clk when a code group violation has been dete cted in the current receive packet. 1.5.2 station management interface the station management interface consists of circuitry which implements the se rial protocol as described in clause 22.2.4.4 of ieee-802.3. a 16-bit shift register receives seria l data applied to the mdio pin at the rising-edge of the mdc clock signal. once the preamble is received, the station management contr ol logic looks for the start-of-frame sequence and a read or write op-code, follow ed by the phyad and regad fields. the default address for the 78q2123/78q2133 is 1. for a rea d operation, the mdio port becomes enabled as an output and the register data is loaded into a shift register for tr ansmission. the 78q2123/78q2133 can work with a one-bit preamble rather than the 32 bits prescribe d by ieee-802.3. this allows for faster programming of the registers. if a register doe s not exist at an address indicated by the regad field or if the phyad field does not match the 78q2123/78q2133 phyad , a read of the mdio port will return all ones. for a write operation, the data is shifted in a nd loaded into the appropriate register after the sixteenth data bit has been received. writes to reg isters not supported by the 78q2123/78q2133 are ignored. when the phyad field is all zeros, the station management entity (sta) i s requesting a broadcast data transaction. all phys sharing the same management interface must respond to this broadcast request. the 78q2123/78q2133 will respond to the broadcast data transaction. 9 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 1.6 additional features 1.6.1 led indicators there are two led pins that can be used to indicate various states of operation of the 78q2123/78q2133. the function of these pins is programmable via the mr23 register as sh own in the table below: led state indication 0 1 = link ok (default led0) 1 1 = rx or tx activity (default led1) 2 1 = tx activity 3 1 = rx activity 4 1 = collision 5 1 = 100 base-tx mode 6 1 = 10 base-t mode 7 1 = full duplex 8 1= link ok & blink = rx or tx activity the default status of these leds are link ok for led0 and rx or tx activity for led1. 1.6.2 interrupt pin the 78q2123 and 78q2133 have an interrupt pin (intr) that is asserted whenever any of t he eight interrupt bits of mr17.7:0 are set. these interrupt bits can be disabled via the mr17.15:8 i nterrupt enable bits. the interrupt polarity bit, mr16.14, controls the active level of the intr pin . when the intr pin is not asserted, the pin is held in a high impedance state. an external pull-up or pull-down resistor may be required for use with the intr pin. 1.6.3 automatic mdi/ mdi-x configuration the 78q2123 and 78q2133 implement the automatic mdi/mdi-x configurati on detailed in ieee-802.3 2002. this function eliminates the need for cross over cables when connecting to ano ther device. when auto-switching is enabled, the 78q2123/78q2133 will attempt to detect activity on its g iven configuration. if no activity is seen for 60 ms, the device will switch to the other confi guration depending on a random number sequence. the initial seed of the random number generator can be set via mr24.3:0. i n addition, the part includes an asynchronous mdix reset that varies from 1.29 seconds to 1 .57 seconds to ensure lock step will not occur between two devices. the 78q2123 and 78q2133 will also allow for auto-switching while the part is not in auto-negotiation mode. the ieee 802.3 specification will not work in this case if the other device is in auto- negotiation mode. the 78q 2123 and 78q 2133 default to auto mdix enabled with parallel detection. register bits mr24.6 and mr24.7 are both defaulted to 1. the 78q2123 and 78q2133 will resolve the proper configuration within 5 seconds. 10 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 2 pin description 2.1 legend type description type description a analog pin ci ttl-level input ciu ttl-level input with pull-up cio ttl-compatible bi-directional pin cis ttl-level input with schmitt trigger coz tristate-able cmos output co cmos output s supply g ground 2.2 mii (media independent interface) signal pin type description tx_clk 15 coz transmit clock: tx_clk is a continuous clock, which provides a timing reference for the tx_en, tx_er and txd[3:0] signals from the mac. the clock frequency is 25 mhz in 100base-tx mode and 2.5 mhz in 10base-t mode. this pin is tri-stated in isolate mode and the txhim mode. tx_en 16 ci transmit enable: tx_en is asserted by the mac to indicate that valid data for transmission is present on the txd[3:0] pins. txd[3:0] [20:17] ci transmit data: txd[3:0] receives data from the mac for transmission on a nibble basis. this data is captured on the rising edge of tx_clk when tx_en is high. tx_er 14 ci transmit error: tx_er is asserted high by the mac to request that an error code-group be transmitted when tx_en is high. in pcs bypass mode, this pin becomes the msb of the transmit 5-bit code group. crs 22 coz carrier sense: when the 78q2123/78q2133 are not in repeater mode, crs is high w henever a non-idle condition exists on either the transmitter or the receiver. in repeater mode, crs is only active when a non-idle condition exists on the receiver. this pin is tri-stated in isolate mode. col 21 coz collision: col is asserted high when a collision has been detected on the media. in 10base-t mode col is also used for the sqe test function. this pin is tri-stated in isolate mode. during half duplex operation, the rising edge of col will occasi onally occur upon the rising edge of tx_clk. rx_clk 12 coz receive clock: rx_clk is a continuous clock, which provides a timing reference to the mac for the rx_dv, rx_er and rxd[3:0] signa ls. the clock frequency is 25 mhz in 100base-tx mode and 2.5 mhz in 10base-t mode. to reduce power consumption in 100base-tx mode, the 78q2123/78q2133 provide an optional mode, enabled through mr16.0, in which rx_clk is held inactive (low) when no receive data is detected. this pin is tri-stated in isolate mode. rx_dv 11 coz receive data valid: rx_dv is asserted high to indicate that valid data is present on the rxd[3:0] pins. in 100base-tx mode, it transitions high with the first nibble of the preamble and is pulled low when the last data nibble has been received. in 10 base-t mode it transitions high when the start-of-frame delimiter (sfd) is detected. this pin is tri-sta ted in isolate mode. 11 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 rxd[3:0] [5:8] coz receive data: received data is provided to the mac via rxd[3:0]. these pins are tri-stated in isolate mode. rx_er 13 coz receive error: rx_er is asserted high when an error is detected during frame reception. in pcs bypass mode, this pin becomes the msb of the receive 5-bit code group. this pin is tri-stated in isolate mode. mdc 2 cis management data clock: mdc is the clock used for transferring data via the mdio pin. mdio 1 cio management data input/output: mdio is a bi-directional port used to access management registers within the 78q2123/78q2133. this pin requires an external pull-up resistor as specified in ieee-802.3. 2.3 control and status signal pin type description rst 23 cis active low reset: when pulled low the pin resets the chip. the reset pulse must be long enough to guarantee stabilization of the supply voltage and startup of the oscillator. refer to the electrical specifications for the reset pulse requirements. there are two other ways to reset t he chip: 1. through the internal power-on-reset (activated when the chip is being powered up). 2. through the mii register bit (mr 0.15). intr 32 coz interrupt pin: this pin is used to signal an interrupt to the media access controller. the pin is held in the high impedance state when an interrupt is not indicated. the pin will be forced high or low to signal an interrupt depending upon the value of the inpol bit (mr16.14). the events which trigger an interrupt can be programmed via the interrupt control register located at address mr17. 2.4 mdi (media dependent interface) signal pin type description txop, txon 30,31 a transmit output positive/negative: transmitter differential outputs for both 10base-t and 100base-tx. rxip, rxin 28,27 a receive input positive/negative: receiver differential inputs for both 10base-t and 100base-tx. 2.5 oscillator/clock signal pin type description xtlp 24 a crystal input: should be connected to a 25 mhz crystal. if an externally generated ttl compatibility clock signal is used, that signal is applied here. xtln 25 a crystal output: should be connected to a 25 mhz crystal. when an external clock source is being used, this pin must be grounded. 2.6 power supply and ground signal pin type description pw r 9, 26 s +3.3vdc supply gnd 10, 29 g ground 12 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 2.7 led signals (programmability is secondary requirement) signal pin type description led0 4 co programmable led. active low. default status: link ok. active to indicate link with far end phy. led1 3 co programmable led. active low. default status: rx or tx activity. active to indicate tx or rx activity on the mdi. other led options selectable via mr23: transmit: on when there is a transmission (normally off). receive: on when there is a reception (normally off). collision: in half duplex mode, this is a collision indicator and turns-on when a collision occurs. in full duplex mode, this led is held off. base-tx: on for 100base-tx connection and off for other connections. ledbtx is off during auto-negotiation. base-t: on for 10base-t connection and off for other connections. ledbt is off during auto-negotiation. full duplex: on when in full duplex mode and off when in half duplex mode. link/act: on for link, blink for activity. 13 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 3 register description the 78q2123/78q2133 implement 13 16-bit registers, which are accessible via the mdio and mdc pins. the supported registers are shown below in the following table. attempts to read unsupp orted registers will be ignored and the mdio pin will not be enabled as an output, as per the i eee 802.3 specification. all of the registers except those that are unique to the 78q2123/78q2133 will respond to the broadcast phyad value of 00000. the registers specific to the 78q2123/78q2133 occu py address space mr16-24. address symbol name default (hex) 0 mr0 control (3100) 1 mr1 status (7849) 2 mr2 phy identifier 1 000e 3 mr3 phy identifier 2 7237 4 mr4 auto-negotiation advertisement (01e1) 5 mr5 auto-negotiation link partner ability 0000 6 mr6 auto-negotiation expansion 0000 7 mr7 not implemented 0000 8-14 mr8-14 reserved 0000 15 mr15 not implemented 0000 16 mr16 vendor specific (0140) 17 mr17 interrupt control/status register 0000 18 mr18 diagnostic register 0000 19 mr19 transceiver control 4xxx 20-22 mr20-22 reserved 0000 23 mr23 led configuration register 0010 24 mr24 mdi/mdix control register (00c0) legend type description type description r readable by management. w writeable by management. wc writeable by management. self clearing. rc readable by management. cleared upon a read operation. 0/1 default value upon power up or reset. 14 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 3.1 mr0: control register bit symbol type default description 0.15 reset r/wc 0 reset: setting this bit to 1 resets the device and sets all registers to their default states. this bit is self-clearing. 0.14 loopbk r/w 0 loopback: when this bit is set to 1, input data at txd[3:0] is output at rxd[3:0]. no transmission of data on the network medium occurs and receive data on the network medium is ignored. by default, the loopback signal path encompasses most of the digital functional blocks. this bit allows for diagnostic testing. 0.13 speedsl r/w 1 speed selection: this bit determines the s peed of operation of the 78q2123/78q2133. setting this bit to 1 indicates 100base-tx operation and a 0 indicates 10base-t mode. this bit will default to a 1 upon reset. when auto-negotiation is enabled, this bit will not be writable and will have no effect on the 78q2123/78q2133. if auto-negotiation is not enabled, this bit may be written to force manual configuration. 0.12 anegen r/w 1 auto-negotiation enable: the auto-negotiation process is enabled by setting this bit to 1. this bit will default to 1. if this bit is cleared to 0, manual speed and duplex mode selection is accomplished through bits 0.13 ( speedsl ) and 0.8 ( duplex ) of the control register. 0.11 pwrdn r/w 0 power-down: the device may be placed in a low power consumption state by setting this bit to 1. while in the power- down state, the device will still respond to management transactions. 0.10 iso r/w 0 isolate: when set to 1, the device will present a high- impedance on its mii output pins. this allows for multiple phys to be attached to the same mii interface. when the device is isolated, it still responds to man agement transactions. 0.9 raneg r/wc 0 restart auto-negotiation: normally, the auto-negotiation process is started at power up. the process can be restarted by setting this bit to 1. this bit is self-clearing. 0.8 duplex r/w 1 duplex mode: this bit determines whether the device supports full- duplex or half-duplex. a 1 indicates full-duplex operation and a 0 indicates half-duplex. this bit will default to 1 upon reset. when auto-negotiation is enabled, this bit will not be writable and will have no effect on the 78q2123/78q2133. if auto-negotiation is not enabled, this bit may be written to force manual configuration. 0.7 colt r/w 0 collision test: when this bit is set to 1, the device will assert the col signal in response to the assertion of the tx_en signal. co llision test is disabled if the pcsbp bit, mr16.1, is high. collision test can be activated regardless of the duplex mode of operation. 0.6:0 rsvd r 0 reserved 15 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 3.2 mr1: status register bits 1.15 through 1.11 reflect the ability of the 78q2123/78q2133. they do not reflect any ability changes made via the mii management interface to bits 0.13 ( speedsl ) , 0.12 ( anegen ) and 0.8 ( duplex )in the control register. bit symbol type default description 1.15 100t4 r 0 100base-t4 ability: reads 0 to indicate the 78q2123/78q2133 do not support 100base-t4 mode. 1.14 100x_f r 1 100base-tx full duplex ability: 0 : not able 1 : able 1.13 100x_h r 1 100base-tx half duplex ability: 0 : not able 1 : able 1.12 10t_f r 1 10base-t full duplex ability: 0 : not able 1 : able 1.11 10t_h r 1 10base-t half duplex ability: 0 : not able 1 : able 1.10 100t2_f r 0 100base-t2 full duplex ability: reads 0 to indicate the 78q2123/78q2133 do not support 100base-t2 full duplex mode. 1.9 100t2_h r 0 100base-t2 half duplex ability: reads 0 to indicate the 78q2123/78q2133 do not support 100base-t2 full duplex mode. 1.8 exts r 0 extended status information availability: reads 0 to indicate the 78q2123/78q2133 do not support extended status information on mr15. 1.7 rsvd r 0 reserved 1.6 mfps r 0 management frame preamble suppression support: a 0 indicates that the 78q2123/78q2133 can read management frames with a preamble. 1.5 anegc r 0 auto-negotiation complete: a logic one indicates that the auto-negotiation process has been completed, and that the contents of registers mr4,5,6 are valid. 1.4 rfault rc 0 remote fault: a logic one indicates that a remote fault condition has been detected and it remains set until it is cleared. this bit can only be cleared by reading this register (mr1) via the management interface. 1.3 anega r (1) auto-negotiation ability: when set, this bit indicates the devices ability to perform auto-negotiation. the value of this bit is determined by the anegen bit (mr0.12). 1.2 link r 0 link status: a logic one indicates that a valid link has been established. if the link status should transition from an ok status to a not-ok status, this bit will become cleared and remains cleared until it is read. 1.1 jab rc 0 jabber detect: in 10base-t mode, this bit is set during a jabber event. after a jabber event, the bit remains set until 16 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet cleared by a read operation. 1.0 extd r 1 extended capability: reads 1 to indicate the 78q2123/78q2133 provide an extended register set (mr2 and beyond). 3.3 mr2: phy identifier register 1 bit symbol type value description 2.15:0 oui [23:6] r 000eh organizationally unique identifier: this value is 00-c0-39 for teridian semiconductor corporation. this register contains the first 16-bits of the identifier. 3.4 mr3: phy identifier register 2 bit symbol type value description 3.15:10 oui [5:0] r 1ch organizationally unique identifier: remaining 6 bits of the oui. 3.9:4 mn r 23h model number: the last 2 digits of the model number 78q2123 are encoded into the 6 bits for both 78q2123 and 78q2133. 3.3:0 rn r 07h revision number: the value 0111 corresponds to the seventh revision of the silicon. 3.5 mr4: auto-negotiation advertisement register bit symbol type default description 4.15 np r 0 next page: not supported. reads logic zero. 4.14 rsvd r 0 reserved 4.13 rf r/w 0 remote fault: setting this bit to 1 allows the device to indicate to the link partner a remote fault condition. 4.12 a7 r 0 reserved. 4.11 a6 r/w 0 asymmetric pause support indication for full duplex links. default is 0 indicating not supported. if the mac supports asymmetric pause, this bit can be written as 1. writing to this register has no effect until auto-negotiation is re-initiated. 4.10 a5 r 0 pause support indication for full duplex links. default is 0 indicating not supported. if the mac supports pause, this bit can be written as 1. writing to this register has no effect until auto-negotiation is re-initiated 4.9 a4 r 0 100base-t4: the 78q2123/78q2133 do not su pport 100base-t4 operation. 4.8 a3 r/w (1) 100base-tx full duplex: if the mr1.14 bit is 1, this bit will be set to 1 upon reset and will be writeable. otherwise, this bit cannot be set to 1 by the management. 4.7 a2 r/w (1) 100base-tx: if the mr1.13 bit is 1, this bit will be set to 1 upon reset and will be writeable. otherwise, this bit cannot be set to 1 by the management. 4.6 a1 r/w (1) 10base-t full duplex: if the mr1.12 bit is 1, this bit will be set to 1 upon reset and will be writeable. otherwise, this bit cannot be set to 1 by the management. 17 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 4.5 a0 r/w (1) 10base-t: if the mr1.11 bit is 1, this bit will be set t o 1 upon reset and will be writeable. otherwise, this bit cannot be set to 1 by the management. 4.4:0 s4:0 r 01h selector field: hard coded with the value of 00001 for ieee 802.3. note: technology ability field: mr4.12:5 are the technology ability field bits (a7:0). th e default value of this field is dependent upon the mr1.15:11 register bits. this field can be ove rwritten by management to auto-negotiate to an alternate common technology. writing to this register has no effect until auto-negotiation is re-initiated. 3.6 mr5: auto-negotiation link partner ability register bit symbol type default description 5.15 np r 0 next page: when 1 is read, it indicates the link partner wishes to engage in next page exc hange. 5.14 ack r 0 acknowledge: when 1 is read, it indicates the link partner has successfully received at least 3 consecutive and consistent flp bursts. 5.13 rf r 0 remote fault: when 1 is read, it indicates the link partner has a fault. 5.12:5 a7:0 r 0 technology ability field: this field contains the technology ability of the link partner. the bit definition is the same as mr4.12:5. 5.4:0 s4:0 r 00h selector field: this field contains the type of message sent by the link partner. for an ieee 802.3 compliant link partner, this field should be 00001. 3.7 mr6: auto-negotiation expansion register bit symbol type default description 6.15:5 rsvd r 0 reserved 6.4 pdf rc 0 parallel detection fault: when 1 is read, it indicates that more than one technology has been detected during link up. this bit is cleared when read. 6.3 lpnpa r 0 link partner next page able: when 1 is read, it indicates the link partner supports the next page function. 6.2 npa r 0 next page able: reads 0 since the 78q2123/78q2133 do not support next page function. 6.1 prx rc 0 page received: reads 1 when a new link code word has been received into the auto-negotiation link partner ability register. this bit is cleared upon read. 6.0 lpanega r 0 link partner auto-negotiation able: when 1 is read, it indicates the link partner is able to participate in the auto- negotiation function. 3.8 mr16: vendor specific register bit symbol type default description 16.15 rptr r/w (0) repeater mode: when set, the 78q2123/78q2133 are put into repeater mode of operation. in this m ode, full duplex is 18 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet prohibited, crs responds to receive activity only and, in 10base-t mode, the sqe test function is disabled. 16.14 inpol r/w 0 when this bit is 0, the intr pin is forced low to signal an interrupt. setting this bit to 1 causes the intr pin to be forced high to signal an interrupt. 16.13 rsvd r 0 reserved 16.12 txhim r/w 0 transmitter high-impedance mode: when set, the txop/txon transmit pins and the tx_clk pin are put into a high-impedance state. the receive circuitry remains fully functional. 16.11 sqei r/w 0 sqe test inhibit: setting this bit to 1 disables 10base-t sqe testing. by default, this bit is 0 and the sqe test is performed by generating a col pulse following the completion of a packet transmission. 16.10 nl10 r/w 0 10base-t natural loopback: setting this bit to 1 causes transmit data received on the txd0-3 pins to be automatically looped back to the rxd0-3 pins when 10base-t mode is enabled. 16.9 rsvd r 0 reserved 16.8 rsvd r 1 reserved 16.7 rsvd r 0 reserved 16.6 rsvd r 1 reserved 16.5 apol r/w 0 auto polarity: during auto-negotiation and 10base-t mode, the 78q2123/78q2133 are able to automatically invert the received signal due to a wrong polarity connection. it does so by detecting the polarity of the link pulses. setting this bit to 1 disables this feature. 16.4 rvspol r/w 0 reverse polarity: the reverse polarity is detected either through 8 inverted 10base-t link pulses (nlp) or through one burst of inverted clock pulses in the auto-negotiation link pulses (flp). when the reverse polarity is detected and if the auto polarity feature is enabled, the 78q2123/78q2133 will invert the receive data input and set this bit to 1. if auto polarity is disabled, then this bit is writeable. writing a 1 to this bit forces the polarity of the receive signal to be reversed. 16.3:2 rsvd r/w 0h reserved: must set to 00. 16.1 pcsbp r/w 0 pcs bypass mode: when set, the 100base-tx pcs and scrambling/ descrambling functions are bypassed. scrambled 5-bit code groups for transmission are applied to the tx_er, txd3-0 pins and received on the rx_er, rxd3-0 pins. the rx_dv and tx_en signals are not valid in this mode. pcsbp mode is valid only when 100base-tx mode is enabled and auto-negotiation is disabled. 16.0 rxcc r/w 0 receive clock control: this function is valid only in 100base- tx mode. when set to 1, the rx_clk signal will be held low when there is no data being received (to save power). the rx_clk signal will restart 1 clock cycle before the assertion of rx_dv and will be shut off 64 clock cycles after rx_dv goes low. rxcc is disabled when loopback mode is enabled (mr0.14 is high). this bit should be kept at logic zero when pcs bypass mode is used. 19 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 3.9 mr17: interrupt control/status register the interrupt control/status register provides the means for controlling and observing the events, which trigger an interrupt on the intr pin. this register can also be used in a polling mode via the mii serial interface as a means to observe key events within the phy via one register address. bits 0 through 7 are status bits, which are each set to logic one based upon an event. these bits are cleare d after the register is read. bits 8 thr ough 15 of this register, when set to logic one, enable their corresponding bit in the lower byte to signal an interrupt on the intr pin. the assertion level of this interrupt signal output on the intr pin can be set via the mr16.14 ( inpol ) bit. bit symbol type default description 17.15 jabber_ie r/w 0 jabber interrupt enable 17.14 rxer_ie r/w 0 receive error interrupt enable 17.13 prx_ie r/w 0 page received interrupt enable 17.12 pdf_ie r/w 0 parallel detect fault interrupt enable 17.11 lp-ack_ie r/w 0 link partner acknowledge interrupt enable 17.10 ls-chg_ie r/w 0 link status change interrupt enable 17.9 rfault_ie r/w 0 remote fault interrupt enable 17.8 aneg- comp_ie r/w 0 auto-negotiation complete interrupt enable 17.7 jab_int rc 0 jabber interrupt: this bit is set high when a j abber event is detected by the 10base-t circuitry. 17.6 rxer_int rc 0 receive error interrupt: this bit is set high when the rx_er signal transitions high. 17.5 prx_int rc 0 page received interrupt: this bit is set high when a new page has been received from the link partner during auto-negotiation. 17.4 pdf_int rc 0 parallel detect fault interrupt: this bit is set high by the auto-negotiation logic when a parallel detect fault condition is indicated. 17.3 lp-ack_int rc 0 link partner acknowledge interrupt: this bit is set high by the auto-negotiation logic when flp bursts are received with the acknowledge bit set. 17.2 ls-chg_int rc 0 link status change interrupt: this bit is set when the link transitions from an ok status to a fail status. 17.1 rfault_int rc 0 remote fault interrupt: this bit is set when a remote fault condition has been indicated by the link partner. 17.0 aneg- comp_int rc 0 auto-negotiation complete interrupt: this bit is set by the auto-negotiation logic upon successful completion of auto-negotiation. 20 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 3.10 mr18: diagnostic register bit symbol type default description 18.15:13 rsvd r 0 reserved 18.12 anegf rc 0 auto-negotiation fail indication: this bit is set when auto-negotiation completes and no common technology was found. it remains set until read. 18.11 dplx r 0 duplex indication: this bit indicates the result of the auto-negotiation for duplex arbitration as follows: 0 = half-duplex was the highest common denominator 1 = full-duplex was the highest common denominator 18.10 rate r 0 rate indication: this bit indicates the result of the auto- negotiation for data rate arbitration as follows: 0 = 10base-t was the highest common denominator 1 = 100base-tx was the highest common denominator 18.9 rxsd r 0 receiver signal detect indication: in 10base-t mode, this bit indicates that manchester data has been detected. in 100base-tx mode, it indicates that the receive signal activity has been detected (but not necessarily locked on to). 18.8 rx_lock r 0 receive pll lock indication: indicates that the receive pll has locked onto the receive signal for the selected speed of operation (10base-t or 100base-tx). 18.7:0 rsvd r 00h reserved: must set to 00h. 3.11 mr19: transceiver control bit symbol type default description 19.15:14 txo[1:0] r/w 01 transmit amplitude selection: sets the transmit output amplitude to account for transmit transformer insertion loss. 00 = gain set for 0.0db of insertion loss. 01 = gain set for 0.4db of insertion loss. 10 = gain set for 0.8db of insertion loss. 11 = gain set for 1.2db of insertion loss. 19.13:0 rsvd r xxxh reserved 3.12 mr20: reserved bit symbol type default description 20.15:0 reserved na xxxxh reserved: must be 0000h. 3.13 mr21: reserved bit symbol type default description 21.15:0 reserved na xxxxh reserved: must be 0000h. 3.14 mr22: reserved bit symbol type default description 22.15:0 reserved na xxxxh reserved: must be 0000h. 21 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 3.15 mr23: led configuration register bit symbol type default description 23.15:8 reserved na <0000> must set to zero on each write to mr23 23.7:4 led1[3:0] r/w <1h> 0000 = link ok 0001 = rx or tx activity (default led1) 0010 = tx activity 0011 = rx activity 0100 = collision 0101 = 100 base-tx mode 0110 = 10 base-t mode 0111 = full duplex 1000 = link ok/blink=rx or tx activity 23.3:0 led0[3:0] r/w <0h> 0000 = link ok (default led0) 0001 = rx or tx activity 0010 = tx activity 0011 = rx activity 0100 = collision 0101 = 100 base-tx mode 0110 = 10 base-t mode 0111 = full duplex 1000 = link ok/blink=rx or tx activity 3.16 mr24: mdi/mdix control register bit symbol type default description 24.15:8 reserved r 0 reserved 24.7 pd_mode r/w 1 write a 1 to this bit to add parallel detect mode. this will allow auto-switching to work when auto-negotiation is off while the other device has it on. 24.6 auto_sw r/w 1 write a 1 to this bit to enable auto switching. 24.5 mdix r/w 0 indicates state of the mdi pair or force configuration: 1 = mdix (cross over) 0 = mdi when auto_sw is a 1, this bit will only be readable. when auto_sw is a 0 this bit can be written to set the configuration. 24.4 mdix_cm r 0 indicates completion of auto-switch sequence. 1 = sequence completed. 0 = sequence in progress or auto-switch is disabled. 24.3:0 mdix_sd r/w <0000> write initial pattern seed for switching algorit hm. the initial seed directly affects attempts [5,4] respectively to write bits [3:0]. setting to [0000] will result in device using its own seed of [0101]. 22 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4 electrical specifications 4.1 absolute maximum ratings operation above maximum rating may perm anently damage the device. parameter rating dc supply voltage (vcc) -0.5 to 4.0 vdc storage temperature -65 to 150 q c pin voltage (except txop/n) -0.3 to (vcc+0.6) vdc pin voltage (txop/n only) -0.3 to (vcc+1.4) vdc pin current r 120 ma 4.2 recommended operating conditions unless otherwise noted, all specifications are valid over these temperatures and supply vol tage ranges. parameter rating dc voltage supply (vcc) 3.3 r 0.3 vdc 78q2123 ambient operating temperature (ta) 0 to 70 q c 78q2133 ambient operating temperature (ta) -40 to 85 q c maximum junction temperature 125 q c package thermal conductivity ( t ja) 50 q c/w 4.3 dccharacteristics parameter symbol conditions min nom max unit supply current i cc vcc = 3.3v; auto-negotiation 10bt (idle) 10bt (normal activity) 100btx 4826 88 88 5635 110110 ma supply current i cc power-down mode 6 ma 23 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 4.4 digital i/o characteristics pins of type ci, ciu, cid, cio parameter symbol conditions min nom max unit input voltage low vil 0.8 v input voltage high vih 2.0 3.6 v input current iil, iih -1 1 p a pull-up resistance rpu type ciu only 38 56 78 k : input capacitance cin 8 pf pins of type cis parameter symbol conditions min nom max unit low-to-high threshold vt+ 2.0 v high-to-low threshold vt- 0.8 v input current iil, iih -1 1 p a input capacitance cin 8 pf input hysteresis vhy 125 mv pins of type coz parameter symbol conditions min nom max unit output voltage low vol iol = 4ma 0.4 v output voltage high voh ioh = -4ma 2.4 v output transition time tt cl = 20pf 6 ns tristate output leakage current iz -1 1 p a pins of type co parameter symbol conditions min nom max unit output voltage low vol iol = 4ma 0.4 v output voltage high voh ioh = -4ma 2.4 v output transition time tt cl = 20pf 6 ns pins of type cio parameter symbol conditions min nom max unit output voltage low vol iol = 4ma 0.4 v output voltage high voh ioh = -4ma 2.4 v output transition time tt cl = 20pf 6 ns 24 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4.5 digital timing characteristics 4.5.1 rst characteristics figure 1: rst pulse duration parameter symbol conditions min nom max unit r pulse assertion treset vcc = 3.3v and oscillator stabilized 30 oscillator clock cycles 4.5.2 mii transmit interface characteristics symbol conditions min nom max unit setup time: tx_clk to txd[3:0], tx_en, tx_er tx su 15 ns hold time: tx_clk to txd[3:0], tx_en, tx_er tx hd 0 ns ckin-to-tx_clk delay t ckin 0 40 ns tx_clk duty-cycle 40 60 % figure 2: transmit inputs to the 78q2123/78q2133 vcc oscillator r t reset 25 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 4.5.3 mii receive interface characteristics symbol conditions min nom max unit receive output delay: rx_clk to rxd[3:0], rx_dv, rx_er rx dly 10 30 ns rx_clk duty-cycle 40 60 % figure 3: receive outputs from the 78q2123/78q2133 4.6 mdio interface input timing characteristics symbol conditions min nom max unit setup time: mdc to mdio mio su 10 ns hold time: mdc to mdio mio hd 10 ns max frequency: mdc f max 25 mhz figure 4: mdio as an input to the 78q2123/78q2133 26 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4.6.1 mdio interface output timing characteristics symbol conditions min nom max unit mdc to mdio data delay mc2d 30 ns mdio output from high z to driven after mdc mcz2d 30 ns mdio output from driven to high z after mdc mcd2z 30 ns figure 5: mdio as an output to the 78q2123/78q2133 27 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 4.6.2 mdio interface output timing figure 6: mdio interface output timing 28 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4.6.3 100base-tx system timing system timing requirements for 100base-tx operation are listed in table 24-2 of clause 24 of ieee 802.3. parameter condition nom unit tx_en sampled to first bit of j on mdi output 12 bt first bit of j on mdi input to crs assert 16 bt first bit of t on mdi input to crs de-assert 23 bt first bit of j on mdi input to col assert 20 bt first bit of t on mdi input to col de-assert 24 bt tx_en sampled to crs assert rptr = low 6 bt tx_en sampled to crs de-assert rptr = low 6 bt 4.6.4 10base-t system timing parameter condition min nom max unit tx_en (mii) to td delay 6 bt rd to rxd at (mii) delay 6 bt collision delay 9 bt sqe test wait 1 p s sqe test duration 1 p s jabber on-time* 20 150 ms jabber off-time* 250 750 ms * guarantee by design. the specifications in the following table are included fo r information only. 29 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 4.7 analog electrical characteristics 4.7.1 100base-tx transmitter parameter condition min nom max unit peak output amplitude (|vp+|, |vp-|) (see note below) best-fit over 14 bit times; 0.4 db transformer loss 950 1050 mvpk output amplitude symmetry | vp +| | vp -| 0.98 1.02 output overshoot percent of vp+, vp- 5 % rise/fall time (tr, tf) 10-90% of vp+, vp- 3 5 ns rise/fall time imbalance | tr - tf | 500 ps duty cycle distortion deviation from best-fit time- grid; 010101... sequence r 250 ps jitter scrambled idle 1.4 ns note: measured at the line side of the transformer. test condition: transformer p/n: tla-6t103 line termination: 100 : 1% 4.7.2 100base-tx transmitter (informative) the specifications in the following table are included for information only. th ey are mainly a function of the external transformer and termination resistors used for measurements. parameter condition min max unit return loss 2 < f < 30 mhz 30 < f < 60 mhz 60 < f < 80 mhz 16 16 20 log f ? ? 30 mhz 1 10 db open-circuit inductance -8 < iin < 8 ma 350 p h 4.7.3 100base-tx receiver parameter condition min nom max unit signal detect assertion threshold 500 600 700 mvppd signal detect de-assertion threshold 275 350 425 mvppd differential input resistance 20 k : jitter tolerance (pk-pk) not tested in production 4 ns baseline wander tracking -75 +75 % signal detect assertion time not tested 1000 p s signal detect de-assertion time not tested 4 p s 30 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4.7.4 10base-t transmitter the manchester-encoded data pulses, the link pulse and the start-of-idle p ulse are tested against the templates and using the procedures f ound in clause 14 of ieee 802.3. parameter condition min nom max unit peak differential output signal (see note below) all data patterns 2.2 2.8 v harmonic content (db below fundamental) any harmonic all ones data not tested 27 db link pulse width 100 ns start-of-idle pulse width last bit 0 last bit 1 300350 ns ns note: measured at the line side of the transformer. test condition: transformer p/n: tla-6t103 line termination: 100 : 1% 4.7.5 10base-t transmitter (informative) the specifications in the following table are included for information only. th ey are mainly a function of the external transformer and termination resistors used for measurements. parameter condition min nom max unit output return loss 15 db output impedance balance 1 mhz < freq < 20 mhz 29 17log f ? ? 10 1 db peak common-mode output voltage 50 mv common-mode rejection 15 v pk , 10.1 mhz sine wave applied to transmitter common-mode. all data sequences. 100 mv common-mode rejection jitter 15 v pk , 10.1 mhz sine wave applied to transmitter common-mode. all data sequences. 1n s 4.7.6 10base-t receiver parameter condition min nom max unit dll phase acquisition time 10 bt jitter tolerance (pk-pk) 30 ns input squelched threshold 500 600 700 mvppd input unsquelched threshold 275 350 425 mvppd differential input resistance 20 k : bit error ratio 10 -10 common-mode rejection square wave 0 < f < 500 khz not tested 25 v 31 downloaded from: http:///
ccd dd v 87 6 5 4 3 2 1 15 28 78q2123/78q2133 data sheet ds_21x3_001 r4 100 r5 100 vcc r2 5.1k led 1 d1 led 0 d2 vcc r1 680 r3 680 vcc intr c1 0.1uf r8 49.9 r9 49.9 vcc r6 r7 c5 c2 vcc j1 mdio mdc rxd3 rxd2 rxd1 rxd0 rxdv r11 100 0.1uf r10 100 9 10 v 11 gn rx_d 78q2123 78q2133 33 pb_gnd 32 intr 31 txon 30 txop 0.01uf t1 1 2 td+ tdct 0.1uf 16 tx+ 15 txct rj45 87 6 rxclk rxer txer txclk txen txd0 txd1 r12 r13 12 rx_clk 13 rx_er 14 tx_er 16 tx_clk tx_en 78q2123 gnd 29 rxip 27 rxin 26 vcc 25 xtln 34 td- 5 nc1 6 nc2 7 rd+ 8 rdct rd- 14 5 tx- 13 4 nc4 12 3 nc3 11 2 rx+ 10 1 rxct 9 rx- txd2 txd3 col crs 100 100 y1 25.000mhz tla-6t118lf vcc r14 r15 c11 c12 r16 r17 r18 r19 r20 r21 c10 c13 c14 49.9 49.9 0.01uf 0.1uf 75 75 75 75 75 75 0.1uf 1.5kv r22 100 r23 100 vcc r24 10k c15 0.1uf 27pf 27pf c13 and c14 must be calibrated in actual application board f or 25.000mhz +/-50ppm. figure 7: application diagram for 78q2123/78q2133 32 rev. 1.6 1718 19 20 21 22 23 24 txd0txd1 txd2 txd3 col crs rst xtlp rxd0rxd1 rxd2 rxd3 led0 led1 mdc mdio 10 9 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 4.8 isolation transformers two simple 1:1 isolation transformers are required at the line interface. transf ormers with integrated common-mode chokes are recommended for exc eeding fcc requirements. this table gives the recommended line transformer characteristics. name value condition turns ratio 1 ct : 1 ct r 5% open-circuit inductance 350 p h (min) @ 10 mv, 10 khz leakage i nductance 0.40 p h (max) @ 1 mhz (min) inter-winding capacitance 25 pf (max) d.c. resistance 0.9 : (max) insertion loss 0.4 db (typ) 0 - 65 mhz hipot 1500 vrms note: the 100base-tx amplitude specifications assume a transformer loss of 0.4 d b. for the transmit line transformer with higher insertion losses, up to 1.2 db of insertion loss can b e compensated by selecting the appropriate setting in the transmit amplitude selection bi ts in register mr19.15:14. 4.9 reference crystal if the internal crystal oscillator is to be used, a crystal with the following characteristics should be chosen. name value units frequency 25.00000 mhz load capacitance* 4** pf frequency tolerance r 50 ppm aging r 2 ppm/yr temperature stability ( 0 - 70 o c) r 5 ppm oscillation mode parallel resonance, fundamental mode parameters at 25 o c r 2 o c ; drive level = 0.5 mw drive level (typ) 50-100 p w shunt capacitance (max) 10 pf motional capacitance (min) 10 pf series resistance (max) 60 : spurious response (max) > 5 db below main within 500 khz * equivalent differential capacitance across the xtlp/xtln pins. ** if crystal with a larger load is used, external shunt capacito rs to ground should be a dded to make up the equivalent capacitance difference. 33 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 t f t clkper t clkhi figure 8: external xtlp oscillator characteristics 4.9.1 external xtlp oscillator characteristics parameter symbol condition min nom max unit xtlp input level see specification for cis-type input xtln input low voltage 0.8 v xtlp frequency f see note 1 25.000 mhz xtlp period tclkper see note 1 40 ns xtlp duty cycle tclkhi / tclkper 40 60 % rise / fall time tr, tf 4.0 ns absolute jitter input signaling requirements = cis 0.1 ns note 1: ieee 802.3 frequency tolerance r 50 ppm. t r xtlp 34 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet 5 package pin designations (top view) mdio mdc ed 1 ed 0 rxd3 rxd2 rxd1 rxd0 xtlp rst crs col txd3 txd2 txd1 txd0 note: for information only, actual package outline will vary depending on package type. figure 9: package pin designations 1 24 2 233 22 4 teridian 21 78q2123 5 20 78q2133 6 19 7 18 8 17 pwr 93 2 i n t r gnd 10 31 txon rx_dv 11 30 txop rx_clk 12 29 gnd rx_er 13 28 rxip tx_er 14 27 rxin tx_clk 15 26 pwr 16 tx_en 25 xtln 35 downloaded from: http:///
78q2123/78q2133 data sheet ds_21x3_001 6 package information package type package code outline no. land pattern no. 32-qfn g3255+3 21-0697 90-0434 32-tqfn t3255+4 21-0140 90-0012 7 ordering information part package option ordering number ic marking 78q2123, lead-free, commercial temp 32-qfn bulk 78q2123/f tape & reel 78q2123r/f 32-tqfn bulk 78q2123s/f tape & reel 78q2123sr/f 78q2133, lead-free, industrial temp 32-qfn bulk 78q2133/f tape & reel 78q2133r/f 32-tqfn bulk 78q2133s/f tape & reel 78q2133sr/f yy: last two digits of year of assembly ww: week of assembly rrrr:die rev code from reliability database ###: will be substituted with the last 3 numeric characters from the lot number @@: will be substituted with the first two alpha characters after the numeric characters from the lot number 36 downloaded from: http:///
ds_21x3_001 78q2123/78q2133 data sheet revision history rev. # date comments 1.0 9/15/2005 first publication. 1.6 4/16/2010 removed the 32-pin tqfp option. 2.0 9/24/2014 added 32-tqfn package. maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integr ated product. no circuit patent licenses duhlpsolhg0d[lp,qwhjudwhguhvhuyhvwkhuljkwwrfkdqjhwkhflufxlwu\dqgvshfl?fdwlrqvzlwkrxwq rwlfhdwdq\wlph7khsdudphwulfydoxhvplqdqgpd[olplwv vkrzqlqwkh(ohfwulfdo&kdudfwhulvwlfvwdeohduhjxdudqwhhg other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2014 maxim integrated products, inc. g for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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