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quad-channel isolators with integrated dc-to-dc converters data sheet adum5410 / adum5411 / adum5412 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2016 analog devices, inc. all rights reserved. technical support www.analog.com features iso power integrated, isolated dc-to-dc converter up to 150 mw output power quad dc to 150 mbps signal isolation channels 24-lead ssop package with 5.3 mm minimum creepage high temperature operation: 105c high common-mode transient immunity: 100 kv/s safety and regulatory approvals ul recognition (pending) 2500 v rms for 1 minute per ul 1577 csa component acceptance notice 5a (pending) vde certificate of conformity (pending) din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 565 v peak applications rs-232 transceivers power supply startup bias and gate drives isolated sensor interfaces industrial plcs general description the adum5410 / adum5411/ adum5412 1 are quad-channel digital isolators with iso power?, integrated, isolated dc-to-dc converters. based on the analog devices, inc., i coupler? technology, the dc-to-dc converters provide regulated, isolated power that is adjustable between 3.15 v and 5.25 v. popular voltage combinations and the associated power levels are shown in table 1. the adum5410 / adum5411/ adum5412 eliminate the need for a separate, isolated dc-to-dc converter in low power, isolated designs. the i coupler chip scale transformer technology is used for isolated logic signals and for the magnetic components of the dc-to-dc converters. the result is a small form factor, total isolation solution. the adum5410 / adum5411/ adum5412 isolators provide four independent isolation channels in a variety of channel configura- tions and data rates (see the ordering guide for more information). functional block diagram gnd 1 i/o 1b i/o 1a v dd1 i/o 1c i/o 2b i/o 2a i/o 2c i/o 1d v e1 nic v ddp gnd 1 gnd 1 pdis v dd2 gnd iso i/o 2d v sel gnd iso v iso v e2 nic gnd iso 1 2 3 4 5 6 7 8 9 10 11 12 14 13 20 19 18 17 16 23 24 22 21 15 osc rect reg pcs nic = no internal connection. leave this pin floating. 4-channel i coupler core adum5410/adum5411/ adum5412 14695-001 figure 1. table 1. power levels input voltage (v) output voltage (v) output power (mw) 5 5 150 5 3.3 100 3.3 3.3 66 table 2. data input/output port assignments ch. pin no. adum5410 adum5411 adum5412 i/o 1a 3 v ia v ia v ia i/o 1b 4 v ib v ib v ib i/o 1c 5 v ic v ic v oc i/o 1d 6 v id v od v od i/o 2a 22 v oa v oa v oa i/o 2b 21 v ob v ob v ob i/o 2c 20 v oc v oc v ic i/o 2d 19 v od v id v id 1 protected by u.s. patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. othe r patents are pending.
adum5410/adum5411/adum5412 data sheet rev. 0 | page 2 of 29 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block digram ................................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics 5 v primary input supply/5 v secondary isolated supply ........................................................... 3 electrical characteristics 3.3 v primary input supply/3.3 v secondary isolated supply ........................................................... 5 electrical characteristics 5 v primary input supply/3.3 v secondary isolated supply ........................................................... 7 electrical characteristics 2.5 v operation digital isolator channels only .............................................................................. 9 electrical characteristics 1.8 v operation digital isolator channels only ............................................................................ 11 package characteristics ............................................................. 13 regulatory approvals ................................................................. 13 insulation and safety related specifications .......................... 13 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics ............................................................................ 14 recommended operating conditions .................................... 14 absolute maximum ratings ......................................................... 15 esd caution ................................................................................ 15 pin configurations and function descriptions ......................... 16 truth tables ................................................................................. 19 typical performa nce characteristics ........................................... 20 terminology .................................................................................... 24 theory of operation ...................................................................... 25 applications information .............................................................. 26 pcb layout ................................................................................. 26 thermal analysis ....................................................................... 27 propagation delay related parameters ................................... 27 emi considerations ................................................................... 27 power consumption .................................................................. 27 insulation lifetim e ..................................................................... 27 outline dimensions ....................................................................... 29 ordering guide .......................................................................... 29 revision his tory 7 /2016 revision 0 : initial version
data sheet adum5410/adum5411/adum5412 rev. 0 | page 3 of 29 specifications electrical character istics 5 v primary input supply /5 v secondary isolated s upply all typical specifications are at t a = 25c, v dd1 = v ddp = v iso = 5 v , v sel r esistor network: r1 = 10 k 1%, r2 = 30 .9 k 1% bet ween v iso and gnd iso ( see figure 31) . minimum/maximum specifications apply over the entire recommended operation range , which is 4.5 v v dd1 , v ddp , v iso 5.5 v , and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 3 . dc -to - dc converter s static specification s parameter symbol min typ max unit test conditions /comme nts dc - to - dc converter s supply setpoint v iso 4.7 5.0 5.4 v i iso = 15 ma , r1 = 10 k , r2 = 30.9 k line regulation v iso (line) 20 mv/v i iso = 15 ma, v dd p = 4.5 v to 5.5 v load regulation v iso (load) 1 5 % i iso = 3 ma to 27 ma output ripple v iso (rip) 75 mv p -p 20 mhz bandwidth, c bo = 0.1 f || 10 f, i iso = 27 ma output noise v iso (n oise ) 200 mv p -p c bo = 0.1 f||10 f, i iso = 27 ma switching frequency f osc 125 mhz p ulse - w idth modulation frequency f pwm 600 khz output supply i iso (max) 3 0 ma v iso > 4.5 v efficiency at i iso (max) 29 % i iso = 27 ma v ddp supply current no v iso load i ddp (q) 14 20 ma full v iso load i ddp (max) 104 140 ma thermal shutdown shutdown temperature 154 c thermal hysteresis 10 c table 4 . data channel supply current specifications 1 m b ps 25 m b ps 1 0 0 mb ps parameter symbol min typ max min typ max min typ max unit test conditions/comments supply current c l = 0 pf adum5410 i dd1 6.8 10 7.8 12 11.8 17.4 ma i dd2 2.1 3.7 3.9 5.7 9.2 13 ma adum5411 i dd1 5.8 10.3 7.0 10.9 11.4 15.9 ma i dd2 4.0 6.85 5.5 8.5 10.3 14.0 ma adum5412 i dd1 4.3 7.7 6.0 9.3 10.3 14.2 ma i dd2 5.3 8.7 6.7 10.1 11.0 14.9 ma table 5 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pulse width distortion (pwd) limit data rate 150 mbps within pwd limit propagation delay t phl , t plh 4.8 7.2 13 ns 50% input to 50% output pulse width distortion pwd 0.5 3 ns |t plh ? t phl | change vs. temperature 1.5 ps/c p ropagation delay skew t psk 6.1 ns between any two units at the same temperature, voltage , and load c hannel matching codirectional t pskcd 0.5 3.0 ns opposing direction t pskod 0.5 3.0 ns jitter 490 ps p -p 70 ps rms
adum5410/adum5411/adum5412 data sheet rev. 0 | page 4 of 29 table 6 . input and output characteristics parameter symbol min typ max unit test conditions/ comments dc specifications input threshold logic high v ih 0.7 v iso or 0.7 v dd1 v logic low v il 0.3 v iso or 0.3 v dd1 v output voltage logic high v oh v dd1 ? 0.2 or v dd2 ? 0.2 v dd1 or v dd2 v i ox 1 = ?20 a, v ix = v ixh 2 v dd1 ? 0.5 or v dd2 ? 0.5 v dd1 ? 0.2 or v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 3 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd 1 , v dd2 , and v ddp s upply positive going threshold v uv+ 1.6 v negative going threshold v uv? 1.5 v hysteresis v uvh 0. 1 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum5410 i dd1 (q) 1.2 2.2 ma v ix = logic 0 i dd2 (q) 2.0 2.72 ma v ix = logic 0 i dd1 (q) 12.0 20.0 ma v ix = logic 1 i dd2 (q) 2.0 2.92 ma v ix = logic 1 adum5411 i dd1 (q) 1.6 2.46 ma v ix = logic 0 i dd2 (q) 1.9 2.62 ma v ix = logic 0 i dd1 (q) 10.0 17.0 ma v ix = logic 1 i dd2 (q) 6.0 10.0 ma v ix = logic 1 adum5412 i dd1 (q) 1.6 2.46 ma v ix = logic 0 i dd2 (q) 1.6 2.46 ma v ix = logic 0 i dd1 (q) 7.2 11.5 ma v ix = logic 1 i dd2 (q) 8.4 11.5 ma v ix = logic 1 dynamic supply current input i ddi (d) 0.01 ma/mbps inputs switching, 50% duty cycle output i ddo (d) 0.01 ma/mbps inputs switching, 50% duty cycle ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 4 |cm h | 75 100 kv/s v ix = v dd1 or v iso , common - mode voltage ( v cm ) = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 i ox is the channel x output current, where x means a, b, c, or d. 2 v ixh is the input side logic high. 3 v ixl is the input side logic low. 4 | cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . | cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both the rising and falling common - mode voltage edges.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 5 of 29 electrical character istics 3.3 v primary input supply /3.3 v secondary isolated s upply all typical specifications are at t a = 25c, v dd1 = v ddp = v iso = 3.3 v , v sel resisto r network : r1 = 10 k, 1%, r2 = 16. 9 k 1% betwee n v iso and gnd iso ( see figure 31) . minimum/maximum specifications apply over the entire recommended operation range , which is 3.0 v v dd1 , v ddp , v iso 3.6 v , and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise noted. table 7 . dc -to - dc converter static specification s parameter symbol min typ max unit test conditions/comments dc - to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 1 0 ma , r1 = 10 k , r2 = 16.9 k line regulation v iso (line) 20 mv/v i iso = 1 0 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 2 ma to 18 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 18 ma output noise v iso (n oise ) 130 mv p -p c bo = 0.1 f||10 f, i iso = 18 ma switching frequency f osc 1 25 mhz p ulse - width modulation frequency f pwm 6 00 khz output supply i iso (max) 2 0 ma 3.6 v > v iso > 3 v efficiency at i iso (max) 27 % i iso = 18 ma v ddp supply current no v iso load i ddp (q) 14 20 ma full v iso load i ddp (max) 77 115 ma thermal shutdown shutdown temperature 154 c thermal hysteresis 10 c table 8 . data channel supply current specifications 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit test conditions/comments supply current c l = 0 pf adum5410 i dd1 6.6 9.8 7.4 11.2 10.7 15.9 ma i dd2 2.0 3.7 3.5 5.5 8.2 11.6 ma adum5411 i dd1 5.65 10.1 6.65 10.5 10.4 14.9 ma i dd2 3.9 6.65 5.2 8.0 9.4 12.8 ma adum5412 i dd1 4.3 7.7 5.6 9.0 9.1 13 ma i dd2 5.0 8.4 6.2 9.6 9.8 13.7 ma table 9 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.7 ns within pwd limit data rate 150 mbps within pwd limit propagation delay t phl , t plh 6.8 14 ns 50% input to 50% output pulse width distortion pwd 0.7 3.0 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 7.5 ns between any two units at the same temperature, voltage, and load channel matching codirectional t pskcd 0.7 3.0 ns opposing direction t pskod 0.7 3.0 ns jitter 640 ps p -p 75 ns rms
adum5410/adum5411/adum5412 data sheet rev. 0 | page 6 of 29 table 10 . input and output characteristics parameter symbol min typ max unit test conditions/ comments dc specifications input threshold logic high v ih 0.7 v iso or 0.7 v dd1 v logic low v il 0.3 v iso or 0.3 v dd1 v output voltage logic high v oh v dd1 ? 0.2 or v dd2 ? 0.2 v dd1 or v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v dd2 ? 0.5 v dd1 ? 0.2 or v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v dd2 , and v ddp s upply positive going threshold v uv+ 1.6 v negative going threshold v uv? 1.5 v hysteresis v uvh 0. 1 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum5410 i dd1 (q) 1.2 2.12 ma v ix = logic 0 i dd2 (q) 2.0 2.68 ma v ix = logic 0 i dd1 (q) 12.0 19.6 ma v ix = logic 1 i dd2 (q) 2.0 2.8 ma v ix = logic 1 adum5411 i dd1 (q) 1.5 2.36 ma v ix = logic 0 i dd2 (q) 1.8 2.52 ma v ix = logic 0 i dd1 (q) 9.8 16.7 ma v ix = logic 1 i dd2 (q) 5.7 9.7 ma v ix = logic 1 adum5412 i dd1 (q) 1.6 2.4 ma v ix = logic 0 i dd2 (q) 1.6 2.4 ma v ix = logic 0 i dd1 (q) 7.2 11.2 ma v ix = logic 1 i dd2 (q) 8.4 11.2 ma v ix = logic 1 dynamic supply current input i ddi (d) 0.01 ma/mbps inputs switching, 50% duty cycle output i ddo (d) 0.01 ma/mbps inputs switching, 50% duty cycle ac specifications output rise/fall time t r /t f 2.5 n s 10% to 90% common - mode transient immunity 1 |cm h | 75 100 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 |cm h | is the maximum common - mode vo ltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both the rising a nd falling common - mode voltage edges.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 7 of 29 electrical character istics 5 v primary input supply /3.3 v secondary isolated s upply all typical specifications are at t a = 25c, v dd1 = v ddp = 5.0 v, v iso = 3.3 v , v sel re sistor netw ork: r1 = 10 k 1% , r2 = 16. 9 k 1% betwee n v iso and gnd iso ( see figure 31) . minimum/maximum specifications apply over the entire recommended operation range , which is 4.5 v v dd1 = v ddp 5.5 v , 3.0 v v iso 3.6 v , and ? 40c t a + 105c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels , unless otherwise no ted. table 11. dc -to - dc converter static specification s parameter symbol min typ max unit test conditions/comments dc - to - dc converter supply setpoint v iso 3.0 3.3 3.6 v i iso = 15 ma , r1 = 10 k , r2 = 16.9 k line regulation v iso (line) 20 mv/v i iso = 15 ma, v dd1 = 3.0 v to 3.6 v load regulation v iso (load) 1 5 % i iso = 3 ma to 27 ma output ripple v iso (rip) 50 mv p -p 20 mhz bandwidth, c bo = 0.1 f||10 f, i iso = 27 ma output noise v iso (n oise ) 130 mv p -p c bo = 0.1 f||10 f, i iso = 27 ma switching frequency f osc 1 25 mhz p ulse - width modulation frequency f pwm 6 00 khz output supply i iso (max) 30 ma 3.6 v > v iso > 3 v efficiency at i iso (max) 24 % i iso = 27 ma v ddp supply current no v iso load i ddp (q) 14 20 ma full v iso load i ddp (max) 85 115 ma thermal shutdown shutdown temperature 154 c thermal hysteresis 10 c table 12 . data channel supply current specifications 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit test conditions/comments supply current c l = 0 pf adum5410 i dd1 6.8 10 7.8 12 11.8 17.4 ma i dd2 2.0 3.7 3.5 5.5 8.2 11.6 ma adum5411 i dd1 5.8 10.3 7.0 10.9 11.4 15.9 ma i dd2 3.9 6.65 5.2 8.0 9.4 12.8 ma adum5412 i dd1 4.3 7.7 6.0 9.3 10.3 14.2 ma i dd2 5.0 8.4 6.2 9.6 9.8 13.7 ma table 13 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.7 ns within pwd limit data rate 150 mbps within pwd limit propagation delay t phl , t plh 6.8 14 ns 50% input to 50% output pulse width distortion pwd 0.7 3.0 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 7.5 ns between any two units at the same temperature, voltage, and load channel matching codirectional t pskcd 0.7 3.0 ns opposing direction t pskod 0.7 3.0 ns jitter 640 ps p -p 75 ns rms
adum5410/adum5411/adum5412 data sheet rev. 0 | page 8 of 29 table 14. input and output characteristics parameter symbol min typ max unit test conditions/ comments dc specifications input threshold logic high v ih 0.7 v iso or 0.7 v dd1 v logic low v il 0.3 v iso or 0.3 v dd1 v output voltage logic high v oh v dd1 ? 0.2 or v dd2 ? 0.2 v dd1 or v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v dd2 ? 0.5 v dd1 ? 0.2 or v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v dd 2 , and v ddp s up ply positive going threshold v uv+ 1.6 v negative going threshold v uv ? 1.5 v hysteresis v uvh 0. 1 v input currents per channel i i ?10 +0.01 +10 a 0 v v i x v dd x quiescent supply current adum5410 i dd1 (q) 1.2 2.2 ma v ix = logic 0 i dd2 (q) 2.0 2.68 ma v ix = logic 0 i dd1 (q) 12.0 20.0 ma v ix = logic 1 i dd2 (q) 2.0 2.8 ma v ix = logic 1 adum5411 i dd1 (q) 1.6 2.46 ma v ix = logic 0 i dd2 (q) 1.8 2.52 ma v ix = logic 0 i dd1 (q) 10.0 17.0 ma v ix = logic 1 i dd2 (q) 5.7 9.7 ma v ix = logic 1 adum5412 i dd1 (q) 1.6 2.46 ma v ix = logic 0 i dd2 (q) 1.6 2.4 ma v ix = logic 0 i dd1 (q) 7.2 11.5 ma v ix = logic 1 i dd2 (q) 8.4 11.2 ma v ix = logic 1 dynamic supply current input i ddi (d) 0.01 ma/mbps inputs switching, 50% duty cycle output i ddo (d) 0.01 ma/mbps inputs switching, 50% duty cycle ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm h | 75 100 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 | cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both the rising and falling common - mode voltage edges.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 9 of 29 electrical character istics 2.5 v operation d igital i solator c hannels o nly all typical specifications are at t a = 25c, v dd1 = v dd2 = 2.5 v. minimum/maximum specifications apply over the entire recommended operation range: 2.25 v v dd1 2.75 v, 2.25 v v dd2 2.75 v, ? 40c t a + 1 0 5c, unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply currents are specified with 50% duty cycle signals. table 15. data channel supply current specifications 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit test conditions/comments supply current c l = 0 pf adum5410 i dd1 6.5 9.8 7.3 11.1 10.4 15.5 ma i dd2 2.0 3.6 3.3 5.2 7.3 10.2 ma adum5411 i dd1 5.6 10.0 6.4 10.4 9.7 14.5 ma i dd2 3.8 6.55 4.8 7.7 8.3 11.5 ma adum5412 i dd1 4.3 7.7 5.4 8.8 8.8 12.7 ma i dd2 5.0 8.4 6.1 9.5 9.5 13.4 ma table 16 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pwd limit data rate 150 mbps within pwd limit propagation delay t phl , t plh 5.0 7.0 14 ns 50% input to 50% output pulse width distortion pwd 0.7 3 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 6.8 ns between any two units at the same temperature, voltage , and load channel matching codirectional t pskcd 0.7 3.0 ns opposing direction t pskod 0.7 3.0 ns jitter 800 ps p -p 190 ps rms
adum5410/adum5411/adum5412 data sheet rev. 0 | page 10 of 29 table 17 . input and output characteristics parameter symbol min typ max unit test conditions/ comments dc specifications input threshold logic high v ih 0.7 v iso or 0.7 v dd1 v logic low v il 0.3 v iso or 0.3 v dd1 v output voltage logic high v oh v dd1 ? 0.2 or v dd2 ? 0.2 v dd1 or v dd2 v i ox = ?20 a, v ix = v ixh v dd1 ? 0.5 or v dd2 ? 0.5 v dd1 ? 0.2 or v dd2 ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0.0 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v dd2 , and v ddp s upply positive going threshold v uv+ 1.6 v negative going threshold v uv? 1.5 v hysteresis v uvh 0.1 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum5410 i dd1 (q) 1.2 2.0 ma v ix = logic 0 i dd2 (q) 2.0 2.64 ma v ix = logic 0 i dd1 (q) 1.2 19.6 ma v ix = logic 1 i dd2 (q) 2.0 2.76 ma v ix = logic 1 adum5411 i dd1 (q) 1.46 2.32 ma v ix = logic 0 i dd2 (q) 1.75 2.47 ma v ix = logic 0 i dd1 (q) 9.7 16.6 ma v ix = logic 1 i dd2 (q) 5.67 9.67 ma v ix = logic 1 adum5412 i dd1 (q) 1.6 2.32 ma v ix = logic 0 i dd2 (q) 1.6 2.32 ma v ix = logic 0 i dd1 (q) 7.2 11.2 ma v ix = logic 1 i dd2 (q) 8.4 11.2 ma v ix = logic 1 dynamic supply current dynamic input i ddi (d) 0.01 ma/mbps inputs switching, 50% duty cycle dynamic output i ddo (d) 0.01 ma/mbps inputs switching, 50% duty cycle ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm h | 75 100 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 | cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both the rising and falling common - mode voltage edges.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 11 of 29 electrical character istics 1.8 v operation d igital i solator c hannels o nly all typical specifications are at t a = 25c, v dd1 = v dd2 = 1.8 v. minimum/maximum specifications apply over the entire recommended operation range: 1.7 v v dd1 1.9 v, 1.7 v v dd2 1.9 v, and ? 40c t a + 1 0 5c , unless otherwise noted. switching specifications are tested with c l = 15 pf and cmos signal levels, unless otherwise noted. supply curr ents are specified with 50% duty cycle signals. table 18. data channel supply current specifications 1 mbps 25 mbps 100 mbps parameter symbol min typ max min typ max min typ max unit test conditions/comments supply current c l = 0 pf adum5410 i dd1 6.4 9.8 7.2 11 10.2 15.2 ma i dd2 1.9 3.5 3.1 5.0 6.8 10 ma adum5411 i dd1 5.5 9.1 6.3 10.0 9.6 14.0 ma i dd2 3.72 6.45 4.8 7.5 8.4 11.2 ma adum5412 i dd1 4.3 7.7 5.3 8.7 8.6 12.6 ma i dd2 4.9 8.3 6.0 9.4 9.3 13.3 ma table 19 . switching specifications parameter symbol min typ max unit test conditions/comments switching specifications pulse width pw 6.6 ns within pwd limit data rate 150 mbps within pwd limit propagation delay t phl , t plh 5.8 8.7 15 ns 50% input to 50% output pulse width distortion pwd 0.7 3 ns |t plh ? t phl | change vs. temperature 1.5 ps/c propagation delay skew t psk 7.0 ns between any two units at the same temperature, voltage , and load channel matching codirectional t pskcd 0.7 3.0 ns opposing direction t pskod 0.7 3.0 ns jitter 470 ps p -p 70 ps rms
adum5410/adum5411/adum5412 data sheet rev. 0 | page 12 of 29 table 20 . input and output characteristics parameter symbol min typ max unit test conditions/ comments dc specifications input threshold logic high v ih 0.7 v ddx v logic low v il 0.3 v dd x v output voltages logic high v oh v ddx ? 0.1 v ddx v i ox = ?20 a, v ix = v ixh v ddx ? 0.4 v ddx ? 0.2 v i ox = ?4 ma, v ix = v ixh logic low v ol 0.0 0.1 v i ox = 20 a, v ix = v ixl 0. 2 0.4 v i ox = 4 ma, v ix = v ixl undervoltage lockout uvlo v dd1 , v dd2 , and v ddp s upply positive going threshold v uv+ 1.6 v negative going threshold v uv? 1.5 v hysteresis v uvh 0.1 v input currents per channel i i ?10 +0.01 +10 a 0 v v ix v ddx quiescent supply current adum5410 i dd1 (q) 1.2 1.92 ma v ix = logic 0 i dd2 (q) 2.0 2.64 ma v ix = logic 0 i dd1 (q) 12.0 19.6 ma v ix = logic 1 i dd2 (q) 2.0 2.76 ma v ix = logic 1 adum5411 i dd1 (q) 1.4 2.28 ma v ix = logic 0 i dd2 (q) 1.73 2.45 ma v ix = logic 0 i dd1 (q) 9.6 16.5 ma v ix = logic 1 i dd2 (q) 5.6 9.6 ma v ix = logic 1 adum5412 i dd1 (q) 1.6 2.28 ma v ix = logic 0 i dd2 (q) 1.6 2.28 ma v ix = logic 0 i dd1 (q) 7.2 11.2 ma v ix = logic 1 i dd2 (q) 8.4 11.2 ma v ix = logic 1 dynamic supply current input i ddi (d) 0.01 ma/mbps inputs switching, 50% duty cycle output i ddo (d) 0.01 ma/mbps inputs switching, 50% duty cycle ac specifications output rise/fall time t r /t f 2.5 ns 10% to 90% common - mode transient immunity 1 |cm h | 75 100 kv/s v ix = v dd1 or v iso , v cm = 1000 v, transient magnitude = 800 v |cm l | 75 100 kv/s v ix = 0 v, v cm = 1000 v, transient magnitude = 800 v 1 | cm h | is the maximum common - mode voltage slew rate that can be sustained while maintaining the voltage output (v o ) > 0.8 v ddx . |cm l | is the maximum common - mode voltage slew rate that can be sustained while maintaining v o > 0.8 v. the common - mode voltage slew rates apply to both the rising and falling common - mod e voltage edges.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 13 of 29 package characteristics table 21. thermal and isolation characteristics parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i- o 10 12 capacitance (input to output) 1 c i- o 2.2 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction to ambient thermal resistance ja 50 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 3 1 the device is considered a 2 - terminal device: pin 1 to pin 8 are shorted together, and pin 9 to pin 16 are shorted together. 2 input capacitance is from any input data pin to ground. 3 see the thermal analysis section for thermal model definitions. regulatory approvals table 22. ul(pending) 1 csa(pending) vde (pending) 2 cqc (pending) recognized u nder 1577 c omponent r ecognition p rogram 1 approved under csa component acceptance notice 5a din v vde v 0884 - 10 (vde v 0884 - 10):2006- 12 certified under cqc11 - 471543- 2012 single p rotection, 2500 v rms i solation v oltage csa 60950 -1 - 07+a1+a2 and iec 60950 - 1, second edition, +a1+a2: reinforced insulation 565 v peak, v iosm = 4 kv peak gb4943.1 - 2011: basic insulation at 400 v rms (565 v peak) basic insulation (1mopp), 250 v rms (354 v peak) basic insulation at 400 v rms ( 565 v peak) csa 61010 -1 - 12 and iec 61010 -1 third edition basic insulation at 300 v rms m ains, 530 v rms (750 v peak) file e214100 file 205078 file 2471900 - 4880 - 0001 file (pending) 1 in accordance with ul 1577, each adum5410 / adum5411 / adum5412 is proof tested by applying an insulation test voltage 30 00 v rms for 1 second (current leakage det ection limit = 10 a). 2 in accordance with din v vde v 0884 - 10, each adum5410 / adum5411 / adum5412 is proof tested by applying an insulation test voltage 1 050 v peak for 1 second (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884 - 1 0 approval. insulation and safet y related specificatio ns table 23. critical safety related dimensions and material properties parameter symbol value unit test conditions/comments rated dielectric insulation voltage 2500 v rms 1 - minute duration minimum external air gap (clearance) l(i01) 5 .3 m m min measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 5 .3 m m min measured from input terminals to output terminals, shortest distance path along body minimum clearance in the plane of the printed circuit board (pcb clearance) l (pcb) 5.6 mm min measured from input terminals to output terminals, shortest distance through air, line of sight, in the pcb mounting plane minimum internal gap (internal clearance) 17 m min minimum distance through insulation tracking resistance (comparative tracking index ) cti > 400 v din iec 112/vde 0303, part 1 isolation group i i material g roup (din vde 0110, 1/89, table 1)
adum5410/adum5411/adum5412 data sheet rev. 0 | page 14 of 29 din v vde v 0884 - 10 (vde v 0884 - 10) insulation character istics these isolators are suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety data is ensured by the protective circuits. the asterisk (*) marking on packages denotes din v vde v 0884 - 10 approval. table 24. vde characteristics description test conditions/comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to i v for rated mains voltage 300 v rms i to i v for rated mains voltage 400 v rms i to ii i climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 565 v peak input to output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 105 9 v peak input to output test voltage, method a v pr after environmental tests subgroup 1 v iorm 1.5 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 848 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd(m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd(m) 678 v peak highest allowable overvoltage transient overvoltage, t tr = 10 sec v iotm 3535 v peak withstand isolation voltage 1 minute withstand rating v iso 2500 v rms surge isolation voltage basic v iosm(test) = 10 kv ; 1.2 s r ise time ; 50 s, 50% fall time v isom 4 000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) case temperature t s 150 c total power dissipation at 25 c i s1 2.5 w insulation resistance at t s v io = 500 v r s >10 9 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200 safe limiting power (w) 14695-002 figure 2 . thermal derating curve, dependence of safety limiting values on case temperature, per din en 60747 - 5- 2 recommended operatin g conditions table 25. parameter symbol min max unit operating temperature 1 t a ?40 + 105 c supply voltages 2 v ddp at v iso = 3.0 v to 3.6 v v ddp 3.0 5.5 v v ddp at v iso = 4.5 v to 5.5 v 4.5 5.5 v v dd1 , v dd2 v dd1 , v dd2 1 .7 5.5 v 1 operation at 105c requires reduction of the maximum load current as specified in table 26. 2 each voltage is relative to its respective ground.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 15 of 29 absolute maximum rat ings ambient temperature (t a ) = 25 c, unless otherwise noted. table 26. parameter rating storage temperature (t st ) ?55c to +150c ambient operating temperature (t a ) ?40c to +105c s upply voltages (v dd 1 , v ddp , v dd2 , v iso ) 1 ?0.5 v to +7.0 v v iso supply current 2 t a = ?40c to +105c 30 ma input voltage (v ia , v ib , v ic , v id , v e1 , v e2 , v sel , pdis ) 1, 3 ?0.5 v to v ddi + 0.5 v output voltage (v oa , v ob , v oc , v od ) 1, 3 ?0.5 v to v ddo + 0.5 v average output current per data output pin 4 ?10 ma to +10 ma common - mode transients 5 ?1 5 0 kv/s to +1 5 0 kv/s 1 all voltages are relative to their respective ground. 2 the v iso pin provides current for dc and dynamic loads on the v iso input/output channels. this current must be included when determining the total v iso supply current. for ambient temperatures betwee n 85c and 105c, the maximum allowed current is reduced. 3 v ddi and v ddo refer to the supply voltages on the input and output sides of a given channel, respectively. see the pcb layout section. 4 see figure 2 for t he maximum rated current values for various temperatures. 5 c ommon - m ode t ransients r efers to common - mode transients across the insulation barrier. common - mode transients exceeding the abs olute maximum ratings may cause latch - up or permanent damage. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any oth er conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. table 27. maximum continuous working volt age supporting 50 - year minimum lifetime 1 parameter max unit applicable certification ac voltage bipolar waveform 560 v peak all certifications, 50- year operation unipolar waveform basic insulation 560 v peak dc voltage basic insulation 560 v peak 1 maximum c ontinuous w orking v oltage r efers to the continuous voltage magnitude imposed across the isol ation barrier. see the insulation lifetime sect ion for more information. esd caution
adum5410/adum5411/adum5412 data sheet rev. 0 | page 16 of 29 pin configurations and function descriptions 1 2 3 4 24 23 22 21 5 20 6 19 7 18 8 9 10 17 16 15 11 12 14 13 adum5410 top view (not to scale) nic = no internal connection. leave these pins floating. gnd 1 v ib v ia v dd1 v ic v ob v oa v oc v id nic nic v ddp gnd 1 gnd 1 pdis v dd2 gnd iso v od v sel gnd iso v iso v e2 nic gnd iso 14695-003 figure 3. adum5410 pin configuration table 28. adum5410 pin function descriptions pin no. mnemonic description 1 v dd1 power supply for the side 1 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v. 2, 9, 12 gnd 1 ground 1. ground reference for the primary isolator. pin 2, pin 9, and pin 12 are internally connected, and it is recommended that these pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v id logic input d. 7, 8, 17 nic no internal connection. leave these pins floating. 10 pdis power disable. when tied to any gnd 1 pin, the power converter is active; when a logic high voltage is applied, the power supply enters a low power standby mode. 11 v ddp primary supply voltage, 3.0 v to 5.5 v. 13, 16, 23 gnd iso ground reference for v dd2 and v iso on side 2. pin 13, pin 16, and pin 23 are internally connected, and it is recommended that these pins be connected to a common ground. 14 v iso secondary supply voltage output for external loads. connect to v dd2 to power the isolator channels. 15 v sel output voltage selection. 18 v e2 output enable 2. when v e2 is high or disconnected, the v oa , v ob , v oc , and v od outputs are enabled. when v e2 is low, the v oa , v ob , v oc , and v od outputs are disabled. in noisy environments, connecting v e2 to either an external logic high or logic low is recommended. 19 v od logic output d. 20 v oc logic output c. 21 v ob logic output b. 22 v oa logic output a. 24 v dd2 power supply for the side 2 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 17 of 29 1 2 3 4 24 23 22 21 5 20 6 19 7 18 8 9 10 17 16 15 11 12 14 13 adum5411 top view (not to scale) nic = no internal connection. leave these pins floating. gnd 1 v ib v ia v dd1 v ic v ob v oa v oc v od v e1 nic v ddp gnd 1 gnd 1 pdis v dd2 gnd iso v id v sel gnd iso v iso v e2 nic gnd iso 14695-004 figure 4. adum5411 pin configuration table 29. adum5411 pin function descriptions pin no. mnemonic description 1 v dd1 power supply for the side 1 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v. 2, 9, 12 gnd 1 ground 1. ground reference for the primary isolator. pin 2, pin 9, and pin 12 are internally connected, and it is recommended that these pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v ic logic input c. 6 v od logic output d. 7 v e1 output enable 1. when v e1 is high or disconnected, the v od output is enabled. when v e1 is low, the v od output is disabled. in noisy environments, connecting v e1 to either an external logic high or logic low is recommended. 8, 17 nic no internal connection. leave these pins floating. 10 pdis power disable. when tied to any gnd 1 pin, the power converter is active; when a logic high voltage is applied, the power supply enters a low power standby mode. 11 v ddp primary supply voltage, 3.0 v to 5.5 v. 13, 16, 23 gnd iso ground reference for v dd2 and v iso on side 2. pin 13, pin 16, and pin 23 are internally connected, and it is recommended that these pins be connected to a common ground. 14 v iso secondary supply voltage output for external loads. connect to v dd2 to power the isolator channels. 15 v sel output voltage selection. 18 v e2 output enable 2. when v e2 is high or disconnected, the v oa , v ob , and v oc outputs are enabled. when v e2 is low, the v oa , v ob , and v oc outputs are disabled. in noisy environments, connecting v e2 to either an external logic high or logic low is recommended. 19 v id logic input d. 20 v oc logic output c. 21 v ob logic output b. 22 v oa logic output a. 24 v dd2 power supply for the side 2 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v.
adum5410/adum5411/adum5412 data sheet rev. 0 | page 18 of 29 1 2 3 4 24 23 22 21 5 20 6 19 7 18 8 9 10 17 16 15 11 12 14 13 adum5412 top view (not to scale) nic = no internal connection. leave these pins floating. gnd 1 v ib v ia v dd1 v oc v ob v oa v ic v od v e1 nic v ddp gnd 1 gnd 1 pdis v dd2 gnd iso v id v sel gnd iso v iso v e2 nic gnd iso 14695-005 figure 5. adum5412 pin configuration table 30. adum5412 pin function descriptions pin no. mnemonic description 1 v dd1 power supply for the side 1 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v. 2, 9, 12 gnd 1 ground 1. ground reference for the primary isolator. pin 2, pin 9, and pin 12 are internally connected, and it is recommended that these pins be connected to a common ground. 3 v ia logic input a. 4 v ib logic input b. 5 v oc logic output c. 6 v od logic output d. 7 v e1 output enable 1. when v e1 is high or disconnected, the v oc and v od outputs are enabled. when v e1 is low, the v oc and v od outputs are disabled. in noisy environments, connecting v e1 to either an external logic high or logic low is recommended. 8, 17 nic no internal connection. leave these pins floating. 10 pdis power disable. when tied to any gnd 1 pin, the power converter is active; when a logic high voltage is applied, the power supply enters a low power standby mode. 11 v ddp primary supply voltage, 3.0 v to 5.5 v. 13, 16, 23 gnd iso ground reference for v dd2 and v iso on side 2. pin 13, pin 16, and pin 23 are internally connected, and it is recommended that these pins be connected to a common ground. 14 v iso secondary supply voltage output for external loads. connect to v dd2 to power the isolator channels. 15 v sel output voltage selection. 18 v e2 output enable 2. when v e2 is high or disconnected, the v oa and v ob outputs are enabled. when v e2 is low, the v oa and v ob outputs are disabled. in noisy environments, connecting v e2 to either an external logic high or logic low is recommended. 19 v id logic input d. 20 v ic logic input c. 21 v ob logic output b. 22 v oa logic output a. 24 v dd2 power supply for the side 2 logic circuits of the device. this pin is independent of v ddp and operates between 3.0 v and 5.5 v.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 19 of 29 truth table s table 31 . truth table (positive logic) v ddp (v) v sel input pdis input logic v iso output (v) notes 5 r1 = 10 k , r2 = 30.9 k low 5 5 r1 = 10 k, r2 = 30.9 k high 0 3.3 r1 = 10 k, r2 = 16.9 k low 3.3 3.3 r1 = 10 k, r2 = 16.9 k high 0 5 r1 = 10 k, r2 = 16.9 k low 3.3 5 r1 = 10 k, r2 = 16.9 k high 0 3.3 r1 = 10 k, r2 = 30.9 k low 5 this c onfiguration is not recommended 3.3 r1 = 10 k, r2 = 30.9 k high 0 table 32 . data section truth table (positive logic) v ddi state 1 v ix input 1 v ddo state 1 v ox output 1 notes powered high powered high normal operation, data is high powered low powered low normal operation, data is low dont c are dont care unpowered high -z output is off unpowered low powered low output default low unpowered high powered indeterminate if a high level is applied to an input when no supply is present, the input can parasitically power the input side , causing unpredictable operation 1 v ddi and v ddo re fer to the supply voltages on the input an d output sides of the given channel, respectively. v ix and v ox refer to the input and output signals of a given channel (channel a, channel b, channel c , or channel d).
adum5410/adum5411/adum5412 data sheet rev. 0 | page 20 of 29 typical performance characteristics 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0 0.020.040.060.08 load current (a) v dd1 = v ddp =5v/v dd2 = 5v v dd1 = v ddp =5v/v dd2 = 3.3v v dd1 = v ddp =3.3v/v dd2 = 3.3v 14695-006 figure 6. power supply efficiency at 5 v/5 v, 5 v/3.3 v, and 3.3 v/3.3 v v dd1 = v ddp = 5v/v dd2 = 3.3v v dd1 = v ddp = 3.3v/v dd2 = 3.3v v dd1 = v ddp = 5v/v dd2 = 5v 14695-007 figure 7. total power dissipation vs. output supply current, i iso , with data channels idle v dd1 = v ddp = 5v/v dd2 = 3.3v v dd1 = v ddp = 3.3v/v dd2 = 3.3v v dd1 = v ddp = 5v/v dd2 = 5v 14695-008 figure 8. isolated i iso as a function of external load, no dynamic current draw at 5 v/5 v, 5 v/3.3 v, and 3.3 v/3.3 v 0 0.4 0.2 0.8 0.6 1.0 1.4 1.8 1.6 2.0 0 0.10 0.05 0.20 0.15 0.25 0.30 0.40 0.45 0.35 0.50 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd1 (v) power dissipation (w) i ddp (a) power dissipation i ddp 14695-009 figure 9. short-circuit input current (i ddp ) and power dissipation vs. v dd1 supply voltage (1ms/div) v iso (100mv/div) 14695-010 figure 10. v iso transient load response, 5 v output, 10% to 90% load step (1ms/div) v iso (100mv/div) 14695-011 figure 11. transient load response, 3 v output, 10% to 90% load step
data sheet adum5410/adum5411/adum5412 rev. 0 | page 21 of 29 (1ms/div) v iso (100mv/div) 14695-012 figure 12. transient load response, 5 v input, 3.3 v output, 10% to 90% load step v iso (v) time (s) 4.970 4.965 4.960 4.955 4.950 4.945 4.940 14695-013 figure 13. output voltage ripple at 90% load, v iso = 5 v v iso (v) time (s) 3.280 2.278 3.276 3.274 3.272 3.270 14695-014 figure 14. output voltage ripple at 90% load, v iso = 3.3 v minimum input vol t age (v) output voltage (v) 14695-015 figure 15. relationship between output voltage and required input voltage, under load, to maintain >80% duty factor in the pwm 500 450 400 350 300 250 200 150 100 ?20 0 20 40 ambient temperature (c) power dissip a tion (mw) 60 80 100 120 ?40 v dd1 = v ddp = 5v/v dd2 = 5v v dd1 = v ddp = 5v/v dd2 = 3.3v 14695-016 figure 16. power dissipation vs. ambient temperature with a 30 ma load 500 450 400 350 300 250 200 150 100 ?20 0 20 40 ambient temperature (c) power dissip a tion (mw) 60 80 100 120 ?40 v ddp = 5v/v dd2 = 3.3v v dd1 = 3.3v/v dd2 = 3.3v v dd1 = 5v/v dd2 = 5v 14695-017 figure 17. power dissipation vs. ambient temperature with a 20 ma load
adum5410/adum5411/adum5412 data sheet rev. 0 | page 22 of 29 supp l y current (ma) 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-018 figure 18 . supply current per input channel vs. data rate for 5 v and 3 .3 v operation supp l y current (ma) 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-019 figure 19 . supply current per output channel vs. data rate for 5 v and 3 .3 v operation (no output load) supp l y current (ma) 10 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-020 figure 20 . supply current per output channel vs. data rate for 5 v and 3 .3 v operation (15 pf outp ut load) i dd1 supp l y current (ma) 16 14 12 10 8 6 4 2 0 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-021 figure 21 . adum5410 v dd1 supply current (i dd1 ) vs. data rate for 5 v and 3 .3 v operation 16 14 12 10 8 6 4 2 0 i dd2 supp l y current (ma) 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-022 figure 22 . adum5410 v dd2 supply current (i dd2 ) vs. data rate for 5 v and 3 .3 v operation 16 14 12 10 8 6 4 2 0 i dd1 supp l y current (ma) 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-023 figure 23 . adum5411 v dd1 sup ply current (i dd1 ) vs. data rate for 5 v and 3 .3 v operation
data sheet adum5410/adum5411/adum5412 rev. 0 | page 23 of 29 16 14 12 10 8 6 4 2 0 i dd2 supp l y current (ma) 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-024 figure 24 . adum5411 v dd2 supply current (i dd2 ) vs. data rate for 5 v and 3.3 v operation d at a r a te (mbps) 0 20 40 60 80 100 120 140 160 i dd1 supp l y current (ma) 5v 3.3v 14695-0124 figure 25 . adum5412 v dd1 supply curren t (i dd1 ) vs. data rate for 5 v and 3.3 v operat ion 16 14 12 10 8 6 4 2 0 i dd2 supp l y current (ma) 0 20 40 60 80 d at a r a te (mbps) 100 120 140 160 5v 3.3v 14695-025 figure 26 . adum5412 v dd2 supply curren t (i dd2 ) vs. data rate for 5 v and 3.3 v operati on 14 12 10 8 6 4 2 0 pro p ag a tion del a y , t plh (ns) ?40 ?20 20 0 40 60 80 temper a ture (c) 100 120 140 5v 3.3v 14695-026 figure 27 . propagation delay , t plh vs. temperature for 5 v and 3 .3 v operation 14 12 10 8 6 4 2 0 pro p ag a tion del a y , t phl (ns) ?40 ?20 20 0 40 60 80 temper a ture (c) 100 120 140 5v 3.3v 14695-027 figure 28 . propagation delay , t phl vs. temperature for 5 v and 3 .3 v operation
adum5410/adum5411/adum5412 data sheet rev. 0 | page 24 of 29 terminology i dd1 (q) i dd1 (q) is the minimum operating current drawn at the v dd1 pin when there is no external load at v iso and the input/output pins are operating below 2 mbps, requiring no additional dynamic supply current. i dd1 (q) reflects the minimum current operating condition. i dd1 (d) i dd1 (d) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 33 mbps with full capacitive load representing the maximum dynamic load conditions. treat r esistive loads on the outputs separately fro m the dynamic load. i dd1 (max) i dd1 (max) is the input current under full dynamic and v iso load conditions. i so (load) i so (load) is the current available to load. propagation delay , t phl t phl propagation delay is measured from the 50% level of the falling edge of the v ix signal to the 50% level of the falling edge of the v ox signal. propagation delay , t plh t plh propagation delay is measured from the 50% level of the rising edge of the v ix sig nal to the 50% level of the rising edge of the v ox signal. propagation delay skew , t psk t psk is the magnitude of the worst - case difference in t phl and/or t plh that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. channel to channel matching , t pskcd /t pskod channel to channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. minimum pulse width the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. maximum data rate the maximum data rate is the fastest data rate at which the specified pulse width distor tion is guaranteed.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 25 of 29 theory of operation the dc-to-dc converter section of the adum5410 / adum5411/ adum5412 works on principles that are common to most modern power supplies. it has a split controller architecture with isolated pwm feedback. v ddp power is supplied to an oscillating circuit that switches current into a chip-scale air core transformer. power transferred to the secondary side is rectified and regulated to a value between 3.15 v and 5.25 v, depending on the setpoint supplied by an external voltag e divider (see equation 1). the secondary (v iso ) side controller regulates the output by creating a pwm control signal that is sent to the primary (v ddp ) side by a dedicated i coupler data channel. the pwm modulates the oscillator circuit to control the power being sent to the secondary side. feedback allows for significantly higher power and efficiency. r1 r2r1 v iso )( v225.1 ? ? (1) where: r1 is a resistor between v sel and gnd iso . r2 is a resistor between v sel and v iso . because the output voltage can be adjusted continuously, there are an infinite number of operating conditions. this data sheet addresses three discrete operating conditions in the specifications section. many other combinations of input and output voltage are possible; figure 15 shows the supported voltage combinations at room temperature. figure 15 was generated by fixing the v iso load and decreasing the input voltage until the pwm was at 80% duty cycle. each of the figures represents the minimum input voltage that is required for operation under this criterion. for example, if the applica- tion requires 30 ma of output current at 5 v, the minimum input voltage at v ddp is 4.25 v. figure 15 also illustrates why the v ddp = 3.3 v input and v iso = 5 v configuration is not recommended. even at 10 ma of output current, the pwm cannot maintain less than 80% duty factor, leaving no margin to support load or temperature variations. typically, the adum5410/ adum5411 / adum5412 dissipate about 17% more power between room temperature and maxi- mum temperature; therefore, the 20% pwm margin covers temperature variations. the adum5410 / adum5411/ adum5412 implement undervoltage lockout (uvlo) with hysteresis on the primary and secondary side input/output pins as well as the v ddp power input. this feature ensures that the converters do not go into oscillation due to noisy input power or slow power-on ramp rates. the digital isolator channels use a high frequency carrier to transmit data across the isolation barrier using i coupler chip scale transformer coils separated by layers of polyimide isolation. using an on/off keying (ook) technique and the differential architecture shown in figure 29, the digital isolator channels have very low propagation delay and high speed. internal regulators and input/output design techniques allow logic and supply voltages over a wide range from 1.7 v to 5.5 v, offering voltage translation of 1.8 v, 2.5 v, 3.3 v, and 5 v logic. the architecture is designed for high common-mode transient immunity and high immunity to electrical noise and magnetic interference. radiated emissions are minimized with a spread spectrum ook carrier and other techniques. figure 29 shows the waveforms of the digital isolator channels that have the condition of the fail-safe output state equal to low, where the carrier waveform is off when the input state is low. if the input side is off or not operating, the low fail-safe output state sets the output to low. transmitter gnd 1 gnd 2 v in v out receiver regulator regulator 14695-028 figure 29. operational block diagram of a single channel with a low fail-safe output state
adum5410/adum5411/adum5412 data sheet rev. 0 | page 26 of 29 applications information pcb layout the adum5410 / adum5411/ adum5412 digital isolators with 0.15 w iso power integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. power supply bypassing is required at the input and output supply pins (see figure 32). note that low esr bypass capacitors of 0.01 f to 0.1 f value are required between the v dd1 pin and gnd 1 pin, and between the v dd2 pin and gnd iso pin, as close to the chip pads as possible, for proper operation of the data channels. the iso power inputs require several passive components to bypass the power effectively, as well as set the output voltage and bypass the core voltage regulator (see figure 30 through figure 32). pdis v ddp gnd 1 10f 0.1f + 10 11 12 14695-029 figure 30. v ddp bias and bypass components v sel viso out iso gnd fb2 gnd iso v iso 0.1f 10f r1 10k ? r2 30k ? 15 14 13 fb1 14695-030 figure 31. v iso bias and bypass components the power supply section of the adum5410/ adum5411/ adum5412 uses a 125 mhz oscillator frequency to efficiently pass power through its chip-scale transformers. bypass capacitors are required for several operating frequencies. noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. these capacitors are most conveniently connected between the v ddp pin and gnd 1 pin, and between the v iso pin and gnd iso pin. to suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. the recommended capacitor values are 0.1 f and 10 f for v dd1 . the smaller capacitor must have a low esr; for example, use of a ceramic capacitor is advised. note that the total lead length between the ends of the low esr capacitor and the input power supply pin must not exceed 2 mm. installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. to reduce the level of electromagnetic radiation, the impedance to high frequency currents between the v iso and gnd iso pins and the pcb trace connections can be increased. using this method of emi suppression controls the radiating signal at its source by placing surface-mount ferrite beads in series with the v iso and gnd iso pins, as seen in figure 32. the impedance of the ferrite bead is chosen to be about 2 k between the 100 mhz and 1 ghz frequency range, to reduce the emissions at the 125 mhz primary switching frequency and the 250 mhz secondary side rectifying frequency and harmonics. see table 33 for examples of appropriate surface-mount ferrite beads. for additional reduction in emissions, pcb stitching capacitance can be implemented with a high voltage smt safety capacitor. for optimal performance, it is important that the capacitor is connected directly between gnd 1 (pin 12) and gnd iso (pin 13), as shown in figure 32.this capacitor is a smt size 1812, has a 3 kv voltage rating, and is manufactured by tdk corporation (c4532c0g3f101k160ka). table 33. surface-mount ferrite beads example manufacturer part no. taiyo yuden bkh1005lm182-t murata electronics blm15hd182sn1 gnd iso v sel nic nic v e2 v e1 /nic pdis v ddp v iso 0.1f 0.1f 0.1f 10f ferrites 10f gnd 1 gnd iso adum5410/ adum5411/ adum5412 gnd 1 v ib v ia v id /v od v ic /v oc v ob v oa v od /v id v oc /v ic v dd1 v dd2 gnd 1 gnd iso 14695-031 0.1f smt 100pf safety capacitor nic = no internal connection. leave this pin floating. figure 32. recommended pcb layout in applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. failure to ensure these steps can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in table 26, thereby leading to latch-up and/or permanent damage.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 27 of 29 thermal analysis the adum5410 / adum5411/ adum5412 consist of four internal die attached to a split lead frame with two die attach pads. for the purposes of thermal analysis, the die is treated as a thermal unit, with the highest junction temperature reflected in the ja value from table 21. the value of ja is based on measurements taken with the devices mounted on a jedec standard, 4-layer board with fine width traces and still air. under normal operating conditions, the adum5410/ adum5411/ adum5412 can operate at full load across the full temperature range without derating the output current. propagation delay related parameters propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see figure 33). the propagation delay to a logic low output may differ from the propagation delay to a logic high. input (v ix ) output (v ox ) t plh t phl 50% 50% 14695-032 figure 33. propagation delay parameters pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. channel to channel matching refers to the maximum amount the propagation delay differs between channels within a single adum5410/ adum5411/ adum5412 component. propagation delay skew refers to the maximum amount the propagation delay differs between multiple adum5410 / adum5411/ adum5412 components operating under the same conditions. emi considerations the dc-to-dc converter section of the adum5410 / adum5411/ adum5412 components must, of necessity, operate at a very high frequency to allow efficient power transfer through the small transformers, which creates high frequency currents that can propagate in circuit board ground and power planes, causing edge and dipole radiation. grounded enclosures are recommended for applications that use these devices. if grounded enclosures are not possible, follow good rf design practices in the layout of the pcb. follow the layout techniques described in the pcb layout section. see the an-0971 application note for the most current pcb layout recommendations for the adum5410 / adum5411 / adum5412. power consumption the v ddp power supply input only provides power to the converter. power for the data channels is provided through v dd1 and v dd2 . these power supplies can be connected to v ddp and v iso if desired, or the supplies can receive power from an independent source. treat the converter as a standalone supply to be utilized at the discretion of the designer. the v dd1 or v dd2 supply current at a given channel of the adum5410/ adum5411/ adum5412 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. to calculate the total v dd1 and v dd2 supply current, the supply currents for each input and output channel corresponding to v dd1 and v dd2 are calculated and totaled. figure 18 and figure 19 show per channel supply currents as a function of data rate for an unloaded output condition. figure 20 shows the per channel supply current as a function of data rate for a 15 pf output condition. figure 21 through figure 26 show the total v dd1 and v dd2 supply current as a function of data rate for adum5410/ adum5411/ adum5412 channel configurations. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation as well as on the materials and material interfaces. the two types of insulation degradation of primary interest are breakdown along surfaces exposed to the air and insulation wear out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulation material cause long-t erm insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the insulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. lower material group ratings are more resistant to surface tracking and, therefore, can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material group. the material group and creepage for the digital isolator channels are presented in table 23. insulation wear out the lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. it is important to verify that the product lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. the working voltage applicable to tracking is specified in most standards.
adum5410/adum5411/adum5412 data sheet rev. 0 | page 28 of 29 testing and modeling show that the primary driver of long- term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insul- ation can be broken down into broad categories, such as dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because this reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as is shown in equation 2. for insulation wear out with the polyimide materials used in these products, the ac rms voltage determines the product lifetime. 22 dc rmsac rms vvv ?? (1) or 22 dc rms rmsac vvv ?? (2) where: v ac rms is the time varying portion of the working voltage. v rms is the total rms working voltage. v dc is the dc offset of the working voltage. calculation and use of parameters example the following example frequently arises in power conversion applications. assume that the line voltage on one side of the isolation is 240 v ac rms and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage, clearance and lifetime of a device, see figure 34 and the following equations. isol a tion vol t age time v ac rms v rms v dc v peak 14695-033 figure 34. critical voltage example the working voltage across the barrier from equation 1 is 22 dc rmsac rms vvv ?? 22 400240 ?? rms v v rms = 466 v this v rms value is the working voltage used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. to obtain the ac rms voltage, use equation 2. 22 dc rms rmsac vvv ?? 22 400466 ?? rmsac v v ac rms = 240 v rms in this case, the ac rms voltage is simply the line voltage of 240 v rms. this calculation is more relevant when the waveform is not sinusoidal. the value is compared to the limits for working voltage in table 27 for the expected lifetime, which is less than a 60 hz sine wave, and it is well within the limit for a 50-year service life. note that the dc working voltage limit is set by the creepage of the package as specified in iec 60664-1. this value can differ for specific system level standards.
data sheet adum5410/adum5411/adum5412 rev. 0 | page 29 of 29 outline dimensions compliant t o jedec s t andards mo-150-ag 060106- a 24 13 12 1 8.50 8.20 7.90 8.20 7.80 7.40 5.60 5.30 5.00 sea ting plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarit y 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 35 . 24 - lead shrink small outline package [ssop] (rs - 24) dimensions shown in millimeters ordering guide model 1 number of inputs, v dd1 side number of inputs, v iso side maximum data rate (mbps) maximum propagation delay, 5 v (ns) maximum pulse width distortion (ns) temperature range ( c) package description package option adum5410brsz 4 0 150 13 3 ?40 to +105 24- lead ssop rs - 24 adum5410brsz - rl7 4 0 150 13 3 ?40 to +105 24- lead ssop rs - 24 adum5411brsz 3 1 150 13 3 ?40 to +105 24- lead ssop rs - 24 adum5411brsz - rl7 3 1 150 13 3 ?40 to +105 24- lead ssop rs - 24 adum5412brsz 2 2 150 13 3 ?40 to +105 24- lead ssop rs - 24 adum5412brsz - rl7 2 2 150 13 3 ?40 to +105 24- lead ssop rs - 24 eval - adum5411ebz evaluation board 2 eval - adum5411uebz evaluation board 3 1 z = rohs compliant part. 2 the eval - adum5 411ebz is packaged with the adum5411brsz installed . 3 the eval - adum5411uebz is packaged without an adum5411 installed. ? 2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d14695 - 0 - 7/16(0)

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