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? 2015 microchip technology inc. ds20005374a-page 1 HV9805 features provides true dc light and protects load from line voltage transients driver topology includes: - boundary conduction mode (bcm) boost converter with power factor correction a) high power factor (98% typical) b) high efficiency (90% typical) - linear post-regulator with low overhead voltage a) zero led current/brightness ripple b) overvoltage protection for leds c) high efficiency d) 4% reference over temperature simple v dd supply: - no auxiliary winding required boost converter cascode switch: - internal switch rated at 700 ma peak - supports up to 25w at 120v ac - supports up to 50w at 230v ac compatibility with sepic topology for low output voltage applications applications led lamps led lighting fixtures general description the HV9805 driver integrated circuit (ic) is targeted at general led lighting products, such as led lamps and led lighting fixtures with a maximum power rating of about 25w at 120v ac and about 50w at 230v ac . a two-stage topology provides true constant current drive for the led load while drawing mains power with high power factor. the first stage, a boundary conduction mode boost converter, transfers power from the ac line to a second stage with high power factor and high efficiency. the second stage, a linear regulator arranged for operation with low overhead voltage, transfers power from the first stage to the led load with true constant current and protects the led load from overvoltage that may pass from mains to the output of the first stage. the ic is particularly geared to drive a high voltage led load. an led load arranged as a high-voltage load is capable of offering cost advantages in terms of heat management and optics. the boost converter employs a cascode switch for high-speed switching and convenient generation of the v dd supply. the control device of the cascode switch is an integral part of the HV9805 and is rated at 700 ma peak. current for powering the v dd supply is derived by way of an internal connection to the cascode switch. applications with low output voltage can be accommodated using the sepic topology. network topology diagram ac off-line led driver with true dc output current downloaded from: http:///
HV9805 ds20005374a-page 2 ? 2015 microchip technology inc. package types typical application circuit HV9805 msop csh csl hvs gndbvs 1 2 3 4 10 9 8 7 crg drv v dd 6 crs hvr 5 ac c bus c bst c rec c hvx c hvy c val c vdd d bst dn val bvs 8 crg 7 crs 6 csh 3 csl 2 drv 10 gnd 9 hvr 5 hvs 4 v dd HV9805 l bst led m bst m crx r lbs r bvb r bvt r crs r csh r csl r hvb r hvt r bst r hvx r val z drv z bst z hvs c bvs 1 r csl = r csa r csh = r csa + r val r csa and r val : see block diagram and section 3.2 . downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 3 HV9805 block diagram ac drv bvs crg crs csl csh gnd v dd hvr hvs r lbs c rec r val r val r csa r csa l bst r bst z bst c bst z drv c val d bst r bvt r bvb led r crs r hvb r hvt c bus m crx c hvx r hvx c hvy c vdd m bst HV9805 z hvs otp inductor current sense linear v dd regulator valley detector line current waveform regulator headroom voltage regulator drv fet gate logic switching v dd regulator v dd fets led current sense led current regulator vddlo bvsuv bvsov hvsok comparators regulator logic headroom voltage sense c bvs ocp v bus i led v hea i bst i bst m 1 m 2 drv fet downloaded from: http:///
HV9805 ds20005374a-page 4 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 5 HV9805 1.0 electrical characteristics absolute maximum ratings ? v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +12v v drv . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +20v v csl , v csh , v bvs , v crs , v crg , v hvs , v hvr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +5.5v junction temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c power dissipation at 25c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625 mw esd protection on all pins (hbm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kv esd protection on all pins (mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150v ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indi cated in the operational sections of this specification is not intended. exposure to maximum rating conditions for extended perio ds may affect device reliability. dc and ac characteristics electrical specifications: unless otherwise specified, all specifications apply at v dd = 8.2v, t a = t j = +25c, f swi =100khz. boldface specifications apply over the ambient temperature (t a = t j ) range of -40c to +125c. parameter sym. min. typ. max. unit conditions v dd supply (v dd ) enable threshold voltage v ena 7.2 7.5 7.8 v v dd rising disable threshold voltage v dis 6.4 6.7 7.1 v dd falling linear regulator resistance r reg 0.42 ? 1.2 k ? v dd voltage v dd 7.9 8.2 8.6 v switching regulator control gain k vdd =( ? t on,vddfet )/( ? v dd ) k vdd 3 s / vv dd =8.0v ( note 2 ) supply current, run state, measured at drv pin i dd 12 . 55 m a first stage, boost regulator (drv) control fet on-resistance r drv 1 ? note 2 overcurrent comparator threshold i ocp 0.75 ? 2.75 a overcurrent comparator blanking time t blk 3 3 0 n s note 2 nominal on-time t onn 2 . 7 sv hvr =1.2v ( note 2 ) maximum on-time t onh 81 3 maximum off-time t ofh 80 110 headroom voltage regulator (hvs, hvr) regulator reference voltage v ref,hvr 1.17 1.25 1.32 v run comparator threshold v run 1 . 2 5 note 2 regulator output voltage, maximum level v hvr 5 . 05 . 5 regulator control gain k hvr =( ? t on, drvfet )/( ? v hvr ) k hvr 2 . 2 s / v v hvr =1.0v ( note 2 ) control amplifier transconductance g hvr 55 75 95 a/v control amplifier sink current i snk,hvr 50 80 a v hvr =2.5v, v hvs =2.25v control amplifier source current i src,hvr 50 80 v hvr =2.5v, v hvs =0.25v note 1: specification is obtained by characterization and is not 100% tested. 2: specification is for design guidance only. downloaded from: http:///
HV9805 ds20005374a-page 6 ? 2015 microchip technology inc. current sense amplifier (csl, csh) sense amplifier transresistance r csa 1 0m v / a note 1 sense amplifier input current range i csa -100 100 a note 2 valley detection propagation delay tp val 50 120 200 ns overdrive current (i csh Ci csl )=-5a bus voltage comparators (bvs) undervoltage upper threshold v uvu 0.45 0.5 0.55 vv bvs rising undervoltage lower threshold v uvl 0.36 0.4 0.46 v bvs falling overvoltage upper threshold v ovu 1.19 1.25 1.31 v bvs rising overvoltage lower threshold v ovl 1.11 1.15 1.2 v bvs falling second stage, constant current regulator (crs, crg) regulator reference voltage v ref,ccr 0.96 1.00 1.04 v soft-start reference level v ssr 2 0% v ref note 2 gate output voltage, maximum level v crg 4.5 5.5 v gate output current, sinking i snk,ccr 12m av crg =4.0v gate output current, sourcing i src,ccr 11 . 5 v crg =0v overtemperature protection disable threshold t dis 1 4 5 c note 1 enable threshold t ena 1 3 0 c note 1 temperature specifications electrical specifications: unless otherwise specified, all voltages are referenced to the gnd pin, t a =t j =+25c. boldface specifications apply over the full operating ambient temperature (t a ) range of -40c to +125c. parameters sym. min. typ. max. units conditions temperature ranges operating ambient temperature range t a -40 +125 c storage temperature range t a -65 +150 c maximum junction temperature t j -40 +150 c package thermal resistances thermal resistance, 10l-msop ? ja 202 c/w dc and ac characteristics (continued) electrical specifications: unless otherwise specified, all specifications apply at v dd = 8.2v, t a = t j = +25c, f swi =100khz. boldface specifications apply over the ambient temperature (t a = t j ) range of -40c to +125c. parameter sym. min. typ. max. unit conditions note 1: specification is obtained by characterization and is not 100% tested. 2: specification is for design guidance only. downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 7 HV9805 2.0 typical performance curves note: unless otherwise indicated, v dd = 8.2v, t a = +25c, f swi =100khz. figure 2-1: v dd supply enable voltage vs. temperature. figure 2-2: v dd supply disable voltage vs. temperature. figure 2-3: v dd supply linear regulator resistance vs. temperature. figure 2-4: v dd supply regulation voltage vs temperature. figure 2-5: v dd supply current draw vs. temperature. figure 2-6: overcurrent threshold vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 v dd enable voltage (v) temperature (c) v ena 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 v dd disable voltage (v) temperature (c) v dis 0.0 0.5 1.0 1.5 2.0 -50-25 0 255075100125150 v dd 6xsso\/lqhdu5hjxodwrun temperature (c) r reg 0 1 2 3 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 v dd voltage (v) temperature (c) v dd 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 v dd supply current (ma) temperature (c) i dd 0 1 2 3 4 -50 -25 0 25 50 75 100 125 150 overcurrent threshold (a) temperature (c) i ocp downloaded from: http:///
HV9805 ds20005374a-page 8 ? 2015 microchip technology inc. note: unless otherwise indicated, v dd = 8.2v, t a = +25c, f swi =100khz. figure 2-7: maximum on-time vs. temperature. figure 2-8: maximum off-time vs. temperature. figure 2-9: headroom voltage regulator reference voltage vs. temperature (run state). figure 2-10: hvr transconductance vs. temperature. figure 2-11: hvr maximum source current vs. temperature. figure 2-12: hvr maximum sink current vs. temperature. 0 5 10 15 20 -50 -25 0 25 50 75 100 125 150 maximum on-time (s) temperature (c) t onh 0 25 50 75 100 -50 -25 0 25 50 75 100 125 150 maximum off-time (s) temperature (c) t ofh 1.20 1.25 1.30 -50 -25 0 25 50 75 100 125 150 hvr reference voltage (v) temperature (c) v ref , hvr 0 25 50 75 100 -50 -25 0 25 50 75 100 125 150 hvr transconductance (a/v) temperature (c) g hvr 0 25 50 75 100 -50 -25 0 25 50 75 100 125 150 hvr source current (a) temperature (c) i src , hvr 0 25 50 75 100 -50 -25 0 25 50 75 100 125 150 hvr sink current (a) temperature (c) i snk,hvr downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 9 HV9805 note: unless otherwise indicated, v dd = 8.2v, t a = +25c, f swi =100khz. figure 2-13: valley detector propagation delay vs. temperature. figure 2-14: undervoltage upper threshold voltage vs. temperature. figure 2-15: undervoltage lower threshold voltage vs. temperature. figure 2-16: overvoltage upper threshold voltage vs. temperature. figure 2-17: overvoltage lower threshold voltage vs. temperature. figure 2-18: constant current regulator reference voltage vs. temperature (run state). 0 50 100 150 200 -50 -25 0 25 50 75 100 125 150 valley detection delay (ns) temperature ( c) tp val 0.0 0.5 1.0 -50 -25 0 25 50 75 100 125 150 undervoltage upper threshold (v) temperature (c) v uvu 0.0 0.5 1.0 -50 -25 0 25 50 75 100 125 150 undervoltage lower threshold (v) temperature (c) v uvl 0.0 0.5 1.0 1.5 2.0 -50 -25 0 25 50 75 100 125 150 overvoltage upper threshold (v) temperature (c) v o v u 0.0 0.5 1.0 1.5 2.0 -50 -25 0 25 50 75 100 125 150 overvoltage lower threshold (v) temperature (c) v ovl 0.90 0.92 0.94 0.96 0.98 1.00 1.02 1.04 1.06 1.08 1.10 -50 -25 0 25 50 75 100 125 150 ccr reference voltage (v) temperature ( c) v ref,ccr downloaded from: http:///
HV9805 ds20005374a-page 10 ? 2015 microchip technology inc. note: unless otherwise indicated, v dd = 8.2v, t a = +25c, f swi =100khz. figure 2-19: crg gate sink current vs. temperature. figure 2-20: crg gate source current vs. temperature. 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 crg sink current (ma) temperature (c) i snk,ccr 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150 crg source current (ma) temperature (c) i src,ccr downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 11 HV9805 3.0 pin description the descriptions of the pins are listed in tab l e 3 - 1 . 3.1 v dd supply support pin (v dd ) the v dd supply is not capable of sourcing a significant current to external circuitry. a significant source of sup- ply current can be created by means of an auxiliary winding on the boost inductor. connect a 10 f ceramic capacitor between the v dd and gnd pins to provide v dd supply filtering and v dd supply holdup. a sizable holdup capacitor is required to maintain an adequate v dd supply voltage near the zero crossings of the ac line voltage, where the supply of current to the v dd supply circuit drops off significantly. 3.2 input pins of the first-stage current sense amplifier (csl, csh) the current sense amplifier senses the boost inductor current for line current-waveform shaping and detecting the drain voltage valley. the sense amplifier is arranged as a differential amplifier featuring unity gain and an output voltage offset of 1.25v, as seen in figure 4-3 . the offset allows a negative boost inductor sense voltage to be processed as a positive voltage. note that positive boost inductor current produces negative sense voltage at the current sense resistor r lbs . the resistance of each gain setting resistor r csa is nominally 10 k ? . two of the gain setting resistors are provided internally to the HV9805, and two are provided externally. complete the differential amplifier setup by adding two r csa resistors of 10 k ? and of 1% tolerance, as indicated in figure 4-3 . to improve drain voltage valley detection, a second set of resistors r val and a capacitor c val can be added to the amplifier setup, as shown in the typical application circuit and block diagram . detection signal amplitude can be adjusted freely by the c val and r val selection, with larger values generating a larger detection signal from the drain voltage swing. starting values of 100 ? and 10pf for r val and c val are suggested. provide detection resistors in both legs of the sense amplifier to keep the amplifier setup balanced. the combination of resistors r val and r csa at the csh pin can be replaced by a single resistor, r csh . refer to the typical application circuit and to the block diagram for more details. 3.3 input pin of the headroom voltage sense amplifier (hvs) connect the hvs pin to the drain of the constant current regulator fet with a resistive divider. the addition of a zener diode at the hvs pin is required to protect the hvs pin from an overvoltage condition at shutdown of the led driver. overvoltage at the hvs pin can occur as the bus capacitor remains charged for a significant time after shutdown. the headroom voltage rises significantly as the forward voltage drop across the led load drops towards zero. consequently, the voltage at the hvs pin rises as well, and may take the voltage at the hvs pin above its absolute maximum rating without an external zener diode in place. table 3-1: pin function table pin symbol i/o description 1v dd pin for support of the v dd supply 2 csl i non-inverting input pin of the current sense amplifier of the first stage 3 csh i inverting input pin of the current sense amplifier of the first stage 4 hvs i input pin of the headroom voltage sense amplifier 5 hvr o output pin of the headroom voltage regulator control amplifier 6 crs i input pin of the current sense amplifier of the second stage 7 crg o output pin of the constant current regulator control amplifier 8 bvs i input pin of the bus voltage sense amplifier 9 gnd ground pin 10 drv o drive pin for control of the boost converter switch downloaded from: http:///
HV9805 ds20005374a-page 12 ? 2015 microchip technology inc. 3.4 output pin of the headroom voltage regulator control amplifier (hvr) connect a gain setting network between the hvr pin and ground to set the response characteristic of the headroom voltage regulator control amplifier. 3.5 input pin of the second-stage current sense amplifier (crs) the sense amplifier senses the led load current for the purpose of constant current regulation. connect this pin to the led current sense resistor r crs . 3.6 output pin of the constant current regulator control amplifier (crg) connect to the gate of the constant current regulator fet. the control amplifier has a limited output voltage capability. use a low threshold fet for the pass transistor of the current regulator. 3.7 input pin of the bus voltage sense amplifier (bvs) bus voltage is sensed in order to detect an undervoltage or overvoltage condition. connect this pin to the bus voltage node by way of a resistive voltage divider. 3.8 ground pin (gnd) ground pin. 3.9 drive pin for control of the boost converter switch (drv) the conduction state of the boost converter switch is controlled by source switching, as explained in more detail in section 4.11.1.2 ?boost converter switch? . connect the drv pin to the source terminal of the external fet. to protect the drv pin from an overvoltage condition during the switch turn-off transition, connect a zener diode to ground. note: the r bvt resistor should be rated for the bus voltage. a typical approach is to split r bvt into a series connection of multiple resistors with lower voltage rating. downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 13 HV9805 4.0 functional description 4.1 introduction the HV9805 control ic provides true dc current drive for led lamps and fixtures with a simple two-stage power supply topology, comprised of a boundary mode boost converter and a linear constant current regulator. the constant current regulator removes the influence of bus voltage variation on the led current and protects the led load from line voltage transients, which may cause a transient increase in the bus voltage. the boost converter output voltage is regulated so as to maintain a sufficient but small headroom voltage at the pass transistor of the constant current regulator. the small headroom voltage keeps pass transistor power dissipation low and overall efficiency high. the ic is targeted at designs operating at a single line voltage, such as 120v ac or 230v ac , and does not support designs for the universal input voltage range. 4.2 regulator structure operation is supported by a number of feedback regulators with various operating modes, a state machine to control these modes and voltage comparators to control the state machine. the four regulators of the control ic are: v dd regulator led current regulator headroom voltage regulator line current waveform regulator the state machine of the regulator logic features the following states: idle state start state run state the transition between states is controlled by the following comparator flags: vddlo, the v dd undervoltage flag busuv, the bus voltage undervoltage flag busov, the bus voltage overvoltage flag hvrok, the headroom voltage ok flag otphi, the overtemperature protection flag 4.3 v dd regulator to power the internal circuits of the HV9805, the v dd regulator establishes a v dd supply voltage of about 8v. the v dd regulator operates in one of two modes: a low-efficiency linear mode for start-up of the v dd supply and a high-efficiency switching mode for regular operation of the v dd supply. referring to the block diagram , current for operation of the v dd supply flows from the boost inductor, the external fet, the drv pin, an internal diode and two internal fets. when operating in linear mode, the first v dd fet m 1 with series resistor is enabled to supply boost inductor current to the v dd supply. the resistor provides for gradual charging of the v dd capacitor and prevents high frequency oscillation in the charging path. when operating in switching mode, the second v dd fet m 2 is fully enabled in the first part of each boost converter switching cycle to guide the linearly rising boost inductor current toward the internal v dd supply and the v dd capacitor. this first part is terminated by the turn-on of the drv fet, which guides the boost inductor current to ground and effectively terminates the supply of current to the v dd supply. the switching v dd regulator section regulates the v dd supply voltage by adjusting the length of the first part of the switching cycle, terminating the first part by the turn-on of the drv fet. the regulator logic sets the regulator mode as follows: in the idle state: linear mode in the start state: switching mode in the run state: switching mode downloaded from: http:///
HV9805 ds20005374a-page 14 ? 2015 microchip technology inc. 4.4 led current regulator the led current regulator regulates the led current i led to a programmable level. the led current can be programmed with the aid of equation 4-1 . equation 4-1: the regulator adjusts the conductance of an external pass fet by adjusting the crg pin voltage, thereby adjusting the gate to the source voltage of the fet. the control amplifier of the led current regulator has high bandwidth and is internally compensated. the regulating amplifier is provided with a two-level reference (v ref ): one at 200 mv, corresponding to 20% of the nominal led current, and a second one at 1v, corresponding to 100% of the nominal led current. the lower level is provided for quick run up of the bus voltage during the start state. feedback is provided by way of a current sense resis- tor and the current sense voltage at the crs pin. the regulator logic controls the regulator mode as follows: idle state: 20% reference level (v ref =200mv) start state: 20% reference level (v ref =200mv) run state: 100% reference level (v ref =1v) v ref, ccr i led r crs ? = where: v ref,ccr = reference voltage for the led current regulator, see dc and ac characteristics table i led = led current, see typical application circuit r crs = sense resistor for sensing the led current, see typical application circuit note 1: the maximum v gs voltage available for control of the external pass fet is limited to about 3.5v, a voltage which is adequate for control of a logic level fet but generally too low for control of a standard gate fet. on the gate side of the pass fet, the maximum crg pin voltage is about 4.5v with respect to ground, while on the source side, the voltage across the sense resistor is 1.0v during regular operation. 2: the voltage rating of the pass transistor need not be as high as the bus voltage. the operating voltage at the drain of the pass transistor is low during regular operation. when the led current regulator turns off, the headroom voltage rises towards the bus voltage. the bus voltage will divide across the led load and the pass transistor according to the impedance level of both devices, with both devices carrying little current. a voltage division will be established based on the leakage characteristic of both devices. the voltage across the pass transistor can be lowered relatively easily by adding a secondary leakage path in parallel with the pass transistor. note that the feedback divider for the hvs signal may function as an appropriate pull-down load for control of the maximum drain voltage. 3: as the headroom voltage rises after the led current regulator shutdown, the volt- age at the hvs pin will rise as well. zener diode z hvs clamps the hvs pin voltage to a voltage within the absolute maximum rating of the hvs pin. downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 15 HV9805 4.5 headroom voltage regulator headroom voltage at the led current regulator is controlled by the headroom voltage regulator. minimize the power dissipation of the led current regulator and therefore minimize the dc level of the headroom voltage (v hdc ), the dissipation being calculated using equation 4-2 . equation 4-2: the dc level of the boost converter output voltage, the bus voltage, adjusts to the sum total of the dc level of the headroom voltage and the operating voltage of the led load. the bus voltage adapts during regular operation to any changes in the operating voltage of the led load. 4.5.1 the regulation process the headroom voltage regulator adjusts the dc level of the headroom voltage by adjusting the on-time of the boost converter switch. the headroom voltage regulator includes an internal control amplifier with external gain setting network, an internally generated reference voltage and a feedback voltage, provided at the hvs pin by an external resistor divider connected at the drain of the led current regulator pass fet. the regulation process can be described as follows: 1. a deviation of the headroom voltage from the desired headroom voltage produces a current at the output of the control amplifier in proportion to the deviation. 2. the current produces a change in the output voltage at the control amplifier output. 3. the change in voltage at the control amplifier output produces a change in the boost converter switch on-time. 4. the change in on-time produces a change in the boost converter output current. 5. the change in the boost converter output cur- rent produces a change in the bus voltage. 6. the change in the bus voltage then reduces the deviation in headroom voltage. the response characteristic of the control amplifier is determined by the compensation network at the output of the control amplifier. in order to prevent distortion of the line current, it is preferable to drive the boundary conduction mode boost converter with a constant on-time during the course of a line cycle. accordingly, variations in on-time due to headroom voltage variation within the line cycle should be suppressed by tailoring the frequency response characteristic of the control amplifier. a particularly large headroom voltage variation at twice the line frequency is present due to the pulsating nature of power delivery from an ac line. the control amplifier can be effectively compensated with a capacitor in the 1 f to 10 f range in series with a 0.1 k ? to 1 k ? resistor. larger capacitance leads to less on-time variation and less line current distortion, but slows down the response to line voltage changes. larger resistance leads to larger distortion of the line current waveform due to a proportional change between the headroom voltage ripple and the on-time, but results in better damping of the transient response to a line voltage or load voltage disturbance. the headroom voltage is programmed to the desired level using equation 4-3 . equation 4-3: the control amplifier produces the output voltage v hvr according to equation 4-4 . p dis i led v hdc ? = where: p dis = average power dissipation within the led current regulator during normal operation, which includes the dissipation in the pass transistor m crx and the dissipation in the sense resistor r crs v hdc = desired dc level of the headroom voltage, see section 4.5.2 . v ref, hvr v hdc k div ? = k div r hvb r hvb r hvt + --------------------------------- = where: v ref, hvr = reference voltage for the headroom voltage regulator, see dc and ac characteristics table k div = attenuation of the headroom voltage divider r hvt , r hvb = top and bottom resistor of the headroom voltage divider, see typical application circuit downloaded from: http:///
HV9805 ds20005374a-page 16 ? 2015 microchip technology inc. equation 4-4: the output voltage of the control amplifier provides the on-time reference for the boost converter control circuitry, according to equation 4-5 . equation 4-5: 4.5.2 required headroom voltage the desired dc level of the headroom voltage is a trade-off between the efficiency of the led current regulator and the size of the bus capacitor. a smaller bus capacitor reduces cost, but leads to larger headroom voltage ripple. the larger ripple requires a larger dc level of the headroom voltage, leading to higher dissipation within the led current regulator. the larger dissipation reduces efficiency, and vice versa. the desired dc level for the headroom voltage should be greater than the sum of the peak bus voltage ripple and the voltage which appears across the led current sense resistor (1v). equation 4-6: the bus voltage ripple is generally dominated by a quasi sinusoidal ripple component at twice mains frequency (100 hz or 120 hz). this ripple component originates from the pulsating nature of the ac power delivery. for example, suppose that the peak amplitude of the bus voltage ripple amounts to 5v. then, given an additional voltage drop across the current sense resistor of 1v, a headroom voltage of at least 6v is required to keep the led current regulator in regulation throughout the mains line cycle. the amplitude of the bus voltage ripple is directly related to the size of the bus capacitor. the ripple voltage can be estimated for a given value of the bus capacitor as shown in equation 4-7 . equation 4-7: v ? v ref, hvr v hvs ? ?? = iv ? g hvr ? = v hvr iz gain ? = z gain r hvx c hvx + ?? c hvy ?? = where: v hvs = headroom voltage regulator sense voltage at the hvs pin, see typical application circuit ? v = differential voltage at the input of the headroom voltage regulator control amplifier i = output current of the headroom voltage regulator control amplifier g hvr = transconductance of the headroom voltage regulator control amplifier, see dc and ac characteristics table v hvr = output voltage of the headroom voltage regulator control amplifier z gain = impedance of the gain setting network r hvx, c hvx, c hvy = resistance, capacitance of the gain setting components, see typical application circuit v hvs k div v ? hea = t on k hvr v hvr ? = where: t on = on-time reference signal for the boost converter switch k hvr = gain of the on-time modulator, see dc and ac characteristics table v hdc v bus ? v crs + ?? ? where: ? v bus = peak ripple of the bus voltage v bus , for v bus see typical application circuit v crs = current sense resistor voltage, effectively equivalent to the v ref,ccr during normal operation, see dc and ac characteristics table v bus ? i led z bus ? i led 1 22 ?? f mains ? c bus ? ----------------------------------------------------------------- - ? = ? where: z bus = impedance seen at the output of the boost converter f mains = mains frequency, 50 hz or 60 hz c bus = capacitance of the bus capacitor, see typical application circuit downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 17 HV9805 the boost converter produces an output current which, in average, is equal to the led current, but oscillates between zero and twice this average at a rate of twice the line frequency. therefore, the dc level and the peak ripple current amplitude of the led current are about equal. the load of the boost converter is essentially a capacitor in parallel with a current sink. the load behaves more or less like a true integrator giving falling gain of 20 db per decade and 90 phase shift. for stability of the control loop, the error amplifier should not add another 90 of phase shift in the loop around the crossover frequency. therefore, a proportional gain is generally required to give an adequate phase margin around the crossover frequency. an integrating term at lower frequency is required to give the loop high dc accuracy. the headroom voltage regulator operates in a number of modes according to the state of the regulator logic: in the idle state: - the output of the control amplifier is grounded, resulting in zero on-time command. the boost converter is effectively off. in the start state: - the output of the control amplifier is open and an internal 10 a source is enabled to allow gradual charging of the external gain setting network to an output voltage of about 1v. in the run state: - the control amplifier is active, sourcing and sinking current into the gain setting network for closed-loop control of the headroom voltage. 4.6 line current waveform regulator the line current waveform regulator is provided to minimize the harmonic distortion of the line current waveform using a feedback control technique. the regulator adjusts the on-time command signal throughout the ac line cycle to minimize line current distortion. the only user configuration required is to provide sufficient amplitude to the boost inductor current sense signal, as provided to the boost inductor current sense amplifier. the boost inductor waveform is sensed in the return path of the bridge rectifier. adjust the sense resistor r lbs for a peak amplitude of 1v or less. the line current waveform regulator interprets the on-time command signal as a reference for the line current amplitude. a sampling unit within the line current waveform regulator samples the rising boost inductor current of each switching cycle at an instant which is proportional to this on-time reference signal. the sampled value is proportional to the line voltage and, given that the line voltage is generally of sinusoidal shape, the series of samples has a sinusoidal envelope as well. accordingly, a sinusoidal reference for the line current waveform is constructed by sampling the boost inductor current. an error amplifier within the line current waveform regulator compares the line current reference with an averaged version of the true boost inductor current. the average represents the line current as drawn from the ac line. discrepancy between the reference and true current is accumulated by an internal control amplifier and translated into an on-time correction signal. the correction signal is added to the on-time command signal as received from the headroom voltage regulator. in practice, a marked increase in on-time is required near the zero-crossing of the line voltage. downloaded from: http:///
HV9805 ds20005374a-page 18 ? 2015 microchip technology inc. 4.7 voltage comparators operation of the regulator logic is supported by a number of voltage comparators which check for the conditions in table 4-1 . 4.8 overtemperature protection overtemperature causes the regulator logic to switch to the idle state, where converter switching is inhibited. table 4-1: regulator logic operation condition description value true false vddlo v dd supply in undervoltage condition the v dd voltage drops below the disable threshold, v dis (6.75v nominal) the v dd voltage rises above the enable threshold, v ena (7.5v nominal) bvsuv bus voltage in undervoltage condition the v bvs voltage drops below the lower threshold, v uvl (0.4v nominal) the v bvs voltage rises above the upper threshold, v uvu (0.5v nominal) bvsov bus voltage in overvoltage condition the v bvs voltage rises above the upper threshold, v ovu (1.25v nominal) the v bvs voltage drops below the lower threshold, v ovl (1.15v nominal) hvsok headroom voltage at nominal operating level the v hvs voltage rises above the run threshold, v run (1.25v nominal) the v hvs voltage drops below the run threshold, v run (1.25v nominal) table 4-2: overtemperature protection condition description value true false otphi the junction temperature rises above the disable threshold, t dis (145c nominal) the junction temperature falls below the enable threshold, t ena (130c nominal) downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 19 HV9805 4.9 the stop signal the stop signal indicates if a condition exists that should inhibit regular driver operation. the stop signal is true whether any one of the vddlo, bvsuv and bvsov signals are true or an overtemperature of the die is detected. the stop signal is effectively an or function of the three comparator signals and the overtemperature protection signal. 4.10 regulator logic state diagram figure 4-1 shows a state diagram of the regulator logic. figure 4-1: regulator logic state diagram. the logic states and associated state transitions are described in sections 4.10.1 C 4.10.3 . 4.10.1 idle state the driver enters the idle state when power is first applied. the idle state is characterized as follows: boost converter switching disabled; v dd supply operating in linear mode. the led current regulator reference is adjusted to 20% of the nominal led current. the control amplifier of the headroom voltage regulator output is shorted to ground, thus producing zero output voltage and an on-time command signal equal to zero. the logic remains in the idle state as long as the stop signal is true, due to undervoltage on the v dd supply or bus voltage or due to overvoltage on the bus voltage. the stop signal is false upon a cold start because of v dd supply undervoltage. 4.10.2 start state the logic transitions to the start state when the stop signal goes false. the start state enables smooth run up of the bus voltage and remains in place until the headroom voltage of the led current regulator reaches the nominal operating level, as indicated by hvsok. the start state is characterized as follows: boost converter switching enabled; v dd supply operating in switching mode. the led current regulator reference is adjusted to 20% of the nominal led current. the control amplifier of the headroom voltage regulator output is in a high impedance state and an internal 10 a current source is enabled for gradual ramping of the amplifier output to a level of 1v. table 4-3: stop signal condition description value true false stop vddlo, bvsuv, bvsov or otphi is true vddlo, bvsuv, bvsov and otphi are false idle stop start run stop hvsok lin ( 1 ) /20% ( 2 ) /0v ( 3 ) swi ( 1 ) /20% ( 2 ) /1v ( 3 ) swi ( 1 ) /100% ( 2 ) /reg ( 3 ) stop note 1: v dd regulator mode 2: led current regulator reference level 3: headroom voltage regulator mode downloaded from: http:///
HV9805 ds20005374a-page 20 ? 2015 microchip technology inc. 4.10.3 run state the logic transitions to the run state once the headroom voltage has built up to the normal operating level or falls back to the idle state if the stop signals activates. the run state enables regular operation of the led driver. the run state is characterized as follows: boost converter switching enabled; v dd supply operating in switching mode. the led current regulator reference is adjusted to 100% of the nominal led current. the control amplifier of the headroom voltage regulator output is enabled and regulating the boost converter switch on-time in closed-loop mode. the logic reverts to the idle state if the stop signal is true, indicating loss of v dd , bus overvoltage or bus undervoltage. note that hvsok is ignored in the run state. loss of headroom voltage is no reason for immediate concern. maintaining the run state allows the headroom voltage regulator to adjust the on-time, should the dc level of the headroom voltage be less than desired. in addition, hvsok alternates between true and false during regular operation, as the headroom voltage alternates between being higher and lower than the target headroom voltage. 4.11 boost converter operation the boost converter is operated in boundary conduction mode with a nominally constant on-time. such an operating mode inherently produces a line current with the same shape and phase as the line voltage, thus resulting in high power factor operation. idealized waveforms are shown in figure 4-2 . boundary conduction mode refers to an operating mode where the inductor current i bst starts from zero and ends at zero, over the course of a switching cycle, thus tracing out a triangular waveform. figure 4-2: idealized boost converter waveforms 230 v ac , 50 hz, 10w, 400 v dc . 0 5 10 15 20 -600 -500 -400 -300 -200 -100 0 100 200 300 400 500 600 line voltage line current gate drive boost inductor current time (ms) line voltage (v) downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 21 HV9805 the average value of a triangular-shaped current is by nature half the peak amplitude. a low-pass filter and a bridge rectifier shape the triangular boost inductor current into a more or less ripple-free line current, with an amplitude which is equal to half of the peak inductor current. whereas the on-time period is constant, the off-time period changes throughout the line cycle, with the off-time becoming longer as the line voltage increases toward the bus voltage. accordingly, the switching frequency varies over the line cycle, being lowest at peak line voltage and highest near the zero crossing of the line voltage. 4.11.1 valley switching the driver incorporates valley switching (quasi-resonant switching), a technique for reducing switching loss at the turn-on event of the boost fet. valley switching adds a third part to the basic boost inductor waveform where the drain voltage is allowed to swing down towards ground, as shown in figure 4-3 . figure 4-3: valley switching waveform diagram. negative polarity strobe valley strobe boost inductor current drain voltage 1.25v current sense amplifier output 1.25v 1.25v r csa r lbs abc r csa r csa r csa current sense amplifier polarity detector valley strobe generator i bst i bst v drn x yz xy z v rec s HV9805 ~625 mv downloaded from: http:///
HV9805 ds20005374a-page 22 ? 2015 microchip technology inc. the three parts of the switching cycle, as shown in figure 4-3 , are as follows: a C i bst rising linearly; v drn near zero b C i bst falling linearly; v drn near v bus c C i bst reversing; v drn falling towards ground the reversal of the boost inductor current occurs naturally after the boost inductor has returned to zero if the switching fet is maintained in the off state. the resonance is driven by capacitively stored energy at the drain node. figure 4-3 indicates the voltage waveform which would result if the drain voltage resonance is allowed to continue for more than one half cycle. the drain voltage falls either part way or all the way to ground depending on the magnitude of the rectified voltage and the bus voltage. the larger the difference between the rectified line voltage and the bus voltage, the larger the drain voltage swing. the drain voltage swings partially to ground when the rectified line voltage is closer to the bus voltage; the drain voltage swings fully to ground when the rectified line voltage is closer to ground. either way, a gain in efficiency is attained as the capacitively stored energy at the drain node is returned in part or as a whole to the line input capacitor. 4.11.1.1 detection of the valley the detection of the valley involves the boost inductor current sense amplifier, a voltage comparator and an edge detector. the current sense amplifier is arranged as a differential amplifier which follows the boost inductor sense signal with a gain of one and adds an offset voltage of about 1.25v (r csa =10k ? ) to keep the amplifier output in positive territory. note that the boost inductor sense signal itself is predominantly of negative polarity when boost inductor current flows in the resistor in the indicated direction. the offset of 1.25v allows sensing of a negative voltage with 1.25v amplitude at sense resistor node s, as shown in figure 4-3 . the polarity comparator indicates when the boost inductor current turns negative by comparing the output of the sense amplifier with the 1.25v offset level. detection of negative polarity results in arming of the valley strobe generator. a strobe is generated when the boost inductor current turns back to positive polarity. this detection technique requires that the amplitude of the negative boost inductor current and thereby the drain voltage swing exceed some minimum value (for example, 25v). for designs where the difference between the bus voltage and the peak of the rectified line voltage is not all that great, it is required to add a secondary signal to aid the detection. the block diagram and the typical application circuit include the c val capacitor and the r val resistor. the resistor capacitor (rc) network generates a signal which is the time derivative of the drain voltage, thus being of the exact same shape and phase as the boost inductor current swing during the resonance interval. a diode clamping network may be required to prevent overdrive of the sense amplifier when the drain voltage makes fast transitions, such as during turn-off of the boost converter switch. 4.11.1.2 boost converter switch the driver employs source driving for control of the conduction state of the boost converter fet. this method is also known as cascode switching, where a low-voltage fet is arranged in series with a high voltage fet. the cascode switch configuration is capable of fast and low loss switching and is furthermore capable of providing a low loss source of current for powering the v dd supply. the conduction state of a fet is determined by its gate-to-source voltage. the gate of the external high voltage fet is permanently biased for full conduction by the external biasing network (r bst , c bst , z bst ). a voltage of at least 15v should be provided at the gate of the external high voltage fet in a HV9805 application. the source voltage of the external high voltage fet is controlled by the voltage at the drv pin. in turn, the voltage of the drv pin is controlled by a number of low-voltage fets internal to the driver, namely the drv fet and two v dd regulator fets. downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 23 HV9805 4.11.1.3 external fet conduction modes ideally, the external high voltage fet is biased for the full conduction mode during switching operation of the boost converter. conduction of the drv fet causes the voltage of the drv pin to be near ground potential, resulting in a gate-to-source voltage of 15v, if the gate of the external high-voltage fet is biased at 15v. accordingly, the gate-to-source voltage of the external high-voltage fet is well in excess of the threshold voltage of a typical high-voltage fet. consequently, the external high-voltage fet and the cascode switch as a whole are conducting in the full conduction mode. conduction of the v dd fet causes the drv pin voltage to be close to the sum of the v dd voltage, one diode forward voltage drop and the voltage drop across the on-resistance of the fet. if the resulting gate-to-source voltage for the external high voltage is in excess of the threshold voltage of the high-voltage fet, then the cascode switch, which consists of the external high-voltage fet and the v dd fet, conducts in full mode during v dd capacitor charging as well. under certain circumstances, a bias voltage greater than 15v is required to attain full conduction of the external fet and the v dd fet at the gate of the external high-voltage fet. when an external high-voltage fet has a high threshold voltage or when the led driver is designed for a high power level, v dd charges with shorter charging times and higher current levels. the higher current levels raise the voltage drop across the on-resistance of the v dd regulator fet and raise the drv pin voltage, reducing the gate-to-source voltage of the external high-voltage fet. 4.11.1.4 drv pin voltage clamp the voltage at the drv pin may exceed the absolute maximum rating of the drv pin voltage during the turn-off transition, due to a fast rising drain voltage of the external high-voltage fet and its parasitic capacitance. as the drain voltage of the external fet rises, so will the drain voltage of the internal fets. the extent is determined by the ratio of device capacitances and is difficult to calculate. it is advisable to provide a form of voltage clamping at the drv pin to clamp the drain voltage to a level below the maximum voltage rating of the pin. the voltage clamping can be arranged in a number of ways, such as adding an external zener diode between the drv pin and ground, adding a small capacitor at the drv pin to ground, or adding a diode from the drv pin to the zener diode of the bias network of the external high-voltage fet. 4.11.1.5 overcurrent protection of the drv fet the internal drv fet is provided with cycle-by-cycle overcurrent protection to protect the internal drv fet. the drv fet is turned off upon detection of an overcurrent condition. the overcurrent comparator signal is blanked for a short time after the start of the drv fet conduction time to avoid nuisance tripping of the overcurrent protection. 4.11.1.6 on-time on-time for the boost converter switch is provided as the sum of two parts. the headroom voltage regulator provides the first part to the switch on-time, which is regulated with low bandwidth to control the headroom voltage dc level. this part of switch on-time, which is nearly constant over an ac line cycle, results in a near sinusoidal line current waveform when the boost converter operates in the boundary conduction mode as discussed in section 4.11 ?boost converter operation? . in practice, the constant switch on-time results in significant line current distortion near the zero crossings of the ac line voltage. a significant boost in switch on-time is required near the line voltage zero crossings to reduce this line current distortion. the line current waveform regulator provides the second part to the switch on-time, which is regulated with high bandwidth to lower line current distortion. the line current waveform regulator generates a sinusoidal reference for the line current with an amplitude which is controlled by the first part of switch on-time. it then generates the second part of switch on-time to reduce the line current distortion, which minimizes the difference between the reference current and average boost inductor current. the on-time modulator of the boost converter is designed for a nominal on-time (t onn ) of 2.7 s, for more information see the dc and ac characteristics table. the nominal on-time was selected to correspond to a switching frequency of around 70 khz. 4.11.1.7 maximum on-time the adjustment in on-time, as provided by the line current waveform regulator, is particularly large around the zero crossings of the line voltage. in order to prevent excessive switch on-time values, an internal timer is provided to limit on-time to the maximum on-time specification t onh of around 10 s. downloaded from: http:///
HV9805 ds20005374a-page 24 ? 2015 microchip technology inc. 4.11.1.8 maximum off-time an internal timer limits maximum off-time to the maximum off-time specification t ofh of around 100 s. the timer triggers the start of the switching cycle if no drain voltage valley is detected within the maximum off-time period. this timer is instrumental in starting the switching process upon the startup of the boost converter, and restarting the process if valley detection is lost due to insufficient drain voltage swing. 4.11.1.9 boost inductor size a starting value for the boost inductor l bst can be derived from the following set of equations: equation 4-8: the above starting value is generally too large and should be adjusted downward for the following two main reasons: to compensate for component losses the presence of valley switching. the presence of valley switching causes an effective loss of power capability, as the drain voltage resonance does not contribute to the transfer of power. the effect of valley switching is detailed in section 5.2 ?practical power rating of the bcm boost converter? . p ac v ac, rms i ? ac, rms = i ac,peak 2i ? ac, rms = v ac,peak 2v ? ac, rms = i swi,peak 2i ? ac, peak = i swi,peak v ac, peak t onn ? l bst ------------------------------------------ - = resolving: l bst 12 -- - v ac, rms 2 t on, nom ? p ac ------------------------------------------------- - ? = where: p ac = desired power capability of the boost converter v ac,rms = rms line voltage i ac,rms = rms line current v ac,peak = peak line voltage i ac,peak = peak line current i swi,peak = peak switch current t onn = nominal on-time, see dc and ac characteristics table downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 25 HV9805 5.0 design guidance 5.1 power rating of the idealized bcm boost converter the maximum power handling of the boost converter depends on several factors including: the ac line voltage the current rating of the internal switch the presence of component losses the presence of valley switching. table 5-1 lists the power rating of a bcm boost converter assuming: a peak switch current of 700 ma zero component losses no implementation of valley switching. 5.2 practical power rating of the bcm boost converter the maximum power level of an HV9805 boundary mode boost converter design will be lower than the levels listed in table 5-1 . this is due to the presence of valley switching and is estimated to be 25w for 120v ac design, and 50w for 230v ac design. a major loss of power capability is caused by the presence of valley switching. valley switching lowers the attainable power rating because the third part of the switching cycle does not contribute to the transfer of power; in fact, it returns a small portion of the transferred power back to the converter input, as is evident by the negative boost inductor current. furthermore, power rating drops if operation at low line is taken into consideration. as can be seen from table 5-1 , the power rating of the bcm boost converter drops from 29.7w to 25.3w when the line voltage has a 15% decrease for a 120v ac design. 5.3 choice of bus voltage and led load voltage the drain voltage valley is detected by monitoring the polarity reversals of the boost inductor current. a small difference between the bus voltage and the rectified line voltage can lead to an insufficient amplitude of the resonating boost inductor current. accordingly, a certain minimum difference should be maintained between the rectified line voltage and the output voltage of the boost converter. a minimum voltage for the led string voltage of 210vdc is suggested for 120v ac applications and 420vdc for 230v ac applications, where operation for a high-line condition of +15% over nominal is assumed. the need for a large differential between the (peak) line voltage and the boost converter output voltage can be reduced by adding the c val and r val circuit at the boost inductor current sense amplifier, as outlined in section 3.2 ?input pins of the first-stage current sense amplifier (csl, csh)? . 5.4 maximum power rating of a sepic driver the power rating of the sepic converter is lower than the power rating of the boost converter for a given peak current rating of the converter switch. the switch in a sepic configuration carries the output current as well as the input current during switch on-time, thereby lowering the input power capability. accordingly, the maximum power of a sepic design is less than the maximum power rating of a boost design. table 5-1: power rating of the boundary mode boost converter ( note 1 ) nominal line voltage (v rms ) line voltage deviation (%) rms line voltage (v rms ) peak line voltage (v peak ) peak switch current (a peak ) power (w) 120 -15 102 144 0.7 25.3 0 120 170 29.7 +15 138 195 34.2 230 -15 196 276 48.4 0 230 325 56.9 -15 265 374 65.5 note 1: assuming zero component loss and absence of valley switching, as a function of ac line voltage. downloaded from: http:///
HV9805 ds20005374a-page 26 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 27 HV9805 6.0 packaging information 6.1 package marking information legend: xx...x product code or customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. package may or may not in clude the corporate logo. 3 e 3 e 10-lead msop example HV9805 502256 downloaded from: http:///
HV9805 ds20005374a-page 28 ? 2015 microchip technology inc. 10-lead msop package outline (mg) 3.00x3.00mm body, 1.10mm height (max), 0.50mm pitch symbol a a1 a2 b d e e1 e l l1 l2 dimen- sion (mm) min 0.75* 0.00 0.75 0.17 2.80* 4.65* 2.80* 0.50 bsc 0.40 0.95 ref 0.25 bsc 0 o 5 o nom - - 0.85 - 3.00 4.90 3.00 0.60 - - max 1.10 0.15 0.95 0.33 3.20* 5.15* 3.20* 0.80 8 o 15 o jedec registration mo-187, variation ba, issue e, dec. 2004. 7klvglphqvlrqlvqrwvshfl?hglqwkh-('(&gudzlqj drawings are not to scale. 1 10 seating plane gauge plane l l1 l2 e e1 e b a a2 a1 seating plane a a top view side view view a-a view b view b 1 (x4) d note 1 (index area d/2 x e1/2) note: 1. $3lqlghqwl?hupxvwehorfdwhglqwkhlqgh[duhdlqglfdwhg7kh3lqlghqwl?hufdqehdproghg pdunlghqwl?hudqhpehggh gphwdopdunhuru a printed indicator. note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging. note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging. downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 29 HV9805 appendix a: revision history revision a (february 2015) original release of this document. downloaded from: http:///
HV9805 ds20005374a-page 30 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 31 HV9805 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. xx package device device: HV9805: off-line led driver package: mg = 10-lead msop package outline (3.00x3.00 mm body, 1.10 mm height (max), 0.50 mm pitch) environmental: g = lead (pb)-free/rohs-compliant package examples: a) HV9805mg-g: off-line led driver, 10ld msop package -x environmental downloaded from: http:///
HV9805 ds20005374a-page 32 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005374a-page 33 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-075-2 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
ds20005374a-page 28 ? 2015 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 germany - pforzheim tel: 49-7231-424750 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 worldwide sales and service 01/27/15 downloaded from: http:///

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