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agilent HDJD-J822-SCR00 color management system feedback controller data sheet features ?0 to 85 c operation ? 2 c serial interface robust cmos-schmitt input cmos/ttl compatible output multiple color input formats cie xyz, yxy, yu??and rgb 3-channel analog interface to color sensor ?x, y and z channels 3-channel 12-bit pwm output red, green, and blue led channels internal computation of calibration data internal clock generator internal reference voltage generator error flag output external push-button interface only passive components required externally applications backlighting general illumination mood/accent lighting color context sensitive appliances description the hdjd-j822 is a cmos mixed- signal ic designed to be the optical feedback controller of an led-based lighting system. a typical system consists of an array of red, green and blue leds, led drivers, a tri-color photosensor that samples the light output, and the hdjd-j822. the ic interfaces directly to the photosensor, processes the color information and adjusts the light output from the leds until the desired color is achieved. to achieve this, the ic integrates a high-accuracy 10-bit analog-to- digital converter front-end, a color data processing logic core, and a high-resolution 12-bit pwm output generator. by employing a feedback system and the hdjd-j822, the light output produced by the led array maintains its color over time and temperature. in addition, the desired color can be specified using a standard cie color space. in addition, by incorporating a standard i 2 c serial interface, specifying the color of the led array? light output is as simple as picking the color coordinates from the cie color space and writing several bytes of data to the device. the output pwm signals are connected directly to the led drivers as enable signals. the pwm signals control the on-time duration of the red, green and blue leds. that duration is continually adjusted in real-time to match the light output from the led array to the specified, desired color.
2 package dimensions dimensions in inches symbol min. nom. max. a 0.093 0.099 0.104 a1 0.004 0.008 0.012 a2 0.088 0.094 0.100 b 0.013 0.016 0.020 c 0.0090 0.0100 0.0125 d 0.599 0.606 0.613 e 0.292 0.296 0.299 e 0.050 bsc. h 0.394 0.402 0.419 h 0.010 0.015 0.019 l 0.016 0.033 0.050 alpha 0 5 8 eh pin 1 indicator d b e a2 a1 a seating plane c h x 45 0 min. see detail a detail a 7 typ. alpha l parting line
3 part numbering system hdjd - j822 - xx x xx option 00: default packaging type r: tape and reel standard pack product packaging sc: soic top view 24-pin soic pin name type 1 xrst di 2 sleep di 3 clk_sel di 4a1 di 5a0 di 6 sda dio 7 scl di 8 test di 9 color di 10 bright di 11 clk_ext di 12 dvdd dp 13 dvss dp 14 pwm_b do 15 pwm_g do 16 pwm_r do 17 err_flag do 18 avss ap 19 rosc ana 20 vref_ext ana 21 sense_z ana 22 sense_y ana 23 sense_x ana 24 avdd ap legend di digital input pin do digital output pin dio digital bi-directional pin dp digital supply/ground pin ana analog interface pin ap analog supply/ground pin xrst p1 p24 avdd sleep p2 p23 sense_x clk_sel p3 p22 sense_y a1 p4 p21 sense_z a0 p5 p20 vref_ext sda p6 p19 rosc scl p7 p18 avss test p8 p17 err_flag color p9 p16 pwm_r bright p10 p15 pwm_g clk_ext p11 p14 pwm_b dvdd p12 p13 dvss pinout of hdjd-j822 color management system feedback controller
4 pin descriptions xrst (pin 1) global, asynchronous, active-low system reset. when asserted low, xrst resets all registers. minimum reset pulse low is 10 s and must be provided by external circuitry. sleep (pin 2) when asserted high, sleep puts the device into sleep mode. in sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic. clk_sel (pin 3) clk_sel is used to select between internal and external clock modes. internal clock mode is selected when clk_sel=0 and external clock mode is selected when clk_sel=1. a1, a0 (pin 4, pin 5) a1 (msb) and a0 (lsb) define the lower two bits of the i 2 c slave address. sda (pin 6) the sda pin is the i 2 c data i/o pin. sda is a bi-directional pin. the i/o direction is defined by an internal signal generated by the i 2 c interface block. scl (pin 7) the scl pin is the i 2 c clock pin. test (pin 8) connect to digital ground (dvss). color, bright (pin 9, pin 10) color and bright are button interface pins. asserting color high with bright low makes the output color go up a color selection ?lider.?to effect a direction change, color and bright must be asserted simultaneously for at least 0.1 second. now, asserting color with bright low makes the output color go down the color selection slider. button brightness control follows a similar procedure. asserting bright high with color low increases or decreases brightness depending on the direction. to effect a direction change, color and bright must be asserted simultaneously for at least 0.1 second. ( refer to application note 5070 for color selection ?lider. ) clk_ext (pin 11) clk_ext is the external clock input pin. users can choose to use an external clock instead of the internal clock generator by setting clk_sel to high. pwm_r, pwm_g, pwm_b (pin 16, pin 15, pin 14) the pwm_r, pwm_g, and pwm_b output pins drive the external led drivers that drive the led arrays. typically pwm_r drives only the red leds, pwm_g drives only the green leds and pwm_b drives only the blue leds. they are the output enable signals of the red, green and blue led drivers. so, they control the on-time duration of the leds. the assertion level of the pwm* signals can be toggled by the user to support both active-low and active-high enable input pins at the led driver side. this is done by configuring the pwml bit of register config1. err_flag (pin 17) the err_flag pin is asserted high when an error condition is detected. the user can determine the type of error by reading the error register. the error conditions are described in the ?igh level description?section. sense_x, sense_y, sense_z (pin 23, pin 22, pin 21) the sense_x, sense_y and sense_z pins are analog input pins which are tied to the x-channel, y-channel and z-channel of the photosensor output respectively. an averaging filter is placed in between the sensor output and the sense_x, sense_y and sense_z pins. the filter is typically a 68 k ? -1 f single-pole low-pass filter. vref_ext (pin 20) the vref_ext pin is an analog input pin, which provides an external reference voltage for the adc. typically, users will use the internal reference generator to operate the adc. however, in specific application conditions, an external reference may be required. the external reference is enabled by setting the vrefs bit of register config1 high. rosc (pin 19) a 68 k ? precision 1% resistor is connected from the rosc to avss pin for use by the internal oscillator. in external clock mode, rosc can be left floating. (refer to application note 5070 for resistor selection.) dvdd, dvss, avdd, avss (pin 12, pin 13, pin 24, pin 18) hdjd-j822 has separate power ground nets for the analog and digital section. a star connection from a central power source is recommended when designing the wiring to these supply pins. dvdd = digital positive supply dvss = digital ground avdd = analog positive supply avss = analog ground
5 general specifications feature value interface i 2 c 100 khz input color format cie xyz, yxy, yu??and rgb (illuminant e) input sensor signal 0 to 2.5 v (typical configuration) minimum dynamic range sensor output > 500 (adc output code, each channel) during calibration output pwm frequency 610 hz nominal (typical configuration) output pwm resolution 12 bits error flag assertion on err_flag pin indicates an error condition device address control upper 5 bits 10101 binary, lower 2 bits defined by a1:a0 pins in that order supply 5 v digital, 5 v analog (nominal) i/o schmitt-cmos input and cmos/ttl compatible output block diagram xrst avdd sleep sense_x clk_sel sense_y a1 sense_z a0 vref_ext mode select vref sensor programmable amplifier reference voltage adc mux clock sda rosc scl avss test err_flag color pwm_r bright pwm_g clk_ext push_button duty factor system controller control signals pwm_b pwm generator dvdd dvss internal oscillator color controller internal registers control config data: setpoint calibration i2c interface control
6 hdjd-j822 block diagram description function description programmable if the sensor output is not within the required dynamic range, the amplifier? gain can be amplifier changed from unity to 2 to boost the sensor signal. adc analog-to-digital converter. converts the sensor signal from analog to digital. vref reference voltage generator. provides a stable voltage level to the adc. can be bypassed with an external reference generator. internal oscillator generates a clock signal for the logic circuits. can be bypassed with an external clock signal. mode select the device operation mode (normal, sleep, internal/external clock) is determined by the status of the sleep and clk_sel pins. i 2 c interface control serial interface controller. manages the i 2 c communications protocol. internal registers the primary method in which the device is configured. contains a bank of registers. each bit is mapped to a specification, function or mode of operation. the internal registers also contain a range of calibration registers. (refer to the ?igh level description?section and the application note 5070 for calibration procedures). color controller contains the color processing algorithms that operate on the sensor data. the algorithms correct the pwm output duty factors if there is a mismatch between the desired color and actual color produced. converts the input color coordinates into an internally understood format. default input format is cie rgb (illuminant e). pwm generator receives the duty factor values from the color controller and generates 3 pwm signals. system controller performs internal functions ?housekeeping, interfacing between blocks, generating control signals, etc. high level description a hardware reset (by asserting xrst) should be performed before starting any operation. it is assumed that factory calibration was performed prior to deployment of hdjd-j822. calibration is discussed at the end of this section. the user controls and configures hdjd-j822 by programming a set of internal registers. the registers are programmed through the i 2 c protocol ?a standard, synchronous, serial interface. the registers define operation modes such as sensor slope, reference voltage selection, color space format, pwm assertion level, etc. selection between internal and external clock can only be made through pin setup. a typical set-up would be: positive sensor slope internal reference voltage 100 hz (nominal) sensor sample rate 610 hz pwm (nominal) active-high pwm output 2.5 mhz (nominal) internal oscillator hdjd-j822 resets into an ?dle mode and the pwm outputs are held low. if the pwm assertion level bit (pwml) of register config1 is changed to high, the pwm outputs will then be held high. however, since the reset condition for that register bit is low, hdjd-j822 always resets with the pwm outputs held low. the next step after setting up the device is to write the calibration data to the calibration registers (address 0x8a to 0xa8 ). the calibration data is typically stored in an external non-volatile memory. after writing the data, the user can set the pwm enable bit (pwme) of register ctrl1 to begin normal operation.
7 the operation begins with the processor taking in the tri-color sensor? digitized readings from the internal adc. that data is compared to the desired color/ brightness setting. the pwm duty factor is adjusted in response to any error signal generated by that comparison operation. the user can change the color/brightness setting at any time by writing to the appropriate device registers (address 0xe8 to 0xed during normal operation). the feedback and processing operation is repeated at a rate of 100 hz (nominal). the pwm signal is applied to the led drivers and controls the on- time duration of the red, green and blue leds. the user can input the desired color/brightness in a variety of color formats such as cie xyz, yxy, yu??and rgb (illuminant e). there are three indicators in register error that monitor the status of the color management system. refer to application note 5070. factory calibration is needed at a system level to create a ?napshot of the initial conditions of the system. the color management algorithm references the snapshot data. in effect, the calibration data trims out variation in the entire signal chain from leds to sensor to filter to adc. the calibration discussion below is brief. refer to application note 5070 for detailed calibration procedures. first, the device is put into ?pen loop?mode by setting the opmd bit of register config1 to high. in open loop mode, the color management algorithm is turned off. second, all leds are switched on to maximum pwm. during this, the adc output is read out to check if the sensor output is within the dynamic range of the system i.e., 500 < pass < 1000. an optional internal 2x gain (1) can be selected if the adc reading is between 250 and 500. this procedure is performed for each sensor channel. next, only the red leds are switched on. an external camera must be set up to capture the cie co-ordinates (preferably xyz) of the red leds. the scaled xyz readings are then sent to the red led camera calibration registers (address 0xe8 to 0xed during calibration mode). next, the gssr bit of register ctrl2 is set to capture the sensor readings of the red leds. the readings are stored in the adc reading registers (sensor_adcz, sensor_adcy, sensor_adcx registers). the user must read those registers and transfer them to the red led sensor calibration registers (address 0xfa to 0xff). this is repeated for green and blue leds. the rcal bit of register ctrl2 is then set, after which hdjd-j822 will compute the 31 bytes of calibration data : cal_data0 to cal_data30 (2) the 2 pieces of calibration data is noted as (1) , and (2) above. the user will need to read them from the device registers via i 2 c and store them in an external non- volatile memory. they will have to be written to the appropriate registers prior to the start of normal operation, and should be part of the system boot-up sequence.
8 electrical specifications absolute maximum ratings (note 1 & 2) parameter symbol minimum maximum units notes storage temperature t stg_abs -65 150 c digital supply voltage, dvdd to dvss v ddd_abs -0.3 6.0 v analog supply voltage, avdd to avss v dda_abs -0.3 6.0 v input voltage v in_abs -0.3 v ddd + 0.3 v all i/o pins solder reflow peak temperature t l_abs 260 c latch-up current i l_abs -100 100 ma human body model esd rating esd hbm_abs 2 kv all pins, human body model mil883 method 3015 machine model esd rating esd mm_abs 200 v recommended operating conditions parameter symbol minimum typical maximum units notes free air operating temperature t a -40 25 85 c digital supply voltage, dvdd to dvss v ddd 4.5 5 5.5 v analog supply voltage, avdd to avss v dda 4.5 5 5.5 v high level output current i oh 3ma low level output current i ol 3ma external clock frequency f clk_ext 1.8 2.5 3.3 mhz rosc resistor r osc 68 k ? (note 3) vref_ext analog input pin input voltage v ref_ext 2.5 4.0 v sense_* input pins input voltage v sense 0.0 v ref v (note 4) vddd or vdda minus sense_* v diff_sense 1.0 v (note 5) internal reference nominal voltage v ref_int 2.45 2.5 2.55 v (note 6) internal oscillator nominal frequency f clk_int 1.8 2.5 3.3 mhz (note 6) with r osc = 68 k ? internal oscillator frequency variation -5 5 % over temperature with r osc = 68 k ?
9 dc electrical specifications over recommended free air operating temperature range, and v ddd = v dda = 4.5 v/5 v/5.5 v (unless otherwise specified). parameter symbol conditions minimum typical maximum units minimum high level input voltage v ih 0.7 v ddd v ddd v (note 7) maximum low level input voltage v il 0 0.3 v ddd v (note 7) digital input pin schmitt +ve threshold v ipos 0.8 v ddd v (note 7) digital input pin schmitt -ve threshold v ineg 0.2 v ddd v (note 7) digital input pin schmitt hysteresis v ihys 1.0 v (note 7) (note 8) minimum high level output voltage v oh v in = v ih or v il 0.9 v ddd v ddd v (note 9) i oh = 3 ma maximum low level output voltage v ol v in = v ih or v il 00.4v (note 10) i ol = 3 ma dynamic digital supply current i ddd_dyn clk_sel=1 4 ma (note 11) f clk_ext = 3.3 mhz sleep-mode digital supply current i ddd_slp 15 a standby digital supply current i ddd_stnby clk_sel=1 15 a dynamic analog supply current i dda_dyn clk_sel=1 3 ma (note 11) f clk_ext = 3.3 mhz sleep-mode analog supply current i dda_slp 15 a standby analog supply current i dda_stnby clk_sel=1 15 a
10 i 2 c timing (sda, scl) symbol parameter min. max. units f scl scl clock frequency 0 100 khz t hd:sta (repeated) start condition hold time 4.0 - s t hd:dat data hold time 0 3.45 s t low scl clock low period 4.7 - s t high scl clock high period 4.0 - s t su:sta repeated start condition setup time 4.7 - s t su:dat data setup time 250 - ns t su:sto stop condition setup time 4.0 - s t buf bus free time between start and stop conditions 4.7 - s figure 1. i 2 c bus timing waveforms. notes: 1. the ?bsolute maximum ratings?are those values beyond which damage to the device may occur. the device should not be operate d at these limits. the parametric values defined in the ?lectrical characteristics?table are not guaranteed at the absolute maximum rati ngs. the ?ecommended operating conditions?table will define the conditions for actual device operation. 2. unless otherwise specified, all voltages are referenced to ground. 3. a 1% precision resistor is recommended. this resistor is tied from the rosc pin to ground. 4. v ref = v ref_int in internal reference configuration. v ref = v ref_ext in external reference configuration. 5. the voltage level at any of the sense_* pins must be lower than v ddd or v dda (whichever is lower) by at least v diff_sense volts. 6. t a = 25 c. room temperature. 7. applies to all di pins. 8. guaranteed by design. 9. applies to all do pins. sda is an open-drain nmos. minimum v oh depends on the pull-up resistor value. 10. applies to all do and dio pins. 11. dynamic testing is performed when the ic is operating in a mode representative of typical operation. t hd:sta t low t high t su:dat t hd:dat t su:sta t su:sto t buf s scl sda sr p s t hd:sta
11 notes on sampling frequency and pwm output frequency the sampling frequency, f samp , which is the frequency at which hdjd-j822 samples the tricolor photosensor, is related to the system clock frequency, f clk . the output pwm frequency, f pwm , is also related to f clk . the system clock is sourced from either the internal oscillator or an external clock. calculation example: f clk = 2.5 mhz (nominal) f samp =f clk /25087 = 100 hz (nominal) f pwm = f clk /4095 = 610 hz (nominal) the internal oscillator frequency varies from part-to-part but it will not vary significantly during operation. register description the user controls and configures hdjd-j822 by programming a set of internal registers, through the i2c protocol. refer to application note 5070 for programming guide and register description. figure 2. start/stop condition. s p start condition stop condition sda scl i 2 c interface description the programming interface to hdjd-j822 is a standard 2-wire serial bus, which follows the i 2 c data transmission protocol. this protocol defines a transmitter as a device that sends data to the bus and a receiver as a device that receives data from the bus. a master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer. a device addressed by the master is called a slave . both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. the bus consists of a serial clock (scl) and a serial data (sda) line. both lines are bi-directional and connected to the positive power supply through a pull-up resistor. when the bus is free, both lines are high. hdjd-j822? i 2 c bus interface always operates as a slave transceiver in standard mode. standard mode has a data transfer rate of up to 100 kbit/s. start/stop condition to begin an i 2 c data transfer, the master must send a unique signal to the bus called a start condition. this is defined as a high to low transition on the sda line while scl is high. the master terminates the transfer by sending another unique signal to the bus called a stop condition. this is defined as a low to high transition on the sda line while scl is high. the bus is considered to be busy after a start (s) condition. it will be considered free a certain time after the stop (p) condition. the bus stays busy if a repeated start (sr) is sent instead of a stop condition. the start and repeated start conditions are functionally identical.
12 data transfer the master initiates data transfer after a start condition. data is transferred in bits with the master generating one clock pulse for each bit sent. for a data bit to be valid, the sda data line must be stable during the high period of the scl clock line. only during the low period of the scl clock line can the sda data line change state to either high or low. figure 3. data bit transfer. a complete data transfer is 8-bits long or 1-byte. each byte is sent most significant bit (msb) first followed by an acknowledge or not acknowledge bit. each data transfer can send an unlimited number of bytes. figure 4. data byte transfer. sda scl msb lsb 12 89 ack 12 8 9 no ack s or sr sr or p start or repeated start condition stop or repeated start condition msb lsb p sr sda scl msb lsb 12 89 ack 12 8 9 no ack s or sr sr or p start or repeated start condition stop or repeated start condition msb lsb p sr
13 acknowledge/not acknowledge the receiver must always acknowledge each byte sent in a data transfer. in the case of the slave-receiver and master- transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either stop the transfer or generate a repeated start to start a new transfer. figure 5. slave-receiver acknowledge. in the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. the master can then send a stop or repeated start condition to begin a new data transfer. in all cases, the master generates the acknowledge or not acknowledge scl clock pulse. figure 6. master-receiver acknowledge. 8 9 sda (slave-receiver) sda (master-transmitter) scl (master) lsb acknowledge acknowledge clock pulse sda pulled low by receiver sda left high by transmitter 89 sda (slave-transmitter) sda (master-receiver) scl (master) lsb p sr not acknowledge acknowledge clock pulse stop or repeated start condition sda left high by receiver sda left high by transmitter
14 addressing each device on the i 2 c bus needs to have a unique address. this is the first byte that is sent by the master-transmitter after the start condition. the protocol defines the address as the first seven bits of the first byte. the eighth bit or least significant bit (lsb) determines the direction of data transfer. a ?ne?in the lsb of the first byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). a ?ero?in this position indicates that the master will write data to the addressed slave (master- transmitter and slave-receiver). a device whose address matches the address sent by the master will respond with an acknowledge for the first byte and set itself up as a slave-transmitter or slave- receiver depending on the lsb of the first byte. the slave address in hdjd-j822 is made up of a fixed part and a programmable part. the fixed part is a6 to a2 and is set as shown in figure 7. the programmable part is a1 and a0, which is set by external package pins. the programmable address pins allows a maximum of four hdjd-j822 chips on the same i 2 c bus to be addressed (address range from 54h to 57h). figure 7. slave addressing. data format hdjd-j822 uses a register-based programming architecture. each register has a unique address and controls a specific function inside the chip. to write to a register, the master first generates a start condition. then it sends the slave address for the device it wants to communicate with. the least significant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then writes the new register data. once the slave acknowledges, the master generates a stop condition to end the data transfer. figure 8. register byte write protocol. msb lsb r/w a1 a6 a5 a4 a3 a2 a0 slave address 10 0 11 a6 a5 a4 a3 a2 a1 a0 w a s a p d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 master sends slave address master writes register address master writes register data master will write data start condition stop condition slave acknowledge a slave acknowledge slave acknowledge
15 to read from a register, the master first generates a start condition. then it sends the slave address for the device it wants to communicate with. the least significant bit (lsb) of the slave address must indicate that the master wants to write to the slave. the addressed device will then acknowledge the master. the master writes the register address it wants to access and waits for the slave to acknowledge. the master then generates a repeated start condition and resends the slave address sent previously. the least significant bit (lsb) of the slave address must indicate that the master wants to read from the slave. the addressed device will then acknowledge the master. the master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. the master then generates a stop condition to end the data transfer. figure 9. register byte read protocol. a6 a5 a4 a3 a2 a1 a0 w a s a d7 d6 d5 d4 d3 d2 d1 d0 master sends slave address master writes register address master will write data start condition slave acknowledge slave acknowledge a6 a5 a4 a3 a2 a1 a0 r sr master sends slave address master will read data repeated start condition a p d7 d6 d5 d4 d3 d2 d1 d0 master reads register data stop condition a master not acknowledge slave acknowledge
16 application diagrams typical operation* button mode operation* refer to application note 5070 for implementation details. *the sda pull-up is only required at system level. it is shown in the diagram for reference only. ch_x ch_y ch_z sensor avdd en_red en_green en_blue led driver dvdd control bus 0 v 2.5 v sense_* vref = internal = 2.5 v xrst clk_ext a0 a1 clk_sel sda scl test color bright pwm_r pwm_b err_flag sense_x sense_y sense_z vref_ext rosc dvdd pwm_g dvss avdd avss sleep dvdd lpf lpf lpf lpf 68 k ? , 1 f passive low pass filter 68 k ? ch_x ch_y ch_z sensor avdd en_red en_green en_blue led driver dvdd control bus 0 v 2.5 v sense_* vref = internal = 2.5 v dvdd xrst clk_ext a0 a1 clk_sel sda scl test color bright pwm_r pwm_b err_flag sense_x sense_y sense_z vref_ext rosc dvdd pwm_g dvss avdd avss sleep dvdd lpf lpf lpf lpf 68 k ? , 1 f passive low pass filter 68 k ?
17 wa b c d e f min. max. min. max. min. max. min. max. min. max. min. max. min. max. 24.4 26.4 12.80 13.20 98 102 225.75 226.25 326 330.25 1.95 2.45 2 2.8 package tape and reel dimensions 24 pin wide body carrier tape notes: 1. 10 sprocket hole pitch cumulative tolerance is 0.2mm. 2. camber not to exceed 1 mm in 100 mm. 3. material: black conductive advantek polystyrene. 4. a0 and b0 measured on a plane 0.3 mm above the bottom of the pocket. 5. k0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7. dimensions are in millimeters. 0.3 0.1 4 0.1 *see note 1 2 0.1 *see note 6 12 0.1 r0.3 max. section a-a r0.5 typ. ? 1.5 0.1 a0 a0 = 10.9 mm 0.1 b0 = 16.0 mm 0.1 k0 = 3.0 mm 0.1 k0 b0 11.5 0.1 *see note 6 1.75 0.1 a a 1.55 + 1.00/?.05 dia. 24 0.3 peak fixed reels d330 p5045 w24/4 peak w f e part no. (variable) size (variable) abcd legend w width a shaft diameter b hub diameter c window size d total reel diameter e shaft key hole f reel thickness notes: 1. material: polystyrene (blue). 2. antistatic coated. 3. flange warpage: 3 mm maximum. 4. all dimensions are in millimeters. 5. esd ?surface resistivity: 10 5 to 10 11 ? /sq.
www.agilent.com/semiconductors for product information and a complete list of distributors, please go to our web site. for technical assistance call: americas/canada: +1 (800) 235-0312 or (916) 788-6763 europe: +49 (0) 6441 92460 china: 10800 650 0017 hong kong: (+65) 6756 2394 india, australia, new zealand: (+65) 6755 1939 japan: (+81 3) 3335-8152(domestic/interna- tional), or 0120-61-1280(domestic only) korea: (+65) 6755 1989 singapore, malaysia, vietnam, thailand, philippines, indonesia: (+65) 6755 2044 taiwan: (+65) 6755 1843 data subject to change. copyright ?2004 agilent technologies, inc. october 11, 2004 5989-1321en

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