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1 datasheet caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2012, 2015. all rights reserved intersil is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. multi-cell li-ion battery manager isl94212 the isl94212 li-ion battery manager ic supervises up to 12 series connected cells. the part provides accurate monitoring, cell balancing and extensive system diagnostics functions. three cell balancing modes are provided: manual balancing mode, timed balancing mode and auto balance mode. the auto balance mode terminates balancing functions when a charge transfer value has been met. the isl94212 communicates to a host microcontroller via an spi interface and to other isl94212 devices using a robust, proprietary, two-wire daisy chain system. the isl94212 is offered in a 64 ld tqfp package and is specified for an operational te mperature range of -40c to +85c. applications ? light electric vehicle (lev); e-moto; e-bike ? battery backup systems; energy storage systems (ess) ?solar farms ? portable and semi-portable equipment features ? up to 12-cell voltage monitors, support li-ion coo 2 , li-ion mn 2 o 4 , and li-ion fepo4 chemistries ? cell voltage measurement accuracy 10mv ? 13-bit cell voltage measurement ? pack voltage measurement accuracy 180mv ? 14-bit pack voltage and temperature measurements ? cell voltage scan rate of 19.5s per cell (234s to scan 12 cells) ? internal temperature monitoring ? up to four external temperature inputs ? robust daisy chain communications system ? integrated system diagnostics for all key internal functions ? hardwired and communicatio ns based fault notification ? integrated watchdog shuts down device if communication is lost ? 7a shutdown current: enable = v ss ?2mbps spi isl94212 dhi2 dlo2 sclk dout din cs host data ready fault to other devices (optional) en monitor board (master or standalone) micro isl94212 dhi1 dlo1 monitor board (dai sy chain - optional) dhi2 dlo2 vg1 vg1 vg1 vg1 vg2 vg2 vg2 figure 1. typical application april 23, 2015 fn7938.1
isl94212 2 fn7938.1 april 23, 2015 submit document feedback table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 recommended operating conditions . . . . . . . . . . . . . . . . . . 7 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . .15 device description and operation . . . . . . . . . . . . . . . . . . . . 21 power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 measurement modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 measurement mode commands . . . . . . . . . . . . . . . . . . . . . . 21 scan once . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan mixed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 scan continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 measure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 cell voltage measurement accuracy . . . . . . . . . . . . . . . . . . 24 temperature monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 cell balancing functions . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 balance setup register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 balance status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 manual balance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 timed balance mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 auto balance mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 balance fet drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 device setup register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 cell balance enabled register . . . . . . . . . . . . . . . . . . . . . . . . . 30 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 spi interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 full duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 non-daisy chain systems . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 normal communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 alarm signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 communication faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 fault response in sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . 34 example communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 daisy chain systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 daisy chain ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 communications protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 communication sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 daisy chain addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 daisy chain commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 identify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ack (acknowledge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 nak (not acknowledge). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 address all. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 alarm signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 watchdog function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 communications faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 communication failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 scan counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 daisy chain communications conflicts . . . . . . . . . . . . . . . . 45 memory checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 settling time following diagnostic activity . . . . . . . . . . . . 45 open wire test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 cell balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 fault signal filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 fault diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 fault response in sleep mode . . . . . . . . . . . . . . . . . . . . . . . . 50 communication and measurement diagrams . . . . . . . . . . 50 measurement timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 51 command timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 response timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . 53 communication and measurement timing tables . . . . . . 56 measurement timing tables. . . . . . . . . . . . . . . . . . . . . . . . . . 56 command timing tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 response timing tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 system registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 cell voltage data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 temperature data, second ary voltage reference data, scan count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 fault registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 setup registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 cell balance registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 reference coefficien t registers . . . . . . . . . . . . . . . . . . . . . . . 69 cells in balance register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 device commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 nonvolatile memory (eeprom) checksum . . . . . . . . . . . . . . 71 applications circuits information . . . . . . . . . . . . . . . . . . . . 72 typical applications circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 72 typical application circuits. . . . . . . . . . . . . . . . . . . . . . . . . . 73 notes on board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
isl94212 3 fn7938.1 april 23, 2015 submit document feedback component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 operating the isl94212 with reduced cell counts . . . . . . . 78 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . .79 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 voltage reference bypass capacitor . . . . . . . . . . . . . . . . . . . 82 cell balancing circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 cell voltage measurements during balancing. . . . . . . . . . . . 83 balancing with scan continuous mode enabled . . . . . . . . . . 83 daisy chain communications system . . . . . . . . . . . . . . . . . . 83 external inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 board level calibration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 worked examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 voltage reference check calculation . . . . . . . . . . . . . . . . . . . 86 cell balancing ? manual mode . . . . . . . . . . . . . . . . . . . . . . . . 87 cell balancing ? timed mode . . . . . . . . . . . . . . . . . . . . . . . . . 87 cell balancing ? auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
isl94212 4 fn7938.1 april 23, 2015 submit document feedback pin configuration isl94212 (64 ld 10x10 tqfp) top view ordering information part number ( notes 2 , 3 , 4 ) part marking trim voltage, v nom (v) temp. range (c) package (rohs compliant) pkg. dwg. # ISL94212INZ ( note 1 ) ISL94212INZ 3.3 -40 to +85 64 ld tqfp q64.10x10d isl94212evkit1z evaluation kit notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 terminatio n finish, which is rohs compliant and compatible with both snpb and pb-free soldering operation s). intersil pb-free products are msl classified at pb-free peak reflow temperatures th at meet or exceed the pb-free requirements of ipc/jedec j std -020. 3. for moisture sensitivity level rating (msl) for the package, please see the intersil isl94212 . for more information on handling and processing moisture sensitive devices, please see techbrief tb363 . 4. for other trim options, please contact marketing . data ready fault dgnd comms select 1 comms select 2 dnc base dnc v3p3 cb10 vc9 cb9 vc8 cb8 vc7 cb7 vc6 cb2 vc1 cb1 vc0 vss vss nc ext2 cb12 vc12 vbat vbat nc dhi2 dlo2 nc ext1 nc nc cb6 vc5 cb5 vc10 cb11 vc11 en vc4 cb4 vc3 cb3 vc2 ext3 nc tempreg ext4 vddext sclk/dhi1 cs /dlo1 nc din/nc dout/nc v2p5 vcc comms rate 0 comms rate 1 ref dnc 48 47 46 45 44 43 42 41 40 39 38 1 2 3 4 5 6 7 8 9 10 11 17 18 19 20 21 22 23 24 25 26 27 64 63 62 61 60 59 58 57 56 55 54 12 13 14 15 16 28 29 30 31 32 53 52 51 50 49 37 36 35 34 33
isl94212 5 fn7938.1 april 23, 2015 submit document feedback pin descriptions symbol pin number description vc0, vc1, vc2, vc3, vc4, vc5, vc6, vc7, vc8, vc9, vc10, vc11, vc12 20, 18, 16, 14, 12, 10, 8, 6, 4, 2, 64, 62, 60 battery cell voltage inputs. vcn connects to the positi ve terminal of celln and the negative terminal of celln+1. (vc12 connects only to the positive terminal of cell12 and vc0 only connects with the negative terminal of cell1.) cb1, cb2, cb3, cb4, cb5, cb6, cb7, cb8, cb9, cb10, cb11, cb12 19, 17, 15, 13, 11, 9, 7, 5, 3, 1, 63, 61 cell balancing fet control outputs. each output cont rols an external fet which provides a current path around the cell for balancing. vbat 58, 59 main ic supply pins. connect to the mo st positive terminal in the battery string. vss 21, 22 ground. these pins connect to the mo st negative terminal in the battery string. ext1, ext2, ext3, ext4 24, 26, 28, 30 external temperature monitor or general purpose inputs . the temperature inputs are intended for use with external resistor networks using ntc type thermistor sense elements but may also be used as general purpose analog inputs at the user?s discretion. 0v to 2.5v input range. tempreg 29 temperature monitor voltage regulator output. this is a switched 2.5v output, which supplies a reference voltage to external ntc thermistor circuits to provide ratiometric adc inputs for temperature measurement. vddext 32 external v3p3 supply input/output. connected to th e v3p3 pin via a switch, this pin may be used to power external circuits from the v3p3 supply. the swit ch is open when the isl94212 is placed in sleep mode . ref 33 2.5v voltage reference decoupling pin. connect a 2. 0f to 2.5f x7r capacitor to vss. do not connect any additional external load to this pin. vcc 34 analog supply voltage input. connect to v3p3 via a 33 resistor. connect a 1f capacitor to ground. v2p5 35 internal 2.5v digital supply decoup ling pin. connect a 1f capacitor to dgnd. v3p3 36 3.3v digital supply voltage input. connect the emitter of the external npn regulator transistor to this pin. connect a 1f capacitor to dgnd. base 38 regulator control pin. connect the external npn transistor?s base. do not let this pin float, dnc 37, 39, 48 do not connect. leave pins floating. comms select 1 41 communications port 1 mode select pin. connect via a 1k ? resistor to v3p3 for daisy chain communications on port 1 or to dgnd for spi operation on port 1. comms select 2 40 communications port 2 mode select pin. connect via a 1k ? resistor to v3p3 to enable port 2 or to dgnd to disable this port. comms rate 0, comms rate 1 43, 42 daisy chain communications data rate setting. connect via a 1k ? resistor to dgnd (?0?) or to v3p3 (?1?) to select between various communication data rates. dgnd 44 digital ground. fault 45 logic fault output. asserted low if a fault condition exists. data ready 46 spi data ready. asserted low when the device is ready to transmit data to the host microcontroller. en 47 enable input. tie to v3p3 to enable the part. tie to dgnd to disable (all ic functions are turned off). dout/nc 49 serial data output (spi) or nc (daisy chain). 0v to 3.3v push-pull output. din/nc 50 serial data input (spi) or nc (daisy chain). 0v to 3.3v input. cs /dlo1 52 chip-select, active low 3.3v input (spi) or daisy chain port 1 lo connection. sclk/dhi1 53 serial-clock input (spi) or daisy chain port 1 hi connection. dhi2 56 daisy chain port 2 hi connection. dlo2 55 daisy chain port 2 lo connection. nc 23, 25, 27, 31, 51, 54, 57 no internal connection.
isl94212 6 fn7938.1 april 23, 2015 submit document feedback block diagram vc12 input buffer/level shi ft and fault detection dhi 2 vc mux adc temp mux ic temp mux sclk/dhi 1 cs /dlo 1 din dout dlo 2 comms select 2 control logic and communications daisy and spi comms tempreg data ready v3p3 cb12 vc11 ext1 ext2 ext3 ext4 dgnd comms select 1 vbat vss cb11 vc10 cb10 vc9 cb9 vc8 cb8 vc7 cb7 vc6 cb6 vc5 cb5 vc4 cb4 vc3 cb3 vc2 cb2 vc1 cb1 vc0 vreg ref vref en comms rate 1 comms rate 0 base fault vcc vddext v2p5 v2p5 reference chain
isl94212 7 fn7938.1 april 23, 2015 submit document feedback absolute maximum rating s thermal information unless otherwise specified. with respect to vss. din, sclk, cs , dout, data ready , comms select n, extn, tempreg, ref, v3p3, vcc, fault , comms rate n, base, en, vddext. . . . . . . . . . . . . . . . . . . . . . .-0.2v to 4.1v v2p5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.2v to 2.9v vbat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 63v dhi1, dlo1, dhi2, dlo2 . . . . . . . . . . . . . . . . . . . . . . .-0.5v to (vbat + 0.5v) vc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 9.0v vc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 18v vc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 18v vc3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 27v vc4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 27v vc5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 36v vc6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 36v vc7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 45v vc8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 45v vc9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 54v vc10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 63v vc11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 63v vc12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to + 63v vcn (for n = 0 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vbat + 0.5v cbn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to vbat + 0.5v cbn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . v(vcn-1) - 0.5v to v(vcn-1) + 9v cbn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . .v(vcn) - 9v to v(vcn) + 0.5v current into vcn, vbat, vss (latch up test) . . . . . . . . . . . . . . . . . . 100ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 2kv machine model (tested per jesd22a115-a) . . . . . . . . . . . . . . . . . . 200v charge device model (tested per jesd22-c101d) . . . . . . . . . . . . . 750v latch-up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma note: dout, data ready , and fault are digital outputs and should not be driven from external sources. v2p5 , ref, tempreg and base are analog outputs and should not be driven from external sources. thermal resistance (typical) ja (c/w) jc (c/w) 64 ld tqfp package ( notes 5 , 6 ) . . . . . . . 42 9 max continuous package power dissipation . . . . . . . . . . . . . . . . . .400mw storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55c to +125c max operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . .+125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions t a , ambient temperature range . . . . . . . . . . . . . . . . . . . . . -40c to +85c v bat . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6v to 60v v bat (daisy chain operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10v to 60v vcn (for n = 1 to 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . v(vcn-1) to v(vcn-1) + 5v vc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.1v to 0.1v cbn (for n = 1 to 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v(vcn-1) to v(vcn-1) + 9v cbn (for n = 10 to 12). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v(vcn) - 9v to v(vcn) din, sclk, cs , dout, data ready , comms select 1, comms select 2, tempreg, ref, v3p3, vcc, fault , comms rate 0, comms rate 1, en, vddext. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 3.6v ext1,ext2,ext3,ext4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0v to 2.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 6. for ? jc , the ?case temp? location is taken at the package top center. electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. parameter symbol test conditions min ( note 7 )typ max ( note 7 )units power-up condition threshold v por v bat voltage (rising) 4.8 5.1 5.6 v power-up condition hysteresis v porhys 400 mv initial power-up delay t por time after vpor condition v ref from 0v to 0.95 x v ref (nom) (en tied to v3p3) device can now communicate 27.125 ms enable pin power-up delay t pud delay after en = 1 to v ref from 0v to 0.95 x v ref (nom) (v bat = 39.6v) - device can now communicate 27.125 ms
isl94212 8 fn7938.1 april 23, 2015 submit document feedback v bat supply current i vbat non-daisy chain configuration. device enabled. no communications, adc, measurement, balancing or open wire detection activity. 6v 10 35 75 a 39.6v 10 64 220 a 60v 10 90 230 a i vbatmaster daisy chain configuration ? master device. enabled. no communications, adc, measurement, balancing or open wire detection activity. 6v 400 530 660 a 39.6v 500 680 900 a 60v 550 750 1000 a peak current when daisy chain transmitting 18 ma i vbatmid daisy chain configuration ? mid stack device. enabled. no communications, adc, measurement, balancing or open wire detection activity. 6v 700 1020 1300 a 39.6v 900 1250 1600 a 60v 1000 1400 1700 a peak current when daisy chain transmitting 18 ma i vbattop daisy chain configuration ? top device. enabled. no communications, adc, measurement, balancing or open wire detection activity. 6v 400 530 660 a 39.6v 500 680 900 a 60v 550 750 1000 a peak current when daisy chain transmitting 18 ma i vbatsleep1 sleep mode (en = 1, daisy chain configuration). 10 19 36 a i vbatsleep2 sleep mode (en = 1, standalone, non-daisy chain) 5 9 18 a i vbatshdn shutdown. device ?off? (en = 0) (daisy chain and non-daisy chain configurations) 5 7 18 a v bat supply current tracking. sleep mode. i vbat sleep en = 1, daisy chain sleep mode configuration. v bat current difference between any two devices operating at the same temperature and supply voltage. 0 10.5 a v bat incremental supply current, balancing i vbatbal all balancing circuits on . incremental current: add to non-balancing v bat current. v bat = 39.6v 200 300 400 a v3p3 regulator voltage (normal) v 3p3n en = 1, load current range 0 to 5 ma. v bat = 39.6v 3.2 3.35 3.5 v v3p3 regulator voltage (sleep) v 3p3s en = 1, load current range. no load. (sleep). v bat = 39.6v 2.4 2.7 3.05 v v3p3 regulator control current i base current sourced from base output. v bat = 6v 1 1.5 ma v3p3 supply current i v3p3 device enabled no measurement activity, normal mode 0.8 1 1.3 ma v ref reference voltage v ref en = 1, no load, normal mode 2.5 v electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 9 fn7938.1 april 23, 2015 submit document feedback vddext switch resistance r vddext switch on-resistance, v bat = 39.6v 5 12 22 ? vcc supply current i vcc device enabled (en = 1) . standalone or daisy configuration. no adc or daisy chain communications active. 2.0 3.25 5.0 ma i vccactive1 device enabled (en = 1) . standalone or daisy configuration. average current during 16ms scan continuous operation. v bat = 39.6v 6.0 ma i vccsleep device enabled (en = 1). sleep mode. v bat = 39.6v 2.4 a i vccshdn device disabled (en = 0). shutdown mode. 0 1.2 9.0 a measurement specifications cell voltage input measurement range v cell vc(n) - vc(n-1). for design reference. 05 v cell monitor voltage resolution v cellres [vc(n)-vc(n-1)] lsb step size (13-bit signed number), 5v full scale value 0.61 mv isl94212 cell monitor voltage error (absolute) ? v cella absolute cell measurement error (cell measurement error compared with applied voltage with 1k series resistor.) temperature = 0c to +50c, v cell = 2.6v to 4.0v -10 10 mv temperature = +50c to +85c, v cell = 2.0v to 4.3v -25 25 mv temperature = -40c to 0c, v cell = 2.0v to 4.3v -35 35 mv isl94212 cell monitor voltage error (relative) ? v cellb relative cell measurement error (max absolute cell measurement error min absolute cell measurement error) temperature = 0c to +50c 0 7.5 mv temperature = -40c to 0c 0 7.5 mv temperature = +50c to +85c 0 20 mv cell input current. note: cell accuracy figures assume a fixed 1k resistor is placed in series with each vcn pin (n = 0 to 12) i vcell vc0 input -2.0 -1 -0.5 a vc1, vc2, vc3 inputs -3.0 -2 -0.9 a vc4 input -0.8 0 0.9 a vc5, vc6, vc7, vc8, vc9, vc10, vc11 inputs 0.5 2 3.2 a vc12 input 0.4 1 2.0 a v bat monitor voltage resolution vbat res adc resolution referred to input (v bat ) level. 14b unsigned number. full scale value = 79.67v. 4.863 mv v bat monitor voltage error ? v bat temperature = 0c to +50c, measured at v bat = 31.2v to 43.2v -180 180 mv temperature = 0c to +50c, measured at v bat = 24v to 48v -230 230 mv temperature = 0c to +50c, measured at v bat = 6v to 59.4v -390 390 mv temperature = -40c to +85c, measured at v bat = 31.2v to 39.6v -320 320 mv temperature = -40c to +85c, measured at v bat = 6v to 48v -440 440 mv temperature = -40c to +85c, measured at v bat = 6v to 59.4v -650 650 mv electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 10 fn7938.1 april 23, 2015 submit document feedback external temperature monitoring regulator v temp voltage on tempreg output. (0 to 2ma load) 2.475 2.5 2.525 v external temperature output impedance r temp output impedance at tempreg pin. 0 0.1 0.2 ? external temperature input range v ext extn input voltage range. for design reference. 0 2344 mv external temperature input pull-up r exttemp pull-up resistor to v tempreg applied to each input during measurement 10 m ? external temperature input offset v extoff v bat = 39.6v -12 12 mv external temperature input inl v extinl -0.65 0.65 mv external temperature input gain error v extg -8 18.5 mv internal temperature monitor error v intmon 10 c internal temperature monitor resolution t intres output resolution (lsb/c). 14b number. 31.9 lsb/c internal temperature monitor output t int25 output count at +25c 9180 decimal over-temperature protection specifications internal temperature limit threshold t intsd balance stops and auto scan stops. temperature rising or falling. 150 c external temperature limit threshold t xt corresponding to 0v (min) and v tempreg (max) external temperature input vo ltages higher than 15/16 v tempreg are registered as open input faults. 0 16383 decimal fault detection system specifications undervoltage threshold v uv programmable. corresponding to 0v (min) and 5v (max) 08191 decimal overvoltage threshold v ov programmable. corresponding to 0v (min) and 5v (max) 08191 decimal v3p3 power-good window v 3ph 3.3v power-good window high threshold. v bat = 39.6v 3.7 3.90 4.05 v v 3pl 3.3v power-good wind ow low threshold. v bat = 39.6v 2.5 2.65 2.8 v v2p5 power-good window v 2ph 2.5v power-good window high threshold. v bat = 39.6v 2.55 2.7 2.9 v v 2pl 2.5v power-good wind ow low threshold. v bat = 39.6v 1.90 2.0 2.15 v vcc power-good window v vcch vcc power-good window high threshold. v bat = 39.6v 3.6 3.75 4.0 v v vccl vcc power-good window low threshold. v bat = 39.6v 2.55 2.7 2.85 v v ref power-good window v rph v ref power-good window high threshold. v bat = 39.6v 2.525 2.7 2.9 v v rpl v ref power-good window low threshold. v bat = 39.6v 2.0 2.30 2.50 v electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 11 fn7938.1 april 23, 2015 submit document feedback v ref reference accuracy error v racc v ref value calculated using stored coefficients. v bat = 39.6v, v ref typical = 2.5v ( see ? voltage reference check calculation ? on page 86. ) temperature = 0c to +50c -15 15 mv temperature = -40c to 0c -40 40 mv temperature = +50c to +85c -22 22 mv voltage reference check timeout t vref time to check voltage reference value from power-on, enable or wake up 20 ms oscillator check timeout t osc time to check main oscillato r frequency from power-on, enable or wake up 20 ms oscillator check filter time t oscf minimum duration of fault required for detection 100 ms cell open wire detection (see sections ? scan wires ? on page 22 , ? iscn, pin37, pin39 ? on page 30 , and ? open wire test ? on page 45 .) open wire current i ow iscn bit = 0; v bat = 39.6v 0.125 0.15 0.175 ma iscn bit = 1; v bat = 39.6v 0.85 1.0 1.15 ma open wire detection time t ow open wire current source ?on? time 4.6 ms open vc0 detection threshold v vc0 cell1 negative terminal (with respect to vss) v bat = 39.6v 1.2 1.5 1.8 v open vc1 detection threshold v vc1 cell1 positive terminal (with respect to vss) v bat = 39.6v 0.6 0.7 0.8 v primary detection threshold, vc2 to vc12 v vc2_12p v(vc(n - 1)) - v(vcn), n = 2 to 12 v bat = 39.6v -2 -1.5 0 v secondary detection threshold, vc2 to vc12 v vc2_12s via adc. vc2 to vc12 only v bat = 39.6v -100 -30 50 mv open v bat fault detection threshold v vbo vc12 - v bat 200 mv open vss fault detection threshold v vsso vss - vc0 250 mv measurement function timing ( note 8 ) cell sample time start time to sample the first cell (cell12) following cs going high. scan voltages command 65 71.5 s cell sample time duration time to scan all 12 cells (sample of cell12 to sample of cell1) scan voltages command. 233 257 s scan voltages processing time time from start of scan to registers loaded to data ready going low 770 847 s scan temperatures processing time time from start of scan to registers loaded to data ready going low 2690 2959 s scan mixed processing time time from start of scan to registers loaded to data ready going low 830 913 s scan wires processing time time from start of scan to registers loaded to data ready going low 59.4 65.3 ms scan all processing time time from st art of scan to registers loaded to data ready going low 63.2 69.5 ms electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 12 fn7938.1 april 23, 2015 submit document feedback measure cell voltage processing time time from start of measurement to register(s) loaded to data ready going low 180 198 s measure v bat voltage processing time time from start of measurement to register(s) loaded to data ready going low 130 143 s measure internal temperature processing time time from start of measurement to register(s) loaded to data ready going low 110 121 s measure external temperature input processing time time from start of measurement to register(s) loaded to data ready going low 2520 2772 s measure secondary voltage reference time time from start of measurement to register(s) loaded to data ready going low 2520 2772 s cell balance output specifications cell balance pin output impedance r cbl cbn output off impedance between cb(n) to vc(n-1): cells 1 to 9 and between cb(n) to vc(n): cells 10 to 12. 3 4 5 m ? cell balance output current i cbh1 cbn output on. (cb1-cb9); v bat = 39.6v; device sinking current. -28 -25 -21 a i cbh2 cbn output on. (cb10-cb12); v bat = 39.6v; device sourcing current. 21 25 28 a cell balance output leakage in shutdown i cbsd en = gnd. v bat = 39.6v. -500 10 700 na external cell balance fet gate voltage vgs cbn output on; external 320k ? between vcn and cbn (n = 10 to 12) and between cbn and vcn-1 (n = 1 to 9) 7.05 8.0 8.95 v internal cell balance output clamp vcbcl i cb = 100a. 8.9 v logic inputs: sclk, cs , din low level input voltage vil 0.8 v high level input voltage vih 1.75 v input hysteresis vhys 100 mv input current iin 0v < v in < v3p3 -1 +1 a input capacitance cin 10 pf logic inputs: en, comms select1, comms select2, comms rate 0, comms rate 1 low level input voltage vil 0.3*v3p3 v high level input voltage vih 0.7*v3p3 v input hysteresis vhys 0.05*v3p3 v input current iin 0v < v in < v3p3 -1 +1 a input capacitance cin 10 pf logic outputs: dout, fault , data ready low level output voltage vol1 at 3ma sink current 00.4 v vol2 at 6ma sink current 00.6 v high level output voltage voh1 at 3ma source current v3p3 ? 0.4v v3p3 v voh2 at 6ma source current v3p3 ? 0.6v v3p3 v electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 13 fn7938.1 april 23, 2015 submit document feedback spi interface timing ( see figures 2 and 3 ) sclk clock frequency f sclk 2 mhz pulse width of input spikes suppressed t in1 50 200 ns enable lead time t lead chip select low to ready to receive clock data 200 ns clock high time t high 200 ns clock low time t low 200 ns enable lag time t lag last data read clock edge to chip select high. 250 ns chip select high time t cs:wait minimum high time for cs between bytes. 200 ns slave access time t a chip select low to dout active. 200 ns data valid time t v clock low to dout valid. 350 ns data output hold time t ho data hold time after falling edge of sclk. 0 ns dout disable time t dis dout disabled following rising edge of cs . 240 ns data setup time t su data input valid prior to rising edge of sclk. 100 ns data input hold time t hi data input to remain valid fo llowing rising edge of sclk. 80 ns data ready start delay time t dr:st chip select high to data ready low. 100 ns data ready stop delay time t dr:sp chip select high to data ready high. 750 ns data ready high time t dr:wait time between bytes. 0.6 s spi communications timeout t spi:to time the cs remains high before spi communications time out - requiring the start of a new command. 100 s dout rise time t r up to 50pf load. 30 ns dout fall time t f up to 50pf load. 30 ns daisy chain communications interface: dhi1, dlo1, dhi2, dlo2 daisy chain clock frequency comms rate (0, 1) = 11 450 500 550 khz comms rate (0, 1) = 10 225 250 275 khz comms rate (0, 1) = 01 112.5 125 137.5 khz comms rate (0, 1) = 00 56.25 62.5 68.75 khz common mode reference voltage v bat /2 v notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. scan and measurement start times are synchronized by the receiver to the falling edge of the 24 th clock pulse (daisy chain syst ems) or to the falling edge of the 16 th clock pulse (non-daisy chain, single de vice systems) of the scan or measure command. clock pulses are at the sclk pin for master and standalone devices, and at the dhi/dlo1 pins for middle and top daisy chain devices. max values are based on characterization o f the internal clock and are not 100% tested. 9. biasing setup as in figure 57 on page 82 or equivalent. electrical specifications v bat = 6 to 60v, t a = -40c to +85c, unless otherwise specified. boldface limits apply across the operating temperature range, -40c to +85c. (continued) parameter symbol test conditions min ( note 7 )typ max ( note 7 )units
isl94212 14 fn7938.1 april 23, 2015 submit document feedback timing diagrams figure 2. spi full duplex (4-wire) interface timing figure 3. spi half duplex (3-wire) interface timing cs sclk dout din t lead t high t low t lag t spi:to t v t a t f t ho t dis t r t hi t su (from c) (from c) (from c) (to c) clock data into isl94212 clock data out of isl94212 t cs:wait cs sclk dout din t dr:wait t dr:sp data ready t a t dr:st signals on din ignored while data ready is low (from c) (to c) (from c) (from c) (to c) clock data into isl94212 clock data out of isl94212 t spi:to t cs:wait
isl94212 15 fn7938.1 april 23, 2015 submit document feedback typical performance curves figure 4. cell voltage reading error from 0c to +50c fi gure 5. cell voltage reading error from -40c to +85c figure 6. pack voltage reading error from 0c to +50c figure 7. pack voltage reading error from -40c to +85c figure 8. ic temperature error vs pack voltage fig ure 9. voltage reference check function vs pack voltage (at +25c) -40 -30 -20 -10 0 10 20 30 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 reading error (mv) cell voltage (v) -40 -30 -20 -10 0 10 20 30 40 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 reading error (mv) cell voltage (v) reading error (mv) -500 -400 -300 -200 -100 0 100 200 300 400 500 0 102030405060 pack voltage (v) reading error (mv) 0 102030405060 pack voltage (v) -800 -600 -400 -200 0 200 400 600 800 -5 -4 -3 -2 -1 0 1 2 3 4 0 10 20 30 40 50 60 pack voltage (v) -40c -20c +25c +60c +105c +85c normalized v ariations (%) -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 6 15 24 33 42 51 60 bgvref accuracy (mv) v bat (v)
isl94212 16 fn7938.1 april 23, 2015 submit document feedback figure 10. voltage reference check function vs temperature (v bat = 39.6) figure 11. v ref shift over htol figure 12. balance current vs pack voltag e figure 13. balance current vs temperature figure 14. open wire test current vs temperature (150a setting) figure 15. open wire test current vs temperature (1ma setting) typical performance curves (continued) -50 -40 -30 -20 -10 0 10 20 30 40 50 -40 -15 10 35 60 85 bgvref accuracy (mv) temperature (c) -0.50 -0.45 -0.40 -0.35 -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 0 100 200 300 400 500 600 700 800 900 1000 hours at +125c v ref shift (mv) 25.40 25.45 25.50 25.55 25.60 0 10 20 30 40 50 60 pack voltage (v) balance current (a) 24.2 24.4 24.6 24.8 25.0 25.2 25.4 25.6 -40 -20 0 20 40 60 80 100 temperature (c) balance current (a) v cell = 3.3v 149 150 151 152 153 154 155 156 157 -40 -20 0 20 40 60 80 100 temperature (c) io pwi (a) v cell = 3.3v 940 945 950 955 960 965 970 -40 -20 0 20 40 60 80 100 temperature (c) io pwi (a) v cell = 3.3v
isl94212 17 fn7938.1 april 23, 2015 submit document feedback figure 16. open wire test current vs pack voltage (150a setting) figure 17. open wire test current vs pack voltage (1ma setting) figure 18. 4mhz oscillator erro r vs vcc figure 19. 4mhz osci llator error vs temperature figure 20. 32khz oscillator erro r vs temperature figure 21. 32khz oscillator error vs vcc typical performance curves (continued) 156.0 156.5 157.0 157.5 158.0 0 10 20 30 40 50 60 pack voltage (v) io pwi (a) 800 850 900 950 1000 0 10 20 30 40 50 60 pack voltage (v) io pwi (a) -0.6 -0.4 -0.2 0 0.2 0.4 2.7 2.9 3.1 3.3 3.5 3.7 vcc (v) error (%) -7 -6 -5 -4 -3 -2 -1 0 1 -40 -20 0 20 40 60 80 100 120 temperature (c) error (%) -5 -4 -3 -2 -1 0 1 -40 -20 0 20 40 60 80 100 120 temperature (c) error (%) -0.6 -0.4 -0.2 0 0.2 0.4 2.7 2.9 3.1 3.3 3.5 3.7 vcc (v) error (%)
isl94212 18 fn7938.1 april 23, 2015 submit document feedback figure 22a. pack voltage sleep current vs temperature at 6v, 39.6v, 60v (standalone mode) figure 22b. pack voltage sleep current vs temperature at 6v, 39.6v, 60v (daisy chain mode) figure 22c. pack voltage sleep current vs temperature at 6v, 39.6v, 60v (daisy chain mode) figure 22d. pack voltage sleep current vs temperature at 6v, 39.6v, 60v (daisy chain mode) figure 23a. pack voltage supply current vs temperature at 6v, 39.6v, 60v (standalone mode) figure 23b. pack voltage supply current vs temperature at 6v, 39.6v, 60v (daisy chain top) typical performance curves (continued) 5 7 9 11 13 15 17 19 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v v bat = 39.6v v bat = 60v 15 17 19 21 23 25 27 29 31 33 35 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (master) v bat = 39.6v (master) v bat = 60v (master) 15 17 19 21 23 25 27 29 31 33 35 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (top) v bat = 39.6v (top) v bat = 60v (top) 15 17 19 21 23 25 27 29 31 33 35 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (mid) v bat = 39.6v (mid) v bat = 60v (mid) 0 20 40 60 80 100 120 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v v bat = 39.6v v bat = 60v 400 450 500 550 600 650 700 750 800 850 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (top) v bat = 39.6v (top) v bat = 60v (top)
isl94212 19 fn7938.1 april 23, 2015 submit document feedback figure 23c. pack voltage supply current vs temperature at 6v, 39.6v, 60v (daisy chain middle) figure 23d. pack voltage supply current vs temperature at 6v, 39.6v, 60v (daisy chain master) figure 24a. pack voltage shutdown current vs temperature (en = 0) at 6v, 39.6v, 60v figure 24b. v bat shutdown current vs temperature (en = 0) at 6v, 39.6v, 60v figure 24c. v bat voltage shutdown current vs temperature (en = 0) at 6v, 39.6v, 60v figure 24d. v bat voltage shutdown current vs temperature (en = 0) at 6v, 39.6v, 60v typical performance curves (continued) 800 900 1000 1100 1200 1300 1400 1500 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (mid) v bat = 39.6v (mid) v bat = 60v (mid) 400 450 500 550 600 650 700 750 800 850 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) i vbat (a) v bat = 6v (master) v bat = 39.6v (master) v bat = 60v (master) 5 6 7 8 9 10 11 12 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature ( c ) i vbat (a) v bat = 6v (standalone) v bat = 39.6v (standalone) v bat = 60v (standalone) 5 6 7 8 9 10 11 12 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i vbat (a) v bat = 60v (master) v bat = 6v (master) v bat = 39.6v (master) 5 6 7 8 9 10 11 12 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i vbat (a) v bat = 60v (mid) v bat = 6v (mid) v bat = 39.6v (mid) 5 6 7 8 9 10 11 12 13 -60 -40 -20 0 20 40 60 80 100 120 140 temperature (c) i vbat (a) v bat = 60v (top) v bat = 39.6v (top) v bat = 6v (top)
isl94212 20 fn7938.1 april 23, 2015 submit document feedback figure 25. vcc supply current vs temperature at 6v, 39.6v, 60v figure 26. v3p3 supply current vs temperature figure 27. cell input current vs temperature figure 28. ce ll input current vs pack voltage (+25c) typical performance curves (continued) 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35 3.40 3.45 3.50 -60 -40 -20 0 20 40 60 80 100 120 temperature ( c ) ivcc (ma) 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 -40 -20 0 20 40 60 80 100 temperature (c) supply current (ma) 6v 39.6v 60v -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 2.5 -40 -20 0 20 40 60 80 100 120 temperature (c) cell input current (a) vc7 vc8 vc9 vc10 vc11 vc6 vc5 vc1 vc2 vc3 vc12 vc4 vc0 vcell = 3.3v -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0 10 20 30 40 50 60 pack voltage (v) vc12 vc11 vc10 vc9 vc8 vc7 vc6 vc5 vc4 vc0 cell input current (a) vc3 vc2 vc1
isl94212 21 fn7938.1 april 23, 2015 submit document feedback device description and operation the isl94212 is a li-ion battery manager ic that supervises up to 12 series connected cells. up to 14 isl94212 devices can be connected in series to support systems with up to 168 cells. the isl94212 provides accurate monitoring, cell balance control, and diagnostic functions. the isl94212 includes a voltage reference, 14 bit a/d converter and registers for control and data. an external microcontroller communicates to the isl94212 through an spi interface. series connected isl94212 devices communicate to each other via a proprietary daisy chain communications interface. the isl94212 devices handle daisy chain communications differently depending on their posi tion within the daisy chain. the isl94212 at one end of the daisy chain acts as a master device for communication purposes. the master device, also called the bottom device, occupies the first position in the daisy chain and communicates to a host microcontroller using an spi interface. a single daisy chain port then connects the master device to the next device in the daisy chain. the device at the other end of the daisy chain from the master is the top device. the top device has a single daisy chain port connection to the device below. devices other than the master and top devices are middle devices. middle devices have two daisy chain port connections. the up port connects to the device above while the down port connects to the device below. the master isl94212 device is device number 1. the top device is device number n, where n equals the total number of isl94212 devices in the daisy chain. the middle devices are numbered 2 to (n-1) with device number 2 being connected to the master device. if n = 2, then there is a master device and a top device, with no middle device. when multiple isl94212 devices are connected to a series of cells, their power supply domain s are normally non-overlapping. the lower (vss) supply of each isl94212 nominally connects to the same potential as the upper (v bat ) supply of the isl94212 device below. the isl94212 provides two multiple parameter measurement ?scanning? modes in addition to single parameter direct measurement capability. these scanning modes provide pseudo simultaneous measurement of all ce ll voltages in the stack. in daisy chain applications all meas urement data is sent with the corresponding device stack address (the position within the daisy chain), parameter identifier, and data address. in stand alone applications (non-daisy chain) da ta is sent without additional address information. this maxi mizes the throughput for full duplex spi operation. daisy chain communication throughput is maximized by allowing streamed data (accessed by a ?read all data? address). the addressed device, the top device and the bottom device act as masters for the purposes of communications timing. all other devices are repeaters, passing data up or down the chain. the only filtering applied to the adc measurements is that resulting from external protection circuits and the limited bandwidth of the measurement path. no additional filtering is performed within the part. this arrangement is typically needed to maintain timing integrity between the cell voltage and pack current measurements. the isl94212 does not measure current. the system performs this separately using other measurement systems. however, the isl94212 does apply filtering to the fault detection systems. power modes the isl94212 has three main power modes: normal mode , sleep mode and shutdown mode (?off?). sleep mode is entered in response to a sleep command or after a watchdog timeout. only the communications input circuits, low speed oscillator and internal registers are active in sleep mode , allowing the part to perform timed scan and balancing activity and to wake up in response to communications. drive the enable pin low to place the part in shutdown mode . when entering shutdown mode, the internal bias for most of the ic is powered down except digital core, sleep mode regulators, and digital input buffers. when ex iting, the device powers up and does not reload the factory programmed configuration data from eeprom. the normal mode consists of an active state and a standby state. in the standby state, all systems are powered and the device is ready and waiting to pe rform an operation in response to commands from the host microcontroller. in the active state, the device performs an operation, such as adc conversion, open wire detection, etc. measurement modes the isl94212 provides three types of measurement modes. ? scan once ? scan continuous ?measure in scan once mode the part performs the requested scan a single time. in scan continuous mode the isl94212 performs repeated scans at intervals controlled by registers settings. measure mode allows a single parameter to be measured. the isl94212 ignores a scan or measure command, when the device is already in a scan mo de or measure mode. but, the command passes through to other devices in the daisy chain. all other communications functions respond normally while the device is scanning or measuring. measurement mode commands measurement modes are activa ted by commands from an external microcontroller. the isl94212 uses a memory mapped command structure. commands are sent to the device using a memory read operation from a sp ecific address. the addresses for the measurement mode commands 1 are shown in table 1 . there are other commands that perform other actions, but these are discussed in other sections. 1. in this document, the terminology for a hex value (e.g., h0000) is modified by a leading value (e.g., 16?) which defines the number of bits. for the measurement mode command address, a value of 6?h02 refers to a binary value of ?00 0010?.
isl94212 22 fn7938.1 april 23, 2015 submit document feedback scan once five different scan functions are available in single scan ( scan once mode .) each scan function is activated by a command from the host microcontroller. the scan functions are: 1. scan voltages 2. scan temperatures 3. scan mixed 4. scan wires 5. scan all the scan once functions are synchronous: all addressed stack devices begin scanning immediately following command receipt. there is a scan start latency between subsequent stack devices of one daisy chain clock cycle (e.g., for a stack of 10 devices with a daisy chain operating at 500khz, the scan start latency between the bottom and top stack devices is approximately 20s). scan voltages the scan voltages command causes the addressed part (or all parts if the common address is used) to scan through the cell voltage inputs followed by the pack voltage. ic temperature is also recorded for use with the internal calibration routines. cell voltages connected to each device are scanned in order from cell-12 (top) to cell-1 (bottom). cell overvoltage and undervoltage compares are performed on each cell voltage sample. the v bat and vss connections are also ch ecked at the end of the scan. cell voltage and pack voltage data, along with any fault conditions are stored in local memory ready for reading by the system host microcontroller. if there is a fault condition, the device sets the fault pin and returns a fault signal (sent down the stack) on completion of a scan. devices revert to the standby state on completion of the scan activity. scan temperatures the scan temperatures command causes the addressed part (or all parts if the common address is used) to scan through the internal and 4 external temperature signals followed by multiplexer loopback and reference measurements. the loopback and reference measurements are part of the internal diagnostics function. over-temperature compares are performed on each temperature measurement depending on the condition of the appropriate bit in the fault setup register. temperature data, along with any fault conditions, are stored in local memory ready for reading by the system host microcontroller. if there is a faul t condition, the device sets the fault pin and returns a fault signal (sent down the stack) on completion of a scan. devices revert to the standby state on completion of the scan activity. scan mixed the scan mixed command causes the addressed part (or all parts if the common address is used) to scan through the cell voltage inputs (followed by the pack voltage) with a single external input (ext1) interposed. ic temperature is also recorded for use with the internal calibr ation routines. cell voltages connected to each device are scanned in order from cell-12 (top) to cell-1 (bottom). the external input ext1 is scanned in the middle of the cell voltages such that half the cells are sampled before ext1 and half after ext1. this mode allows ext1 to be used for an external voltage me asurement, such as a current sensing and performs it along with the cell voltage measurements, reducing the latency between measurements. cell overvoltage and cell underv oltage compares are performed on each cell voltage sample. the v bat and vss conditions are also checked at the end of the scan. the scan mixed command is intended for use in standalone systems, or by the master devi ce in stacked applications, and would typically measure a single system parameter, such as battery current. other stack devices also measure their ext1 input but these would normally be ignored by the host. cell voltage, pack voltage and ex t1 data, along with any fault conditions are stored in local memory ready for reading by the system host microcontroller. access the data from the ext1 measurement by a direct read et1 voltage command or by the all temperatures read command. if there is a fault condition, the device sets the fault pin and returns a fault signal (sent down the stack) on completion of a scan. devices revert to the standby state on completion of the scan activity. scan wires the scan wires command causes the addressed part (or all parts if the common address is used) to measure all the vcn pin voltages while applying load currents to each input pin in turn. this is part of the fault detection system. if there is a fault condition, the device sets the fault pin and returns a fault signal (sent down the stack) on completion of a scan. no cell voltage data is sent as a result of the scan wires command. devices revert to the standby state on completion of this activity. scan all the scan all command incorporates the scan voltages, scan wires and scan temperatures commands and causes the addressed part (or all parts if the common address is used) to execute each of these three scan functions once, in sequence (see figure 29 on page 25 for example on timing). table 1. measurement mode command addresses register address command suffix command scan once 6?h01 6?h00 scan voltages 6?h02 6?h00 scan temperatures 6?h03 6?h00 scan mixed 6?h04 6?h00 scan wires 6?h05 6?h00 scan all scan continuous 6?h06 6?h00 scan continuous measure 6?h08 6 bit addr of element to measure measure
isl94212 23 fn7938.1 april 23, 2015 submit document feedback scan continuous scan continuous mode is used primarily for fault monitoring and incorporates the scan voltages, scan temperatures and scan wires commands. the scan continuous command causes the addressed part to set the scan bit in the device setup register and performs a succession of scans at a predet ermined scan rate. each device operates asynchronously on its own clock. this is similar to the scan all command except that the scans are repeated at intervals determined by the scn0-3 bits in the fault setup register. the scan inhibit command is used to stop scanning (i.e., receipt of this command by the ta rget device resets the scan bit and stops the scan continuous function). the isl94212 provides an option that pauses cell balancing activity while measuring cell voltages in scan continuous mode . this is controlled by the bdds bit in the device setup register. if bdds is set, then cell balancing is inhibited during cell voltage measurement and for 10ms before the cell voltages are scanned. balancing is reenabled at the end of the scan to allow balancing to continue. this function only applies during the scan continuous and the auto balance functions and allows the implementation of a circuit arrangement that can be used to diagnose the condition of external balancing components. it is up to the host microcontroller to manually stop balancing functions (if required) when operatin g a scan once or measure command. the scan continuous scan interval is set using the scn3:0 bits (lower nibble of the fault setup register.) the temperature and wire scans occur at slower rates and depend on the value of the scan interval selected. the scan system is synchronized such that the wire and temperature scans always follow a voltage scan. the three scan sequences, depend ing on the scans required at a particular instance, are as follows: ?scan voltages ? scan voltages, scan wires ? scan voltages, scan wires, scan temperatures. the temperature and wire scans occur at 1/5 the voltage scan rate for voltage scan intervals above 128ms. below this value the temperature scan interval is fixe d at 512ms. the behavior of the wire scan interval is determined by the wscn bit in the fault setup register. a bit value of ?1? causes the wire scan to be performed at the same rate as the temperature scan. a bit value of ?0? causes the wire scan rate to track the voltage scan rate for voltage scan intervals above 51 2ms while at and below this value the wire scan is performed at a fixed 512ms rate. table 2 shows the various scan rate combinations available. data is not automatically returned while devices are in scan continuous mode except in the case where a fault condition is detected. the results of volt age and temperature scans are stored in local volatile memory and may be accessed at any time by the system host microcontrolle r. devices may be operated in scan continuous mode while in normal mode or in sleep mode . devices revert to the sleep mode or remain in normal mode , as applicable on completion of each scan. the response to a detected fault condition is to send the fault signal, either immediately in the case of standalone devices or daisy chain devices in normal mode , or following transmission of the wakeup signal if the device is being used in a daisy chain configuration and is in sleep mode . to operate the ?scan continuous? function in sleep mode the host microcontroller simply configures the isl94212, starts the scan continuous mode and then sends the sleep command. the isl94212 then wakes itself up each time a scan is required. note that for the fastest scan settings (scan interval codes 0000, 0001 and 0010) the main measurement functions do not power down between scans, since the isl94212 remains in normal mode . measure this command allows a single cell voltage, internal temperature, any of the four external temper ature inputs or the secondary voltage reference measurements to be made. the command incorporates a 6-bit suffix that contains the address of the required measurement element. see table 3 on page 24 . the device matching the target addr ess responds by conducting the single measurement and loading the result to local memory. the host microcontroller then reads fr om the target device to obtain the measurement result. all devices revert to the standby state on completion of this activity. table 2. scan continuous timing modes scan interval scn3:0 scan interval (ms) temp scan (ms) wire scan wscn = 0 (ms) wire scan wscn = 1 (ms) 0000 16 512 512 512 0001 32 512 512 512 0010 64 512 512 512 0011 128 512 512 512 0100 256 1024 512 1024 0101 512 2048 512 2048 0110 1024 4096 1024 4096 0111 2048 8192 2048 8192 1000 4096 16384 4096 16384 1001 8192 32768 8192 32768 1010 16384 65536 16384 65536 1011 32768 131072 32768 131072 1100 65536 262144 65536 262144
isl94212 24 fn7938.1 april 23, 2015 submit document feedback cell voltage measurement accuracy the cell voltage monitoring system comprises two basic elements; a level shift to eliminate the cell common mode voltage and an analog-to-digital conversion of the cell voltage. each isl94212 is calibrated at a specific cell input voltage value, v nom . cell voltage measurement error data is given in ? measurement specifications ? on page 9 for various voltage and temperature ranges with voltage ranges defined with respect to v nom . plots showing the typical error distribution over the full input range are included in the ? typical performance curves ? section beginning on page 15 . temperature monitoring one internal and four external temperature inputs are provided together with a switched bias voltage output (tempreg, pin 29). the voltage at the tempreg output is nominally equal to the adc reference voltage such that the external voltage measurements are ratiometric to the adc reference (see figure 61 on page 85 ). the temperature inputs are intended for use with external resistor networks using ntc type thermistor sense elements but may also be used as general purpose analog inputs. each temperature input is applied to the adc via a multiplexer. the isl94212 converts the voltage at each input and loads the 14-bit result to the appropriate register. the tempreg output is turned ?on? in response to a scan temperatures or measure temperature command. a dwell time of 2.5ms is provided to allow external circuits to settle, after which the adc measures each external input in turn. the tempreg output turns ?off? afte r measurements are completed. figure 29 on page 25 shows an example temperature scan with the isl94212 operating in scan continuous mode with a scan interval of 512ms. the preceding voltage and wire scans are shown for comparison. the external temperature inputs are designed such that an open connection results in the input being pulled up to the full scale input level. this function is provided by a switched 10m pull-up from each input to vcc. this feature is part of the fault detection system and is used to detect open pins. the internal ic temperature, al ong with the auxiliary reference voltage and multiplexer loopback signals, are sampled in sequence with the external sign als using the scan temperatures command. the converted value from each temperature input is also compared to the external over-temperature limit and open connection threshold values on condition of the [ tst4:1] bits in the fault setup register (see ? fault setup: ? on page 64 .) if a tstn bit is set to ?1?, then the temperature value is compared to the external temperature threshol d and a fault occurs if the measured value is lower than the threshold value. if a tstn bit is set to ?0?, then the temperatur e measurement is not compared to the threshold value and no fault occurs. the [tst4:1] bits are ?0? by default. table 3. measure command target element addresses measure command measure element address (suffix) description 6?h08 6?h00 v bat voltage 6?h01 cell 1 voltage 6?h02 cell 2 voltage 6?h03 cell 3 voltage 6?h04 cell 4 voltage 6?h05 cell 5 voltage 6?h06 cell 6 voltage 6?h07 cell 7 voltage 6?h08 cell 8 voltage 6?h09 cell 9 voltage 6?h0a cell 10 voltage 6?h0b cell 11 voltage 6?h0c cell 12 voltage 6?h10 internal temperature reading 6?h11 external temperature input 1 reading 6?h12 external temperature input 2 reading 6?h13 external temperature input 3 reading 6?h14 external temperature input 4 reading 6?h15 reference voltage (raw adc) value. use to calculate corrected reference value using reference coefficient data. see page 2 data, address 6?h38 ? 6?h3a.
isl94212 25 fn7938.1 april 23, 2015 submit document feedback cell balancing functions cell balancing is an important function in a battery pack consisting of a stack of multiple li-ion cells. as the cells charge and discharge, differences in each cell?s ability to take on and give up charge, typically leads to cells with different states of charge. the problem with a stack of cells having different states of charge is that li-ion cell s have a maximum voltage, above which it should not be charge d and a minimum voltage, below which it should not be discharged. the extreme case, where one cell in the stack is at the maximu m voltage and one cell is at the minimum voltage, results in a no nfunctional battery stack, since the battery stack cannot be charged or discharged. cell balancing is performed using external mosfets and external current setting resistors (see figure 30 on page 30 ). each mosfet is controlled independently by the cb1 to cb12 pins of the isl94212. the cb1 to cb12 outputs are controlled either directly, or indirectly by an external microcontroller through bits in various control registers. the balancing functions within the isl94212 are controlled by multiple registers: ? balance setup register (all balance modes, see table 4 ) ? balance status register (all balance modes, see table 7 on page 26 ) ? device setup register (auto balance mode only, see table 13 on page 30 ) ? watchdog/balance time regist er (timed and auto balance modes, see table 9 on page 27 ) ? balance values registers (a uto balance only, see example in table 11 on page 28 ) additional registers are provid ed for the balance timeout ( timed mode and auto balance mode ) and balance value ( auto balance mode only). balance setup register the balance setup register (see table 7 ) contents break down into 4 sub groups. ? balance wait time: bwt[2:0] bits (also referred to as balance dwell time) ? balance status pointer: bsp[3:0] bits ? balance enable: ben bit ? balance mode: bmd[1:0] bits balance wait time the balance wait time control bi ts, bwt[2:0], set the interval between balancing operations in auto balance mode , as shown in table 5 . hi-z hi-z hi-z 512ms 2.5v 2.5ms voltage scan wire scan temperature scan 2.69ms tempreg pin adc sampling 765s 59.4ms figure 29. scan timi ng example during scan continuous mode and scan all mode table 4. balance setup register (address 6?h13) 7654321 9 0 8 bsp2 bsp1 bsp0 bwt2 bwt1 bwt0 bmd1 bmd0 ben bsp3 table 5. balance wait time control bits bwt[2:0] seconds 000 0 001 1 010 2 011 4 100 8 101 16 110 32 111 64
isl94212 26 fn7938.1 april 23, 2015 submit document feedback balance status pointer see ? balance status register ? . balance enable when all of the other balance co ntrol bits are properly set, setting the balance enable bit to ?1? starts the balance operation. the ben bit can be set by writing directly to the balance setup register or by sending a balance enable command. balance mode three methods of cell balance control are provided (see table 6 ). in manual mode , the host microcontroller directly controls the state of each mosfet output. in timed mode , the host microcontroller programs a balance duration value and selects which cells are to be balanced, then starts the balance operation. the isl94212 turns all the fets off when the balance duration has been reached. in auto balance mode , the host microcontroller programs the is l94212 to control the balance mosfets to remove a programmed ?charge delta? value from each cell. the isl94212 does this by controlling the amount of charge removed from each cell over a number of cycles, rather than trying to balance all cells to a specific voltage. balance status register the balance status register contents control which external balance fet is turned on during a balance event. each bit in the balance status register controls one external balancing fet, such that bit 0 [bal1] controls the cell 1 fet and bit 11 [bal12] controls the fet for cell 12 (see table 7 .) bits are set to enable the balancing for that cell and cleared to disable balancing. the balance status register is a ?multiple instance? register. there are 13 locations within this register. the balance status pointer bsp[3:0] points to one of these 13 locations in the register (see table 7 ). only one location in the balance status register may be ac cessed at a time. the balance status register instance at pointer location 0 ( bsp[3:0] = 0000) is used for manual balance mode and timed balance mode . the balance status register instances at pointer locations 1 to 12 (bsp[3:0] = 4?h1 to 4?hc) are used for auto balance mode . the arrangement is illustrated in table 7 . in auto balance mode , the isl94212 increments the balance status pointer on each auto balance cycle to step through balance status register locations 1 to 12. this allows the programming of up to twelve different balance profiles for each auto balance operation. on each auto balance cycle, the balance status pointer increments by one. when the operation encounters a zero value at a pointer location, the auto balance operation returns to the pattern at location 1 and resumes balancing with that pattern. more information about the auto balance mode is provided in ? auto balance mode ? on page 27 . example balancing setup information is provided in ? auto balance mode cell balancing example ? on page 88 . manual balance mode select manual balance mode by setting the balance mode bits bmd[1:0] to 2?b01. to manually control the cells to be balanced, set the balance status pointer to zero: bsp[3:0] = 4?b0000. then, program the cells to be balanced by setting bits in the balance status register (e.g., to balance cell 5, set the bal5 bit to 1). enable balancing, either by setting the ben bit in the balance setup register or by sendin g a balance enable command. disable balancing either by resett ing the ben bit or by sending a balance inhibit command. the balance enable and balance inhibit commands may be used with the ?address all? device address to control all devices in a stack simultaneously. balancing is not possible in manual balance mode while the isl94212 is in sleep mode . if the watchdog timer is off and the sleep command is received while the device is balancing, then balancing stops immediately and the device goes into the sleep mode . if the watchdog timer is active during balancing and the device receives the sleep command, then balancing also stops immediately and the device goes into the sleep mode , but the wdtm bit is set when the watchdog timer expires. (see table 8 ). table 6. balance mode control bits bmd[1:0] balance mode 00 off 01 manual 10 timed 11 auto table 7. balance status register and balance status pointer bsp [3:0] balance status register (address 6?h14) bal 12 bal 11 bal 10 bal 9 bal 8 bal 7 bal 6 bal 5 bal 4 bal 3 bal 2 bal 1 0000 reserved for manual and timed balance modes 0001 auto balance status register 1 0010 auto balance status register 2 0011 auto balance status register 3 0100 auto balance status register 4 0101 auto balance status register 5 0110 auto balance status register 6 0111 auto balance status register 7 1000 auto balance status register 8 1001 auto balance status register 9 1010 auto balance status register 10 1011 auto balance status register 11 1100 auto balance status register 12
isl94212 27 fn7938.1 april 23, 2015 submit document feedback the watchdog timer function pr otects the battery from excess discharge due to balancing, in the event that communications is lost while the part is in manual balance mode . all balancing ceases and the device goes into the sleep mode if the watchdog timeout value is exceeded. timed balance mode select timed balance mode by setting the balance mode bits bmd[1:0] to 2?b10. to set up a timed balance operation, set the balance status pointer to zero: bsp[3:0] = 4?b0000. then program the cells to be balanced by setting bits in the balance status register (e.g., to balance cells 7 and 10, set bal7 and bal10 bits to 1). set the balance on time. the balance on time is programmable in 20 second intervals from 20 seconds to 42.5 minutes using btm[6:0] bits. these bits are in locations [13:7] of the watchdog/balance time register. see tables 9 and 10 for details. enable balancing, either by setting the ben bit in the balance setup register or by sending a balance enable command. the selected balance fets (corresponding to the bits set in balance status register location 4?b0000) turn on when ben is asserted and turn off when the balance timeout period is met. resetting ben, either directly or by using the balance inhibit command stops the balancing functions and resets the timer values. when ben is reasserted, or when a new balance enable command is received, balancing resumes, using the full time specified by the btm[6:0] bits. when the balance timeout period is met, the end of balance (eob) bit in the device setup register is set and ben is reset. balancing is not possible in the timed balance mode while the isl94212 is in sleep mode . if the watchdog timer is off and the sleep command is received while the device is balancing, then balancing stops immediately and the device goes into sleep mode . if the watchdog timer is active during balance and the device receives the sleep command, then balancing also stops immediately and the device enters sleep mode , but the wdtm bit is set when the watchdog timer expires (see table 8 ). the watchdog can be disabled at any time by writing the watchdog password (6?h3a) to the watchdog password bits [wp5:0] in the device setup register (see table 13 on page 30 ), and then writing 6?h00 to the watchdog timeout bits [wdg5:0] in the watchdog/balance time register (see table 9 ). auto balance mode auto balance mode provides the capability to perform balancing autonomously and in an intelligent manner. thermal issues are accommodated by the provision of the multiple instance balance status register and a balance wait time. cells are balanced with periodic measurements being performed at the balance cycle on time interval (see table 10 ). these measurements are used to calculate the reduction in state of charge (soc) with each balancing cycle and to terminate balancing of a particular cell when the total soc change target has been reached. select auto balance mode by setting the balance mode bits bmd[1:0] to 2?b11. in auto balance mode, the isl94212 cycles through each balance status register instance and turns on the balancing outputs corresponding to the bits set in each balance status register instance. auto balance sequence the auto balance sequence is programmed using the ?multiple instance? balance status register and the balance status pointer bits. the first cycle of the auto balance operation begins with the balance status pointer at location 1, specifying the first balance status register instance. for the next auto balance cycle, the balance status pointer incremen ts to location 2. for each subsequent cycle, the pointer in crements to the next balance status register instance, unti l a zero value instance is encountered. at this point the sequence repeats from the table 8. manual and timed balance mode watchdog timer, balance, sleep operation watchdog timer actions off receiving a sleep command immediately stops balancing and the device enters the sleep mode . on if the device has not received a sleep command before the watchdog timer expires, then when the watchdog timer does expire, balance stops, the wdtm bit is set and the device enters the sleep mode . receiving a sleep command immediately stops balancing and the device enters the sleep mode . then, when the watchdog timer expires, the wdtm bit is set. table 9. watchdog/balance time register (address 6?h15) 765 13 4 12 3 11 2 10 1 9 0 8 btm0 wdg6 wdg5 wdg4 wdg3 wdg2 wdg1 wdg0 btm6 btm5 btm4 btm3 btm2 btm1 table 10. balance cycle on time settings btm[6:0] minutes 0000000 disabled 0000001 0.33 0000010 0.67 0000011 1.00 -- 1111101 41.67 1111110 42.00 1111111 42.33
isl94212 28 fn7938.1 april 23, 2015 submit document feedback balance status register instance at the balance status pointer location 1 until all the cells have met their soc adjustment value. for example, to balance odd numbered cells during the first cycle and even numbered cells on the second cycle: (see example in ? cell balancing ? auto mode ? on page 88 .) ? first set the balance status pointer to 1: bsp[3:0] = 0001. ? specify the even bits by setting balance status register bits 0, 2, 4, 6, 8 and 10 to ?1?. balance status register = 14?h0555 ? set the balance status pointer to 2: bsp[3:0] = 0010 . ? specify the odd bits by setting balance status register bits 1, 3, 5, 7, 9 and 11 to ?1?. balance status register = 14?h0aaa ? set the balance status pointer to 3: bsp[3:0] = 0011. ? specify sequence termination by resetting all the bits in the balance status register to zero. the next cycle will go back to balance status pointer = 1. balance status register = 14?h0000. ? leave the balance status pointer to 3: bsp[3:0] = 0011. auto balance timing set the desired interval between balancing cycles using the balance wait time bits bwt[2:0] (locations [4:2] of the balance setup register), see table 4 on page 25 and table 5 on page 25 . set the balance cycle on time using the btm[6:0] bits (locations [13:7] of the watchdog/bal ance time register), see tables 9 and 10 on page 27 . set or clear the bdds bit, bit 7 in the device setup register, as required. if bdds is set, then cell balancing is turned off 10ms before the cell voltage scan at the end of each balance cycle. if bdds is cleared, then balance functions remain ?on? during auto balance mode cell scan measur ements. bdds must be set in auto balance mode when using the standard battery connection configuration shown in figure 50 on page 73 . auto balance (delta soc) value the next step in setting up an auto balance operation is to program the balance value for each cell. the balance value (delta soc) is the difference between the present charge in a cell and the desired charge for that cell. the method for calculating the state of charge for a cell is left to the system designer. typically, determining the state of charge is dependent on the chosen cell type and manufacturer, is dependent on cell voltage, charge and discharge rates, temperature, age of the cell, number of cycles, and other factors. tables for determining soc are often available from the battery cell manufacturer. the balance value itself is a function of the current soc, required soc, balancing leg impedance, and sample interval. this value is calculated by the host microcontroller for each cell. the balancing leg impedance is made up of the external balance fet and balancing resistor. the sample interval is equal to the balance cycle on time period (e.g., each cell voltage is sampled at the end of the balance on time). the balancing value b for each cell is calculated using the formula shown in equation 1 . (see also ? balance value calculation example ? on page 88 ): where: b = the balance register value currentsoc = the present soc of the cell (coulombs) targetsoc = the required soc value (coulombs) z = the balancing leg impedance (ohms) dt = the sampling time interval (balance cycle on time in seconds) 8191/5 = a voltage to hex conversion value the balancing leg impedance is normally the sum of the balance fet r ds(on) and the balance resistor. the balancing value (b) can also be defined as in the set of equations following. auto balance is guided by equations 2 and 3 : where: dt = balance cycle on time t = total balance time looking at equations 2 and 3 , the impedance drops out of the equation, leaving only voltage and time elements. thus, ?b? becomes a collection of voltag es that integrate during the balance cycle on time, and accumulate over the total balance time period, to equal the programmed delta capacity. twelve 28-bit registers are provided for the balance value for each cell. the balance values are programmed for all cells as needed using balance value registers 6?h20 to 6?h37 (see table 11 for the contents of the cell1 balance values register). at the end of each balance cycle on time interval the isl94212 measures the voltage on each of the cells that were balanced during that interval. the measured values are then subtracted from the balance values for those cells. this process continues until the balance value for each cell is zero, at which time the auto balancing process is complete. table 11. balance values register cell1 (address 6?h20, 6?h21) addr 7 15 6 14 5 13 4 12 3 11 2 10 1 9 0 8 6?20 b0107 b0106 b0105 b0104 b0103 b0102 b0101 b0100 b0113 b0112 b0111 b0110 b0109 b0108 6?21 b0121 b0120 b0119 b0118 b0117 b0116 b0115 b0114 b0127 b0126 b0125 b0124 b0123 b0122 (eq. 1) b 8191 5 ------------ - currentsoc t etsoc arg C ?? z dt ---- - ? ? = soc i t ? v z --- - t ? == (eq. 2) bsoc z dt ---- - ? v z --- - t ? z dt ---- - ? v dt ---- - t ? === (eq. 3)
isl94212 29 fn7938.1 april 23, 2015 submit document feedback auto balance operation once all of the cell balance fet controls, the balance values and the timers are set up, balance is enabled either by setting the ben bit in the balance setup register or by sending a balance enable command. once enabled, the isl94212 cycles through each instance of the balance status register for the duration given by the balance timeout. between each balance status register instance, the device does a scan all operation and inserts a delay equal to the balance wait time. the process continues with the balance status pointer wrapping back to 1 until all the balance value registers equal zero. if one cell balance value register reaches zero before the others, balancing for that cell stops, but the others continue. resetting ben, either directly or by using the balance inhibit command, stops the balancing functions but maintains the current balance value register contents. auto balancing continues from the balance status register location 1 when ben is reasserted. when auto balancing is complete, the end of balance (eob) bit in the device setup register is set and ben bit is reset. balancing is not possible using the auto balance mode while the isl94212 is in sleep mode . if the sleep command is received while the device is balancing (and the watchdog timer is off) then balancing continues until it is finished and device enters sleep mode . if the watchdog timer is active during the auto balance mode and the device receives the sleep command, then balancing immediately stops and device enters sleep mode . the wdtm bit is set when the wa tchdog timer expires (see table 12 ). the watchdog can be disabled at any time by writing the watchdog password (6?h3a) to the watchdog password bits [wp5:0] in the device setup register (see table 13 on page 30 ) and then writing 6?h00 to the watchdog timeout bits [wdg5:0] in the watchdog/balance time register (see table 9 on page 27 ). balance fet drivers external balancing fets are cont rolled by current sources or current sinks attached to the cell balancing (cb) pins. the gate voltage on each fet is then controlled by a locally placed gate-to-source resistor. voltage cl amps are included at each cb output to limit the maximum gate drive voltage. series gate resistors are used to protect both the external fet and internal ic circuits from external voltage transient effects. an internal gate-to-source connected resistor is used to provide a redundant gate discharge path. a mix of n-channel and p-channel devices are used for the external fets in order to remove the need for a charge pump. cell 12, cell 11 and cell 10 balance positions use p-channel devices. the remaining positions use n-channel devices. the basic balance fet drive arrangement is shown in figure 30 . additional circuit guidelines are provided in the ? typical applications circuits ? on page 72 . reduced cell counts for fewer th an 12 cells ar e accommodated by removing connections to the cells in the middle of the stack first. the top and bottom cell locations are always occupied. see ? operating the isl94212 with reduced cell counts ? on page 78 for suggested cell configurations when using fewer than 12 cells. table 12. auto balance mode watchdog timer, balance, sleep operation watchdog timer actions off receiving a sleep command puts the device into sleep mode when the auto balance operation is finished. on if the device has not received a sleep command, then when the watchdog timer expires, balance stops, the wdtm bit is set and the device enters sleep mode . when the device receives a sleep command, balance stops immediately. when the watchdog timer expires, the wdtm bit is set and the device enters sleep mode .
isl94212 30 fn7938.1 april 23, 2015 submit document feedback device setup register bdds a function is provided to allow any cell balancing activity to be paused while measuring cell volt ages in scan continuous mode and auto balance mode. this is co ntrolled by the bdds bit in the device setup register (address 6?h19) (see table 13 ). if bdds is set, then cell balancing is inhibited during cell voltage measurement and for 10ms befo re the cell voltage scan. balancing is reenabled at the end of the scan. this function only applies during the scan continuous mode and the auto balance mode. it is up to the host microcontroller to manually stop balancing functions (if required) before sending a scan or measure command. watchdog password before writing a zero to the watchdog timer, which turns off the timer, it is necessary to write a password to the [wp5:0] bits. the password value is 6?h3a. eob this end of balance bit indicates that a timed balance mode or an auto balance mode has completed. scan this bit is set in response to a scan continuous command and cleared by the scan inhibit command. iscn, pin37, pin39 the iscn bit is used in the open wire scan. pin37 and pin39 bits show the state of the respective device pins. cell balance enabled register to facilitate the system monitoring of the cell balance operation, the isl94212 has a register that shows the present state of the balance drivers. table 14 shows the cells being balanced register, located on page 2 at addr ess 6?h3b. if the bit is ?1? it indicates that the cbn output is enabled. a ?0? indicates that the cbn output is disabled. figure 30. external fet driving circuits isl78600 isl94212
isl94212 31 fn7938.1 april 23, 2015 submit document feedback system configuration the isl94212 provides two communications systems. an spi synchronous port is provided for communication between a microcontroller and the isl94212 . for standalone (non-daisy chain) systems, the spi port is the only port needed. in systems where there is more than one isl94212, daisy chain (asynchronous) ports provide communication between the spi port on the master and other isl94212 devices. the communications setup is controlled by the comms select 1 and comms select 2 pins on each device. these pins specify whether the isl94212 is a standalone device, the daisy chain master, the daisy chain top, or a middle position in the daisy chain. see figures 31 and 32 and table 15 . this configuration also specifies the use of spi or daisy chain on the communication ports. . all communications are conducted through the spi port in single 8-bit byte increments. the msb is transmitted first and the lsb is transmitted last. commands in non-daisy chain systems are composed of a read /write bit, page address (3 bi ts), data address (6 bits) and data (6 bits). commands in daisy chain systems are composed of a device address (4 bits), a read /write bit, page address (3 bits), data address (6 bits), data (6 bits), and crc (4 bits). commands and data are memory mapped to 14-bit data locations. the memory map is arranged in pages. pages 1 and 2 are used for volatile data. page 3 contains the action and communications administration commands. page 4 accesses non-volatile memory. page 5 is used for factory test. spi interface the isl94212 operates as a spi slave capable of bus speeds up to 2mbps. four lines make up the spi interface: sclk, din, dout and cs . the spi interface operates in either full duplex or half duplex mode depending on the daisy chain status of the part. the dout line is normally tri-st ated (high impedance) to allow use in a multidrop bus. dout is only active when cs is low. full duplex operation in non-daisy chain applications, the spi bus operates as a standard, full duplex, spi port. read and write commands are sent to the isl94212 in 8-bit blocks. cs is taken high between each block. data flow is controlled by interpreting the first bit of each transaction and counting the requisite number of bytes. it is the host microcontroller?s resp onsibility to ensure that commands are correctly formulated as an incorrect formulation, (e.g., read bit instead of write bit), would cause the port to lose synchronization. there is a time out period associated with the cs inactive (high) condition, which resets all the communications counters. this effectively resets the spi port to a known starting condition. if cs stays high for more than 100s then the spi state machine resets. the isl94212 responds to read commands by loading the requested data to its output buffer. the output buffer contents are then loaded to the shift register when cs goes low and are shifted out on the dout line on the falling edges of sclk . this sequence continues until all the requested data has been sent. all single register read comm ands and responses are 2-bytes long. all bytes are handled in pairs during device reads. device writes are 3-bytes long. table 15. communications mode control comms select 1 comms select 2 port 1 comm port 2 comm communications configuration 00 spi (full duplex) disabled standalone 01 spi (half duplex) enabled daisy chain, master device setting 1 0 daisy chain disabled daisy chain, top device setting 1 1 daisy chain enabled daisy chain middle device setting spi comms select2 comms select1 vss figure 31. non-daisy chain communications connections and select isl94212 spi comms select2 comms select1 v3p3 comms select2 comms select1 v3p3 comms select2 comms select1 v3p3 vss vss vss daisy up daisy down daisy up figure 32. daisy chain communications connections and selection daisy down isl94212 isl94212 isl94212
isl94212 32 fn7938.1 april 23, 2015 submit document feedback a pending device response from a previous command is sent by the isl94212 during the first 2 bytes of the 3-byte write transaction. the third byte from the isl94212 is then discarded by the host microcontroller. this maintains sequencing during 3-byte (write) transactions. half duplex operation the spi operates in half duplex mode in daisy chain applications (see table 15 on page 31 ). data flow is controlled by a handshake system using the data ready and cs signals. data ready is controlled by the isl94212. cs is controlled by the host microcontroller. this handshake accommodates the delay between command receipt and device response due to the latency of the daisy chain communications system. responses from stack devices are received by the stack master (stack bottom device). the stack master then asserts its data ready output once the first full data byte is available. the host microcontroller re sponds by asserting cs and clocking the data out of the dout port. the data ready line is then cleared and dout is tri-stated in response to cs being taken high. in this mode the din and dout lines may be connected externally. half duplex communications are conducted using the data ready /cs handshake as follows: 1. the host microcontroller sends a command to the isl94212 using the cs line to select the isl94212 and clocking data into the isl94212 din pin. 2. the isl94212 asserts data ready low when it is ready to send data to the host microcontroller. when data ready is low, the isl94212 is in transmit mode and will ignore any data on din. 3. the host microcontroller asserts cs low and clocks 8 bits of data out of dout using sclk . 4. the host microcontroller then raises cs . the isl94212 responds by raising data ready and tri-stating dout. 5. the isl94212 reasserts data ready for the next byte and so on. the host microcontroller must service the isl94212 if data ready is low before sending further commands. any data sent to din while data ready is low is ignored by the isl94212. a 4 byte data buffer is provided for spi communications. this accommodates all single tran saction responses. multiple responses, such as those that may be produced by a device detecting an error would overflow this buffer. it is important therefore that the host microcontrol ler reads the first byte of data before a 5 th byte arrives on the master device?s daisy chain port so as not to risk losing data. the data ready output from the isl94212 is not asserted if cs is already asserted. it is possible for the microcontroller to interrupt a sequential data transfer by asserting cs before the isl94212 asserts data ready . this causes a conflict with the communications and is not recommended. a conflict created in this manner would be recognized by the microcontroller either not receiving the expected response or receiving a communications failure notification. interface timing for full and half duplex spi transfers are shown in figures 2 and 3 on page 14 . examples of full duplex spi re ad and write sequences are shown in figures 33 and 34 . figure 33. spi write example: write undervoltage threshold data 1 0 1 0 0 1 0 0 da ta t ype dat a address cell u nd er v oltage threshold data 0 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 note 1 note 1 note 2 dou t din cs sclk high im pedan ce not d eterm in ed a ctive notes: 10. last data byte pair from previous command. 11. not defined. msb lsb note 10 note 10 note 11
isl94212 33 fn7938.1 april 23, 2015 submit document feedback non-daisy chain systems in non-daisy chain (standalone) systems, all communications sent from the master are 2 or 3 bytes in length. data read and action commands are 2 bytes. da ta writes are 3 bytes. device responses are 2 bytes in length and contain data only. commands are composed of a read /write bit, page (3 bits), data address (6 bits) and data (6 bits). action commands, such as scan and communications administration commands are treated as reads. non-daisy chain communications are conducted without crc (cyclical redundancy check) error detection. the rules for non-daisy chain installations are shown in table 16 . normal communications non-daisy chain devices do not generate a response to write or system level commands. data integrity may be verified by reading register contents after writing. the isl94212 does nothing in response to a write or administration command that is not recognized. an unrecognized read command returns 16?h0000. an incomplete command, such as may occur if communications are interrupted , is registered as an unrecognized command either when cs is taken high or after a timeout period. the communications interface is reset after the timeout period. the following commands have no meaning in non-daisy chain systems such as: ?identify ?ack ?nak the sleep and wakeup comman ds are sent as normal commands. the device resets on receipt of the reset command. alarm signals the fault logic output is asserted low in response to a fault condition. the output then remains low until the bits of the fault status register are reset. th e host microcontroller writes 14?h0000 to this register to clear the bits. bits in the fault data registers must first be cleared be fore the associated bits in the fault status register can be cleare d. additionally, the fault status of each part may be obtained at any time by reading the fault status register. the fault logic output is asserted in sleep mode , if a fault has been detected and has not been cleared. communication faults there is no specific response to a communications fault. a fault is indicated by an absence of normal communications function. non-daisy chain device responses are 2-byte sequences containing 14-bit data with leading zeros. non-daisy chain responses are conducted without crc (cyclical redundancy check) error detection. figure 34. spi read example: read cell 7 data high im pedan ce not determined 0 0 0 1 0 0 0 1 dat a type da ta address c ell 7 data 0 0 0 1 0 1 1 1 note 1 dout din cs sclk note 3 ac tive 0 0 0 0 1 0 1 0 note 1 1 1 0 0 0 0 0 0 note 3 note 13 note 13 notes: 12. last data byte pair from previous command. 13. next command (or 8?h00 if no command). note 12 note 12 table 16. isl94212 data interpretation rules for non-daisy chain installations first bit in sequence page data address interpretation 0 011 001000 measure command. last six bits of transmission contain element address. 0 any all other device read or action command. last six bits of transmission are zero. 1 any any device write command.
isl94212 34 fn7938.1 april 23, 2015 submit document feedback fault response in sleep mode when a standalone device is in sleep mode , the device may still detect faults if operating in the scan continuous mode . if an error occurs, the fault output pin is asserted low. example communications an example read response is shown in figure 35 . examples of the various write command structures for non-daisy chain installations are shown in figures 36a through 36f . daisy chain systems the daisy chain communication is intended for use with large stacks of battery cells where a number of isl94212 devices are used. daisy chain ports a daisy chain consists of a bottom device, a top device and up to 12 middle devices. the isl94212 device located at the bottom of the stack is called the master and communicates to the host microcontroller using spi communications and to other isl94212 devices using the daisy chain port. each middle device provides two daisy chain ports: one is connected to the isl94212 above in the stack and the ot her to the isl94212 below. communications between the spi and daisy chain interfaces are buffered by the master device to accommodate timing differences between the two systems. the daisy chain ports are full y differential, dc balanced, bidirectional and ac-coupled to provide maximum immunity to emi and other system transients while only requiring two wires for each port. four operating da ta rates are available and are configurable by pin selection using the comms rate 0 and comms rate 1 pins (see table 17 ). maximum operating data rates is 2mbps for the spi interface. when using the daisy chain communications system it is recommended that the synchron ous communications data rate be at least twice that of the daisy chain system. the communications pins are monitored when the device is in sleep mode , allowing the part to wake up in response to communications. figure 36a. device level command: sleep figure 36b. device level command: wake up figure 36c. device read: get cell 7 data figure 36d. device level command: scan voltages figure 35. non-daisy chain devi ce response example: cell 7 voltage = 16?h170a (3.6v) 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 ldg. zero (15, 14) data (13, 0) byte 1 byte 0 msb lsb 1 1 0 0 1 0 1 0 0 0 0 0 0 0 page (14, 12) data address (11, 6) trailing zeros (5, 0) byte 1 byte 0 msb lsb 00 r /w 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 data address (11, 6) trailing zeros (5, 0) byte 1 byte 0 msb lsb page (14, 12) r /w 0 1 0 0 0 1 1 1 0 0 0 0 0 0 page (14, 12) data address (11, 6) trailing zeros (5, 0) byte 1 byte 0 msb lsb 00 r /w 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 data address (11, 6) trailing zeros (5, 0) byte 1 byte 0 msb lsb page (14, 12) r /w figure 36e. device level command: measure cell 5 voltage figure 36f. device write: write external temperature limit = 14?h0fff figure 36. non-daisy chain de vice read and write examples table 17. daisy chain communications data rate selection comms rate 0 comms rate 1 data rate (khz) 00 62 01 125 1 0 250 1 1 500 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 data address (11, 6) element address (5, 0) byte 1 byte 0 msb lsb page (14, 12) r /w 1 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 data address (19, 14) data (13, 0) byte 2 byte 1 msb 1 1 1 1 1 1 1 1 byte 0 lsb page r /w
isl94212 35 fn7938.1 april 23, 2015 submit document feedback communications protocol all daisy chain communications are passed from device to device such that all devices in the stack receive the same information. each device then decodes the me ssage and responds as needed. the originating device (master in the case of commands, addressed device or top stack devi ce in the case of responses) generates the system clock and da ta stream. each device delays the data stream by one clock cycle. each device knows its stack location (see command ? identify ? on page 40 ). each device knows the total number of devices in the stack. each originating device adds a number of clock pulses to the daisy chain data stream to allow transmission through the stack. all communications from the host microcontroller are passed from device to device to the last device in the chain (top device). the top device responds to read and writ e messages with an ?ack? (or with the requested data if this is the addressed device and the message was a read command). the addresse d device then waits to receive the ?ack? before responding. with data, in the case of a read, or with an ?ack? in the case of a wr ite. action commands such as the scan commands do not require a response. a read or write communications tran smission is only considered to be complete following receipt of a response from the target device or the identification of a communi cations fault condition. the host microcontroller should not transm it further data until either a response has been received from the target stack device or a communications fault condition has been identified. a normal daisy chain communications sequence for a stack of 10 devices: read device 4, cell 7 data, is illustrated in figure 37 on page 35 . the maximum response time: time from the rising edge of cs at the end of the first byte of a read /write command, sent by the host microcontroller, to the assertion of data ready by the master device, is given in table 18 for various daisy chain data rates. table 18. maximum response ti mes for daisy chain read and write commands. stack of 10 devices maximum time to assertion of data ready unit daisy chain data rate 500 250 125 62.5 khz response time 240 480 960 1920 s figure 37. daisy chain read example ?read device 4, cell 7?, stack of 10 devices ? host microcontroller sends ?read device 4, cell 7? = packet a ? master begins relaying packet a following receipt of the 1 st byte of a. master adds 10 extra clock cycles to allow all stack devices to relay the message. ? device 4 receives and decodes ?read device 4, cell 7? and waits for a response from top stack device. ? top stack device (device 10) receives and decodes packet a. ? device 10 responds ?ack?. device 10 adds 10 clock cycles to allow all stack devices to relay the message. ? device 4 receives and decodes ack. ? device 4 transmits the cell 7 data = packet b. device 4 subtracts one clock cycle to synchronize timing for lower stack devices to relay the message. ? master asserts data ready after receiving the 1 st byte of packet b. ? host responds by asserting cs and clocking out 8 bits of data from dout. cs is taken high following the 8 th bit. the master responds by taking data ready high and tri-stating dout. master asserts data ready after receiving the next byte and so on. aaa bb b b packet a sclk din dout cs data ready master tx master rx device 4 tx device 4 rx device 10 tx device 10 rx daisy chain spi packet a 4 daisy clock pulses packet a 10 extra clocks 6 extra clocks no extra clocks 10 daisy clock pulses ack 10 extra clocks ack 5 extra clocks packet b 4 extra clocks packet b no extra clocks
isl94212 36 fn7938.1 april 23, 2015 submit document feedback communication sequences all daisy chain device responses ar e 4-byte sequences, except for the responses to the read all co mmand. all responses start with the device stack addr ess. all responses use a 4-bit crc. the response to the ?read all commands? is to send a normal 4-byte data response for the first data segment and continue sending the remaining data segments in 3-byte sections composed of data address, data and crc. this creates an anomaly with the normal crc usage in that the first 4 bytes have a 4-bit crc at the end (operating on 3.5 bytes of data) while the remaining bytes have a crc which only operates on 2.5 bytes. the host microcontroller, having requested the data, must be prepared for this. daisy chain devices require device stack address information to be added to the basic command set. daisy chain writes are 4-byte sequences. daisy chain reads are 3 bytes. action commands, such as scan and communications administration commands are treated as reads. daisy chain communications employ a 4-bit crc (cyclic redundancy check) using a polynomial of the form 1 + x + x 4 . the first four bits of each daisy chain transmission contain the st ack address, which can be any number from 0001 to 1110. all devices respond to the address all (1111) and identify (0000) stac k addresses. the fifth bit is set to ?1? for write and ?0? for read. the rules for daisy chain installations are shown in table 19 . crc calculation daisy chain communications employ a 4-bit crc using a polynomial of the form 1 + x + x 4 . the polynomial is implemented as a 4 stage internal xor standard linear feedback shift register as shown in figure 38 . the crc value is calculated using the base command data only. the crc value is not included in the calculation. the host microcontroller calculates the crc when sending commands or writing data. the calculation is repeated in the isl94212 and checked for compliance. the isl94212 calculates the crc when responding with data (device reads). the host microcontroller then repeats th e calculation and checks for compliance. table 19. isl94212 data interpretation rules for daisy chain installations first 4 bits in sequence 5 th bit (r /w) page data address interpretation stack address [3:0] (nonzero) 0 011 001000 measure command. data address is followed by 6-bit element address. 0000 0 011 001001 identify command. data addres s is followed by device count data. stack address [3:0] (nonzero) 0 any all other device re ad command. data address is followed by 6 zeros. stack address [3:0] (nonzero) 1 any any device write command. + ff0 ff1 ff2 ff3 + din figure 38. 4-bit crc calculation
isl94212 37 fn7938.1 april 23, 2015 submit document feedback attribute vb_name = "isl94212evb_crc4_lib" ' file - isl94212evb_crc4_lib.bas ' copyright (c) 2010 intersil ' ------------------------------------------------------------- ---------------- option explicit '*********************************************************** ' crc4 routines '*********************************************************** public function checkcrc4(my array() as byte) as boolean 'returns true if crc4 checksum (low nibble of last byte in mya rray) 'is good. array can be any length dim crc4 as byte dim lastnibble as byte lastnibble = myarray(ubound(myarray)) and &hf crc4 = calculatecrc4(myarray) if lastnibble = crc4 then checkcrc4 = true else checkcrc4 = false end if end function public sub addcrc4( myarray() as byte) 'adds crc4 checksum (low nibble in last byte in array) 'array can be any length dim crc4 as byte crc4 = calculatecrc4(myarray) myarray(ubound(myarray)) = (m yarray(ubound(myarray)) and &hf0) or crc4 end sub public function calculatecrc4(b yref myarray() as byte) as byte 'calculates/returns the crc4 c hecksum of array contents exclud ing 'last low nibble. a rray can be any length dim size as integer dim i as integer dim j as integer dim k as integer dim bit0 as boolean, bit1 as boolean, bit2 as boolean, bit3 as boolean dim ff0 as boolean, ff1 as boolean, ff2 as boolean, ff3 as boo lean dim carry as boolean dim arraycopy() as byte dim result as byte 'copy data so we do not clobber source array redim arraycopy(lbound(myarray) to ubound(myarray)) as byte for i = lbound(myarray) to ubound(myarray) arraycopy(i) = myarray(i) next 'initialize bits bit0 = false bit1 = false bit2 = false bit3 = false 'simple implementation of crc4 ( using polynomial 1 + x + x^4) for i = lbound(arraycopy ) to ubound(arraycopy) 'last nibble is ignored for crc4 calculations if i = ubound(arraycopy) then k = 4 else k = 8 end if for j = 1 to k 'shift left one bit carry = (arraycop y(i) and &h80) > 0 arraycopy(i) = (arraycopy(i) and &h7f) * 2 'see isl94212 datasheet, fig 11: 4-bit crc calculation ff0 = carry xor bit3 ff1 = bit0 xor bit3 ff2 = bit1 ff3 = bit2 bit0 = ff0 bit1 = ff1 bit2 = ff2 bit3 = ff3 next j next i 'combine bits to obtain crc4 result result = 0 if bit0 then result = result + 1 end if if bit1 then result = result + 2 end if if bit2 then result = result + 4 end if if bit3 then result = result + 8 end if calculatecrc4 = result end function figure 39. crc calculation routine (visual basic) example
isl94212 38 fn7938.1 april 23, 2015 submit document feedback daisy chain addressing when used in a daisy chain system each individual device dynamically assigns itself a unique address (see ? identify ? on page 40 ). in addition, all daisy chain devices respond to a common address allowing them to be controlled simultaneously (e.g., when using the balance enable and balance inhibit commands). see ? communication and measurement diagrams ? on page 50 and ? communication and measurement timing tables ? on page 56 . the state of the comms select 1, comms select 2, comms rate 0, and comms rate 1 pins can be checked by reading the csel[2:1] and crat[1:0] bits in the comms setup register, (see table 20 ). the size[3:0] bits show the number of devices in the daisy chain and the addr[3:0] bits indicate the location of a device within the daisy chain. examples of the various read an d write command structures for daisy chain installations are shown in figures 40c through 40g . the msb is transmitted first and the lsb is transmitted last. table 20. comms setup register (address 6?h18) 765 13 4 12 3 11 2 10 1 9 0 8 size3 size2 size1 size0 addr3 addr2 addr1 addr0 crat1 crat0 csel2 csel1 figure 40a. device level command: sleep figure 40b. device leve l command: wake up figure 40c. device level command: device 9, scan voltages figure 40d. device read: device 9, get cell 7 data figure 40e. element level command: device 4, measure cell 5 voltage 0 0 1 1 0 0 1 0 1 0 0 0 0 0 0 0 data address (15, 10) zero (9, 4) byte 2 byte 1 msb lsb 1 1 1 1 device address (23, 20) 1 1 1 0 crc (3, 0) byte 0 page (18, 16) r /w 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 data address (15, 10) zero (9, 4) byte 2 byte 1 msb lsb 1 1 1 1 device address (23, 20) 0 1 1 1 crc (3, 0) byte 0 page (18, 16) r /w 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 data address (15, 10) zero (9, 4) byte 2 byte 1 msb lsb 1 0 0 1 device address (23, 20) 1 1 1 1 crc (3, 0) byte 0 page (18, 16) r /w 0 0 0 1 0 0 0 1 1 1 0 0 0 0 0 0 data address (15, 10) zero (9, 4) byte 2 byte 1 msb lsb 1 0 0 1 device address (23, 20) 1 1 0 0 crc (3, 0) byte 0 page (18, 16) r /w 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 data address (15, 10) element address (9, 4) byte 2 byte 1 msb lsb 0 1 0 0 device address (23, 20) 0 1 0 1 crc (3, 0) byte 0 page (18, 16) r /w
isl94212 39 fn7938.1 april 23, 2015 submit document feedback response examples are shown in figures 41a through 41d . figure 40f. identify command figure 40g. device write: de vice 7, write external te mperature limit = 14?h0fff figure 40. daisy chain device read and write examples 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 data address (15, 10) device count (9, 4) byte 2 byte 1 msb lsb 0 0 0 0 device address (23, 20) 0 1 0 0 crc (3, 0) byte 0 page (18, 16) r /w 1 0 1 0 0 1 0 0 1 0 0 0 1 1 1 1 data address (23, 18) data (17, 4) byte 3 byte 2 msb lsb 0 1 1 1 device address (31, 28) 1 0 0 0 crc (3, 0) byte 1 1 1 1 1 1 1 1 1 byte 0 page (26, 24) r /w identify , device 4, mid stack device 0 0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 data address (23, 18) data (17, 4) byte 3 byte 2 msb lsb 1 0 0 1 device address (31, 28) 0 1 0 0 crc (3, 0) byte 1 0 0 0 0 1 0 1 0 byte 0 page (26, 24) r /w 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 data address (23, 18) zeros (17, 4) byte 3 byte 2 msb lsb 1 0 1 0 device address (31, 28) 0 1 0 0 crc (3, 0) byte 1 0 0 0 0 0 0 0 0 byte 0 page (26, 24) r /w 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 data address (23, 18) device type/ address (17, 4) byte 3 byte 2 msb lsb 0 0 0 0 device address (31, 28) 0 1 1 0 crc (3, 0) byte 1 0 0 1 1 0 1 0 0 byte 0 page (26, 24) r /w
isl94212 40 fn7938.1 april 23, 2015 submit document feedback daisy chain commands normal communications include th e normal usage of the read, write and system level commands. system level commands come in two types: action commands such as the scan and measure commands which require the devices to perform measurements and administration commands such as reset. daisy chain devices also use commands such as ack to indicate communications status. all daisy chain communications, except the scan, measure and reset co mmands, require a response from the addressed device. identify identify mode is a special case mode that must be executed before any other communications to daisy chained devices, except for the sleep and wakeup commands. the identify command initiates address assignments to the devices in the daisy chain stack. while in identify mode devices determine their stack position. identify mode is entered on receipt of the ?base? identify command (this is the identify command with the device address set to 6?h00). the top stack device responds ack on receiving the base identify command and then enters the identify mode . other stack devices wait to allow the ack response to be relayed to the host microcontroller then they enter identify mode . once in identify mode all stack devices except the master load address 4?h0 to their stack ad dress register. the master (identified by the state of the comms select pins = 2?b01) loads 4?h1 to its stack address. on receiving the ack response the host microcontroller then sends the identify command wi th stack address 6?h2 (i.e., 24?h0000 0011 0010 0100 0010 0110). the stack address is bolded. the last four bits are the corresponding crc value. the master passes the command onto the stack. the device at stack position 2 responds by setting the stack address bits (addr[3:0]) and stack size bits (size[3:0]) in the comms setup register to 4?h2 and returns the identify re sponse with crc and an address of 6?h32 (i.e., 32?b0000 0011 0010 01 11 0010 0000 0000 1111). the address bits are bolded. the address bits contains the normal stack address (2?h0010) and the state of the comms select pins (2?b11). note that the in an identify response the data lsbs are always zero. the host microcontroller then sends the identify command with stack address 6?h3. device 3 re sponds by setting its stack address and stack size informat ion to 4?h3 and returning the identify response with address 6?h33. devices 1 and 2 set their stack size information to 4?h3. the process continues with the host microcontroller incrementing the stack address unti l all devices in the stack have received their stack address. id entified devices update their stack size information with each new transmission. the stack top device (identified by the state of the comms select pins = 10) loads the stack address and stack size information and returns the identify response with address 6?h2x, where x corresponds to the stack position of the top device. the host microcontroller recognizes the to p stack response and loads the total number of stack devices to local memory. the host microcontroller then sends the i dentify command with data set to 6?h3f. devices exit identify mode on receipt of this command. the stack top device responds ack. an example identify transmit and receive sequence for a stack of 3 devices is shown in figure 42 . when in normal mode , only the base identify command is recognized by devices. any other identify command variant or an identify command sent with a nonzero stack address causes a nak response from th e addressed device(s). figure 41d. device data response: de vice 9, read all cell voltage data figure 41. daisy chain device response examples 0 0 0 1 0 0 1 1 0 0 1 0 1 1 1 0 data address 0ch (311, 306) cell 12 data (305, 292) byte 39 byte 38 msb 1 0 0 1 device address (319,316) 1 1 0 0 crc (291,288) byte 37 0 0 0 1 0 1 0 0 byte 36 0 0 1 0 1 1 0 1 0 1 1 1 data address 0bh (287, 282) cell 11 data (281, 268) byte 35 0 0 0 1 crc (287, 264) byte 34 0 0 0 0 1 0 1 0 byte 33 0 0 0 1 1 1 0 1 1 1 1 0 data address 0ah (263, 258) cell 10 data (257, 244) byte 32 0 0 0 1 crc (243, 240) byte 31 0 0 0 1 0 1 0 0 byte 30 0 0 0 0 0 0 0 1 0 0 1 0 data address 00h (23, 18) pack voltage data (17, 4) byte 2 0 0 0 1 crc (3, 0) byte 1 1 0 0 0 1 1 1 1 byte 0 lsb page (314, 312) r /w
isl94212 41 fn7938.1 april 23, 2015 submit document feedback . identify timing to determine the time required to complete an identify operation, refer to table 21 . in the table are two spi command columns showing the time required to send the identify command and receive the response (with an spi clock of 1mhz.) in the case of the master, there are no daisy chain clocks, so all three bytes of the send and four bytes of the receive are accumulated. for the daisy chain devices, the daisy communication overlaps with two of the spi send bytes and with three of the spi receive bytes, so there is no extra time needed for these bits. once the device receives the identify command, it adds a delay time before sending the response back to the master. then, on receiving the daisy response, the master sends the response to the host through the spi port. there is a column showing the time for each identify command and, in the second column from the right, is a column showing the total accumulated time required to send all identify commands for each of the cell configurations. the final column on the right adds the identify complete timing to the total. the identify complete command takes the same number of clock cycles as the last identify command. figure 42. identify example. stack of 3 devices send identify command tx 03 24 04 rx 03 30 00 0c send identify device 2 tx 03 24 26 rx 03 27 20 0f send identify device 3 tx 03 24 37 rx 03 26 30 05 send identify complete tx 03 27 fe rx 33 30 00 01 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 1 0 0 1 0 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 table 21. identify timing with daisy chain operating at 500khz number of devices (2 minimum) spi command send time ( s) daisy transmit time ( s) response delay (s) daisy receive time (s) spi command receive time (s) time for each device (s) identify total time (s) identify + identify complete time (s) 1 (master) 24 0 0 0 32 56 56 56 2 8 50 18 66 8 150 206 356 3 8 52 18 68 8 154 360 514 4 8 54 18 70 8 158 518 676 5 8 56 18 72 8 162 680 842 6 8 58 18 74 8 166 846 1012 7 8 60 18 76 8 170 1016 1186 8 8 62 18 78 8 174 1190 1364 9 8 64 18 80 8 178 1368 1546 10 8 66 18 82 8 182 1550 1732 11 8 68 18 84 8 186 1736 1922 12 8 70 18 86 8 190 1926 2116 13 8 72 18 88 8 194 2120 2314 14 8 74 18 90 8 198 2318 2516
isl94212 42 fn7938.1 april 23, 2015 submit document feedback ack (acknowledge) ack is used by daisy chain devices to acknowledge receipt of a valid command. ack is also useful as a communications test command: the stack top device returns ack in response to successful receipt of the ack command. no other action is performed in response to an ack. nak (not acknowledge) receipt of an unrecognized comman d by either the target device or the top stack device results in a nak being returned by that device. if a command addressed to all devices using the address all stack address 1111 or the identify stack address 0000 is not recognized by any device, then all devices not recognizing the command respond nak. in this case, the host microcontroller receives the nak response from the lowest stack device that failed to recognize the command. an incomplete command (e.g., one that is less than the length re quired) also causes a nak to be returned. reset all digital registers can be reset to their power-up condition using the reset command. daisy chain devices must be rese t in sequence from top stack device to stack bottom (master) device. sending the reset command to all devices using th e address all stack address has no effect. there is no response from the stack when sending a reset command. all stack address and stack size information is set to zero in response to a reset command. once all devices have been reset it is necessary to reprogram the stack address and stack size information using the identify command. note: a reset command should be issued following a ?hard reset? in which the en pin is toggled. address all the ?address all? stack addre ss 1111 is used with device commands to cause all stack devices to perform functions simultaneously. table 22. identify timing with daisy chain operating at 250khz number of devices (2 minimum) spi command send time (s) daisy transmit time ( s) response delay ( s) daisy receive time (s) spi command receive time (s) time for each device (s) identify total time (s) identify + identify complete time (s) 1 (master) 24 0 0 0 32 56 56 56 2 8 100 34 132 8 282 338 620 3 8 104 34 136 8 290 628 918 4 8 108 34 140 8 298 926 1224 5 8 112 34 144 8 306 1232 1538 6 8 116 34 148 8 314 1546 1860 7 8 120 34 152 8 322 1868 2190 8 8 124 34 156 8 330 2198 2528 9 8 128 34 160 8 338 2536 2874 10 8 132 34 164 8 346 2882 3228 11 8 136 34 168 8 354 3236 3590 12 8 140 34 172 8 362 3598 3960 13 8 144 34 176 8 370 3968 4338 14 8 148 34 180 8 378 4346 4724 table 23. ?address all? compatibility function ?address all? compatible scan voltages yes scan temperatures yes scan mixed yes scan wires yes scan all yes scan continuous no scan inhibit no measure no identify (special command ? only responds to 0000 stack address) no sleep yes nak no ack no comms failure no wakeup yes balance enable yes
isl94212 43 fn7938.1 april 23, 2015 submit document feedback alarm signals bits are set in the following fault data registers: ? overvoltage register (address 6?h00), ? undervoltage register (address 6?h01), ? open wires register (address 6?h02), ? over-temperature register (address 6?h06) bits are also set in the fault status register (address 6?h04) in response to a fault being detected. additionally, the bits from each of the fault data registers are or?d and reflected to bits in the fault status register (o ne bit per data register). a fault is registered when any of the bits in the fault status register is asserted. two fault re sponse methods are provided to indicate the existence of a fault: a fault response is sent via the daisy chain communications interface and the fault logic output is asserted low immediatel y on detection of the fault. the fault output remains low until the bi ts of all fault data registers and the fault status register are reset (host microcontroller writes 14?h0000 to these registers to clear the bits). the daisy chain fault response is immediate, as long as there is no communication activity on the device ports and comprises the normal fault status register read response. the fault response is only sent for the first fault occurrence. subsequent faults do not activate the fault response until af ter the fault status register has been cleared. if a fault occurs while the device ports are active, then the device waits until communication activi ty ceases before sending the fault response. the host microcontroller has the option to wait for this response before sending th e next message. alternately, the host microcontroller may send the next message immediately (after allowing the daisy chain ports to clear ? see ? sequential daisy chain communications ? on page 55 ). any conflicts resulting from additional tran smissions from the stack are recognized by the lack of response from the stack. table 24 provides the maximum time from data ready going low for the last byte of the normal response to data ready going low for the first byte of the fault response in the case where a fault response is held up by active communications. further, read communications to the device, return the fault response followed by the requested data. write communications return only the fault response. action commands return nothing. the host microcontroller resets th e register bits corresponding to the fault by writing 14?h0000 to th e fault status register, having first cleared the bits in the fault data register(s) if these are set. the device then responds ack as with a normal write response since the fault status bits are now cleared. this also prevents further fault responses unless the fault reappears, in which case the fault response is repeated. watchdog function a watchdog function is provided as part of the daisy chain communications fault detection system. the watchdog has no effect in non-daisy chain systems. the watchdog timeout is settable in two ranges using the lower 7 bits of the watchdog/balance time register (see table 25 ). the low range (7?b0000001 to 7?b0111111) provides timeout settings in 1s increments from 1s to 63s. the high range (7?b1000000 to 7?b1111111) provide timeout setting s in 2 minute intervals from 2 minutes to 128 minutes (see table 26 for details). . a zero setting (7?b0000000) disabl es the watchdog function. a watchdog password function is provided to guard against accidental disabling of the watchd og function. the upper 6 bits of the device setup register must be set to 6?h3a (111010) to allow the watchdog to be set to zero. th e watchdog is disabled by first writing the password to the device setup register (see table 13 on page 30 ) and then writing zero to the lower bits of the watchdog/balance time register. the password function does not prevent changing the watchdog timeout setting to a different nonzero value. balance inhibit yes reset no calculate register checksum no check register checksum no table 24. maximum time between data ready signals ? delayed fault response signals maximum time between data ready assertions unit daisy chain data rate 500 250 125 62.5 khz fault response 68 136 272 544 s table 23. ?address all? compatibility (continued) function ?address all? compatible table 25. watchdog/balance time register (address 6?h15) 765 13 4 12 3 11 2 10 1 9 0 8 btm0 wdg6 wdg5 wdg4 wdg3 wdg2 wdg1 wdg0 btm6 btm5 btm4 btm3 btm2 btm1 table 26. watchdog timeout settings wdg[6:0] timeout 0000000 disabled 0000001 1s 0000010 2s -- 0111110 62s 0111111 63s 1000000 2 min 1000001 4 min -- 1111110 126 min 1111111 128 min
isl94212 44 fn7938.1 april 23, 2015 submit document feedback each device must receive a valid communications sequence before its watchdog timeout period is exceeded. failure to receive valid communications within the required time causes the wdgf bit to be set in the fault status register and the device to be placed in sleep mode , with all measurement and balancing functions disabled. daisy chain devices assert the fault output in response to a watchdog fault and maintain this asserted state while in sleep mode . notice that no watchdog fa ult response is automatically sent on the daisy chain interface. the watchdog continues to function when the isl94212 is in sleep mode . parts in sleep mode assert the fault output when the watchdog timer expires. a valid communications sequence is one that requires an action or response from the device. a ddress all commands, such as the scan and balance commands provide a simple way to reset the watchdog timers on all devices with a single communication. single device communications (e.g., ack ) must be sent individually to each device to reset the watchdog timer in that device. a read of the fault status re gister of each device is also a good way to reset the watchdog timer on each device. this functionality guards against si tuations where a runaway host microcontroller might continually send data. communications faults communication failure all commands except the scan , measure and reset commands require a response from either the stack top device or the target device (see table 27 ), each device in the stack waits for a response from the stack device above. correct receipt of a command is indicated by the correct response. failure to receive a response within a timeout peri od indicates a communications fault. the timeout value is stack position dependent. the device that detects the fault then transmits the communications failure response, which includes its stack address. if the target device receives a communications failure response from the device above then th e target device relays the communications failure followed by the requested data (in the case of a read) or simply relays the communications failure only (in the case of a write, balance command, etc). the maximum time required to return the comm unications failure response to the host microcontroller (the time from the falling edge of the 24th clock pulse of an spi command to receiving a data ready low signal) is given for various data rates in table 28 . a communications fault can be caused by one of three circumstances: the communications system has been compromised, the device causing the fault is in sleep mode or that a daisy chain input port is in the wrong idle state. this latter condition is unlikely but could arise in response to external influence, such as a large transient event. the daisy chain ports are forced to the correct idle condition at the end of each communication. an external event would have the potential to ?flip? the input such that the port settles in the inverse state. a flipped input condition recovers during the normal course of communications. if a flipped input is suspected, having received notification of a communications fault condition for example, the user may send a sequence of all 1?s (e.g., ff ff ff ff) to clear the fault. wait for the resulting nak response and then send an ack to the device that reported the fault. the ?all 1? sequence allows a device to correct a flipped co ndition via normal end of the table 27. summary of normal communications responses and the communications timeout function command top stack device response target device response device waits for a response for this command? read ack data yes write ack ack yes scan voltages - - no scan temperatures -- no scan mixed - - no scan wires - - no scan all - - no scan continuous ack ack no scan inhibit ack ack no measure - - no identify ack nak no sleep ack nak no nak ack ack yes ack ack ack yes comms failure (note) nak nak yes wakeup ack nak no balance enable ack ack yes balance inhibit ack ack yes reset - - no calc checksum ack ack yes check checksum ack ack yes note: comms failure is a device response only and has no meaning as a command. table 28. maximum time to communications failure response maximum time to assertion of data ready unit daisy chain data rate 500 250 125 62.5 khz communications failure response 5.8 11.6 23.2 46.4 ms table 27. summary of normal communications responses and the communications timeout function (continued) command top stack device response target device response device waits for a response for this command?
isl94212 45 fn7938.1 april 23, 2015 submit document feedback communication process. the command fb ff ff ff also works and contains the correct crc value (should this be a consideration in the way the control software is set up). if the process mentioned previously results in a communications failure response, the next step is for the host microcontroller to send a sleep command, wait for a ll stack devices to go to sleep, then send a wakeup command. if successful then the host microcontroller receives an ack once all devices are awake. in the case where a single stack device was asleep, the devices above the sleeping device would not have received the sleep command and would respond to the wakeup sequence with a nak due to incomplete communications. the host microcontroller would then send a command (e.g., ack) to check that all devices are awake. this process can be repeated as often as needed to wakeup sleeping devices. in the event that the wakeup command does not generate a response, this is a likely indica tion that the communications have been compromised. the ho st microcontroller may send a sleep command to all units. if the communications watchdog is enabled then all parts go automatically into sleep mode when the watchdog period expires so long as there are no valid communications activity. table 27 provides a summary of the normal responses and an indicati on if the device waits for a response from the variou s communications commands. scan counter a scan counter is provided to allow confirmation of receipt of the scan and measure commands. this is a 4-bit counter located in the scan count register (page 1, address 6?h16). the counter increments each time a scan or measure command is received. this allows the host microcon troller to compare the counter value before and after the scan or measure command was sent to verify receipt. the counter wraps to zero when overflowed. the scan counter increments whenever the isl94212 receives a scan or measure command. the isl94212 does not perform a requested scan or measure function if there is already a scan or measure function in progress, but it still increments the scan counter. daisy chain communications conflicts conflicts in the daisy chain system can occur if both a stack device and the host microcontrolle r are transmitting at the same time, or if more than one stac k device transmits at the same time. conflicts caused by a stack device transmitting at the same time as the host microcontrolle r are recognized by the absence of the required response (e.g., an ack response to a write command), or by the scan counter not being incremented in the case of scan and measure commands. conflicts which arise from more than one device transmitting simultaneously can occur if two devices detect faults at the same time. this can occur when the stac k is operating normally (e.g., if two devices register an undervolta ge fault in response to a scan voltages command sent to all de vices). it is recommended that the host microcontroller checks the fault status register contents of all devices whenever a fault response is received from one device. memory checksum there are two checksum operations, one for the eeprom and one for the page 2 registers. two registers are provided to verify the contents of eeprom memory. one (page 4, address 6?h3f) contains the correct checksum value, which is calculated during factory testing at intersil. the other (page 5, address 6?h00) contains the checksum value calculated each time the nonvolatile memory is loaded to shadow registers, either after a power cycle or after a device reset. an inequality between these two numbers indicates corruption of the shadow regi ster contents (and possible corruption of eeprom data). th e external microc ontroller needs to compare the two registers, sinc e it is not automatic. resetting the device (using the reset command) reloads the shadow registers. a persistent difference between these two register values indicates eeprom corruption. all page 2 registers (device config uration registers) are subject to a checksum calculation. a calculate register checksum command calculates the page 2 checksum and saves the value internally (it is not accessible). the calculate register checksum command may be run any time, bu t should be sent whenever a page 2 register is changed. a check register checksum command recalculates the page 2 checksum and compares it to the internal value. the occurrence of a page 2 checksum error sets the par bit in the fault status register and causes a fault response accordingly. the normal response to a par error is for the host microcontroller to rewrite the page 2 register contents. a par fault also causes the device to cease any scanning or cell balancing activity. see items 42 through 49 in table 30 on page 47 . settling time following diagnostic activity the majority of diagnostic functi ons within the isl94212 do not affect other system activity and there is no requirement to wait before conducting further measurements. the exceptions to this are the open wire test and cell balancing functions. open wire test the open wire test loads each vcn pin in turn with 150a or 1ma current. this disturbs the cell voltage measurement while the test is being applied e.g., a 1ma test current applied with an input path resistance of 1k reduces the pin voltage by 1v. the time required for the cell voltage to settle following the open wire test is dependent on the time constant of components used in the cell input circuit. th e standard input circuit ( figure 50 on page 73 ) with the components given in table 48 on page 77 provide settling to within 0.1mv in approximately 2.8ms. this time should be added at the end of each open wire scan to allow the cell voltages to settle. cell balancing the standard applic ations circuit ( figure 50 on page 73 ) configures the balancing circuits so that the cell input measurement reads close to zero volts when balancing is activated. there are time consta nts associated with the turn-on
isl94212 46 fn7938.1 april 23, 2015 submit document feedback and turn-off characteristics of the cell balancing system that must be allowed for when conducting cell voltage measurements. the turn-on time of the balancing circuit is primarily a function of the 25a drive current of the cell balancing output and the gate charge characteristic of the mosfet and needs to be determined for a particular setup. turn-on settling times to within 2mv of final ?on? value are typically less than 5ms. the turn-off time is a function of the mosfet gate charge and the vgs connected resistor and capacitor values (for example r 27 and c 27 in figure 50 on page 73 ) and is generally longer than the turn-on time. as with the turn-on case, the turn-off time needs to be determined for the particular components used. turn-off settling times in the range 10ms to 15ms are typical for settling to within 0.1mv of final value. fault signal filtering filtering is provided for the cell overvoltage, cell undervoltage, v bat open and vss open tests. these fault signals use a totalizing method in which an unbroken sequence of positive results is required to validate a fault condition. the sequence length (number of sequ ential positive samples) is set by the [tot2:0] bits in the fault setup register. see table 29 . separate filter functions are provided for each cell input and for the v bat and vss open faults. the filter is reset whenever a test results in a negative result (no fa ult). all filters are reset when the fault status register [tot2:0] bi ts are changed. when a fault is detected, the [tot2:0] bits should be rewritten. the cell overvoltage, cell undervoltage, v bat open and vss open faults are sampled at the same time at the end of a scan voltages command. the cell unde rvoltage and cell overvoltage signals are also checked follo wing a measure cell voltage command. fault diagnostics the isl94212 incorporates extens ive fault diagnostics functions, which include cell overvoltage and undervoltage as well as open cell input detection. the current status of all faults is accessible using the isl94212 registers. table 30 shows a summary of commands and responses for the various fault diagnostics functions. table 29. fault totalizing time (ms) as a function of scan interval and number of totalized samples scan interval code scan interval (ms) totalize ? fault setup register 1 000 2 001 4 010 8 011 16 100 32 101 64 110 128 111 0000 16 16 32 64 128 256 512 1024 2048 0001 32 32 64 128 256 512 1024 2048 4096 0010 64 64 128 256 512 1024 2048 4096 8192 0011 128 128 256 512 1024 2048 4096 8192 16384 0100 256 256 512 1024 2048 4096 8192 16384 32768 0101 512 512 1024 2048 4096 8192 16384 32768 65536 0110 1024 1024 2048 4096 8192 16384 32768 65536 131072 0111 2048 2048 4096 8192 16384 32768 65536 131072 262144 1000 4096 4096 8192 16384 32768 65536 131072 262144 524288 1001 8192 8192 16384 32768 65536 131072 262144 524288 1048576 1010 16384 16384 32768 65536 131072 262144 524288 1048576 2097152 1011 32768 32768 65536 131072 262144 524288 1048576 2097152 4194304 1100 65536 65536 131072 262144 524288 1048576 2097152 4194304 8388608
isl94212 47 fn7938.1 april 23, 2015 submit document feedback table 30. summary of fault diagnostics commands and responses item diagnostic function action required register read/write comments 1 static fault detection functions. check fault status (or look for normal fault response) read fault status register the main internal functions of the isl94212 are monitored continuously. bits are set in the faul t status register is response to faults being detected in these functions. 2 oscillator check function check for device in sleep mode if stack returns a communications failure response. oscillator faults are detected as part of the static fault detection functions. the response to an oscillator fault detection is to set the osc bit in the fault status register and then to enter sleep mode . a sleeping device does not respond to normal communications, producing a communications failure no tification from the next device down the stack. the normal recovery procedure is send repeated sleep and wakeup commands ensure all devices are awake. 3 cell overvoltage set cell overvoltage limit write overvoltage limit register full scale value 14'h1fff = 5v 4 set fault filter sample value write tot bits in fault setup register default is 3'b011 (8 samples) - (see ? fault setup: ? on page 64 ) 5 identify which inputs have cells connected write cell setup register a '0' bit value indicates cell is connec ted. a '1' bit value indicates no cell connected to this input. the overvoltage test is not applied to unconnected cells. 6 scan cell voltages send scan voltages command a cell overvoltage condition is fla gged after a number of sequential overvoltage conditions are recorded for a single cell. the number is programmed above in item 4. 7 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 8 check overvoltage fault register read overvoltage fault register only required if the fault status register returns a fault condition. 9 reset fault bits reset bits in overvoltage fault register followed and bits in fault status register. 10 reset fault filter change the value of the [tot2:0] bi ts in the fault setup register and then change back to the required value. this resets the filter. the filter is also reset if a false overvoltage test is encountered. 11 cell undervoltage set cell undervoltage limit write undervoltage limit register full scale value 14'h1fff = 5v 12 set fault filter sample value write tot bits in fault setup register default is 3'b011 (8 samples) 13 identify which inputs have cells connected write cell setup register a '0' bit value indicates cell is connec ted. a '1' bit value indicates no cell connected to this input. the undervoltage test is not applied to unconnected cells. 14 scan cell voltages send scan voltages command a cell undervoltage condition is flagged after a number of sequential undervoltage conditions are recorded for a single cell. the number is programmed above in item 12. 15 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 16 check undervoltage fault register read undervoltage fault register only required if the fault status register returns a fault condition. 17 reset fault bits reset bits in undervoltage fault register followed by bits in fault status register. 18 reset fault filter change the value of the [tot2:0] bi ts in the fault setup register and then change back to the required value. this resets the filter. the filter is also reset if a false undervoltage test is encountered. 19 v bat or vss connection test set fault filter sample value write tot bits in fault setup register default is 3'b011 (8 samples)
isl94212 48 fn7938.1 april 23, 2015 submit document feedback 20 scan cell voltages send scan voltages command a open condition on v bat or vss is flagged after a number of sequential open conditions are recorded fo r a single cell. the number is programmed in item 19. 21 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 22 reset fault bits reset bits in the fa ult status register. 23 reset fault filter change the value of the [tot2:0] bi ts in the fault setup register and then change back to the required value. this resets the filter. the filter is also reset if a false open test is encountered. 24 open wire test set scan current value write device setup register: iscn = 1 or 0 sets scan current to 1ma (recommended) by setting iscn = 1. or, set the scan current to 150a by setting iscn = 0. 25 identify which inputs have cells connected write cell setup register a '0' bit value indicates cell is connec ted. a '1' bit value indicates no cell connected to this input. cell in puts vc2 to vc12: the open wire detection system is disabled for cell inputs with a '1' setting in the cell setup register. cell inputs vc0 and vc1 are not affected by the cell setup register. 26 activate scan wires function send scan wires command wait for scan wires to complete. 27 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 28 check open wire fault register read open wire fault register only required if the fault status register returns a fault condition. 29 reset fault bits reset bits in open wire fault register followed by bits in fault status register. 30 over- temperature indication set external temperature limit write external temp limit register full scale value 14'h3fff = 2.5v 31 identify which inputs are required to be tested write fault setup register bits tst1 to tst4 a '1' bit value indicates input is tested. a '0' bit value indicates input is not tested. 32 scan temperature inputs send scan temperatures command an over-temperature condition is flagged immediately if the input voltage is below the limit value. 33 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 34 check over-temperature fault register read over-temperature fault register only required if the fault status register returns a fault condition. 35 reset fault bits reset bits in over-temperature fault register followed by bits in fault status register. 36 reference check function read reference coefficient a read reference coefficient a register 37 read reference coefficient b read reference coefficient b register 38 read reference coefficient c read reference coefficient c register 39 scan temperature inputs send scan temperatures command 40 read reference voltage value read reference voltage register 41 calculate voltage reference value see voltage reference check calculation in the ? worked examples ? on page 86 of this data sheet. table 30. summary of fault diagnostic s commands and responses (continued) item diagnostic function action required register read/write comments
isl94212 49 fn7938.1 april 23, 2015 submit document feedback 42 register checksum calculate register checksum value send calc register checksum command this causes the isl94212 to calculate a checksum based on the current contents of the page 2 regist ers. this action must be performed each time a change is made to the register contents. the checksum value is stored for later comparison. 43 check register checksum value send check register checksum command the checksum value is recalculated and compared to the value stored by the previous calc register checksum command. the par bit in the fault status register is set if these two numbers are not the same. 44 check fault status read fault status register the device sends the fault status register contents automatically if a fault is detected, if the register value is zero before the fault is detected. 45 re-write registers load all page 2 registers with their correct values. this is only required if a par fault is registered. it is recommended that the host reads back the register contents to verify values prior to sending a calc register checksum command. 46 reset fault bits reset bits in the fa ult status register. 47 eeprom misr checksum read checksum value stored in eeprom read the eeprom misr register 48 read checksum value calculated by isl94212 read the misr checksum register the checksum value is calculated each time the eeprom contents are loaded to registers, either following the application of power, cycling the en pin followed by a host initiated reset command, or simply the host issuing a reset command. 49 compare checksum values correct function is indicated by th e two values being equal. memory corruption is indicated by an unequal comparison. in this event the host should send a reset command and repeat the check process. table 30. summary of fault diagnostic s commands and responses (continued) item diagnostic function action required register read/write comments
isl94212 50 fn7938.1 april 23, 2015 submit document feedback sleep mode devices enter sleep mode in response to a sleep command, a watchdog time out or in response to an oscillator fault. devices wakeup in response to a wakeup command or to a scan continuous cycle if the device was set to sleep mode with scan continuous mode active. using a sleep command or wakeup command does not require that the devices in a stack are identified first. they do not need to know their position in the stack. in a daisy chain system, the sleep command must be written using the address all stack address: 1111. the command is not recognized if sent with an indi vidual device address and causes the addressed device to respond nak. the top stack device responds ack on receiving a valid sleep command. having received a valid sleep command, devices wait before entering the sleep mode . this is to allow time for the top stack device to respond ack, or for all devices that don?t recognize the command to respond nak, and fo r the host microcontroller to respond with another comman d. receipt of any valid communications on port 1 of th e isl94212 before the wait period expires cancels the sleep command. receipt of another sleep command restarts the wait timers. table 31 provides the maximum wait time for various daisy chain data rates. the communications fault checking ti meout is not applied to the sleep command. a problem with the communications is indicated by a lack of response to the host microcontroller. the host microcontroller may choose to do nothing if no response is received in which case devices that received the sleep command go to sleep when the wait time expires. devices that do not receive the message go to sleep when their watchdog timer expires (as long as this is enabled). wakeup the host microcontroller wakes up a stack of sleeping devices by sending the wakeup command to the master stack device. the wakeup command must be writte n using the address all stack address: 1111. the command is no t recognized if sent with an individual device address and causes the master device to respond nak. the master exits sleep mode on receipt of a valid wakeup command and proceeds to transm it the wakeup signal to the next device in the stack. the wakeup signal is a few cycles of a 4khz clock. each device in the chain wakes up on receipt of the wakeup signal and proceeds to send the signal onto the next device. any communications received on port 1 by a device which is transmitting the wakeup signal on port 2 are ignored. the top stack device, after waking up, waits for some time before sending an ack response to the master. this wait time is necessary to allow for the wakeup signal being originated by a stack device other than the master. see ?fault response in sleep mode? in the following section fo r more information. the master device passes the ack on to the host microcontroller to complete the wakeup sequence. the total time required to wakeup a complete stack of devices is dependent on the number of devices in the stack. table 32 gives the maximum time from wakeup command transmission to receipt of ack response (data ready asserted low) for stacks of 8 devices and 14 devices at various daisy chain data rates (interpolate linearly for different number of devices). there is no additional checking for communications faults while devices are waking up. a communications fault is indicated by the host microcontroller not receiving an ack response within the expected time. fault response in sleep mode devices may detect faults if operating in scan continuous mode while also in sleep mode . daisy chain devices registering a fault in sleep mode proceed to wakeup the other devices in the stack (e.g., middle devices send the wakeup signal on both port s). any communications received by a device on one port while it is transmitting the wakeup signal on its other port are ignored. after receiving the wakeup signal, the top stack device waits before sending an ack response on port 1. this is to allow other stack devices to wakeup. the total wait time is dependent on the nu mber of devices in the stack. the time from a device detecting a fault to receipt of the ack response is also dependent on the stack position of the device. see table 32 for maximum response times for stacks of 8 and 14 devices. the normal host microcontroller response to receiving an ack while the stack is in sleep mode is to read the fault status register contents of each device in the stack to determine which device (or devices) has a fault. communication and measurement diagrams collecting voltage and temperat ure data from daisy chained isl94212 devices consists of three separate types of operations: a command to initiate measurement, the measurement itself, and a command and response to retrieve data. commands are the same for all types of operations, but the timing is dependent on the number of devices in the stack, the daisy chain clock rate, and the spi clock rate. table 31. maximum wait time for devices entering sleep mode maximum wait time from transmission of sleep command unit daisy chain data rate 500 250 125 62.5 khz time to enter sleep mode 500 1000 2000 4000 s note: devices exit sleep mode on receipt of a valid wakeup command. table 32. maximum wakeup times for stacks of 8 devices and 14 devices (wakeup command to ack response) maximum wakeup times unit daisy chain data rate 500 250 125 62.5 khz stack of 8 devices 636363 63 ms stack of 14 devices 100 100 100 100 ms
isl94212 51 fn7938.1 april 23, 2015 submit document feedback actual measurement operations occur within the device and start with the last bit of the command byte and end with data being placed in a register. meas urement times are dependent on the isl94212 internal clock. this clock has the same variations (and is related to) the daisy chain clock. responses have different timing calculations, based on the position of the addressed device in the daisy chain stack and the daisy chain and spi clock rates. measurement timing diagrams all measurement timing is derived from the isl94212?s internal oscillators. figures given as typi cal are those obtained with the oscillators operating at their no minal frequencies and with any synchronization timing also at nominal value. maximum figures are those obtained with the oscillators operating at their minimum frequencies and with the maximum time for any synchronization timing. measurement timing begins with a start scan signal. this signal is generated internally by the isl94212 at the last clock falling edge of the scan or measure command. (this is the last falling edge of the spi clock in the case of a standalone or master device, or the last falling edge of the daisy chain clock, in the case of a daisy chain device). daisy chain middle or top devices impose an additional synchron ization delays. communications sent on the spi port are passed on to the master device?s daisy chain port at the end of the first byte of data. then, for each device, there is an additional delay of one daisy chain clock cycle. on receiving the start scan signal, the device initializes measurement circuits and proceeds to perform the requested measurement(s). once the measurements are made, some devices perform additional oper ations, such as checking for overvoltage conditions. the measurement command ends when registers are updated. at this time the registers may be read using a separate command. refer to the ? spi interface timing ( see figures 2 and 3 ) ? on page 13 of the electrical specifications table for the time required to complete each measurement type. a more detailed timing breakdown is provided for each measurement type shown in the following. see figure 43 for the measurement timing for a standalone device. see figure 44 for the measurement timing for daisy chain devices. tables 34 through 39 give the typical an d maximum timing for the critical elements of measurement process. each table shows the timing from the last edge of the scan command clock. scan command measure update registers din sck internal scan internal operation figure 43. measurement timing (standalone) see tables 34 through 39 figure 44. measurement timing (6 device daisy chain). spi scan command din sck internal operation daisy chain scan command scan/measure update registers internal (daisy chain unit 6) unit 2 unit 6 4 daisy chain clocks see figure 46 on page 53 , tables 40 and 41 on page 58 operation (master) see tables 34 through 39 scan/measure update registers see tables 34 through 39
isl94212 52 fn7938.1 april 23, 2015 submit document feedback command timing diagram notes: 14. master adds extra byte of zeros as part of daisy protocol 15. master adds n-2 clocks to allow communication to the end of the chain. figure 45. command timing 4 * t d (p1 receive) (p1 receive) (p1 receive) device 6 device 2 device 14 master (from device 13) to start of scan (master) to start of scan (top/middle) to end of command where: t spi = spi clock period t d = daisy chain clock period t cs:wait = cs high time t lead = cs low to first spi clock t lag = last spi clock cs high n = stack position of target device n = stack position of top device t1a t spi 8 ? t lead t lag ++ 3 ? 2t cswait ? + = t1b t spi 8t lead t lag t d 28 n 2 C + ?? ? +++ ? 2 ? s + = t1c t spi 8 ? t lead t lag ++ t d 34 n 2 C + ?? ? + = daisy clock 12 * t d (p2 transmit) 8* t d 12 * t d t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8 * t d 8* t d 8* t d 8* t d 8 * t d 2 * t d 8* t d 2s 2s 2s (from device 5) 2 * t d 8* t d scan 2 * t d scan 8* t d 8* t d t1b commands: ?scan voltages ? scan temperatures ?scan mixed ?scan wires ?scan all ?measure ?read ?write ?scan continuous ?scan inhibit ? sleep ?nak spi command dout sck cs t lead t lag t cs:wait t spi t1c 2 * t d scan ( note 14 )( note 15 ) t1a
isl94212 53 fn7938.1 april 23, 2015 submit document feedback response timing diagrams responses are different for master, middle, and to p devices. the response timings are shown in figures 46 , 47 , and 48 . figure 46. response timing (master device) device 6 device 2 device 14 master 8* t d 8* t d 8* t d 4*t d (p2 receive) t cs data ready din sck 2s 4 * t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 12 * t d 8* t d 8* t d 8* t d 8* t d where: t spi = spi clock period t d = daisy chain clock period t cs = host delay from data ready low to the cs low t drsp = cs high to data ready high t drwait = data ready high time t lead = cs low to first spi clock t lag = last spi clock cs high n = stack position of top device d = number of data bytes d = 4 for one register read (or ack/nak response) d = 40 for read all voltages d = 22 for read all temperatures d = 22 for read all faults d = 43 for read all setup t2 8 t spi t drsp t drwait t cs t lead t lag ++ +++ ? ?? d ? t drsp t d + 42 n 2 8 + C + ?? ? C 4 ? s + = t2 (p1 transmit) 8 * t d (p1 transmit) (p1 transmit) 2s 8* t d daisy chain ack response t dr:sp t dr:wait cs t lead t lag 2*t d 2s 8 * t d
isl94212 54 fn7938.1 april 23, 2015 submit document feedback notes: 16. top device adds (n - n - 1) daisy clocks to allow communications to the targeted middle stack device. 17. middle stack device adds (n - 2) daisy clocks to allow communications to the master device. figure 47. response timing (middle stack device) response timing diagrams responses are different for master, middle, and to p devices. the response timings are shown in figures 46 , 47 , and 48 . (continued) t cs daisy chain ack response device 6 device 2 device 14 master (p2 receive) (p1 transmit) (p1 transmit) (p1 transmit) data ready din sck (from device 7) where: t d = daisy chain clock period t spi = spi clock period n = stack position of top device n = stack position of middle stack device t cs = delay imposed by host from data ready to the first spi clock cycle d = number of bytes in the middle stack device response e.g. read all cell data = 40 bytes, register or ack response = 4 bytes. t3 t d 50 n n C 1 C + ?? ? 4 ? s + = t4 t spi 8t cs t lead t lag t drsp t d d8n2 C + ? ?? ? ++ + + + ? 2 ? s + = 2s daisy chain read data response t3 t4 2s 7*t d (= n - n - 1) n n 8* t d 8* t d 8* t d 8* t d 7* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 4*t d 8* t d 8* t d 8* t d 8* t d 2s 8* t d (p2 receive) 8* t d 8* t d 8* t d 8* t d response command 4* t d cs t dr:sp t lead t lag 2*t d 2s 8 * t d note 17 note 16
isl94212 55 fn7938.1 april 23, 2015 submit document feedback sequential daisy chain communications when sending a sequence of co mmands to the master device, the host must allow time, after each response and before sending the next command, for th e daisy chain ports of all stack devices (other than the master) to switch to receive mode. this wait time is equal to 8 daisy chain clock cycles and is imposed from the time of the last edge on the master?s input daisy chain port to the last edge of the firs t byte of the subsequent command on the spi, (see figure 33 ). the minimum recommended wait time, between the host receiving th e last edge of a response and sending the first edge of the next command, is given for the various daisy chain data rates in table 33 . figure 48. response timing (top device) response timing diagrams responses are different for master, middle, and to p devices. the response timings are shown in figures 46 , 47 , and 48 . (continued) device 6 device 2 device 14 master 8* t d 8* t d 8* t d 4*t d (p2 receive) t cs data ready din sck 2s 2s 4 * t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 8* t d 12 * t d 8* t d 8* t d 8* t d 8* t d where: t spi = spi clock period t d = daisy chain clock period t cs = host delay from data ready to the first spi clock t drsp = cs high to data ready high t lead = cs low to first spi clock t lag = last spi clock cs high n = stack position of top device d = number of bytes in response t5 t spi 8 ? t lead t lag t drsp +++ t cs t d d8 ? 10 n 2 C ++ ?? ? + 4 ? s ++ = t5 (p1 transmit) 8 * t d (p1 transmit) (p1 transmit) daisy chain data response cs t dr:sp t lead t lag 2*t d 2s 8 * t d
isl94212 56 fn7938.1 april 23, 2015 submit document feedback communication and measurement timing tables measurement timing tables scan voltages the scan voltages command initiates a sequence of measurements starting with a sc an of each cell input from cell 12 to cell 1, followed by a measurement of pack voltage. additional measurements are then performed for the internal temperature and to check the connection integrity test of the vss and v bat inputs. the process completes with the application of calibration parameters and the loading of registers. table 34 shows the times after the start of scan that the cell voltage inputs are sampled. the voltages are held until the adc completes its conversion. scan temperatures the scan temperatures command turns on the tempreg output and, after a 2.5ms settling interval, samples the ext1 to ext4 inputs. tempreg turns off on completion of the ext4 measurement. the reference voltage, ic temperature and multiplexer loopback function ar e also measured. the sequence is completed with respective registers being loaded. figure 49. minimum wait between commands (daisy chain response - top device) din sck unit 2 unit n data ready spi response spi command next spi command minimum wait time between commands. see table 33 table 34. scan voltages function timing - daisy chain master or standalone device event typ (s) max (s) sample cell 12 17 19 sample cell 11 38 42 sample cell 10 59 65 sample cell 9 81 89 sample cell 8 102 112 sample cell 7 123 135 sample cell 6 144 159 sample cell 5 166 182 sample cell 4 187 206 sample cell 3 208 229 sample cell 2 229 252 sample cell 1 251 276 complete cell voltage capture (adc complete). sample vbat 304 334 complete vbat voltage capture 318 349 measure internal temperature 423 465 complete vss test 550 605 complete vbat test 726 799 load registers 766 842 table 35. scan temperatures function timing? daisy chain master or standalone device event elapsed time (s) typ max turn on tempreg 2 2 sample ext1 2518 2770 ~ sample ext4 2564 2820 sample reference 2584 2842 measure internal temperature 2689 2958 load registers 2689 2958
isl94212 57 fn7938.1 april 23, 2015 submit document feedback scan mixed the scan mixed command performs all the functions of the scan voltages command but interposes a measurement of the ext1 input between the cell 7 and cell 6 measurements. scan wires the scan wires command initiates a sequence in which each input is loaded in turn with a te st current for a duration of 4.5ms (default). at the end of this time the input voltage is checked and the test current is turned off. the result of each test is recorded and the open wire fault and faul t status registers are updated (data latched) at the conclusion of the tests. scan all the scan all command combines the s can voltages, scan wires and scan temperatures commands into a single scan function. measure command single parameter measurements of the cell voltages, pack voltage, ext1 to ext4 inputs , ic temperature and reference voltage are performed using the measure command. command timing tables the command timing tables (see tables 40 and 41 ) include the time from the start of the command to the start of an internal operation and the time required for the communication to complete (since the internal oper ation begins before the end of the daisy chain command.) in the case of a comm and that starts a scan or measurement, the host needs to wait unti l the command completes, by reaching the last device, plus a communications wait time (see table 33 ) before sending another command. for a read command, the response begins in the top device immediately following the end of the command. in calculating overall timing, use the time for each target device command. this time is repeated for each device in the daisy chain, except when an ?address all? option is used. in an address all operation, use the command ti ming for the top device in the stack to determine when the command ends, but use the time to start of scan for each device to determine when that device begins its internal voltage sampli ng. for example, in a stack of six devices, it takes 86.9s for the command to complete, but internal operations start at 7.8s for the master, 66.7s for device 2, 68.9s for device 3, etc . table 36. scan mixed function timing ? daisy chain master or standalone device event typ (s) max (s) sample cell 12 17 19 sample cell 11 38 42 sample cell 10 59 65 sample cell 9 80 88 sample cell 8 101 111 sample cell 7 122 134 complete cell voltage capture 12-7 sample ext1 176 194 complete ext1 capture 192 211 sample cell 6 207 228 sample cell 5 228 251 sample cell 4 249 274 sample cell 3 270 297 sample cell 2 291 321 sample cell 1 312 344 complete cell voltage capture 6-1 sample vbat 367 404 complete vbat voltage capture 381 419 load registers 829 911 table 37. scan wires function timing ? daisy chain master or standalone device event elapsed time (ms) typ max turn on vc0 current 0.03 0.05 test vc0 4.5 5.0 turn on vc1 current 4.6 5.1 test vc1 9.1 10.0 ~ turn on vc12 current 54.9 60.3 test vc12 59.4 65.3 load registers 59.4 65.3 table 38. scan all function timing ? daisy chain master or standalone device event elapsed time (ms) typ max start scan voltages 0 0 start scan wires 0.8 0.9 start scan temperatures 60.1 66.2 complete sequence 62.8 69.1 table 39. various measure function timings ? daisy chain master or standalone device event elapsed time (s) typ max measure cell voltage 178 196 measure pack voltage 122 134 measure ext input 2517 2768 measure ic temperature 106 116 measure reference voltage 106 116
isl94212 58 fn7938.1 april 23, 2015 submit document feedback in tables 40 and 41 , the calculation assumes a daisy chain (and internal) clock that is 10% slower than the nominal and an spi clock that is running at the nomi nal speed (since the spi clock is normally crystal controlled.) for the 500khz daisy setting, timing assumes a 450khz clock. response timing tables response timing depends on the nu mber of devices in the stack, the position of the device in the stack, and how many bytes are read back. there are four ?sizes? of read responses that are as follows: ?single register read or ack/na k responses, where four bytes are returned by the read command ? read all voltage response, which returns 40 bytes ? read all temps or read all faults responses, which returns 22 bytes ? read all setup registers response, which returns 43 bytes in the following tables, the master, middle and top device response times for any number of daisy chain devices are included with the command timing for that configuration. the right hand column shows the total time to complete the read operation. this is calculated by equation 4 : where n = number of devices in the stack. in the following tables, internal and daisy clocks are assumed to be slow by 10% and the spi clock is assumed to be at the stated speed. for an example, consider a stack of 6 devices. to get the full scan time with a daisy clock of 500khz and spi clock of 2mhz, it takes 77.6s from the start of the scan all command to the start of the internal scan (see table 40 ), 842s to complete a scan of all voltages (see table 34 on page 56 ), 5.334ms to read all cell voltages from all devices (see table 44 on page 60 ) and 18s delay before issuing another command. in this case, all cell voltages in the host controller can be updated every 6.28ms. table 40. maximum command timing (daisy clock = 500khz, spi clock = 2mhz) target device time to start of scan for target device ( s ) command time to start of response (daisy) (s) 1 13.8 2 68.7 80.1 3 70.9 82.3 4 73.2 84.5 5 75.4 86.7 6 77.6 88.9 7 79.8 91.2 8 82.1 93.4 9 84.3 95.6 10 86.5 97.8 11 88.7 100.1 12 90.9 102.3 13 93.2 104.5 14 95.4 106.7 table 41. maximum command timing (daisy clock = 250khz, spi clock = 2mhz) target device time to start of scan for target device ( s ) command time to start of response (daisy) (s) 1 13.8 2 130.9 155.6 3 135.4 160.1 4 139.8 164.5 5 144.3 168.9 6 148.7 173.4 7 153.2 177.8 8 157.6 182.3 9 162.1 186.7 10 166.5 191.2 11 170.9 195.6 12 175.4 200.1 13 179.8 204.5 14 184.3 208.9 nt command ? ?? n2 C ?? t mid ? ?? t top t master +++ (eq. 4)
isl94212 59 fn7938.1 april 23, 2015 submit document feedback 4-byte response tables 42 and 43 show the calculated timing for read operations for 4 byte responses. this is the timing for an ack or nak, as well as read register command. table 42. read timing (max): 4-byte respon se, daisy clock = 500khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 80 139 110 250 410 3 82 142 201 113 455 702 4 85 144 203 115 666 1004 5 87 146 206 117 880 1314 6 89 148 208 119 1099 1633 7 91 151 210 121 1323 1961 8 93 153 212 124 1550 2298 9 96 155 215 126 1783 2643 10 98 157 217 128 2020 2998 11 100 159 219 130 2261 3361 12 102 162 221 133 2506 3734 13 105 164 223 135 2757 4115 14 107 166 226 137 3011 4505 table 43. read timing (max): 4-byte respon se, daisy clock = 250khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 156 228 204 432 743 3 160 233 383 208 824 1304 4 165 237 388 213 1226 1884 5 169 242 392 217 1636 2480 6 173 246 397 221 2055 3095 7 178 251 401 226 2483 3727 8 182 255 406 230 2919 4378 9 187 259 410 235 3365 5045 10 191 264 415 239 3820 5731 11 196 268 419 244 4283 6435 12 200 273 423 248 4755 7156 13 205 277 428 253 5237 7895 14 209 282 432 257 5727 8652
isl94212 60 fn7938.1 april 23, 2015 submit document feedback 40-byte response tables 44 and 45 show the calculated timing for read operations for 40-byte responses. specifically, this is the timing for a read all voltages command. table 44. read timing (max): 40-byte resp onse, daisy clock = 500khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 80 643 750 1394 1554 3 82 646 841 753 2239 2486 4 85 648 843 755 3090 3428 5 87 650 846 757 3944 4378 6 89 652 848 759 4803 5337 7 91 655 850 761 5667 6305 8 93 657 852 764 6534 7282 9 96 659 855 766 7407 8267 10 98 661 857 768 8284 9262 11 100 663 859 770 9165 10265 12 102 666 861 773 10050 11278 13 105 668 863 775 10941 12299 14 107 670 866 777 11835 13329 table 45. read timing (max): 40-byte resp onse, daisy clock = 250khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 156 732 1484 2216 2527 3 160 737 1663 1488 3888 4368 4 165 741 1668 1493 5570 6228 5 169 746 1672 1497 7260 8104 6 173 750 1677 1501 8959 9999 7 178 755 1681 1506 10667 11911 8 182 759 1686 1510 12383 13842 9 187 763 1690 1515 14109 15789 10 191 768 1695 1519 15844 17755 11 196 772 1699 1524 17587 19739 12 200 777 1703 1528 19339 21740 13 205 781 1708 1533 21101 23759 14 209 786 1712 1537 22871 25796
isl94212 61 fn7938.1 april 23, 2015 submit document feedback 22-byte response tables 46 and 47 show the calculated timi ng of read operations for 22-byte responses. this is the timing for read all temperature or read all faults command. table 46. read timing (max): 22-byte resp onse, daisy clock = 500khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 80 391 430 822 982 3 82 394 521 433 1347 1594 4 85 396 523 435 1878 2216 5 87 398 526 437 2412 2846 6 89 400 528 439 2951 3485 7 91 403 530 441 3495 4133 8 93 405 532 444 4042 4790 9 96 407 535 446 4595 5455 10 98 409 537 448 5152 6130 11 100 411 539 450 5713 6813 12 102 414 541 453 6278 7506 13 105 416 543 455 6849 8207 14 107 418 546 457 7423 8917 table 47. read timing (max): 22-byte respon se, daisy clock = 250khz, spi clock = 2mhz top stack device command time to start of response (each daisy device) ( s ) master response time to complete response (daisy) ( s ) middle response time to complete response (each mid daisy device) ( s ) top response time to complete response (daisy) ( s ) response all devices ( s ) command + response all devices ( s ) 2 156 480 844 1324 1635 3 160 485 1023 848 2356 2836 4 165 489 1028 853 3398 4056 5 169 494 1032 857 4448 5292 6 173 498 1037 861 5507 6547 7 178 503 1041 866 6575 7819 8 182 507 1046 870 7651 9110 9 187 511 1050 875 8737 10417 10 191 516 1055 879 9832 11743 11 196 520 1059 884 10935 13087 12 200 525 1063 888 12047 14448 13 205 529 1068 893 13169 15827 14 209 534 1072 897 14299 17224
isl94212 62 fn7938.1 april 23, 2015 submit document feedback system registers system registers contain 14-bits each. all register locations are memory mapped using a 9-bit address. the msbs of the address form a 3-bit page address. page 1 (3?b001) registers are the measurement result registers for cell voltages and temperatures. page 3 (3?b011) is used for commands. pages 1 and 3 are not subject to the checksum calcul ations. page addresses 4 and 5 (3?b100 and 3b?101), with the exception of the eeprom checksum registers, are rese rved for internal functions. all page 2 registers (device configuration registers), together with the eeprom checksum registers, are subject to a checksum calculation. the checksum is calculated in response to the calculate register checksum command using a multiple input shift register (misr) error detection technique. the checksum is tested in response to a check register checksum command. the occurrence of a checksum error sets the par bit in the fault status register and causes a fault response accordingly. the normal response to a par error is for the host microcontroller to re-write the page 2 register contents. a par fault also causes the device to cease any scanning or cell balancing activity. a description of each register is included in ? register descriptions ? as follows and includes a depiction of the register with bit names and initialization values at power-up, when the en pin is toggled and the device receives a reset command, or when the device is reset. bits which reflect the state of external pins are notated ?pin? in the initialization space. bits which reflect the state of nonvolatile memory bits (eeprom) are notated ?nv? in the initialization space. initialization values are shown below each bit name. reserved bits (indicated by grey areas) should be ignored when reading and should be set to ?0? when writing to them. register descriptions cell voltage data base addr (page) access address range description 3?b001 read only 6?h00 - 6?h0c and 6?h0f measured cell voltage and pack voltage values. address 001111 accesses all cell and pack voltage data with one read operation. see figure 41d on page 40 . cell and pack voltage values are output as 13-bit signed integers with the 14 th bit (msb) denoting the sign, (e.g., positive full scale is 14?h1fff, 8191 deci mal, negative full scale is 14?h2000, 8192 decimal). access page addr register address description read only 3?b001 6?h00 vbat voltage 6?h01 cell 1 voltage 6?h02 cell 2 voltage 6?h03 cell 3 voltage 6?h04 cell 4 voltage 6?h05 cell 5 voltage 6?h06 cell 6 voltage 6?h07 cell 7 voltage 6?h08 cell 8 voltage 6?h09 cell 9 voltage 6?h0a cell 10 voltage 6?h0b cell 11 voltage 6?h0c cell 12 voltage 6?h0f read all cell voltages if ? hexvalue 10 8191 ? vbat hexvalue 10 16384 C ?? 15.9350784 2.5 ? ? 8192 --------------------------------------------------------------- --------------------------------------------------------------- ------- - = ? C ?? 22.5 ? ? 8192 --------------------------------------------------------------- ------------------------------------- = ? ? 8192 --------------------------------------------------------------- ---------------- = ? ? ? 8192 ----------------------------------------------------- = temperature data, secondary volt age reference data, scan count base addr (page) access address range description 3?b001 see individual register 6?h10 - 6?h16 and 6?h1f measured temperature, second ary reference, scan count. address 011111 accesses all these data in a continuous read (see figure 41d on page 40 .) temperature and reference values are output as 14-bit unsigned integers, (e.g., full scale is 14?h3fff (16383 decimal)). vtemp hexvalue 10 2.5 ? 16384 -------------------------------------------- =
isl94212 63 fn7938.1 april 23, 2015 submit document feedback access page addr register address description read only 3?b001 6?h10 internal temperature reading. 6?h11 external temperature input 1 reading. 6?h12 external temperature input 2 reading. 6?h13 external temperature input 3 reading. 6?h14 external temperature input 4 reading. 6?h15 reference voltage (raw adc) value. use to calculate corrected reference value using reference coefficient data. see page 2 data, address 6?h38 ? 6?h3a. read/ write 3?h001 6?h16 scan count: current scan instruction count. count is incremented each time a scan command is received and wraps to zero when overflowed. register may be compar ed to previous value to confirm scan command receipt. bit designations: 131211109876543210 reserved scn3 scn2 scn1 scn0 0 0 0 0 0 0 0 0 0 00000 read only 3?h001 6?h1f read all: temperature data, secondary voltage reference data, scan count (locations 6?h10 - 6?h16) fault registers base addr (page) access address range description 3?h010 read/ write 6?h00 - 6?h05 and 6?h0f fault registers. fault setup and status information. address 6? h0f accesses all fault data in a continuous read (daisy chain configuration only). see figure 41d on page 40 . access page addr register address description read/ write 3?h010 6?h00 overvoltage fault: overvoltage fault on cells 12 to 1 correspond with bits of12 to of1, respectively. default values are all zero. bits are set to 1 when faults are detected. the contents of this register may be reset via register write (14?h0000). 131211109876543210 reserved of12 of11 of10 of9 of8 of7 of6 of5 of4 of3 of2 of1 0 0000000000000 read/ write 3?h010 6?h01 undervoltage fault: undervoltage fault on cells 12 to 1 correspo nd with bits uf12 to uf1, respectively. default values are all zero. bits are set to 1 when faults are detected. the contents of this register may be reset via register write (14?h0000). 131211109876543210 reserved uf12 uf11 uf10 uf9 uf8 uf7 uf6 uf5 uf4 uf3 uf2 uf1 0 0000000000000 read/ write 3?h010 6?h02 open wire fault: open wire fault on pins vc12 to vc0 corresp ond with bits oc12 to oc0, respectively. default values are all zero. bits are set to 1 when faults are detected. the contents of this register may be reset via register write (14?h0000). 131211109876543210 reser ved oc12 oc11 oc10 oc9 oc8 oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 00000000000000
isl94212 64 fn7938.1 april 23, 2015 submit document feedback read/ write 3?h010 6?h03 fault setup: these bits control various fault configurations. default values are shown below, as are descriptions of each bit. 131211109876543210 reser ved tst4 tst3 tst2 tst1 tst0 tot2 tot1 tot0 wscn scn3 scn2 scn1 scn0 00001001110000 scn0, 1, 2, 3 scan interval code. decoded to provide the scan interval setup for the auto scan function. initialized to 0000 (16ms scan interval). see table 2 on page 23 . wscn scan wires timing control. set to 1 for tracki ng of the temperature scan interval. set to 0 for tracking of the cell voltage scan interval above 512ms. interval is fixed at 512ms for faster cell scan rates. see table 2 on page 23 . tot0, 1, 2 fault totalize code bits. decoded to provide the required fault totalization. an unbroken sequence of positive fault results equal to the totalize amount is needed to verify a fault condition. initialized to 011 (8 sample totalizing.) see table 29 on page 46 . this register must be re-written following an error detection resulting from totalizer overflow. tst0 controls temperature testing of internal ic temperature. set bit to 1 to enable internal temperature test. set to 0 to disable (not recommended). initialized to 1 (on). tst1 to tst4 controls temperature testing on the external temperature inputs 1 to 4, respectively. set bit to 1 to enable the corresponding temperature test. set to 0 to disable. allows external inputs to be used for general voltage monitoring without imposing a limit value. tst1 to tst4 are initialized to 0 (off). access page addr register address description
isl94212 65 fn7938.1 april 23, 2015 submit document feedback read/ write 3?h010 6?h04 fault status: the fault logic output is an or function of the bits in this regi ster: the output will be asserted low if any bits in the fault status register are set. 131211109876543210 mux reg ref par ovss ov bat ow uv ov ot wdgf osc reserved 000000000000 0 0 osc oscillator fault bit. bit is set in response to a fault on either the 4mhz or 32khz oscillators. note that communications functions may be di srupted by a fault in the 4mhz oscillator. wdgf watchdog timeout fault. bit is set in response to a watchdog timeout. ot over-temperature fault. ?or? of over-temperature fault bi ts: tflt0 to tflt4. this bit is latched. the bits in the over-temperature fault register must first be reset before this bit can be reset. reset by writing 14?h0000 to this register. ov overvoltage fault . ?or? of overvoltage fault bits: of1 to of12. this bit is latched. the bits in the overvoltage fault register must first be reset before this bit can be reset. reset by writing 14?h0000 to this register. uv undervoltage fault . ?or? of undervoltage fault bits: uf1 to uf12. this bit is latched. the bits in the undervoltage fault register must first be reset before this bit can be reset. reset by writing 14?h0000 to this register. ow open wire fault. ?or? of open wire fault bits: oc0 to oc12. this bit is latched. the bits in the open wire fault register must first be reset be fore this bit can be reset. reset by writing 14?h0000 to this register. ov bat open wire fault on v bat connection. bit set to 1 when a fault is detected. may be reset via register write (14?h0000). ovss open wire fault on vss connection. bit set to 1 when a fault is detected. may be reset via register write (14?h0000). par register checksum (parity) error. this bit is set in response to a register checksum error. the checksum is calculated and stored in respon se to a calc register checksum command and acts on the contents of all page 2 registers. the check register checksum command is used to repeat the calculation and compare the results to the stored value. the par bit is then set if the two results are not equal. this bit is not set in response to a nonvolatile eeprom memory checksum error. see table on page 71 . ref voltage reference fault. this bit is set if the voltage reference value is outside its ?power-good? range. reg voltage regulator fault. this bit is set if a voltage regulator value (v3p3, vcc or v2p5) is outside its ?power-good? range. mux temperature multiplexer error. this bit is set if the vcc loopback check returns a fault. the vcc loopback check is performed at the end of each temperature scan. read/ write 3?h010 6?h05 cell setup: default values are shown below, as are descriptions of each bit. 131211109876543210 ffsn ffsp c12 c11 c10 c9 c8 c7 c6 c5 c4 c3 c2 c1 00000000000000 c1 to c12 enable/disable cell overvoltage, undervoltage and open wire detection on cell 1 to 12, respectively. set to 1 to disable ov/uv and open wire tests. ffsp force adc input to full scale positive. all cell scan readings forced to 14'h1fff. all temperature scan readings forced to 14'h3fff. ffsn force adc input to full scale negative. al l cell scan readings forced to 14'h2000. all temperature scan readings forced to 14'h0000. note: the adc input functions normally if both ffsn and ffsp are set to '1' but this setting is not supported. access page addr register address description
isl94212 66 fn7938.1 april 23, 2015 submit document feedback read/ write 3?h010 6?h06 over-temperature fault: over-temperature fault on cells 12 to 1 correspond with bits of12 to of1, respectively. default values are all zero. bits are set to 1 when fault are detected. the contents of this register may be reset via register write (14?h0000). 131211109876543210 reserved tflt4 tflt3 tflt2 tflt1 tflt0 0 0 0 0 0 0 0 0 000000 tflt0 internal over-temperature fault. bit set to 1 when a fault is detected. may be reset via register write (14?h0000). tflt1 - tflt4 external over-temperature inputs 1 to 4 (respectively.) bit set to 1 when a fault is detected. may be reset via register write (14?h0000). read only 3?h010 6?h0f read all fault and cell setup data from locations: 6?h00 - 6?h06. see figure 41d on page 40 . access page addr register address description setup registers base addr (page) access address range description 3?b010 6?h10 - 6?h1d and 6?h1f device setup registers. all device setup data. access page addr register address description read/ write 3?b010 6?h10 overvoltage limit: overvoltage limit value overvoltage limit is compared to the measured values for cell s 1 to 12 to test for an overvoltage condition at any of the cells. bit 0 is the lsb, bit 12 is the msb. bi t 13 is not used and must be set to 0. 131211109876543210 reser ved ov12 ov11 ov10 ov9 ov8 ov7 ov6 ov5 ov4 ov3 ov2 ov1 ov0 01111111111111 read/ write 3?b010 6?h11 undervoltage limit: undervoltage limit value undervoltage limit is compared to the measured values for cells 1 to 12 to test for an undervoltage condition at any of the cells. bit 0 is the lsb, bit 12 is the msb. bi t 13 is not used and must be set to 0. 131211109876543210 reser ved uv12 uv11 uv10 uv9 uv8 uv7 uv6 uv5 uv4 uv3 uv2 uv1 uv0 00000000000000 read/ write 3?b010 6?h12 external temperature limit: over-temperature limit value over-temperature limit is compared to the measured valu es for external temperatures 1 to 4 to test for an over-temperature condition at any input. the temperat ure limit assumes ntc temperature measurement devices (i.e., an over-temperature condition is indicated by a temperature reading below the limit value). bit 0 is the lsb, bit 13 is the msb. 131211109876543210 etl13 etl12 etl11 etl10 etl9 etl8 etl7 etl6 etl5 etl4 etl3 etl2 etl1 etl0 00000000000000
isl94212 67 fn7938.1 april 23, 2015 submit document feedback read/ write 3?b010 6?h13 balance setup: default values are shown below, as are descriptions of each bit. 131211109876543210 reserved ben bsp3 bsp2 bsp1 bsp0 bwt2 bwt1 bwt0 bmd1 bmd0 0 0 0 00000000000 bmd0, 1 balance mode . these bits set balance mode. bmd1 bmd0 mode 00 off 01 manual 10 timed 11 auto bwt0, 1, 2 balance wait time. register contents are decoded to provide the required wait time between device balancing. this is to assist with thermal management and is used with the auto balance mode . see table 4 on page 25 . bsp0, 1, 2, 3 balance status register pointer. points to one of the 13 incidents of the balance status register. balance status register 0 is used for manual balance mode and timed balance mode . balance status registers 1 to 12 are used for auto balance mode . reads and writes to the balance status register are accomplish ed by first configuring the balance status register pointer (e.g., to read (write) balance status register 5, load 0101 to the balance status register pointer, then read (write) to the balance status register). see table 7 on page 26 . ben balance enable. set to ?1? to enable balancing. ?0? inhi bits balancing. setting or clearing this bit does not affect any other register contents. balance enable and balance inhibit commands are provided to allow control of this function without requiring a register write. these commands have the same effect as setti ng this bit directly. this bit is cleared automatically when balancing is complete and the eob bit (see ? 6?h19 ? on page 68 ) is set. read/ write 3?b010 6?h14 balance status the balance status register is a multiple incidence regi ster controlled by the bsp0-4 bits in the balance setup register . see table 7 on page 26 . bit 0 is the lsb, bit 11 is the msb. 131211109876543210 reserved bal 12 bal 11 bal 10 bal 8 bal 8 bal 7 bal 6 bal 5 bal 4 bal 3 bal 2 bal 1 0 0000000000000 bal1 to bal12 cell 1 to cell 12 balance control, respectively. a bit set to 1 enables balance control (turns fet on) of the corresponding cell. writing this bit enables balance output for the current incidence of the balance status register for th e cells corresponding to the particular bits, depending on the condition of ben in the balance setup register. read this bit to determine the current status of each cell?s balance control. read/ write 3?b010 6?h15 watchdog/balance time defaults are shown below: 131211109876543210 btm6 btm5 btm4 btm3 btm2 btm1 btm0 wdg6 wdg5 wdg4 wdg3 wdg2 wdg1 wdg0 00000001111111 wdg0 to wdg6 watchdog timeout setting. decoded to pr ovide the time out value for the watchdog function. see ? watchdog function ? on page 43 for details. the watchdog may only be disabled (set to 7?h00) if the watchdog password is set. the watchdog setting can be changed to a nonzero value without writing to the watchdog password. see ? device setup register ? on page 30 . initialized to 7?h7f (128 minutes). btm0 to btm6 balance timeout setting. decoded to provide the time out value for timed balance mode and auto balance mode . initialized to 7?00 (disabled). see table 9 on page 27 . access page addr register address description
isl94212 68 fn7938.1 april 23, 2015 submit document feedback read/ write 3?b010 6?h16 6?h17 user register 28 bits of register space arranged as 2 x 14 bits available for user data. these registers have no effect on the operation of the isl94212. these registers are included in the register checksum function. read only 3?b010 6?h18 comms setup 131211109876543210 reserved crat1 crat0 csel 2 csel 1 size 3 size 2 size 1 size 0 addr 3 addr 2 addr 1 addr 0 0 0coms rate1 pin coms rate0 pin coms sel2 pin coms sel1 pin 00000000 addr0-3 device stack address. the stack address (d evice position in the stack) is determined automatically by the device in response to an ?identify? command. the resulting address is stored in addr0-3 and is used internally for communications paring and sequencing. the stack address may be read by the user but not written to. size0-3 device stack size (top stack device address). corresponds to the number of devices in the stack. the stack size is determined automatically by the stack devices in response to an ?identify? command. the resulting number is st ored in size0-3 and is used internally for communications paring and sequencing. the stack size may be read by the user but not written to. csel1, 2 communications setup bits . these bits reflect the state of the comms select 1,2 pins and determine the operating mode of the communications ports. see table 15 on page 31 . crat0, 1 communications rate bits . these bits reflect the state of the comms rate 0,1 pins and determine the bit rate of the daisy chain communications system. table 17 on page 34 . read/ write 3?b010 6?h19 device setup 131211109876543210 wp5wp4wp3wp2wp1wp0bdds reser ved iscn scan eob reser ved pin37 pin39 0000000 0000 0pinpin pin37, pin39 these bits indicate the signal level on pin 37 and pin 39 of the device. eob end of balance. this bit is set by the device when balancing is complete. this function is used in the timed balance mode and auto balance mode . the ben bit is cleared as a result of this bit being set. initialized to 1. scan scan continuous mode . this bit is set in response to a scan continuous command and cleared by a scan inhibit command. iscn set wire scan current source/sink values. set to 0 for 150a. set to 1 for 1ma. bdds balance condition during measuremen t. controls the balance condition in scan continuous mode and auto balance mode . set to 1 to have balancing functions turned off 10ms prior to and during cell voltage measurement. set to 0 for normal operation (balancing functions not affected by measurement). wp5:0 watchdog disable password. these bits must be set to 6?h3a (111010) before the watchdog can be disabled. disable watchdog by writing 7?h00 to the watchdog bits. read only value set in eeprom 3?b010 6?h1a internal temperature limit bit 0 is the lsb, bit 13 is the msb. 131211109876543210 itl 13 itl 12 itl 11 itl 10 itl 8 itl 8 itl 7 itl 6 itl 5 itl 4 itl 3 itl 2 itl 1 itl 0 nv nv nv nv nv nv nv nv nv nv nv nv nv nv itl1 to itl12 ic over-temperature limit value. over -temperature limit is compared to the measured values for internal ic temperature to test fo r an over-temperature condition. the internal temperature limit value is stored in nonvolatile memory during test and loaded to these register bits at power-up. the register contents may be read by the user but not written to. read only 3?b010 6?h1b 6?h1c serial number the 28b serial number programmed in nonvolatile memory during factory test is mirrored to these 2 x 14 bit registers. the serial number may be read at any time but may not be written. access page addr register address description
isl94212 69 fn7938.1 april 23, 2015 submit document feedback read only value set in eeprom 3?b010 6?h1d trim voltages 131211109876543210 tv5 tv4 tv3 tv2 tv1 tv0 reserved nv nv nv nv nv nv ignore the conten ts of these bits tv5:0 trim voltage (vnom). the nominal cell voltage is programmed to nonvolatile memory during test and loaded to the trim voltage regist er at power up. the vnom value is a 7-bit representation of the 0v to 5v cell voltage input range with 50 (7?h32) representing 5v (e.g., lsb = 0.1v). the parts are additionally marked wi th the trim voltage by the addition of a two digit code to the part number e.g., 3.3v is denoted by the code 33. (1 bit per 0.1v of trim voltage, so 0 to 50 decimal covers the full range.) read only 3?h010 6?h1f read all setup data from locations: 6?h10 - 6?h1d. see figure 41d on page 40 . access page addr register address description cell balance registers base addr (page) access address range description 3?b010 read/ write 6?h20 - 6?h37 cell balance registers. these registers are loaded with data related to change in soc desired for each cell. this data is then used during auto balance mode . the data value is decremented with each successive adc sample until a zero value is reached. the register space is arranged as 2 x 14-bit per cell for 24 x 14-bit total. the registers are cleared at device power up or by a reset command. see ? auto balance mode ? on page 27 . access page addr register address description read/ write 3?b010 6?h20 cell 1 balance value bits 0 to 13. 6?h21 cell 1 balance value bits 14 to 27. ~ 6?h36 cell 12 balance value bits 0 to 13. 6?h37 cell 12 balance value bits 14 to 27. reference coefficient registers base addr (page) access address range description 3?b010 read only 6?h38 - 6?h3a reference coefficients. bit 13 is the msb, bit 0 is the lsb access page addr register address description read only value set in eeprom 3?b010 6?h38 reference coefficient c reference calibration coefficient c lsb. use with coefficients a and b and th e measured reference value to obtain the compensated reference measurement. this result ma y be compared to limits given in the ?electrical specifications? table beginning on page 7 to check that the reference is within limits. the register contents may be read by the user but not written to. 131211109876543210 rcc 13 rcc 12 rcc 11 rcc 10 rcc 9 rcc 8 rcc 7 rcc 6 rcc 5 rcc 4 rcc 3 rcc 2 rcc 1 rcc 0 nv nv nv nv nv nv nv nv nv nv nv nv nv nv
isl94212 70 fn7938.1 april 23, 2015 submit document feedback read only 3?b010 6?h39 reference coefficient b reference calibration coefficient b lsb. use with coeffici ents a and c and the measured reference value to obtain the compensated reference measurement. this result ma y be compared to limits given in the ?electrical specifications? table beginning on page 7 to check that the reference is within limits. the register contents may be read by the user but not written to. 131211109876543210 rcb 13 rcb 12 rcb 11 rcb 10 rcb 9 rcb 8 rcb 7 rcb 6 rcb 5 rcb 4 rcb 3 rcb 2 rcb 1 rcb 0 nv nv nv nv nv nv nv nv nv nv nv nv nv nv read only 3?b010 6?h3a reference coefficient a reference calibration coefficient a lsb. use with coeffici ents b and c and the measured reference value to obtain the compensated reference measurement. this result ma y be compared to limits given in the ?electrical specifications? table beginning on page 7 to check that the reference is within limits. the register contents may be read by the user but not written to. 131211109876543210 rca 8 rca 7 rca 6 rca 5 rca 4 rca 3 rca 2 rca 1 rca 0 reserved nv nv nv nv nv nv nv nv nv ignore the content of these bits access page addr register address description cells in balance register base addr (page) access address range description 3?b010 read only 6?h3b cells in balance (valid for non-daisy chain configuration only). access page addr register address description read only 3?b010 6?h3b cells balance enabled this register reports the current condition of the cell balance outputs. bit 0 is the lsb, bit 11 is the msb. 131211109876543210 reserved cben 12 cben 11 cben 10 cben 8 cben 8 cben 7 cben 6 cben 5 cben 4 cben 3 cben 2 cben 1 0 0000000000000 bali1 to bali12 indicates the current balancing status of cell 1 to cell 12 (respectively). ?1? indicates balancing is enabled for this cell. ?0? indicates that balancing is turned off. device commands base addr (page) access address range description 3?b011 read only 6?h01 - 6?h14 device commands. actions and communication s administration. not physical registers but memory mapped device commands. commands from host and de vice responses are all configured as reads (base addr msb = 0). write operations breaks the communication ru les and produce nak from the target device.
isl94212 71 fn7938.1 april 23, 2015 submit document feedback nonvolatile memory (eeprom) checksum a checksum is provided to verify the contents of eeprom memory. two registers are provided. one contains the correct checksum value, which is calculated during factory testing at intersil. the other contains the checksum value that is calculated each time the non volatile memory is loaded to shadow registers, either after a power cycle or after a device reset. also refer to ? memory checksum ? on page 45 . page addr register address description 3?b011 6?h01 scan voltages. device responds by scanning v bat and all 12 cell voltages and stor ing the results in local memory. 6?h02 scan temperatures. device responds by scanning external temperatur e inputs, internal temperature, and the secondary voltage reference, and storing the results in local memory. 6?h03 scan mixed. device responds by scanning v bat , cell and ext1 voltages and storing the results in local memory. the ext1 measurement is performed in the middle of the cell voltag e scans to minimize measurement latency between the cell voltages and the voltage on ext1. 6?h04 scan wires. device responds by scanning for pin connection faults and stores the results in local memory. 6?h05 scan all. device responds by performing the functions of the sc an voltages, scan temperatures, and scan wires commands in sequence. results are stored in local memory 6?h06 scan continuous. places the device in scan continuous mode by setting the device setup register scan bit. 6?h07 scan inhibit. stops scan continuous mode by clearing the device setup register scan bit. 6?h08 measure. device responds by measuring a targeted single parameter (cell voltage/v bat /external or internal temperatures or secondary voltage reference). 6?h09 identify. special mode function used to determine device stack position and address. devices record their own stack address and the total number of devices in the stack. see ? identify ? on page 40 for details. 6?h0a sleep. places the part in sleep mode (wakeup via daisy comms). see ? sleep mode ? on page 50 . 6?h0b nak. device response if communications is not recognized. th e device responds nak down the daisy chain to the host microcontroller. the host microcontroller typically retransmits on receiving a nak. 6?h0c ack. used by host microcontroller to verify communication s without changing anything. devices respond with ack. 6?h0e comms failure. used in daisy chain implementations to communicate comms failure. if a communication is not acknowledged by a stack device, the last stack device that did receive the communication responds with comms failure. this is part of the communications integrity checking. devices downstream of a communications fault are alerted to the fault condition by the watchdog function. 6?h0f wakeup. used in daisy chain implementations to wakeup a sleeping stack of devices. the wakeup command is sent to the bottom stack device (master device) via spi. the master device then wakes up the rest of the stack by transmitting a low frequency clock. the top stack device responds ack once it is awake. see ? wakeup ? on page 50 . 6?h10 balance enable. enables cell balancing by setting ben . may be used to enable cell balancing on all devices simultaneously using the address all stack address 1111. 6?h11 balance inhibit. disables cell balancing by clearing ben . may be used to disable cell balancing on all devices simultaneously using the address all stack address 1111. 6?h12 reset. resets all digital registers to its power-up state (i.e., reloads the factory programmed configuration data from non-volatile memory. stops all scan and balancing activity. dais y chain devices must be reset in sequence starting with the top stack device and proceeding down the stack to the bottom (master) device. the reset command must be followed by an identify command (daisy chain configuration) before volatile registers can be re-written. 6?h13 calculate register checksum. calculates the checksum value for the current pa ge 2 register contents (registers with base address 0010). see ? system registers ? on page 62 . 6?h14 check register checksum. verifies the register contents are correct for th e current checksum. an incorrect result sets the par bit in the fault status register, which starts a standard fault response. see ? system registers ? on page 62 . base addr (page) access address range description 100 read only 6?h3f nonvolatile memory multiple input shift register (m isr) register. this checksum value for the nonvolatile memory contents. it is programmed during factory testing at intersil. 101 read only 6?h00 misr shadow register checksum value. this value is calculated when shadow registers are loaded from nonvolatile memory either after a power cycle or a reset.
isl94212 72 fn7938.1 april 23, 2015 submit document feedback applications circuits information typical applications circuits typical applications circuits are shown in figures 50 to 53 . table 48 on page 77 contains recommended component values. all external (off-board) inputs to the isl94212 are protected against battery voltage transients by rc filters, they also provide a current limit function during ho t plug events. the isl94212 is calibrated for use with 1k series protection resistors at the cell inputs. v bat uses a lower value resistor to accommodate the v bat supply current of the isl94212. a value of 27 is used for this component. as much as possible, the time constant produced by the filtering applied to v bat should be matched to that applied to the cell 12 moni toring input. component values given in table 48 produce the required matching characteristics. figure 50 on page 73 shows the standard arrangement for connecting the isl94212 to a stack of 12 cells. the cell input filter is designed to maximize emi suppression. these components should be placed cl ose to the connector with a well controlled ground to minimize noise for the measurement inputs. the balance circuits shown in figure 50 provide normal cell monitoring when the balance circuit is turned off, and a near zero cell voltage reading when the balanc e circuit is turned on. this is part of the diagnostic function of the isl94212. figure 51 on page 74 shows connections for the daisy chain system, setup pins, power supply and external voltage inputs for daisy chain devices other than the master (stack bottom) device. the remaining circuits are discussed in more detail later in this datasheet. figure 52 on page 75 shows the daisy chain system, setup pins, microcontroller interface, powe r supply and external voltage inputs for the daisy chain master device. figure 52 is also applicable to standalone (non-dai sy chain) devices although in this case the daisy chain components connected to dhi2 and dlo2 would be omitted. figure 53 on page 76 shows an alternate arrangement for the battery connections in which the cell input circuits are connected directly to the battery terminal and not via the balance resistor. in this condition the balance diagno stic function capability is removed.
isl94212 73 fn7938.1 april 23, 2015 submit document feedback typical application circuits figure 50. battery connection circuits r29 q1 c27 r27 r2 r28 c2 60 61 vc12 cb12 b12 r32 q2 c28 r30 r3 r31 c3 62 63 vc11 cb11 b11 r35 q3 c29 r33 r4 r34 c4 64 1 vc10 cb10 b10 r36 q4 c30 r37 r5a r38 c5 2 3 vc9 cb9 b9 r39 q5 c31 r40 r6 r41 c6 4 5 vc8 cb8 b8 r42 q6 c32 r43 r7 r44 c7 6 7 vc7 cb7 b7 r45 q7 c33 r46 r8 r47 c8 8 9 vc6 cb6 b6 r48 q8 c34 r49 r9 r50 c9 10 11 vc5 cb5 b5 r51 q9 c35 r52 r10 r53 c10 12 13 vc4 cb4 b4 r54 q10 c36 r55 r11 r56 c11 14 15 vc3 cb3 b3 r57 q11 c37 r58 r12 r59 c12 16 17 vc2 cb2 b2 r60 q12 c38 r61 r13 r62 c13 18 19 vc1 cb1 b1 b0 20 vc0 d1 r1 c1 58 59 vbat vbat b12b 21 vss 22 vss b0b place ? these ? com ponents ? close ? to ? connector isl94212 r5b c39 r71 pack ? voltage isl94212
isl94212 74 fn7938.1 april 23, 2015 submit document feedback figure 51. non battery connections, middle and top daisy chain devices typical application circuits (continued) c44 c45 r65 r66 c43 c42 r63 r64 c51 c52 r69 r70 c50 c49 r67 r68 dhi2 dlo2 56 55 53 52 dhi1 dlo1 comms ? rate ? 0 comms ? rate ? 1 comms ? select ? 1 comms ? select ? 2 43 42 41 40 dgnd 44 connect ? pin ? 47 ? to ? v3p3 ? to ? enable connect ? pin ? 47 ? to ? vss ? to ? disable v2p5 35 base 38 v3p3 36 vcc 34 ref 33 ext4 ext3 ext2 ext1 c58 c59 c60 c61 30 28 26 24 daisy ? up ? hi daisy ? up ? lo daisy ? dn ? hi daisy ? dn ? lo ext ? in ? 4 ext ? in ? 3 ext ? in ? 2 ext ? in ? 1 r83 r84 r85 r86 tempreg 29 place ? these ? components ? close ? to ? connector place ? these ? components ? close ? to ? device v3p3 r81 c53 c56 c55 c54 c57 r82 q13 r87 r90 r93 r96 isl94212 en 47 pack ? voltage connect ? pins ? 40 ? ?43 ? to ? v3p3 ? or ? vss depending ? on ? comms selection ? and ? daisy ? chain ? clock ? speed r100 ext ? return ? (x4) isl94212
isl94212 75 fn7938.1 april 23, 2015 submit document feedback figure 52. non battery connections, master daisy chain device typical application circuits (continued) dhi2 comms ? rate ? 0 comms ? rate ? 1 comms ? select ? 1 comms ? select ? 2 43 42 41 40 dgnd 44 pack ? vol tage v2p5 35 base 38 v3p3 36 vcc 34 ref 33 ext4 ext3 ext2 ext1 c58 c59 c60 c61 30 28 26 24 ext ? in ? 4 ext ? in ? 3 ext ? in ? 2 ext ? in ? 1 r83 r84 r85 r86 tempreg 29 place ? these ? components ? close ? to ? connector place ? these ? components ? close ? to ? device v3p3 r81 c53 c56 c55 c54 c57 r82 q13 r87 r90 r93 r96 isl94212 sclk 53 microcontroller interface cs 52 din 50 dout 49 data ? ready 46 fault 45 en 47 c44 c45 r65 r66 c43 c42 r63 r64 dlo2 56 55 daisy ? up ? hi daisy ? up ? lo connect ? pins ? 40 ? ?43 ? to ? v3p3 ? or ? vss depending ? on ? comms selection ? and ? daisy ? chain ? clock ? speed connect ? pin ? 47 ? to ? v3p3 ? to ? enable connect ? pin ? 47 ? to ? vss ? to ? disable r100 ext ? return ? (x4) isl94212
isl94212 76 fn7938.1 april 23, 2015 submit document feedback figure 53. battery connection circuits alternative configuration typical application circuits (continued) r29 q1 c27 r27 r2 r28 c2 60 61 vc12 cb12 b12 r32 q2 c28 r30 r3 r31 c3 62 63 vc11 cb11 b11 r35 q3 c29 r33 r4 r34 c4 64 1 vc10 cb10 b10 r36 q4 c30 r37 r5 r38 c5 2 3 vc9 cb9 b9 r39 q5 c31 r40 r6 r41 c6 4 5 vc8 cb8 b8 r42 q6 c32 r43 r7 r44 c7 6 7 vc7 cb7 b7 r45 q7 c33 r46 r8 r47 c8 8 9 vc6 cb6 b6 r48 q8 c34 r49 r9 r50 c9 10 11 vc5 cb5 b5 r51 q9 c35 r52 r10 r53 c10 12 13 vc4 cb4 b4 r54 q10 c36 r55 r11 r56 c11 14 15 vc3 cb3 b3 r57 q11 c37 r58 r12 r59 c12 16 17 vc2 cb2 b2 r60 q12 c38 r61 r13 r62 c13 18 19 vc1 cb1 b1 b0 20 vc0 d1 r1 c1 58 59 vbat vbat b12b 21 vss 22 vss b0b place ? these ? components ? close ? to ? connector pack ? voltage isl94212 r71 c39 isl94212 isl94212
isl94212 77 fn7938.1 april 23, 2015 submit document feedback notes on board layout referring to figure 50 on page 73 (battery connection circuits), the basic input filter stru cture comprises resistors r 2 to r 13 , r 71 and capacitors c 2 to c 13 , c 39 . these components provide protection against transients and emi for the cell inputs. they carry the loop currents produced by emi and should be placed as close to the connector as possible. the ground terminals of the capacitors must be connected directly to a solid ground plane. do not use vias to connect these capacitors to the input signal path or to ground. any vias should be placed in line to the signal inputs so that the inductance of these forms a low pass filter with the grounded capacitors. referring to figure 51 on page 74 , the daisy chain components are shown to the top right of the drawing. these are split into two sections. components to the right of this section should be placed close to the board connector with the ground terminals of capacitors connected directly to a solid ground plane. this is the same ground plane that serves the cell inputs. components to the left of this section should be placed as closely to the device as possible. the battery connector and daisy chain connectors should be placed closely to each other on the same edge of the board to minimize any loop current area. two grounds are identified on the circuit diagram. these are nominally referred to as noisy and quiet grounds. the noisy ground, denoted by an ?earth? symbol carries the emi loop currents and digital ground currents while the quiet ground is used to define the decoupling voltage for voltage reference and the analog power supply rail. the quiet and noisy grounds should be joined at the vss pin. keep th e quiet ground area as small as possible. the circuits shown to the bottom right of figure 51 on page 74 provide signal conditioning and emi protection for the external temperature inputs. these inputs are designed to operate with external ntc thermistors. see ? external inputs ? on page 85 for more information about component selection. table 48. recommended component values for figures ( figures 50 to 53 ) resistors value components 0r101 27 r1 33 r82 1k r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r71 100 r29, r32, r35, r36, r39, r42, r45, r48, r5 1, r54, r57, r60, r63, r64, r67, r68, r81 2k r5a, r5b 470 r65, r66, r69, r70 10k r28, r31, r34, r38, r41, r44, r47, r50, r53, r 56, r59, r62, r83, r84, r85, r86, r87, r90, r93, r96, r100a, r100b, r100c, r100d 330k r27, r30, r33, r37, r40, r43, r46, r49, r52, r55, r58, r61 capacitors value voltage components 200p 100 c42, c43, c49, c50 220p 500 c44, c45, c51, c52 10n 50 c27, c28, c29, c30, c31, c32, c33, c34, c35, c36, c37, c38, c58, c59, c60, c61 22n 100 c2, c3, c4, c5, c6, c7, c8, c9, c10, c11, c12, c13, c39 220n 100 c1 1 10 c53, c54, c56 1 100 c55 2.2 10 c57 zener diodes value example components 60v 1n5371brlg d1
isl94212 78 fn7938.1 april 23, 2015 submit document feedback component selection certain failures associated with external components can lead to unsafe conditions in electronic modules. a good example of this is a component that is connected between high energy signal sources failing short. such a condition can easily lead to the component overheating and damaging the board and other components in its proximity. one area to consider with the external circuits on the isl94212 is the capacitors connected to the cell monitoring inputs. these capacitors are normally protected by the series protection resistors but could present a safety hazard in the event of a dual point fault where both the capacitor and associated series resistor fail short. also, a short in one of these capacitors would dissipate the charge in the battery cell if left uncorrected for an extended period of time. it is recommended that capacitors c 1 to c 13 be selected to be ?fail sa fe? or ?open mode? types. an alternative strategy would be to replace each of these capacitors with two devices in series, each with double the value of the single capacitor. a dual point failure in the balancing resistor (r 29 , r 32 , r 35 , etc.) of figure 50 on page 73 and associated balancing mosfet (q 1 to q 12 ) could also give rise to a shorted cell condition. it is recommended that the balancing resistor be replaced by two resistors in series. operating the isl94212 with reduced cell counts when using the isl94212 with fewer than 12 cells it is important to ensure that each used ce ll has a normal input circuit connection to the top and bottom monitoring inputs for that cell. the simplest way to use the isl94212 with any number of cells is to always use the full input circuit arrangement for all inputs, and short together the unused inputs at the battery terminal. in this way each cell input sees a normal source impedance independent of whether or not it is monitoring a cell. the cell balancing components asso ciated with unconnected cell inputs are not required and can be removed. unused cell balance outputs should be tied to the adjacent cell voltage monitoring pin. the input circuit component count can be reduced in cases where fewer than 10 cells are being monitored. it is important that cell inputs that are being used are not connected to other (unused) cell inputs as this would affect measurement accuracy. figure 54 on page 79 , figure 55 on page 80 , and figure 56 on page 81 show examples of systems with 10 cells, 8 cells, and 6 cells, respectively. the component notations and values used in figures 55 and 56 are the same as those used in figures 50 to 53 . in figure 56 the resistor associated with the input filter on vc9 is noted as r 5 , rather than r 5a . this value change is needed to maintain the correct input network impedance in the absence of the cell 9 balance circuits.
isl94212 79 fn7938.1 april 23, 2015 submit document feedback typical application circuits figure 54. battery connection circuits, system with 10 cells r29 q1 c27 r27 r2 r28 c2 60 61 vc12 cb12 b10 r32 q2 c28 r30 r3 r31 c3 62 63 vc11 cb11 b9 r35 q3 c29 r33 r4 r34 c4 64 1 vc10 cb10 b8 r36 q4 c30 r37 r38 c5 2 3 vc9 cb9 b7 r39 q5 c31 r40 r6 r41 c6 4 5 vc8 cb8 b6 r7 c7 6 7 vc7 cb7 r8 c8 8 9 vc6 cb6 r48 q8 c34 r49 r9 r50 c9 10 11 vc5 cb5 b5 r51 q9 c35 r52 r10 r53 c10 12 13 vc4 cb4 b4 r54 q10 c36 r55 r11 r56 c11 14 15 vc3 cb3 b3 r57 q11 c37 r58 r12 r59 c12 16 17 vc2 cb2 b2 r60 q12 c38 r61 r13 r62 c13 18 19 vc1 cb1 b1 b0 20 vc0 d1 r1 c1 58 59 vbat vbat b10b 21 vss 22 vss b0b place ? these ? components ? close ? to ? connector isl94212 r5 r71 c39 pack ? voltage isl94212
isl94212 80 fn7938.1 april 23, 2015 submit document feedback figure 55. battery connection circuits, system with 8 cells typical application circuits (continued) r29 q1 c27 r27 r2 r28 c2 60 61 vc12 cb12 b8 r32 q2 c28 r30 r3 r31 c3 62 63 vc11 cb11 b7 r35 q3 c29 r33 r4 r34 c4 64 1 vc10 cb10 b6 r36 q4 c30 r37 r38 c5 2 3 vc9 cb9 b5 r6 c6 4 5 vc8 cb8 6 7 vc7 cb7 r9 c9 8 9 vc6 cb6 10 11 vc5 cb5 r51 q9 c35 r52 r10 r53 c10 12 13 vc4 cb4 b4 r54 q10 c36 r55 r11 r56 c11 14 15 vc3 cb3 b3 r57 q11 c37 r58 r12 r59 c12 16 17 vc2 cb2 b2 r60 q12 c38 r61 r13 r62 c13 18 19 vc1 cb1 b1 b0 20 vc0 d1 r1 c1 58 59 vbat vbat b8b 21 vss 22 vss b0b place ? these ? components ? close ? to ? connector isl94212 r5 r71 c39 pack ? voltage isl94212
isl94212 81 fn7938.1 april 23, 2015 submit document feedback figure 56. battery connection circuits, system with 6 cells typical application circuits (continued) r29 q1 c27 r27 r2 r28 c2 60 61 vc12 cb12 b6 r32 q2 c28 r30 r3 r31 c3 62 63 vc11 cb11 b5 r35 q3 c29 r33 r4 r34 c4 64 1 vc10 cb10 b4 r38 c5 2 3 vc9 cb9 4 5 vc8 cb8 6 7 vc7 cb7 r10 c10 8 9 vc6 cb6 10 11 vc5 cb5 12 13 vc4 cb4 r54 q10 c36 r55 r11 r56 c11 14 15 vc3 cb3 b3 r57 q11 c37 r58 r12 r59 c12 16 17 vc2 cb2 b2 r60 q12 c38 r61 r13 r62 c13 18 19 vc1 cb1 b1 b0 20 vc0 d1 r1 c1 58 59 vbat vbat b6b 21 vss 22 vss b0b place ? these ? components ? close ? to ? connector isl94212 r5 r71 c39 pack ? voltage isl94212
isl94212 82 fn7938.1 april 23, 2015 submit document feedback power supplies the two vbat pins, along with v3p3, vcc and vddext are used to supply power to the isl94212. power for the high voltage circuits and sleep mode internal regulators is provided via the vbat pins. v3p3 is used to supply the logic circuits and vcc is similarly used to supply the low vo ltage analog circuits. the v3p3 and vcc pins must not be connected to external circuits other than those associated with the isl94212 main voltage regulator. the vddext pin is provided for use with external circuits. the isl94212 main low voltage regulator uses an external npn pass transistor to supply 3.3v power for the v3p3 and vcc pins. this regulator is enabled whenever the isl94212 is in normal mode and may also be used to po wer external circuits via the vddext pin. an internal switch connects the vddext pin to the v3p3 pin. both the main regulator and the switch are off when the part is placed in sleep mode or shutdown mode (en pin low.) the pass transistor?s base is connected to the isl94212 base pin. a suitable configurat ion for the external components associated with the v3p3, vcc and vddext pins is shown in figure 57 . the external pass transistor is required. do not allow this pin to float. voltage reference bypass capacitor a bypass capacitor is required between ref (pin 33) and the analog ground vss. the total value of this capacitor should be in the range 2.0f to 2.5f. use x7r type dielectric capacitors for this function. the isl94212 continuously performs a power-good check on the ref pin voltage starting 20ms after a power-up, enable or wakeup condition. if the ref capacitor is too large, then the reference voltage may not reach its target voltage range before the power-good check starts and result in a ref fault. if the capacitor is too small, then it may lead to inaccurate voltage readings. cell balancing circuits the isl94212 uses external mosfets for the cell balancing function. the gate drive for these is derived from on-chip current sources on the isl94212, which are 25a nominally. the current sources are turned on and off as needed to control the external mosfet devices. the current sources are turned off when the device is in shutdown mode or in sleep mode . the isl94212 uses a mix of n-channel and p-channel mosfets for the external balancing function. the top three cell locations, cell 10, 11, 12 are configured to use p-channel mosfets while the remaining cell locations, cell 1 through 9, use n-channel mosfets. figure 58 shows the circuit detail for one cell balancing system with typical component values. an n-channel mosfet (cell locations 1 through 9) is shown. the gate of the external fet is normally protected against excessive voltages during cell voltage transients by the action of the parasitic cgs and cgd capacitances. these momentarily turn on the fet in the event of a large transient, thus limiting the vgs values to reasonable levels. a 10nf capacitor is included between the mosfet gate and source terminals to protect against emi effects. this capacitor provides a low impedance path to ground at high frequencies and prevents the mosf et turning on in response to high frequency interference. the external component values should be chosen to prevent the 9v clamp at the output from the isl94212 from activating. figure 57. isl94212 regulator and external circuit supply arrangement to ? external ? circuits r1 vddext c3 isl78600 isl78610 vcc v3p3 base c2 c4 c1 r2 q1 pac k voltage d1 isl94212 component value r 1 note 18 r 2 33 c 1 note 19 c 2 1 f c 3 1 f c 4 1 f q 1 note 20 notes: 18. r 1 should be sized to pass the maximum supply current at the minimum specified battery pack voltage. 19. c 1 should be selected to produce a time constant with r 1 of a few milliseconds. c 1 and r 1 provide transient protection for the collector of q 1 . component values and voltage ratings should be obtained through simulation of measurement of the worst case transient expected on v bat . 20. q 1 should be selected for power dissipation at the maximum specified battery voltage and load current. the load current includes the v3p3 and vcc currents for the isl94212 and the maximum current drawn by external circuits supplied via vddext. the voltage rating should be determined as described in note 19 .
isl94212 83 fn7938.1 april 23, 2015 submit document feedback cell voltage measurements during balancing the standard cell balancing circuit ( figure 50 on page 73 and figure 58 on page 84 ) is configured so that the cell measurement is taken from the drain connection of the balancing mosfet. when balancing is enabled for a cell, the resulting cell measurement is then the voltage across the balancing mosfet (vgs voltage). this system provides the diagnostic for the cell balancing function. the input voltage of the cell adjacent to the mosfet drain connection is also affected by this mechanism: the input voltage for this cell increases by the same amount that the voltage of the balance cell decreases. for example, if cell 2 and cell 3 ar e both at 3.6v and balancing is enabled for cell 2, then the volt age across the balancing mosfet may be only 50mv. in this case, cell 2 would read 50mv and cell 3 would read 7.15v. the cell 3 value in this case is outside the measurement range of the cell input. cell 3 would then read full scale voltage, which is 4.9994v. this full scale voltage reading will occur if the sum of the voltages on the two adjacent cells is greater than the total of 5v plus the ?balancing on? voltage of the balanced cell. table 49 shows the cell affected when each cell is balanced. the voltage measurement behavior outlined above is modified by impedances in the cell connector and any associated wiring. the balance current passes through the connections at the top and bottom of the balanced cell. this effect further reduces the measured voltage on the balanc ed cell and also increase the voltage measured on cells abov e and below the balanced cell. for example, if cell 4 is balanced with 100ma and the total impedance of the connector and wiring for each cell connection is 0.1 , then cell 4 would read low by an additional 20mv (10mv due to each connection) while cells 3 and 5 would both read high by 10mv. balancing with scan continuous mode enabled cell balancing may be active while the isl94212 is operating in scan continuous mode . in scan continuous mode the isl94212 scans cell voltages, temperatures and open wire conditions at a rate determined by the scan interval bits in the fault setup register. (see table 2 on page 23 ). the behavior of the balancing functions while operating in scan continuous mode is controlled by the bdds bit in the device setup register. if bdds is set, then cell balancing is inhibited during cell voltage measurements and for 10ms before the cell voltage scan to allow the balance devices to turn off. balancing is reenabled at the end of the scan and then balancing continues. daisy chain communications system the isl94212 daisy chain communications system uses differential, ac-coupled signaling. the external circuit arrangement is symmetrical to provide a bidirectional communications function. the performance of the system under transient voltage and emi conditions is enhanced by the use of a capacitive load. a schematic of th e daisy chain circuit is shown in figure 59 . the basic circuit elements are the series resistor and capacitor elements r 1 and c 1 , which provide the transient current limit and ac coupling functions, and th e line termination components c 2 , which provide the capacitive load. capacitors c 1 and c 2 should be located as closely as possible to the board connector. the ac coupling capacitors c 1 need to be rated for the maximum voltage, including transients, that will be applied to the interface. specific component values are needed for correct operation with each daisy chain data rate and are given in table 50 . the daisy chain operates with st andard unshielded twisted pair wiring. the component values given in table 50 will accommodate cable capacitance values from 0pf to 50pf when operating at the 500khz data ra te. higher cable capacitance values may be accommodated by either reducing the value of c 2 or operating at lower data rates. the values of components in figure 59 are given in table 50 for various daisy chain operating data rates. the circuit and component values in figure 59 and table 50 will accommodate cables with differential capacitance values in the ranges given. this allows a range of cable lengths to be accommodated through careful selection of cable properties. the circuit in figure 59 provides full isolation when used with off board wiring. the daisy chain extern al circuit can be simplified in cases where the daisy chain system is contained within a single board. figure 60 on page 85 and table 51 on page 85 show the circuit arrangement and component values for single board use. in this case the ac coupling capacitors c 1 need only be rated for the maximum transient voltage expected from device to device. table 49. cell readings during balancing cell balanced cell with low reading cell with high reading 11 2 22 3 33 4 44 5 55 6 66 7 77 8 88 9 99* 10* 10 10* 9* 11 11 10 12 12 11 note: *cells 9 and 10 produce a different result from the other cells. cell 9 uses an n-channel mosfet while cell 10 uses a p-channel mosfet. the circuit arrangement used with th ese devices produces approximately half the normal cell voltage when balancing is enabled. the adjacent cell then sees an increase of half the voltage of the balanced cell.
isl94212 84 fn7938.1 april 23, 2015 submit document feedback figure 58. balance circuit arrangement isl94212 figure 59. isl94212 daisy ch ain circuit implementation table 50. component values in figure 59 for various daisy chain data rates component daisy chain clock rates comments 500khz 250khz 125khz 62.5khz c 1 (4 pcs) 220pf 470pf 1nf 2.2nf npo dielectric type capacitors are recommended. please consult intersil if y type or "open mode" devices are required for your application. c 2 (4 pcs) 200pf ( note ) 440pf 940pf 2nf use same dielectric type as c 1 r 1 (4 pcs) 470 ? 470 ? 470 ? 470 ? r 2 (4 pcs) 100 ? 100 ? 100 ? 100 ? cable capacitance range 0 to 50pf 0 to 100pf 0 to 200pf 0 to 400pf note: can be accommodated using two 100pf capacitors in parallel.
isl94212 85 fn7938.1 april 23, 2015 submit document feedback . external inputs the isl94212 provides 4 external inputs for use either as general purpose analog inputs or for ntc type thermistors. each of the external inputs has an internal pull-up resistor, which is connected by a switch to the vcc pin whenever the tempreg output is active. this arrangement results in an open input being pulled up to the v cc voltage. inputs above 15/16 of full scale are registered as open inputs and cause the relevant bit in the over-temperature fault register, along with the ot bit in the fault status register to be set, on condition of the respective temperature test enable bit in the fault setup register. the user must then read the register value associated with the faulty input to determine if the fault was due to an open input (value above 15/16 full scale) or an over-temperature condition (value below the external temp limit setting). the arrangement of the external inputs is shown in figure 61 using the ext4 input as an example. it is important that the components are connected in the sequence shown in figure 61 , e.g., c 1 must be connected such the trace from this capacitor?s positive terminal connects to r 2 before connecting to r 1 . this guarantees the correct operation of the various fault detection functions. the function of each of the components in figure 61 is listed in table 52 together with the diagnostic result of an open or short fault in each component figure 60. isl94212 daisy chain ? bo ard level implementation circuit table 51. daisy chain component values for board level implementation component tolerance daisy chain data rate 500khz 250khz 125khz 62.5khz c 1 (2 pcs) 5% 100pf 220pf 470pf 1nf c 2 (4 pcs) 5% 220pf 470pf 1nf 2.2nf r 1 (4 pcs) 1k ? 1k ? 1k ? 1k ? figure 61. connection of ntc thermistor to input ext4 isl94212
isl94212 86 fn7938.1 april 23, 2015 submit document feedback board level calibration for best accuracy, the isl94212 may be recalibrated after soldering to a board using a simple resistor trim. the adjustment method involves obtaining the average cell reading error for the cell inputs at a single temperature and cell voltage value and applying a select-on-test resistor to zero the average cell reading error. the adjustment system uses a re sistor placed either between vddext and v ref or v ref and vss as shown in figure 62 . the value of resistor r 1 or r 2 is then selected based on the average error measured on all cells at 3.3v per cell and room temperature e.g., with 3.3v on each cell input scan the voltage values using the isl94212 and record the average reading error (isl94212 reading ? cell voltage value). table 53 shows the value of r 1 and r 2 required for various measured errors. to use table 53 , find the measured error value closest to the result obtained with measurements using the isl94212 and select the corresponding resistor value. alternatively, if finer adjustment resolution is required then this may be obtained by interpolation using table 53 . worked examples the following worked examples are provided to assist with the setup and calculations associated with various functions. voltage reference check calculation table 52. component functions and diagnostic results for circuit of figure 61 component function diagnostic result r 1 protection from wiring shorts to external hv connections. open: open wire detection short: no diagnostic result r 2 measurement high-side resistor open: low input level (over-temperature indication) short: high input level (open wire indication). thermistor open: high input level (open wire indication). short: low input level (over-temperature indication) c 1 noise filter. connects to measurement ground vss. open: no diagnostic result. short: low input level (over-temperature indication) figure 62. cell reading accuracy adjustment system table 53. component values for accuracy calibration adjustment of figure 62 measured error at vc = 3.3v (mv) v 78600 - v cell (mv) r 1 (k ? ) r 2 (k ? ) 4 205 dnp 3274dnp 2412dnp 1 825 dnp 0dnpdnp -1 dnp 2550 -2 dnp 1270 -3 dnp 866 -4 dnp 649 dnp = do not populate table 54. example register data r/w page address parameter value (hex) decimal 0 001 010000 ic temperature 14?h2425 9253 0 001 010101 reference voltage 14?h20a7 8359 0 010 111000 coefficient c 14?h00a4 164 0 010 111001 coefficient b 14?h3fcd -51 0 010 111010 coefficient a 9?h006 6
isl94212 87 fn7938.1 april 23, 2015 submit document feedback coefficients a, b and c are two?s compliment numbers. b and c have a range +8191 to -8192. a has a range +255 to -256. coefficient b above is a negati ve number (hex value > 1fff). the value for b is 14?h3fcd - 14h3fff- 1 or (16333 10 -16383 10 -1)= -51. coefficient a occupies the upper 9 bits of register 6?b111010 (6'h3a). one way to extract the coef ficient data from this register is to divide the complete register value by 32 and rounding the result down to the nearest inte ger. with 9'h006 in the upper 9 bits, and assuming the lower 5 bits are 0, the complete register value will be 14'h0c0 = 192 decimal. divide this by 32 to obtain 6. coefficients a, b and c are used with the ic temperature reading to calibrate the reference voltage reading. the calibration is applied by subtracting an ad justment of the form (see equation 5 ) from the reference voltage reading. an example calculation using the data from table 54 is given in equation 6 . where 9180 is the internal temperature monitor reading at +25c (see the ?electrical specifications? table, t int25 on page 10 ). cell balancing ? manual mode refer to ? manual balance mode ? on page 26 . example: activate balancing on cells 1, 5, 7 and 11 step 1. write balance setup register: set manual balance mode , balance status pointer, and turn off balance. bmd = 01 ( manual balance mode ) bwt = xxx bsp = 0000 (balance status pointer location 0) ben = 0 (balancing disabled) note: green text indicates a register change . step 2. write balance status register: set bits 0, 4, 6 and 10 bal12:1 = 0100 0101 0001 step 3. enable balancing using balance enable command or enable balancing by setting ben directly in the balance setup register: ben = 1 the balance fets attached to cells 1, 5, 7 and 11 turn on. turn balancing off by resetting ben or by sending the balance inhibit command (page 3, address 6?h11). cell balancing ? timed mode refer to ? timed balance mode ? on page 27 . example: activate balancing on cells 2 and 8 for 1 minute. step 1. write balance setup register: set timed balance mode , balance status pointer, and turn off balance. bmd = 10 ( timed balance mode ) bwt = xxx bsp = 0000 (balance status pointer location 0) ben = 0 (balancing disabled) step 2. write balance status register: set bits 1 and 7 bal12:1 = 0000 1000 0010 balance setup register r /w page address data 1 010 010011 xx xx00 000x xx01 x = don?t care (eq. 5) adjustment a 256 8192 ? ----------------------------- dt 2 b 8192 ------------ - + ? dt c + ? = dt 9253 9180 C 2 -------------------------------- 36.5 == adjustment 6 256 8192 ? ----------------------------- 36.5 ?? 2 51 8192 ------------ - 36.5 164 163.8 = + ? C ? = corrected v ref 8359 163.8 8195.2 = C = v ref value 8195.2 16384 ----------------- - 5 2.5010 = ? =
isl94212 88 fn7938.1 april 23, 2015 submit document feedback step 3. write balance timeout settin g to the watchdog/balance time register (page 2, ad dress 6?h15, bits [13:7]) btm6:1 = 0000011 (1 minute) step 4. enable balancing using balance enable command or enable balancing by setting ben directly in the balance setup register: ben = 1 the balance fets attached to cells 2 and 8 turn on. the fets turn off after 1 minute. balancing may be stopped by resetting ben or by sending the balance inhibit command. cell balancing ? auto mode refer to ? auto balance mode ? on page 27 . balance value calculation example this example is based on a cell state of charge (soc) of 9360 coulombs, a target soc of 8890 coulombs, a balancing leg impedance of 31 (30 resistor plus 1 fet on resistance) and a sampling time interval of 5 minutes (300 seconds). the balance value is calculated using equation 10 . the value 8191/5 is the scaling factor of the cell voltage measurement. the value of 28?h00136ca is loaded to the required cell balance register and the value 7?b0001111 (5 minutes) is loaded to the balance time bits in the watchdog/balance time register. in this example, the total coulomb difference to be balanced is: 470 coulomb (9360 - 8890). at 3.3v/31 *300s = 31.9 coulomb per cycle, it takes about 15 cycles for the balancing to terminate. auto balance mode cell balancing example the following describes a simp le setup to demonstrate the auto balance mode cell balancing function of the isl94212. note that this balancing setup is not related to the balance value calculation in equation 10 . auto balance cells using the following criteria: ? balance time = 20s ? balance wait time (dead time between balancing cycles) = 8s ? balancing disabled during cell measurements. ? balance values: see table 55 ? balance status register: set up balance: cells 1, 4, 7 and 10 on 1 st cycle. cells 3, 6, 9 and 12 on 2 nd cycle. cells 2, 5, 8 and 11 on 3 rd cycle (see table 56 ) watchdog/balance time register r /w page address data 1 010 010101 00 0001 1xxx xxxx x = don?t care ? the lower bits are the watchdog timeout value and should be set to a time longer than the balance time. a value of 111 1111 is suggested. balance enable command r /w page address data 0 011 010000 00 0000 balance setup register r /w page address data 1 010 010011 xx xx1x xxxx xxxx b 8191 5 ------------ - 9360 8890 C ?? 31 300 --------- - ? ? 79562 = 28 ? h00136ca = = (eq. 10) table 55. cell balance values (hex) for each cell cell 1 cell 2 cell 3 cell 4 cell 5 cell 6 cell 7 cell 8 cell 9 cell 10 cell 11 cell 12 28?h 406a 28?h 3e4d 28?h 0 28?h 292f 28?h 3e00 28?h 0 28?h 2903 28?h 3d06 28?h 0 28?h 151e 28?h 502 28?h 6d6 table 56. balance status setup bps [3:0] cell 123456 78 9 10 11 12 0000 reserved for manual balance mode and timed balance mode 0001100100100100 0010001001001001 0011010010010010
isl94212 89 fn7938.1 april 23, 2015 submit document feedback step 1. write balance value registers step 2. write bdds bit in device setup register (turn balancing functions off during measurement) bdds = 1 step 3. write balance timeout settin g to the watchdog/balance time register: balance timeout code = 0000001 (20 seconds) btm6:0 = 000 0001 step 4. set up balance status register (from table 56 on page 88 ) step 4a . write balance setup register: set auto balance mode , set 8 second balance wait time, and set balance off: bmd = 11 ( auto balance mode ) bwt = 100 (8 seconds) ben = 0 (balancing disabled) step 4b . write balance setup register: set balance status pointer = 1 bsp = 0001 (balance status pointer = 1) step 4c. write balance status register: set bits 1, 4, 7 and 10 bal12:1 = 0010 0100 1001 step 4d . write balance setup register: set balance status pointer = 2 bsp = 0010 (balance status pointer = 2 ) balance value registers r/w page address data (hex) cell 1 010 100000 14?h006a 1 1 010 100001 14?h0001 1 010 100010 14?h3e4d 2 1 010 100011 14?h0000 1 010 100100 14?h0000 3 1 010 100101 14?h0000 1 010 100110 14?h292f 4 1 010 100111 14?h0000 1 010 101000 14?h3e00 5 1 010 101001 14?h0000 1 010 101010 14?h0000 6 1 010 101011 14?h0000 1 010 101100 14?h2903 7 1 010 101101 14?h0000 1 010 101110 14?h3d06 8 1 010 101111 14?h0000 1 010 110000 14?h0000 9 1 010 110001 14?h0000 1 010 110010 14?h151e 10 1 010 110011 14?h0000 1 010 110100 14?h0502 11 1 010 110101 14?h0000 1 010 110110 14?h06d6 12 1 010 110111 14?h0000 balance value registers (cell1) - value 28?h406a 6?20 b0107 b0106 b0105 b0104 b0103 b0102 b0101 b0100 01101010 b0113 b0112 b1011 b0110 b0109 b0108 000000 6?21 b0121 b0120 b0119 b0118 b0117 b0116 b0115 b0114 00000001 b0127 b0126 b0125 b0124 b0123 b0122 000000 device setup register r /w page address data 1 010 011001 xx xxxx 1xxx xxxx x = don?t care balance timeout register r /w page address data 1 010 010101 00 0000 1xxx xxxx x = don?t care ? the lower bits are the watchdog timeout value and should be set to a time longer than the balance time. a value 111 1111 is suggested. balance setup register r /w page address data 1 010 010011 xx xx0x xxx1 0011 x = don?t care balance setup register r /w page address data 1 010 010011 xx xxx0 001x xxxx x = don?t care balance status register r /w page address data 1 010 010100 xx 0010 0100 1001 balance setup register r /w page address data 1 010 010011 xx xxx0 010x xxxx x = don?t care
isl94212 90 fn7938.1 april 23, 2015 submit document feedback step 4e. write balance status register: set bits 3, 6, 9 and 12 bal12:1 = 1001 0010 0100 step 4f . write balance setup register: set balance status pointer = 3 bsp = 0011 (balance status pointer = 3 ) step 4g. write balance status register: set bits 2, 5, 8 and 11 bal12:1 = 0100 1001 0010 step 4h . write balance setup register: set balance status pointer = 4 bsp = 0100 (balance status pointer = 4) step 4i. write balance status register: set bits to all zero to set the end point for the instances. bal12:1 = 0000 0000 0000 step 5. enable balancing using the balance enable command or enable balancing by setting ben directly in the balance setup register: ben = 1 the balance fets cycle through each instance of the balance status register in a loop, interposing the balance wait time between each instance. the measured voltage of each cell being balanced is subtracted from the ba lance value for that cell at the end of each balance status instance. the process continues until the balance value register for each cell contains zero. balance status register r /w page address data 1 010 010100 xx 1001 0010 0100 balance setup register r /w page address data 1 010 010011 xx xxx0 011x xxxx x = don?t care balance status register r /w page address data 1 010 010100 xx 0100 1001 0010 balance setup register r /w page address data 1 010 010011 xx xxx0 100x xxxx x = don?t care balance status register r /w page address data 1 010 010100 xx 0000 0000 0000 balance enable command r /w page address data 0 011 010000 00 0000 balance setup register r /w page address data 1 010 010011 xx xx1x xxxx xxxx register map r/w + page address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read write bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0001 000000 v bat voltage vb7 vb6 vb5 vb4 vb3 vb2 vb1 vb0 vb13 vb12 vb11 vb10 vb9 vb8 0001 000001 cell 1 voltage c1v7 c1v6 c1v5 c1v4 c1v3 c1v2 c1v1 c1v0 c1v13 c1v12 c1v11 c1v10 c1v9 c1v8 0001 000010 cell 2 voltage c2v7 c2v6 c2v5 c2v4 c2v3 c2v2 c2v1 c2v0 c2v13 c2v12 c2v11 c2v10 c2v9 c2v8 0001 000011 cell 3 voltage c3v7 c3v6 c3v5 c3v4 c3v3 c3v2 c3v1 c3v0 c3v13 c3v12 c3v11 c3v10 c3v9 c3v8 0001 000100 cell 4 voltage c4v7 c4v6 c4v5 c4v4 c4v3 c4v2 c4v1 c4v0 c4v13 c4v12 c4v11 c4v10 c4v9 c4v8 0001 000101 cell 5 voltage c5v7 c5v6 c5v5 c5v4 c5v3 c5v2 c5v1 c5v0 c5v13 c5v12 c5v11 c5v10 c5v9 c5v8
isl94212 91 fn7938.1 april 23, 2015 submit document feedback 0001 000110 cell 6 voltage c6v7 c6v6 c6v5 c6v4 c6v3 c6v2 c6v1 c6v0 c6v13 c6v12 c6v11 c6v10 c6v9 c6v8 0001 000111 cell 7 voltage c7v7 c7v6 c7v5 c7v4 c7v3 c7v2 c7v1 c7v0 c7v13 c7v12 c7v11 c7v10 c7v9 c7v8 0001 001000 cell 8 voltage c8v7 c8v6 c8v5 c8v4 c8v3 c8v2 c8v1 c8v0 c8v13 c8v12 c8v11 c8v10 c8v9 c8v8 0001 001001 cell 9 voltage c9v7 c9v6 c9v5 c9v4 c9v3 c9v2 c9v1 c9v0 c9v13 c9v12 c9v11 c9v10 c9v9 c9v8 0001 001010 cell 10 voltage c10v7 c10v6 c10v5 c10v4 c10v3 c10v2 c10v1 c10v0 c10v13 c10v12 c10v11 c10v10 c10v9 c10v8 0001 001011 cell 11 voltage c11v7 c11v6 c11v5 c11v4 c11v3 c11v2 c11v1 c11v0 c11v13 c11v12 c11v11 c11v10 c11v9 c11v8 0001 001100 cell 12 voltage c12v7 c12v6 c12v5 c12v4 c12v3 c12v2 c12v1 c12v0 c12v13 c12v12 c12v11 c12v10 c12v9 c12v8 0001 001111 all cell voltage data daisy chain configuration only. this command returns all page 1 data from address 6?h00 through 6?h0c in a single data stream. see ? communication sequences ? on page 36 and ?address all? on page 42. see example in figure 41d on page 40 . 0001 010000 ic temperature ict7 ict6 ict5 ict4 ict3 ict2 ict1 ict0 ict13 ict12 ict11 ict10 ict9 ict8 0001 010001 external temperature input 1 voltage (ext1 pin) et1v7 et1v6 et1v5 et1v4 et1v3 et1v2 et1v1 et1v0 et1v13 et1v12 et1v11 et1v10 et1v9 et1v8 0001 010010 external temperature input 2 voltage (ext2 pin) et2v7 et2v6 et2v5 et2v4 et2v3 et2v2 et2v1 et2v0 et2v13 et2v12 et2v11 et2v10 et2v9 et2v8 0001 010011 external temperature input 3 voltage (ext3 pin) et3v7 et3v6 et3v5 et3v4 et3v3 et3v2 et3v1 et3v0 et3v13 et3v12 et3v11 et3v10 et3v9 et3v8 0001 010100 external temperature input 4 voltage (ext4 pin) et4v7 et4v6 et4v5 et4v4 et4v3 et4v2 et4v1 et4v0 et4v13 et4v12 et4v11 et4v10 et4v9 et4v8 0001 010101 secondary reference voltage rv7 rv6 rv5 rv4 rv3 rv2 rv1 rv0 rv13 rv12 rv11 rv10 rv9 rv8 0001 010110 scan count scn3 scn2 scn1 scn0 0001 011111 all temperature data daisy chain configuration only. this command returns all page 1 data from address 6?h10 through 6?h16 in a single data stream. see ? communication sequences ? on page 36 and ? address all ? on page 42 . 0010 1010 000000 overvoltage fault of8 of7 of6 of5 of4 of3 of2 of1 of12 of11 of10 of9 0010 1010 000001 undervoltage fault uf8 uf7 uf6 uf5 uf4 uf3 uf2 uf1 uf12 uf11 uf10 uf9 register map (continued) r/w + page address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read write bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
isl94212 92 fn7938.1 april 23, 2015 submit document feedback 0010 1010 000010 open wire fault oc7 oc6 oc5 oc4 oc3 oc2 oc1 oc0 oc12 oc11 oc10 oc9 oc8 0010 1010 000011 fault setup tot2 tot1 tot0 wscn scn3 scn2 scn1 scn0 ttst4 ttst3 ttst2 ttst1 ttst0 0010 1010 000100 fault status ow uv ov ot wdgf osc 0 0 mux reg ref par ovss ov bat 0010 1010 000101 cell setup c8 c7 c6 c5 c4 c3 c2 c1 ffsn ffsp c12 c11 c10 c9 0010 1010 000110 over-temperature fault tflt4 tflt3 tflt2 tflt1 tflt0 0010 001111 all fault data daisy chain configuration only. th is command returns all page 2 data from address 6?h00 through 6?h06 in a single data stream. see ? communication sequences ? on page 36 and ? address all ? on page 42 . 0010 1010 010000 overvoltage limit ov7 ov6 ov5 ov4 ov3 ov2 ov1 ov0 ov13 ov12 ov11 ov10 ov9 ov8 0010 1010 010001 undervoltage limit uv7 uv6 uv5 uv4 uv3 uv2 uv1 uv0 uv13 uv12 uv11 uv10 uv9 uv8 0010 1010 010010 external temp limit etl7 etl6 etl5 etl4 etl3 etl2 etl1 etl0 etl13 etl12 etl11 etl10 etl9 etl8 0010 1010 010011 balance setup bsp2 bsp1 bsp0 bwt2 bwt1 bwt0 bmd1 bmd0 ben bsp3 0010 1010 010100 balance status (cells to balance) bal8 bal7 bal6 bal5 bal4 bal3 bal2 bal1 bal12 bal11 bal10 bal9 0010 1010 010101 watchdog/balance ti me btm0 wdg6 wdg5 wdg4 wdg3 wdg2 wdg1 wdg0 btm6 btm5 btm4 btm3 btm2 btm1 0010 1010 010110 user register ur7 ur6 ur5 ur4 ur3 ur2 ur1 ur0 ur13 ur12 ur11 ur10 ur9 ur8 0010 1010 010111 user register ur 21 ur20 ur19 ur18 ur17 ur16 ur15 ur14 ur27 ur26 ur25 ur24 ur23 ur22 0010 011000 comms setup size3 size2 s ize1 size0 addr3 addr2 addr1 addr0 crat1 crat0 csel2 csel1 0010 1010 011001 device setup bdds 0iscnscaneob 0pin 37pin 39 wp5 wp4 wp3 wp2 wp1 wp0 0010 011010 internal temp limit itl7 itl6 itl5 itl4 itl3 itl2 itl1 itl0 itl13 itl12 itl11 itl10 itl9 itl8 0010 011011 serial number 0 sn7 sn6 sn5 sn4 sn3 sn2 sn1 sn0 sn13 sn12 sn11 sn10 sn9 sn8 0010 011100 serial number 1 sn21 sn20 sn19 sn18 sn17 sn16 sn15 sn14 sn27 sn26 sn25 sn24 sn23 sn22 register map (continued) r/w + page address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read write bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
isl94212 93 fn7938.1 april 23, 2015 submit document feedback 0010 011101 trim voltage reserved tv5 tv4 tv3 tv2 tv1 tv0 0010 011111 all setup data daisy chain configuration only. th is command returns all page 2 data from address 6?h10 through 6?h1d in a single data stream. see ? communication sequences ? on page 36 and ? address all ? on page 42 . 0010 1010 100000 cell 1 balance value 0 b0107 b0106 b0105 b0104 b0103 b0102 b0101 b0100 b0113 b0112 b1011 b0110 b0109 b0108 0010 1010 100001 cell 1 balance value 1 b0121 b0120 b0119 b0118 b0117 b0116 b0115 b0114 b0127 b0126 b0125 b0124 b0123 b0122 0010 1010 100010 cell 2 balance value 0 b0207 b0206 b0205 b0204 b0203 b0202 b0201 b0200 b0213 b0212 b1011 b0210 b0209 b0208 0010 1010 100011 cell 2 balance value 1 b0221 b0220 b0219 b0218 b0217 b0216 b0215 b0214 b0227 b0226 b0225 b0224 b0223 b0222 ~~ ~ 0010 1010 110111 cell 12 balance value 1 b1221 b1220 b1219 b1218 b1217 b1216 b1215 b1214 b1227 b1226 b1225 b1224 b1223 b1222 0010 111000 reference coefficient c rcc7 rcc6 rcc5 rcc4 rcc3 rcc2 rcc1 rcc0 rcc13 rcc12 rcc11 rcc10 rcc9 rcc8 0010 111001 reference coefficient b rcb7 rcb6 rcb5 rcb4 rcb3 rcb2 rcb1 rcb0 rcb13 rcb12 rcb11 rcb10 rcb9 rcb8 0010 111010 reference coefficient a rca2 rca1 rca0 reserved rca8 rca7 rca6 rca5 rca4 rca3 0010 111011 cell balance enabled cben8 cb en7 cben6 cben5 cben4 cben3 bal2 cben1 cben12 cben11 cben10 cben9 0011 000001 scan voltages 0011 000010 scan temperatures 0011 000011 scan mixed 0011 000100 scan wires 0011 000101 scan all 0011 000110 scan continuous 0011 000111 scan inhibit 0011 001000 measure 0011 001001 identify 0011 001010 sleep 0011 001011 nak 0011 001100 ack 0011 001110 comms failure 0011 001111 wakeup 0011 010000 balance enable register map (continued) r/w + page address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read write bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
isl94212 94 fn7938.1 april 23, 2015 submit document feedback 0011 010001 balance inhibit 0011 010010 reset 0011 010011 calc register checksum 0011 010100 check register checksum 0100 111111 eeprom misr data register 14-bit misr eepr om checksum value. programmed during test. 0101 000000 misr calculated checksum 14-bit shad ow register misr checksum value. calculated when shadow registers are loaded from nonvolatile memory register map (continued) r/w + page address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read write bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
isl94212 95 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7938.1 april 23, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change april 23, 2015 fn7938.1 changed ground references in figure 1 on page 1. abs max ?absolute maximum ratings? on page 7 changed the text in the esd ratings from capacitive discharge to charge device model ?recommended operating conditions? on page 7 moved ext1, ext2, ext3, ext4, which had voltage range 0v to 3.6v to separate line with voltage range 0v to 2.5v. added to ?base? in ?pin descriptions? on page 5, ?do not let this pin float.? table 3 on page 24, changed ?cell 0 voltage? to ?vbat voltage?. section , ?crc calculation,? on page 36: added example software crc calculation code (figure 39 on page 37.) section , ?reset,? on page 42 - added note: ?a reset command should be issued following a ?hard reset? in which the en pin is toggled.? changed ?fault signal filtering? on page 46 to add the co mment in 2nd paragraph, ?when a fault is detected, the [tot2:0] bits should be rewritten.? table 30 on page 47, changed in comments for ?read checksum value calculated by isl94212? from: ...?cycling the en pin or the host issuing a reset command.? to: ...?cycling the en pin followed by a host initiated reset command, or simply the host issuing a reset command.? changed section, ?system registers,? on page 62. changed in 4th paragraph 1st sentence ?when the en pin is low? to ?when the en pin is toggled and the device receives a reset command?. section, ?register descriptions,? on page 62: changed ?cell 0 voltage? to ?vbat voltage? and added voltage calculation equations. system register description ?tot0, 1, 2? on page 64 added the comment, ?this register must be re-written following an error detection resulting from totalizer overflow.? added to last sentence 2nd paragraph in section, ?power supplies,? on page 82, ?the external pass transistor is required. do not allow this pin to float.? changed all pin name references to all caps. updated definitions for shutdown mode in ?power modes? on page 21 and ?reset? on page 42. table 50 on page 84, updated recommendation for c1 replaced ?measurement and communication timing? sectio n (pages 51 to 58 of previous document) with new sections ?communication and measur ement diagrams? on page 50 and ?commu nication and measurement timing tables? on page 56 with new figures and tables to offe r more clarity and flexibility in communication and measurement timing calculations. december 14, 2012 fn7938.0 initial release.
isl94212 96 fn7938.1 april 23, 2015 submit document feedback package outline drawing q64.10x10d 64 lead thin plastic quad flatpack package rev 2, 9/12 bottom view detail "a" side view top view notes: ms-026, variation acd. 8. controlling dimension: millimeter. this outline conforms to jedec publication 95 registration condition. dambar cannot be located on the lower radius protrusion shall be 0.08mm total at maximum material does not include dambar pr otrusion. allowable dambar 6. package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package. 1. all dimensioning and tolerancing conform to ansi y14.5-1982 . 2. datum plane h located at mold parting line and coincident with lead, where lead exits plastic body at bottom of par ting line. 3. datums a-b and d to be determined at centerline between leads where leads exit plastic body at datum plane h. 4. dimensions do not include m old protrusion. allowable mold protrusion is 0.254mm. 9. 7. 5. these dimensions to be determined at datum plane h. 10. dimensions in ( ) are for reference only. or the foot. 0.20 min. (1.00) 0.09/0.20 0.20 0.03 base metal 0.09/0.16 7 0.22 0.05 0.05 11/13 with lead finish 0.08 c ma-b d 0.05/0.15 r. min. 0.08 see detail "a" c 0.08 1.20 max / / 0.10 c 1.00 0.05 h gauge 0.60 0.15 0-7 0.25 0 min. 4x 0.50 c a-b d 0.20 3 a 0.20 4x 3 a-b hd 5 b 4 d 3 12.00 10.00 4 5 12.00 10.00 2 scale: none plane

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