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d a t a sh eet preliminary speci?cation 2003 apr 10 integrated circuits UDA1355H stereo audio codec with spdif interface
2003 apr 10 2 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H contents 1 features 1.1 general 1.2 control 1.3 iec 60958 input 1.4 iec 60958 output 1.5 digital i/o interface 1.6 adc digital sound processing 1.7 dac digital sound processing 2 general description 3 ordering information 4 quick reference data 5 block diagram 6 pinning 7 functional description 7.1 ic control 7.2 microcontroller interface 7.3 clock systems 7.4 iec 60958 decoder 7.5 iec 60958 encoder 7.6 analog input 7.7 analog output 7.8 digital audio input and output 7.9 power-on reset 8 application modes 8.1 static mode pin assignment 8.2 static mode basic applications 8.3 microcontroller mode pin assignment 8.4 microcontroller mode applications 9 spdif signal format 9.1 spdif channel encoding 9.2 spdif hierarchical layers 9.3 timing characteristics 10 l3-bus description 10.1 device addressing 10.2 register addressing 10.3 data write mode 10.4 data read mode 11 i 2 c-bus description 11.1 characteristics 11.2 bit transfer 11.3 byte transfer 11.4 data transfer 11.5 register address 11.6 device address 11.7 start and stop conditions 11.8 acknowledgment 11.9 write cycle 11.10 read cycle 12 register mapping 12.1 address mapping 12.2 read/write registers mapping 12.3 read registers mapping 13 limiting values 14 thermal characteristics 15 characteristics 16 timing characteristics 17 package outline 18 soldering 18.1 introduction to soldering surface mount packages 18.2 reflow soldering 18.3 wave soldering 18.4 manual soldering 18.5 suitability of surface mount ic packages for wave and reflow soldering methods 19 data sheet status 20 definitions 21 disclaimers 22 purchase of philips i 2 c components
2003 apr 10 3 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 1 features 1.1 general 2.7 to 3.6 v power supply integrated digital interpolator filter and digital-to-analog converter (dac) 24-bit data path in interpolator no analog post filtering required for dac integrated analog-to-digital converter (adc), programmable gain amplifier (pga) and digital decimator filter 24-bit data path in decimator master or slave mode for digital audio data i/o interface i 2 s-bus, msb-justified, lsb-justified 16, 18, 20, and 24 bits formats supported on digital i/o interface. 1.2 control controlled by means of static pins or microcontroller (l3-bus or i 2 c-bus) interface. 1.3 iec 60958 input on-chip amplifier for converting iec 60958 input to cmos levels supports level i, ii and iii timing selectable iec 60958 input channel, one of four supports input frequencies from 28 to 96 khz lock indication signal available on pin lock 40 status bits can be read for left and right channel via l3-bus or i 2 c-bus channel status bits available via l3-bus or i 2 c-bus: lock, pre-emphasis, audio sample frequency, two channel pulse code modulation (pcm) indication and clock accuracy pre-emphasis information of incoming iec 60958 bitstream available in register detection of digital data preamble, such as ac3, available on pin in microcontroller mode. 1.4 iec 60958 output cmos output level converted to iec 60958 output signal full-swing digital signal, with level ii timing using crystal oscillator clock 32, 44.1 and 48 khz output frequencies supported in static mode 32, 44.1 and 48 khz output frequencies (including double and half of these frequencies) supported in microcontroller mode via microcontroller, 40 status bits can be set for left and right channel. 1.5 digital i/o interface supports sampling frequencies from 16 to 100 khz supported static mode: Ci 2 s-bus format C lsb-justified 16 and 24 bits format C msb-justified format. supported microcontroller mode: Ci 2 s-bus format C lsb-justified 16, 18, 20 or 24 bits format C msb-justified format. bck and ws signals can be slave or master, depending on application mode. 1.6 adc digital sound processing supports sampling frequencies from 16 to 100 khz analog front-end includes a 0 to +24 db pga in steps of 3 db, selectable via microcontroller interface digital independent left and right volume control of +24 to - 63.5 db in steps of 0.5 db via microcontroller interface bitstream adc operating at 64f s comb filter decreases sample rate from 64f s to 8f s decimator filter (8f s to f s ) made of a cascade of three fir half-band filters. 1.7 dac digital sound processing digital de-emphasis for 32, 44.1, 48 and 96 khz audio sampling frequencies automatic de-emphasis when using iec 60958 to dac soft mute made of a cosine roll-off circuit selectable via pin mute or l3-bus interface
2003 apr 10 4 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H programmable digital silence detector interpolating filter (f s to 64f s or f s to 128f s ) comprising a recursive and a fir filter in cascade selectable fifth-order noise shaper operating at 64f s or third-order noise shaper operating at 128f s (specially for low sampling frequencies, e.g. 16 khz) generating bitstream for dac filter stream dac (fsdac) in microcontroller mode: C left and right volume control (for balance control) 0to - 78 db and - C left and right bass boost and treble control C optional resonant bass boost control C mixing possibility of two data streams. 2 general description the UDA1355H is a single-chip iec 60958 decoder and encoder with integrated stereo digital-to-analog converters and analog-to-digital converters employing bitstream conversion techniques. the UDA1355H has a selectable one-of-four spdif input (accepting level i, ii and iii timing) and one spdif output which can generate level ii output signals with cmos levels. in microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the ic, offering a flexible analog, digital and spdif converter chip with possibilities for off-chip sound processing via the digital input and output interface. a lock indicator is available on pin lock when the iec 60958 decoder and the clock regeneration mechanism is in lock. by default the dac output and the digital data interface output are muted when the decoder is not in lock. the UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock-on to an incoming spdif or digital audio signal, and in the mean time generating a stable signal by means of the crystal oscillator for driving, for example, the adc or spdif output signal. using the crystal oscillator (which requires a 12.288 mhz crystal) and the on-chip low jitter pll, all standard audio sampling frequencies (f s = 32, 44.1 and 48 khz including half and double these frequencies) can be generated. 3 ordering information type number package name description version UDA1355H qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2
2003 apr 10 5 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 4 quick reference data symbol parameter conditions min. typ. max. unit supplies v dda1 dac supply voltage 2.7 3.0 3.6 v v dda2 adc supply voltage 2.7 3.0 3.6 v v ddx crystal oscillator and pll supply voltage 2.7 3.0 3.6 v v ddi digital core supply voltage 2.7 3.0 3.6 v v dde digital pad supply voltage 2.7 3.0 3.6 v i dda1 dac supply current f s = 48 khz; power-on - 4.7 - ma f s = 96 khz; power-on - 4.7 - ma f s = 48 khz; power-down - 1.7 -m a f s = 96 khz; power-down - 1.7 -m a i dda2 adc supply current f s = 48 khz; power-on - 10.2 - ma f s = 96 khz; power-on - 10.4 - ma f s = 48 khz; power-down - 0.2 -m a f s = 96 khz; power-down - 0.2 -m a i ddx crystal oscillator and pll supply current f s = 48 khz; power-on - 0.9 - ma f s = 96 khz; power-on - 1.2 - ma i ddi digital core supply current f s = 48 khz; all on - 18.2 - ma f s = 96 khz; all on - 34.7 - ma i dde digital pad supply current f s = 48 khz; all on - 0.5 - ma f s = 96 khz; all on - 0.7 - ma t amb ambient temperature - 40 - +85 c digital-to-analog converter; f i = 1 khz; v dda1 = 3.0 v v o(rms) output voltage (rms value) - 900 - mv d v o output voltage unbalance - 0.1 - db (thd+n)/s total harmonic distortion-plus-noise to signal ratio iec 60958 input; f s =48khz at 0 db -- 88 - db at - 20 db -- 75 - db at - 60 db; a-weighted -- 37 - db iec 60958 input; f s =96khz at 0 db -- 83 - db at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio iec 60958 input; code = 0; a-weighted f s = 48 khz - 98 - db f s = 96 khz - 96 - db a cs channel separation - 100 - db
2003 apr 10 6 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H analog-to-digital converter; f i = 1 khz; v dda2 = 3.0 v v i (rms) input voltage (rms value) v o = - 1.16 dbfs digital output - 1.0 - v d v i input voltage unbalance - 0.1 - db (thd+n)/s total harmonic distortion-plus-noise to signal ratio f s = 48 khz at 0 db -- 85 - db at - 60 db; a-weighted -- 35 - db f s = 96 khz at 0 db -- 85 - db at - 60 db; a-weighted -- 35 - db s/n signal-to-noise ratio code = 0; a-weighted f s = 48 khz - 97 - db f s = 96 khz - 95 - db a cs channel separation - 100 - db external crystal f xtal crystal frequency - 12.288 - mhz c l(xtal) crystal load capacitor - 10 - pf device reset t rst reset time - 250 -m s power consumption p tot total power consumption iec 60958 input; f s =48khz dac in playback mode - 74 - mw dac in power-down mode - 63 - mw symbol parameter conditions min. typ. max. unit
2003 apr 10 7 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 5 block diagram ha ndbook, full pagewidth mgu826 comb filter deci- mator audio feature processor noise shaper inter- polator audio feature processor input and output select adc xtal clock and timing data in control interface iec 60958 decoder adc dac dac data out iec 60958 encoder slicer 13 40 42 44 9 8 10 5 29 30 31 20 17 18 19 7 14 34 36 16 43 2 3 1 23 24 25 26 21 22 4 33 35 28 12 v ddx xtalin xtalout vinl vinr reset rtcb wsi datai bcki spdif0 spdif1 spdif2 spdif3 slicer_sel0 slicer_sel1 lock voutl voutr mute wso datao bcko spdifout v ssx v adcp v dda2 clk_out v ssa1 v sse v adcn v ssa2 v ssis mp0 mp1 mp2 sel_static mode2 mode1 mode0 v ddi v ref v dde v dda1 15 32 37 27 38 6 39 11 41 UDA1355H fig.1 block diagram.
2003 apr 10 8 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 6 pinning symbol pin pad (1) description bcki 1 bpt4mtht5v bit clock input (master or slave) wsi 2 bpt4mtht5v word select input (master or slave) datai 3 iptht5v digital data input lock 4 op4mc pll lock indicator output spdifout 5 op4mc spdif output v dde 6 vdde digital pad supply voltage v sse 7 vsse digital pad ground datao 8 ops5c digital data output wso 9 bpt4mtht5v word select output (master or slave) bcko 10 bpt4mtht5v bit clock output (master or slave) clk_out 11 op4mc clock output; 256f s or 384f s v ddx 12 vddco crystal oscillator and pll supply voltage xtalin 13 apio crystal oscillator input xtalout 14 apio crystal oscillator output v ssx 15 vssco crystal oscillator and pll ground reset 16 ipthdt5v reset input mode0 17 apio mode selection input 0 for static mode or microcontroller mode (grounded for i 2 c-bus) mode1 18 bpts5tht5v mode selection input 1 for static mode or ao address input and output for microcontroller mode mode2 19 bpts5tht5v mode selection input 2 for static mode or u_rdy output for microcontroller mode sel_static 20 apio selection input for static mode, i 2 c-bus mode or l3-bus mode slicer_sel0 21 bpts5tht5v spdif slicer selection input 0 for static mode and user bit output for microcontroller mode slicer_sel1 22 bpts5tht5v spdif slicer selection input 1 for static mode and ac3 preamble detect output for microcontroller mode spdif0 23 apio spdif input 0 spdif1 24 apio spdif input 1 spdif2 25 apio spdif input 2 spdif3 26 apio spdif input 3 v ddi 27 vddi digital core supply voltage v ssis 28 vssis digital core ground mp0 29 apio multi-purpose pin 0: frequency select for static mode, not used for microcontroller mode mp1 30 iptht5v multi-purpose pin 1: sfor1 for static mode, scl for i 2 c-bus mode and l3clock for l3-bus mode mp2 31 iic400kt5v multi-purpose pin 2: sfor0 for static mode, sda for i 2 c-bus mode and l3data for l3-bus mode v adcp 32 vddco positive adc reference voltage v adcn 33 vssco negative adc reference voltage
2003 apr 10 9 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H note 1. see table 1. table 1 pad description vinl 34 apio adc left channel input v ssa2 35 vssco adc ground vinr 36 apio adc right channel input v dda2 37 vddco adc supply voltage v ref 38 apio reference voltage for adc and dac v dda1 39 vddco dac supply voltage voutl 40 apio dac left channel output v ssa1 41 vssco dac ground voutr 42 apio dac right channel output rtcb 43 ipthdt5v test control input mute 44 iipthdt5v dac mute input pad description iptht5v input pad; push-pull; ttl with hysteresis; 5 v tolerant ipthdt5v input pad; push-pull; ttl with hysteresis; pull-down; 5 v tolerant op4mc output pad; push-pull; 4 ma output drive; cmos ops5c output pad; push-pull; 5 ns slew rate control; cmos bpt4mtht5v bidirectional pad; push-pull input; 3-state output; 4 ma output drive; ttl with hysteresis; 5 v tolerant bpts5tht5v bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; ttl with hysteresis; 5 v tolerant iic400kt5v i 2 c-bus pad; 400 khz i 2 c-bus specification with open drain; 5 v tolerant apio analog pad; analog input or output vddco analog supply pad vssco analog ground pad vdde digital supply pad vsse digital ground pad vddi digital core supply pad vssis digital core ground pad symbol pin pad (1) description
2003 apr 10 10 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H handbook, full pagewidth 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 UDA1355H mgu828 v adcn v adcp mp2 mp1 v ssis v ddi spdif3 spdif2 spdif1 spdif0 bcki wsi datai lock spdifout v dde datao wso clk_out mp0 rtcb voutr v ssa1 voutl v dda1 v ref vinr v ssa2 vinl mute v dda2 xtalin xtalout v ssx reset mode0 mode1 sel_static slicer_sel0 slicer_sel1 v ddx mode2 v sse bcko fig.2 pin configuration. 7 functional description 7.1 ic control the UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the i 2 c-bus with a clock up to 400 khz or the l3-bus with a clock up to 2 mhz. it is recommended to use the microcontroller interface since this gives full access to all the ic features. the two microcontroller interfaces only differ in interface format. the register addresses and features that can be controlled are identical for l3-bus mode and i 2 c-bus mode. the UDA1355H can operate in three control modes: static mode with limited features l3-bus mode with full featuring i 2 c-bus mode with full featuring. the modes are selected via the 3-level pin sel_static according to table 2. table 2 control mode selection via pin sel_static 7.2 microcontroller interface the UDA1355H has a microcontroller interface and all the sound processing features and system settings can be controlled by the microcontroller. the controllable settings are: restoring l3-bus defaults power-on settings for all blocks digital interface input and output formats volume settings for the decimator pga gain settings level mode high static mode mid i 2 c-bus mode low l3-bus mode
2003 apr 10 11 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H set two times 40 bits of channel status bits of the spdif output select one of four spdif input sources enable digital mixer inside interpolator control mute and mixer volumes of digital mixer selection of filter mode and settings of treble and bass boost for the interpolator (dac) section volume settings of interpolator selection of soft mute via cosine roll-off (only effective in l3-bus control mode) and bypass of auto mute selection of de-emphasis enable and control of digital mixer inside interpolator. the readable settings are: mute status of interpolator pll lock and adaptive lock two times 40 bits of channels status bits of the spdif input signal. 7.3 clock systems the UDA1355H has two clock systems. the first system uses an external crystal of 12.288 mhz to generate the audio related system clocks. only a crystal with a frequency of 12.288 mhz is allowed. the second system is a pll which locks on the spdif or incoming digital audio signal (e.g. i 2 s-bus) and recovers the system clock. 7.3.1 c rystal oscillator clock system the crystal oscillator and the on-chip pll and divider circuit can be used to generate internal and external clock signals related to standard audio sampling frequencies (such as 32, 44.1 and 48 khz including half and double of these frequencies). the audio frequencies supported in either microcontroller mode or static mode are given in table 3. table 3 output frequencies remarks : if an application mode is selected which does not need a crystal oscillator, the crystal oscillator cannot be omitted. the reason is that the interpolator switches to the crystal clock when an spdif input signal is removed. this switch prevents the noise shaper noise from moving inside the audio band as the pll gradually decreases in frequency. if no accurate output frequency is needed, the crystal can be replaced with a resonator. instead of the crystal, a 12.288 mhz system clock can be applied to pin xtalin. the block diagram of the crystal oscillator and the pll circuit is given in fig.3. basic audio frequency output frequency micro- controller mode static mode 32 khz 256 16 khz 384 16 khz 256 32 khz 256 32 khz 384 32 khz 256 64 khz 384 64 khz 44.1 khz 256 22.05 khz 384 22.05 khz 256 44.1 khz 256 44.1 khz 384 44.1 khz 256 88.2 khz 384 88.2 khz 48 khz 256 24 khz 384 24 khz 256 48 khz 256 48 khz 384 48 khz 256 96 khz 384 96 khz
2003 apr 10 12 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 7.3.2 pll clock system the pll locks on the incoming digital data of the spdif or ws input signal. the pll recovers the clock from the spdif or wsi signal and removes jitter to produce a stable system clock (see fig.4). 7.3.3 w ord selection detection circuit this circuit is clocked by the 12.288 mhz crystal oscillator clock and generates a word selection (ws) detection signal. if the ws detector does not detect any ws edge, defined as 7 times low and 7 times high, then the ws detection signal is low. this information can be used to set the clock for the noise shaper in the interpolator. this will prevent noise shaper noise in the audio band. 7.3.4 c lock output the UDA1355H has a clock output pin (pin clk_out), which can be used to drive other audio devices in the system. in microcontroller mode the output clock is 256f s or 384f s . in static mode the output clock is 256 times 32, 44.1 and 48 khz. the source of the output clock is either the crystal oscillator or the pll, depending on the selected application and control mode. 7.4 iec 60958 decoder the UDA1355H iec 60958 decoder can select one of four spdif input channels. an on-chip amplifier with hysteresis amplifies the spdif input signal to cmos level, making it possible to accept both analog and digital spdif signals (see fig.5). 7.4.1 a udio data from the incoming spdif bitstream 24 bits of data for the left and right channel are extracted. there is a hard mute (not a cosine roll-off mute) if the iec 60958 decoder is out of lock or detects bi-mark phase encoding violations. the lock indicator and the key channel status bits are accessible in l3-bus mode. the UDA1355H supports the following sample frequencies and data rates, including half and double of these frequencies: f s = 32 khz; resulting in a data rate of 2.048 mbit/s f s = 44.1 khz; resulting in a data rate of 2.8224 mbit/s f s = 48 khz; resulting in a data rate of 3.072 mbit/s. handbook, halfpage mgu830 13 xtalin xtalout clk_out 12.288 mhz 14 11 UDA1355H crystal oscillator pll module 256f s or 384f s clock l3-bus or i 2 c-bus register setting pll clock fig.3 crystal oscillator clock system. mgu827 slicer 23 24 25 26 2 spdif0 spdif1 spdif2 spdif3 wsi UDA1355H iec 60958 decoder pll select spdif source 256f s or 384f s fig.4 pll clock system. handbook, halfpage mgu829 23 24 25 26 spdif0 spdif1 spdif2 spdif3 75 w 180 pf 10 nf UDA1355H fig.5 iec 60958 input circuit.
2003 apr 10 13 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 7.4.2 c hannel status and user bits as well as the data bits there are several iec 60958 key channel status bits: pre-emphasis and audio sampling frequency bits two channel pcm indicator bits clock accuracy bits. in total 40 status bits per channel are recovered from the incoming iec 60958 bitstream. these are readable via the microcontroller interface. user bits, which can contain a large variety of data, such as cd text, are output to pin slicer_sel0 (see table 4). in microcontroller mode this signal contains the raw user bits extracted from the spdif bitstream. signal u_rdy gives a pulse on pin mode2 each time there is a new user bit available. both signals can be used by an external microcontroller to grab and decode the user bits. table 4 signal names in microcontroller mode 7.4.3 d igital data audio and digital data can be transmitted in the spdif bitstream. the pcm channel status bit should be set to logic 1 if the spdif bitstream is carrying digital data instead of audio data, but in practice it proves that not all equipment handles these channel status bits properly. in the UDA1355H, digital data is detected via bit pcm, or via the sync bytes as specified by iec. these sync bytes are two sync words, f872h and 4e1fh (two subframes) preceded by four or more subframes filled with zeros. signal ac3 is kept high for 4096 frames when the UDA1355H detects this burst preamble. signal ac3 is present on pin slicer_sel1 in microcontroller mode (see table 4). 7.5 iec 60958 encoder when using the crystal oscillator clock, the iec 60958 encoder output is a full-swing digital signal with level ii timing. when the recovered clock from the pll is used the iec 60958 encoder will function correctly but will not meet level ii timing requirements. 7.5.1 s tatic mode all user and channel status bits are set to logic 0. this is default value specified by iec. in static mode 0 and 2, the selected spdif input channel can be looped through to pin spdifout (see fig.6). 7.5.2 m icrocontroller mode two times 40 channel status bits can be set. default value for each status bit is logic 0. when setting the channel status bits, it is possible to set only the left channel status bits and have the bits copied to the right channel. the procedure of writing the channel status bits is as follows: 1. set bit spdo_valid = 0 to prevent immediately sending the status bits during writing. 2. set bit l_r_copy = 1 if the right channel needs the same status bits as the left channel or set bit l_r_copy = 0 if the right channel needs different status bits to the left channel. 3. write the left and right channel status bits. 4. set bit spdo_valid = 1 after writing all channel status bits to the register. starting from the next spdif block the iec 60958 encoder will use the new status bits. in microcontroller modes 2 and 13, the selected spdif input channel can be looped through to pin spdifout (see fig.6). pin name signal name slicer_sel0 user mode2 u_rdy slicer_sel1 ac3
2003 apr 10 14 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H handbook, full pagewidth mgu833 iec 60958 encoder iec 60958 decoder slicer slicer_sel [ 1:0 ] mode [ 2:0 ] sel_static select spdif source spdif out spdout_sel1 spdout_sel0 spdif source 23 24 25 26 spdif0 spdif1 spdif2 spdif3 21, 22 spdout_sel2 mode [ 3:0 ] 17 to 19 20 5 UDA1355H fig.6 selection options for spdif output. 7.6 analog input 7.6.1 adc the analog input is equipped with a programmable gain amplifier (pga) which can be controlled via the microcontroller interface. the control range is from 0 to 24 db gain in 3 db steps independent for the left and right channels. in applications in with a 2 v (rms) input signal, a 12 k w resistor must be used in series with the input of the adc. the 12 k w resistor forms a voltage divider together with the internal adc resistor and ensures that the voltage, applied to the input of the ic, never exceeds 1 v (rms). in the application for a 2 v (rms) input signal, the pga must be set to 0 db. when a 1 v (rms) input signal is applied to the adc in the same application, the pga gain must be set to 6 db. an overview of the maximum input voltages allowed with and without an external resistor and the pga gain setting is given in table 5. table 5 maximum input voltage; v dd =3v 7.6.2 d ecimation the decimation from 64f s is performed in two stages: comb filter and decimation filter. the first stage realizes a fourth-order characteristic with a decimation factor of eight. the second stage consists of three half-band filters each decimating by a factor of two. table 6 shows the characteristics. table 6 decimation ?lter characteristics note 1. the output is not 0 db when v i(rms) =1vatv dd =3v. this is because the analog components can spread over the process. when there is no external resistor, the - 1.16 db scaling prevents clipping caused by process mismatch. in the adc path there are left and right independent digital volume controls with a range from +24 to - 63.5 db and - db. this volume control is also used as a digital linear mute that can be used to prevent plops when powering-up or powering down the adc front path. external resistor (12 k w ) pga gain setting maximum input voltage present 0 db 2 v (rms) 6 db 1 v (rms) absent 0 db 1 v (rms) 6 db 0.5 v (rms) item conditions value (db) pass-band ripple 0 to 0.45f s 0.02 stop band >0.55f s - 60 dynamic range 0 to 0.45f s 140 overall gain from adc input to digital output dc; v i = 0 db; note 1 - 1.16 sin x x ----------- -
2003 apr 10 15 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 7.6.3 dc filtering in the decimator there are two digital dc blocking circuits. the first blocking circuit is in front of the volume control to remove dc bias from the adc output. the dc bias is added in the adc to prevent audio band idle tones occurring in the noise shaper. with the dc components removed, a signal gain of 24 db can be achieved. the second blocking circuit removes the dc components introduced by the decimator stage. 7.6.4 o verload detection bit overflow = 1 when the output data in the left or right channel is larger than - 1.16 db of the maximum possible digital swing. this condition is set for at least 512f s cycles (that is 11.6 ms at f s = 44.1 khz). this time-out is reset for each infringement. 7.7 analog output 7.7.1 a udio feature processor the audio feature processor provides automatic de-emphasis for the iec 60958 bitstream. in microcontroller mode all features are available and there is a default mute on start up. 7.7.2 i nterpolating filter the digital filter interpolates from 1f s to 64f s , or from 1f s to 128f s , by cascading a half-band filter and a fir filter. the stereo interpolator has the following basic features: 24-bit data path mixing of two channels: C to prevent clipping inside the core, there is an automatic signal level correction of - 6 db scaling before mixing and +6 db gain after digital volume control C position of mixing can be set before or after bass boost and treble C master volume control and mute with independent left and right channel settings for balance control C independently left and right channel de-emphasis, volume control and mute (no left or right) C output of the mixer is to the i 2 s-bus or iec 60958 decoder. full fir filter implementation for all the upsampling filters integrated digital silence detection for left and right channels with selectable silence detection time support for 1f s and 2f s input data rate and 192 khz audio via i 2 s-bus. the stereo interpolator has the following sound features: linear volume control using 14-bit coefficients with 0.25 db steps: range 0 to - 78 db and - db; hold for master volume and mixing volume control a cosine roll-off soft mute with 32 coefficients; each coefficient is used for four samples, in total 128 samples are needed to fully mute or de-mute (approximately 3 ms at f s = 44.1 khz) independent selectable de-emphasis for 32, 44.1, 48 and 96 khz for both channels treble is the selectable positive gain for high frequencies. the edge frequency of the treble is fixed and depends on the sampling frequency. treble can be set independently for left and right channel with two settings: Cf c = 1.5 khz; f s = 44.1 khz; 0 to 6 db gain range with 2 db steps Cf c = 3 khz; f s = 44.1 khz; 0 to 6 db gain range with 2 db steps. normal bass boost is the selectable positive gain for low frequencies. the edge frequency of the bass boost is fixed and depends on the sampling frequency. normal bass boost can be set independently for the left and right channel with two sets: Cf c = 250 hz; f s = 44.1 khz; 0 to 18 db gain range with 2 db steps Cf c = 300 hz; f s = 44.1 khz; 0 to 24 db gain range with 2 db steps. resonant bass boost optional function is selected if bit bass_sel = 1. when selected, the characteristics are determined by six 14-bit coefficients. resonant bass boost controls the left and right channel with the same characteristics. when resonant bass boost is selected, the treble control also changes to a single control for both channels following the gain setting of the left channel. a software program is available for users to generate the required six 14-bit coefficients by entering the desired centre frequency (f c ), positive or negative peak gain, sampling frequency (f s ) and shape factor (see figs 7 and 8).
2003 apr 10 16 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 7 interpolation ?lter characteristics 7.7.3 d igital mixer the UDA1355H has a digital mixer inside the interpolator. the digital mixer can be used as a cross over or a selector. a functional block diagram of the mixer mode is shown in fig.9. this mixer can be used in microcontroller mode only. the UDA1355H can be set to the mixer mode by setting bit mix = 1. in the mixer mode, there are three volume and mute controls available: for source 1, for source 2 and for the master (sum) signal. all three volume ranges can be controlled in 0.25 db steps. to prevent clipping inside the mixer, the signals are scaled with - 6 db before mixing, therefore the sum of the two signals is always equal to or lower than 0 db. after the mixing there is a 6 db gain in the master volume control. this means that at the analog output the signal can clip, but the clipping can be undone by decreasing the master volume control. the output of the mixer is available via the i 2 s-bus output or via the spdif output. the output signal of the mixer is scaled to a maximum of 0 db, so the digital output can never clip. item conditions value (db) pass-band ripple 0 to 0.45f s 0.035 stop band >0.55f s - 60 dynamic range 0 to 0.4535f s 140 handbook, halfpage mgu832 gain (db) - 6 - 10 - 2 6 2 10 - 8 - 4 4 0 8 11010 2 10 3 f (hz)) fig.7 resonant bass boost example 1. f c =70hz f s = 44.1 khz peak gain = 10 db shape factor = 1.4142 handbook, halfpage mgu831 gain (db) - 6 - 10 - 2 6 2 10 - 8 - 4 4 0 8 11010 2 10 3 f (hz)) fig.8 resonant bass boost example 2. f c =70hz f s = 44.1 khz peak gain = 10 db shape factor = 1.4142
2003 apr 10 17 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H handbook, full pagewidth mgu834 de-emphasis volume and mute master volume and mute bass-boost and treble int. filter de-emphasis volume and mute to interpolation filter and dac output output of mixer l3/i 2 c bit UDA1355H channel 1 channel 2 mixing before sound features mixing after sound features 1f s 2f s fig.9 digital mixer (dac) inside the interpolator dsp. 7.7.4 d igital silence detector the UDA1355H is equipped with a digital silence detector. this detects whether a certain amount of consecutive samples are 0. the number of samples can be set with bits sd_value[1:0] to 3200, 4800, 9600 or 19600 samples. the digital silence detection status can be read via the microcontroller interface. 7.7.5 n oise shaper (dac) the noise shaper shifts in-band quantization noise to frequencies above the audio band. the noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter (fsdac). this noise shaping technique enables high signal-to-noise ratios to be achieved. the UDA1355H is equipped with two noise shapers: a third-order noise shaper operating at 128fs. which is used at low sampling frequencies (8 to 16 khz) to prevent noise shaper noise shifting into the audio band for the fifth-order noise shaper a fifth-order noise shaper operating at 64f s . which is used at high sampling frequencies (from 32 khz upwards). when the noise shaper changes, the clock to the fsdac changes and the filter characteristic of the fsdac also changes. the effect on the roll of is compensated by selecting the filter matching speed and order of the noise shaper. 7.7.6 f ilter stream dac the fsdac is a semi digital reconstruction filter that converts the 1-bit data bitstream of the noise shaper to an analog output voltage. the filter coefficients are implemented as current sources and are summed at virtual ground of the operational amplifier output. in this way, very high signal-to-noise performance and low clock jitter sensitivity are achieved. a post filter is not needed due to the inherent filter function of the fsdac. on-chip amplifiers convert the fsdac output current to an output voltage signal capable of driving a line output. the output voltage of the fsdac scales proportionally with the supply voltage. 7.7.7 dac mute the dac and interpolator can be muted by setting pin mute to a high level. the output signal is muted to zero via a cosine roll-off curve and the dac is powered down. when pin mute is at low level the signal rise follows the same cosine curve. to prevent plops in case of changing inputs, clock to the dac or application modes, a special mute circuit for the dac is implemented (see table 8). in all application modes in which the dac is active the dac can be muted by pin mute. the microcontroller mute bits and pin mute act as an or function.
2003 apr 10 18 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 8 muting to prevent plopping occasion bit de-mute condition mt1 mt2 mtm input selection select channel 1 source x -- no mute after selection select channel 2 source - x - no mute after selection select chip mode pll is source for the dac -- x wait until pll is locked again crystal is source for the dac -- x no mute after selection select between microcontroller mode and static mode pll is source for the dac -- x wait until pll is locked again crystal is source for the dac -- x no mute after selection audio features select noise shaper order -- x no mute after selection select fsdac output polarity -- x no mute after selection select spdif input -- x pll is locked again select mixer --- no mute needed select mixer position --- no mute needed select crystal clock source -- x no mute after selection 7.8 digital audio input and output the selection of the digital audio input and output formats and master or slave modes differ for static and microcontroller mode. in master mode, when 256f s output clock is selected and the digital interface is master, the bck output clock will be 64f s . in case 384f s output clock is selected, the bck output clock will be 48f s . in the static mode the digital audio input formats are: i 2 s-bus lsb-justified; 16 bits lsb-justified; 24 bits msb-justified. the digital audio output formats are: i 2 s-bus msb-justified. in the microcontroller mode, the following formats are independently selectable: i 2 s-bus lsb-justified; 16 bits lsb-justified; 18 bits lsb-justified; 20 bits lsb-justified; 24 bits msb-justified. 7.9 power-on reset the UDA1355H has a dedicated reset pin with an internal pull-down resistor. in this way a power-on reset circuit can be made with a capacitor and a resistor at pin reset. the external resistor is needed since the pad is 5 v tolerant. this means that there is a transmission gate in series with the input and the resistor inside the pad cannot be seen from the outside world (see fig.10). the reset timing is determined by the external pull-down resistor and the external capacitor which is connected to pin reset. at power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the microcontroller mode. since the bit controlling the clock of the synchronous registers is set to enable, the synchronous registers are also reset.
2003 apr 10 19 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H the clock should be running during the reset time. when no clock can be guaranteed in microcontroller mode, a soft reset should be given when the system is running by writing to register 7fh. 8 application modes in this chapter the application modes for static mode and microcontroller mode are described. the UDA1355H can be controlled by static pins, the l3-bus or i 2 c-bus interface. due to the limitations imposed by the pin count, only basic functions are available in static mode. for optimum use of the UDA1355H features, the microcontroller mode is strongly recommended. there are 11 application modes available in the static mode and 14 application modes in microcontroller mode. the application modes are explained in the two sections: section 8.2 explains the application modes 0 to 10. section 8.4 explains the more advanced features of modes 0 to 10 and modes 12 to 14 available in the microcontroller mode. 8.1 static mode pin assignment the default values for all non-pin controlled settings are identical to the start-up defaults from the microcontroller mode. whether bck and ws are master or slave depends on the selected application mode. table 9 defines the pin functions in static mode. mgu835 handbook, halfpage transmission gate for 5v tolerance UDA1355H 16 reset v ss fig.10 5 v tolerant pull-down input pad. table 9 static mode pin assignment pin static mode symbol level description 4 lock low iec 60958 decoder out of lock (when spdif input) or clock regeneration out of lock (i 2 s-bus input) high iec 60958 decoder in lock (when spdif input) or clock regeneration in lock (i 2 s-bus input) 16 reset low normal operation high reset 17, 18, 19 mode0, mode1, mode2 - select application mode; see table 10 20 sel_static high static pin control low microcontroller mode 22, 21 slicer_sel1, slicer_sel0 low, low iec 60958 input from pin spdif0 low, high iec 60958 input from pin spdif1 high, low iec 60958 input from pin spdif2 high, high iec 60958 input from pin spdif3 29 freq_sel low select 44.1 khz sampling frequency for the crystal oscillator, note 1 mid select 32 khz sampling frequency for the crystal oscillator, note 1 high select 48 khz sampling frequency for the crystal oscillator, note 1
2003 apr 10 20 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H note 1. fpll 256fs is output from pin clkout in pll locked static mode. 8.2 static mode basic applications the static application modes are selected with the pins mode2, mode1 and mode0, with pin mode0 being a 3-level pin. in table 10, the encoding of the pins mode[2:0] is given. table 10 static mode basic applications notes 1. in column mode selection pins means: l: pin at 0 v; m: pin at half v ddd ; h: pin at v ddd . 2. in column clock means: xtal: the clock is based on the crystal oscillator; pll: the clock is based on the pll. 30, 31 sfor1, sfor0 low, low set i 2 s-bus format for digital data input and output interface low, high set lsb-justi?ed 16 bits format for digital data input interface and msb-justi?ed format for digital data output interface high, low set lsb-justi?ed 24 bits format for digital data input interface and msb-justi?ed format for digital data output interface high, high set msb-justi?ed format for digital data input and output interface 44 mute low normal operation high mute active mode mode selection pins (1) clock (2) pll locks on input spdif input spdif output adc dac i 2 s-bus input slave i 2 s-bus output master mode2 mode1 mode0 0 l l l pll pll - pll - pll spdif 1l l m - pll - pll pll - i 2 s-bus 2 l l h pll pll - pll pll pll spdif 3l h l - xtal xtal -- xtal - 4l h m - xtal xtal xtal xtal xtal - 5l h h - xtal xtal xtal xtal xtal - 6h l l - pll xtal pll pll xtal i 2 s-bus 7 h l m pll xtal xtal pll - xtal spdif 8h l h - xtal xtal pll pll xtal i 2 s-bus 9 h h l pll xtal - xtal xtal pll spdif 10 h h m pll xtal - pll xtal pll spdif 11 h h h not used pin static mode symbol level description
2003 apr 10 21 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H the first 11 application modes are given in this section. schematic diagrams of these application modes are given in table 11. in this table the basic features are mentioned and also the extra features in case of microcontroller mode are given. it should be noted that the blocks running at the crystal clock (xtal) are marked unshaded while the blocks running at the pll clock are shaded. table 11 overview of static mode basic applications mode features schematic 0 data path: input spdif to outputs dac, i 2 s or spdifout via loop through. features: system locks onto the spdif input signal bck and ws are master microcontroller mode: C dac sound features can be used C spdif input channel status bits (two times 40 bits) can be read. 1 data path: input i 2 s to outputs dac or spdif (level ii not guaranteed: depends on i 2 s-bus clock). features: system locks onto the wsi signal bcki and wsi are slave microcontroller mode: C dac sound features can be used C spdif output channel status bits (two times 40 bits) setting. mgu836 spdif in spdifout mute i 2 s output i 2 s master pll spdif lock dac i 2 s slave mgu837 i 2 s input mute spdif out pll i 2 s lock dac
2003 apr 10 22 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 2 data path: input spdif to outputs i 2 s or spdifout via loop through input i 2 s to output dac. features: possibility to process input spdif via i 2 s-bus using an external dsp and then to output dac system locks onto the spdif input signal i 2 s input and output with bck and ws are master microcontroller mode: see section 8.4. 3 data path: input adc to outputs i 2 s or spdif. features: crystal oscillator generates the clocks microcontroller mode: C pga gain setting C volume control in decimator setting C spdif output channel status bits (two times 40 bits) setting. 4 data path: input adc to output i 2 s input i 2 s to outputs dac or spdif. features: possibility to process input adc via i 2 s-bus using a external dsp and then to outputs dac or spdif crystal oscillator generates the clocks i 2 s input and output with bck and ws are master microcontroller mode: see section 8.4. mode features schematic mgu838 spdif in spdifout mute i 2 s output i 2 s master pll spdif lock dac i 2 s slave external dsp (e.g. equalizing, spatializing) (saa7715) i 2 s input i 2 s master spdif out mgu839 i 2 s output xtal adc spdif out mgu840 mute i 2 s output i 2 s master xtal dac adc i 2 s slave external dsp (e.g. equalizing, spatializing) (saa7715) i 2 s input
2003 apr 10 23 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 5 data path: input adc to outputs i 2 s or spdif input i 2 s to output dac. features: possibility to process input adc via i 2 s-bus using an external dsp and then to output dac crystal oscillator generates the clocks i 2 s input and output with bck and ws are master microcontroller mode: see section 8.4. 6 data path: input adc to output i 2 s input i 2 s to outputs dac or spdif (level ii not guaranteed: depends on i 2 s-bus clock). features: possibility to process input adc via i 2 s-bus using an external dsp and then to outputs dac or spdif crystal oscillator generates the clocks for input adc and output i 2 s wsi is slave wso is master microcontroller mode: see section 8.4. mode features schematic spdif out mgu841 mute i 2 s output i 2 s master xtal dac adc i 2 s slave external dsp (e.g. equalizing, spatializing) (saa7715) i 2 s input pll i 2 s lock spdif out mgu842 mute i 2 s output i 2 s master xtal dac adc i 2 s slave external dsp (saa7715) i 2 s input
2003 apr 10 24 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 7 data path: input spdif to output dac input adc to outputs spdif or i 2 s. features: crystal oscillator generates the clocks for outputs spdif and i 2 s pll locks onto the spdif input signal ws of i 2 s output is master microcontroller mode: C decimator features can be used C dac sound features can be used C spdif input channel status bits (two times 40 bits) can be read C spdif output channel status bits (two times 40 bits) setting. 8 data path: input adc to outputs spdif or i 2 s input i 2 s to output dac. features: possibility to process input adc, via i 2 s-bus using an external dsp and then to output dac crystal oscillator generates the clocks for outputs spdif and i 2 s wsi is slave wso master microcontroller mode: C decimator features can be used C dac sound features can be used C spdif output channel status bits (two times 40 bits) setting. mode features schematic i 2 s master spdif in pll spdif lock spdif out mgu843 mute i 2 s output xtal dac adc external dsp (e.g. sample rate convertor) (saa7715) pll i 2 s lock spdif out mgu844 mute i 2 s output i 2 s master xtal dac adc i 2 s slave i 2 s input
2003 apr 10 25 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 9 data path: input spdif to output i 2 s input i 2 s to outputs dac or spdif. features: possibility to process input spdif, via i 2 s-bus using an external dsp and then to outputs dac or spdif bck and ws being master for both i 2 s input and output (different clocks) input i 2 s to outputs dac and spdif; bck and ws being master; clocks based on crystal oscillator microcontroller mode: C dac sound features can be used C spdif output channel status bits (two times 40) setting. 10 data path: input spdif to output dac or i 2 s input i 2 s-bus to output spdif. features: possibility to process input spdif, via i 2 s-bus using an external dsp and then to output spdif input spdif to outputs i 2 s and dac; locking onto the spdif input signal; bck and ws being master input i 2 s to output spdif; bck and ws being master; clocks are generated by the crystal oscillator microcontroller mode: C dac sound features can be used C spdif input channel status bits (two times 40) can be read C spdif output channel status bits (two times 40) setting. 11 not used 12 see microcontroller mode 13 see microcontroller mode 14 see microcontroller mode 15 not used mode features schematic mgu845 spdif in mute i 2 s output i 2 s master pll spdif lock dac i 2 s slave external dsp (e.g. sample rate convertor) (saa7715) i 2 s input xtal spdif out mgu846 spdif in mute i 2 s output i 2 s master pll spdif lock dac i 2 s slave external dsp (e.g. sample rate convertor) (saa7715) i 2 s input xtal spdif out
2003 apr 10 26 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 8.3 microcontroller mode pin assignment in microcontroller mode all features become available, such as volume control, pga gain and mixing (in some modes). the pin functions are defined in table 12. table 12 microcontroller mode pin assignment pin symbol l3-bus symbol i 2 c-bus level description 4 lock lock low fpll and spdif are out of lock high fpll in lock when spdif is not used; fpll or spdif in lock when spdif is used 16 reset reset low normal operation high reset 17 no function no function low connect to ground 18 a0 a0 - a0 address input/output bit (for microcontroller register) 19 u_rdy u_rdy low user bit stable high new user bit 20 sel_static sel_static mid i 2 c-bus mode low l3-bus mode high static mode 21 user user - user bit output (new bit every spdif sub-frame) 22 ac3 ac3 low no i 2 s-bus data preamble detected high i 2 s-bus data preamble detected 29 l3mode no function - l3mode for l3-bus mode; no function for i 2 c-bus 30 l3clock scl - l3clock for l3-bus mode or scl for i 2 c-bus mode 31 l3data sda - l3data for l3-bus mode or sda for i 2 c-bus mode 44 mute mute low no mute high mute active
2003 apr 10 27 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 8.4 microcontroller mode applications in table 13, the encoding of bits mode[3:0] in the microcontroller mode is given. table 13 microcontroller mode applications note 1. in column clock means: xtal: the clock is based on the crystal oscillator; pll: the clock is based on the pll. mode mode bits clock (1) pll locks on input mode[3:0] spdif input spdif output adc dac i 2 s-bus input slave i 2 s-bus output master 0 0000 pll pll - pll - pll spdif 1 0001 - pll - pll pll - i 2 s 2 0010 pll pll pll pll pll pll spdif 3 0011 - xtal xtal -- xtal - 4 0100 - xtal xtal xtal xtal xtal - 5 0101 - xtal xtal xtal xtal xtal - 6 0110 - pll xtal pll pll xtal i 2 s 7 0111 pll xtal xtal pll - xtal spdif 8 1000 - xtal xtal pll pll xtal i 2 s 9 1001 pll xtal xtal xtal xtal pll spdif 10 1010 pll xtal pll pll xtal pll spdif 11 1011 not used 12 1100 pll xtal xtal pll pll xtal spdif 13 1101 pll pll xtal pll pll xtal spdif 14 1110 - pll pll pll pll pll i 2 s 15 1111 not used
2003 apr 10 28 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H in the microcontroller mode, more features are available. the application modes are given in table 14. some modes are the same in terms of data path as for the static mode. these modes are already explained in section 8.2. some modes are combined into one mode (like modes 4 and 5). table 14 overview of microcontroller modes mode feature schematic 0 see static mode 1 see static mode 2 data path: inputs adc, i 2 s and spdif to outputs dac, i 2 s or spdif. features: all clocks are related to the spdif clock i 2 s input and output have master bck and ws spdif input channel status bits (two times 40) can be read output spdif supported but the timing not according to level ii: depends on i 2 s-bus clock output spdifout loop through can be selected with independent spdif input channel select. 3 see static mode 4 + 5 data path: inputs adc and i 2 s to outputs dac, i 2 s or spdif. features: mode 4 and 5 are combined in microcontroller mode crystal oscillator generates the clocks i 2 s input and output have master bck and ws spdif output channel status bits (two times 40) setting. adc mgu847 spdif in mute i 2 s output i 2 s master pll spdif lock dac i 2 s slave external dsp (e.g. equalizing, spatializing) (saa7715) i 2 s input spdif out spdif out spdif out adc mgu848 mute i 2 s output i 2 s master xtal dac i 2 s slave external dsp (e.g. equalizing, spatializing) (saa7715) i 2 s input
2003 apr 10 29 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 6 see static mode 7 see static mode 8 see static mode 9 data path: inputs adc and i 2 s to outputs dac or spdif input spdif to output i 2 s. features: input spdif to output i 2 s with bck and ws being master; the clocks for this are recovered from the spdif input signal the rest of the clocks are generated by the crystal oscillator spdif input channel status bits (two times 40) can be read spdif output channel status bits (two times 40) setting possibility to process input spdif, via i 2 s-bus using an external dsp and then to outputs dac or spdif. 10 data path: inputs adc and spdif to outputs dac or i 2 s input i 2 s to output spdif. features: bck and ws are master spdif input channel status bits (two times 40) can be read spdif output channel status bits (two times 40) setting possibility to process inputs adc or spdif, via i 2 s-bus using an external dsp and then to output spdif. 11 not used mode feature schematic pll spdif lock xtal spdif in spdif out adc mgu849 mute i 2 s output i 2 s master dac i 2 s slave external dsp (e.g. sample rate convertor) (saa7715) i 2 s input pll spdif lock xtal spdif in spdif out adc mgu850 mute i 2 s output i 2 s master dac i 2 s slave external dsp (e.g. sample rate convertor) (saa7715) i 2 s input
2003 apr 10 30 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12 data path: input adc to outputs i 2 s or spdif inputs i 2 s and spdif to output dac. features: bck and ws of i 2 s output are master inputs spdif and i 2 s to output dac with mixing/selection possibility; clocks are generated from spdif input signal, and bck and ws are master spdif input channel status bits (two times 40) can be read spdif output channel status bits (two times 40) setting. 13 data path: input adc to output i 2 s inputs i 2 s and spdif to outputs dac or spdif. features bck and ws being master spdif input channel status bits (two times 40) can be read output spdif supported but the timing not according to level ii output spdifout loop through can be selected with independent spdif input channel select. 14 data path: inputs adc and i 2 s to outputs dac spdif and i 2 s. features: all clocks are related to ws signal of i 2 s-bus input master bck and ws for i 2 s output; slave bck and ws for i 2 s input spdif output channel status bits (two times 40) can be set; level ii timing depends on the i 2 s-bus clocks. 15 not used mode feature schematic i 2 s master i 2 s slave pll spdif lock xtal spdif in spdif out adc mgu851 mute i 2 s output dac i 2 s input adc mgu852 spdif in mute i 2 s output pll spdif lock dac i 2 s input spdif out spdif out xtal i 2 s master i 2 s slave spdif out pll adc mgu853 mute i 2 s output dac i 2 s input i 2 s master i 2 s slave i 2 s lock
2003 apr 10 31 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 9 spdif signal format 9.1 spdif channel encoding the digital signal is coded using biphase mark code (bmc), which is a kind of phase modulation. in this scheme, a logic 1 in the data corresponds to two zero-crossings in the coded signal, and a logic 0 to one zero-crossing. an example of the encoding is given in fig.11. 9.2 spdif hierarchical layers the spdif signal format is shown in fig.12. a pcm signal is transmitted in sequential blocks. each block consists of 192 frames. each frame contains two sub-frames, one for each channel. each subframe is preceded by a preamble. there are three types of preambles: b, m and w. preambles can be spotted easily in an spdif bitstream because these sequences never occur in the channel parts of a valid spdif bitstream. the sub-frame format is represented by fig.13. a sub-frame contains a single audio sample word which may be 24 bits wide, a validity bit which indicates whether the sample is valid, a bit containing user data, a bit indicating the channel status and a parity bit for this sub-frame. the data bits 31 to 4 in each sub-frame are encoded using a bmc scheme. the sync preamble contains a violation of the bmc scheme and can be detected. table 15 indicates the values of the preambles. handbook, halfpage data clock bmc mgu606 fig.11 biphase mark encoding. fig.12 spdif signal format handbook, full pagewidth channel 1 mmm ww w b channel 2 channel 1 sub-frame channel 2 channel 1 channel 2 channel 1 channel 2 frame 0 frame 191 frame 191 block mgu607 sub-frame handbook, full pagewidth sync preamble auxiliary 03478 27 28 31 l s b l s b m s b p audio sample word c u v validity flag user data channel status parity bit mgu608 fig.13 sub-frame format
2003 apr 10 32 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 15 preambles 9.3 timing characteristics 9.3.1 f requency requirements the spdif specification iec 60958 supports three levels of clock accuracy: level i high accuracy: tolerance of transmitting sampling frequency shall be within 50 10 - 6 level ii, normal accuracy: all receivers should receive a signal of 1000 10 - 6 of nominal sampling frequency level iii, variable pitch shifted clock mode: a deviation of 12.5% of the nominal sampling frequency is possible. the UDA1355H inputs support level i, ii, and iii as specified by the iec 60958 standard. 9.3.2 r ise and fall times rise and fall times (see fig.14) are defined as: rise time = fall time = rise and fall times should be in the range: 0% to 20% when the data bit is a logic 1 0% to 10% when the data bits are two succeeding logic 0. 9.3.3 d uty cycle the duty cycle (see fig.14) is defined as: duty cycle = the duty cycle should be in the range: 40% to 60% when the data bit is a logic 1 45% to 55% when the data bits are two succeeding logic 0. 10 l3-bus description the exchange of data and control information between the microcontroller and the UDA1355H is accomplished through a serial hardware l3-bus interface comprising the following pins: mp0: mode line with signal l3mode mp1: clock line with signal l3clock mp2: data line with signal l3data. the exchange of bytes in l3-bus mode is lsb first. the l3-bus format has two modes of operation: address mode data transfer mode. the address mode is used to select a device for a subsequent data transfer. the address mode is characterized by l3mode being low and a burst of 8 pulses on l3clock, accompanied by 8 bits (see fig.15). the data transfer mode is characterized by l3mode being high and is used to transfer one or more bytes representing a register address, instruction or data. basically two types of data transfers can be defined: write action: data transfer to the device read action: data transfer from the device. 10.1 device addressing the device address consists of one byte with: data operating mode (dom) bits 0 and 1 representing the type of data transfer (see table 16) address bits 2 to 7 representing a 6-bit device address. preceding state channel coding 01 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 t r t l t h + --------------- 100% t f t l t h + --------------- 100% handbook, halfpage 90% t h 50% 10% mgu612 t r t f t l fig.14 rise, fall time and duty cycle. t h t l t h + --------------- 100%
2003 apr 10 33 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 16 selection of data transfer the device address of the UDA1355H is given in table 17, being the first 6 bits of the device address byte. the address can be set one of two by using pin mode1 (pin a0 in microcontroller mode). table 17 l3-bus device address remark : when using the device address, there is often misunderstanding. this is caused by the fact that the data is sent lsb first. this means that when we use the device address in, for example the philips l3-bus/i 2 c-bus bithacker, we have to use the address like lsb ? msb. for the UDA1355H this means that the device address to be used is either 10h (010000) or 30h (110000). 10.2 register addressing after sending the device address, including data operating mode (dom) bits indicating whether the information is to be read or written, one data byte is sent using bit 0 to indicate whether the information will be read or written and bits 1 to 7 for the destination register address. basically there are three methods for register addressing: addressing for write data: bit 0 is logic 0 indicating a write action to the destination register, followed by bits 1 to 7 indicating the register address (see fig.15) addressing for prepare read: bit 0 is logic 1 indicating that data will be read from the register (see fig.16) addressing for data read action: in this case the device returns a register address prior to sending data from that register. when bit 0 is logic 0, the register address is valid; in case bit 0 is logic 1 the register address is invalid. 10.3 data write mode the data write mode is explained in the signal diagram of fig.15. for writing data to a device, 4 bytes must be sent (see table 18): byte 1 starting with 01 for signalling the write action to the device, followed by the device address byte 2 starting with 0 for signalling the write action, followed by 7 bits indicating the destination address in binary format with a6 being the msb and a0 being the lsb byte 3 with bit d15 being the msb byte 4 with bit d0 being the lsb. it should be noted that each time a new destination register address needs to be written, the device address must be sent again. 10.4 data read mode for reading data from the device, first a prepare read must be done and then data read. the data read mode is explained in the signal diagram of fig.16. for reading data from a device, the following 6 bytes are involved (see table 19): byte 1 with the device address including 01 for signalling the write action to the device byte 2 is sent with the register address from which data needs to be read. this byte starts with 1, which indicates that there will be a read action from the register, followed again by 7 bits for the destination address in binary format with a6 being the msb and a0 being the lsb byte 3 with the device address including 11 is sent to the device. the 11 indicates that the device must write data to the microcontroller byte 4, sent by the device to the bus, with the (requested) register address and a flag bit indicating whether the requested register was valid (bit is logic 0) or invalid (bit is logic 1) byte 5, sent by the device to the bus, with the data information in binary format with d15 being the msb byte 6, sent by the device to the bus, with the data information in binary format with d0 being the lsb. dom bits transfer bit 0 bit 1 0 0 not used 1 0 not used 0 1 write data or prepare read 1 1 read data msb address lsb 00001a0
2003 apr 10 34 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 2003 apr 10 34 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... mgs753 l3clock l3mode l3data 0 write l3 wake-up pulse after power-up device address dom bits register address data byte 1 data byte 2 10 fig.15 data write mode. mgs754 l3clock l3mode l3data 0 read valid/non-valid device address prepare read send by the device dom bits register address device address register address data byte 1 data byte 2 111 0/1 1 fig.16 data read mode.
2003 apr 10 35 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 18 l3-bus write data table 19 l3-bus read data byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 a0 10000 2 data transfer register address 0 a6 a5 a4 a3 a2 a1 a0 3 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 4 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 byte l3-bus mode action first in time last in time bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 address device address 0 1 a0 10000 2 data transfer register address 1 a6 a5 a4 a3 a2 a1 a0 3 address device address 1 1 a0 10000 4 data transfer register address 0 or 1 a6 a5 a4 a3 a2 a1 a0 5 data transfer data byte 1 d15 d14 d13 d12 d11 d10 d9 d8 6 data transfer data byte 2 d7 d6 d5 d4 d3 d2 d1 d0 11 i 2 c-bus description 11.1 characteristics the bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to the supply voltage (v dd ) via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz ic the recommendation for this type of bus from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 to 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. 11.2 bit transfer one data bit is transferred during each clock pulse (see fig.17). the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to be able to run on this high frequency all the inputs and outputs connected to this bus must be designed for this high speed i 2 c-bus according the philips specification. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.17 bit transfer on the i 2 c-bus.
2003 apr 10 36 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 11.3 byte transfer each byte (8 bits) is transferred with the msb first (see table 20). table 20 byte transfer 11.4 data transfer a device generating a message is a transmitter; a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves. 11.5 register address the register addresses in the i 2 c-bus mode are the same as in the l3-bus mode. 11.6 device address before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. the device address can be one of two, being set by bit a0 which corresponds to pin mode1. the UDA1355H acts as a slave receiver or a slave transmitter. therefore, the clock signal scl is only an input signal. the data signal sda is a bidirectional line. the UDA1355H slave address is shown in table 21. table 21 i 2 c-bus slave address 11.7 start and stop conditions both data and clock line will remain high when the bus in not busy. a high-to-low transition of the data line, while the clock is high, is defined as a start condition (s). a low-to-high transition of the data line while the clock is high is defined as a stop condition (p); (see fig.18). 11.8 acknowledgment the number of data bits transferred between the start and stop conditions from the transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit (see fig.19). at the acknowledge bit the data line is released by the master and the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull-down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition. msb bit lsb 76543210 device address r/ w a6 a5 a4 a3 a2 a1 a0 - 0 0 1 1 0 1 a0 0/1 handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.18 start and stop conditions on the i 2 c-bus.
2003 apr 10 37 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.19 acknowledge on the i 2 c-bus. 11.9 write cycle the write cycle is used to write groups of two bytes to the internal registers for the digital sound feature control and system setting. it is also possible to read these locations for chip status information. the i 2 c-bus configuration for a write cycle is shown in table 22. the write cycle is used to write the data to the internal registers. the device and register addresses are one byte each, the setting data is always a couple of two bytes. the format of the write cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1355H. 4. after this the microcontroller writes the 8-bit register address (addr) where the writing of the register content of the UDA1355H must start. 5. the UDA1355H acknowledges this register address (a). 6. the microcontroller sends two bytes data with the most significant (ms) byte first and then the least significant (ls) byte. after each byte an acknowledge is followed from the UDA1355H. 7. if repeated groups of two bytes are transmitted, then the register address is auto incremented. after each byte an acknowledge is followed from the microcontroller. 8. finally, the UDA1355H frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 22 master transmitter writes to the UDA1355H registers in the i 2 c mode. note 1. auto increment of register address. device address r/ w register address data 1 data 2 (1) data n (1) s 0011010 0 a addr a ms1 a ls1 a .... a ..... a msn a lsn a p acknowledge from UDA1355H
2003 apr 10 38 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 2003 apr 10 38 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 11.10 read cycle the read cycle is used to read the data values from the internal registers. the i 2 c-bus configuration for a read cycle is shown in table 23 the format of the read cycle is as follows: 1. the microcontroller starts with a start condition (s). 2. the first byte (8 bits) contains the device address 0011010 and a logic 0 (write) for the r/ w bit. 3. this is followed by an acknowledge (a) from the UDA1355H. 4. after this microcontroller writes the 8-bit register address (addr) where the reading of the register content of the UDA1355H must start. 5. the UDA1355H acknowledges this register address (a). 6. then the microcontroller generates a repeated start (sr). 7. then the microcontroller generates the device address 0011010 again, but this time followed by a logic 1 (read) of the r/ w bit. an acknowledge (a) follows from the UDA1355H. 8. the UDA1355H sends two bytes data with the most significant (ms) byte first and then the least significant (ls) byte. after e ach byte an acknowledged follows from the microcontroller. 9. if repeated groups of two bytes are transmitted, then the register address is auto incremented. after each byte an acknowledg e follows from the microcontroller. 10. the microcontroller stops this cycle by generating a negative acknowledge (na). 11. finally, the UDA1355H frees the i 2 c-bus and the microcontroller can generate a stop condition (p). table 23 master transmitter reads from the UDA1355H registers in the i 2 c-bus mode note 1. auto increment of register address. device address r/ w register address device address r/ w data 1 data 2 (1) data n (1) s 0011010 0 a addr a sr 0011010 1 a ms1 a ls1 a ... a ... a msn a lsn na p acknowledge from UDA1355H acknowledge from master
2003 apr 10 39 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12 register mapping in this chapter the register addressing of the microcontroller interface of the UDA1355H is given. in section 12.1, the mapping of the readable and writable registers is given. the explanation of the register definitions are explained in sections 12.2 and 12.3. 12.1 address mapping table 24 register map settings address r/w description system settings 00h r/w crystal clock power-on setting; crystal clock and pll divider settings; mode and ws detector settings; clock output setting 01h r/w i 2 s-bus output format settings 02h r/w i 2 s-bus input format settings 03h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 04h r/w analog power and clock settings interpolator 10h r/w master volume control settings 11h r/w mixer volume settings 12h r/w sound feature and bass boost and treble settings 13h r/w gain select; de-emphasis and mute settings 14h r/w dac polarity; noise shaper selection; mixer; source selection; silence detector and interpolator oversampling settings 18h r mute and silence detector status read-out 19h r/w resonant bass boost coef?cient k1 setting 1ah r/w resonant bass boost coef?cient km setting 1bh r/w resonant bass boost coef?cient a1 setting 1ch r/w resonant bass boost coef?cient a2 setting 1dh r/w resonant bass boost coef?cient b1 setting 1eh r/w resonant bass boost coef?cient b2m setting decimator 20h r/w adc gain settings 21h r/w adc mute and pga gain settings; 22h r/w adc polarity and dc cancellation settings 28h r mute status and over?ow adc read-out spdif input 30h r/w spdif power control and spdif input settings 40h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 59h r spdif lock; bit error information and spdif encoder output status read-out 5ah r spdif input status bits 15 to 0 left channel read-out 5bh r spdif input status bits 31 to 16 left channel read-out 5ch r spdif input status bits 39 to 32 left channel read-out
2003 apr 10 40 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12.2 read/write registers mapping 12.2.1 s ystem settings table 25 register address 00h 5dh r spdif input status bits 15 to 0 right channel read-out 5eh r spdif input status bits 31 to 16 right channel read-out 5fh r spdif input status bits 39 to 32 right channel read-out spdif output 50h r/w spdif output valid; left to right channel status bit copy; power control and spdif output selection setting 51h r/w spdif output status bits 39 to 24 left channel setting 52h r/w spdif output status bits 23 to 8 left channel setting 53h r/w spdif output status bits 7 to 0 left channel setting 54h r/w spdif output status bits 39 to 24 right channel setting 55h r/w spdif output status bits 23 to 8 right channel setting 56h r/w spdif output status bits 7 to 0 right channel setting 60h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 61h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 62h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 63h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation 64h r/w reserved for manufacturers evaluation and should be kept untouched for normal operation device id 7eh r device id; version software reset 7fh r/w restore l3-bus defaults bit 15 14 13 12 11 10 9 8 symbol expu - pon_xtal pll xtl_div4 xtl_div3 xtl_div2 xtl_div1 xtl_div0 default 0 0 1 0 1 0 0 0 bit 7 6 5 4 3 2 1 0 symbol mode3 mode2 mode1 mode0 ws_detct_en ws_detct_set clkout_ sel1 clkout_ sel0 default 0 0 1 0 1 0 1 0 address r/w description
2003 apr 10 41 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 26 description of register bits (address 00h) table 27 crystal oscillator output frequencies bit symbol description 15 expu expu. bit expu is reserved for manufacturers evaluation and should be kept untouched for normal operation of UDA1355H. 14 - reserved 13 pon_xtalpll power control crystal oscillator and pll. if this bit is logic 0, then the crystal oscillator and pll are turned off; if this bit is logic 1, then the crystal oscillator and pll are running. 12 to 8 xtl_div[4:0] crystal oscillator clock divider setting. value to select the sampling frequency and the system clock output frequency (256f s or 384f s ). when 256f s is selected, the master bcki and bcko clock frequency of digital interface running with crystal oscillator clock will be 64f s ; when 384f s is selected, it will be 48f s (see table 27). 7 to 4 mode[3:0] microcontroller application mode setting. value to select the microcontroller application mode (see table 28). 3 ws_detct_en word select detector enable. if this bit is logic 0, then ws detector is disabled; if this bit is logic 1, then ws detector is enabled. 2 ws_detct_set word select detector limit setting. if this bit is logic 0, then the lower frequency limit of the ws detector is 4095 clock cycles (3 khz); if this bit is logic 1, then the lower frequency limit of the ws detector is 2047 clock cycles (6 khz). 1 and 0 clkout_sel[1:0] clock output select. if these bits are 00 or 10, then the bcki and bcko clock frequency of digital interface running with fpll clock will be 64f s ; otherwise, it will be 48f s . the selection between 256f s and 384f s for the crystal clock output is set via the bits xtl_div[4:0]: 00 = fpll clock 256f s 01 = fpll clock 384f s 10 = crystal clock 11 = crystal clock xtl_div4 xtl_div3 xtl_div2 xtl_div1 xtl_div0 output rate based on 32 khz 00000256 16 khz 00001384 16 khz 00010256 32 khz 00011384 32 khz 00100256 64 khz 00101384 64 khz based on 44.1 khz 00110256 22.05 khz 00111384 22.05 khz 01000256 44.1 khz 01001384 44.1 khz 01010256 88.2 khz 01011384 88.2 khz
2003 apr 10 42 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 28 application mode selection table 29 register address 01h based on 48 khz 01100256 24 khz 01101384 24 khz 01110256 48 khz 01111384 48 khz 10000256 96 khz 10001384 96 khz mode3 mode2 mode1 mode0 function 0000 mode 0 0001 mode 1 0010 mode 2 0011 mode 3 0100 mode 4 0101 mode 5 0110 mode 6 0111 mode 7 1000 mode 8 1001 mode 9 1010 mode 10 1011 mode 11 1100 mode 12 1101 mode 13 1110 mode 14 1111 mode 15 bit 15 14 13 12 11 10 9 8 symbol --- -- - - mute_dao default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol pon_digo - digout1 digout0 - sforo2 sforo1 sforo0 default 1 0 1 0 0 0 0 0 xtl_div4 xtl_div3 xtl_div2 xtl_div1 xtl_div0 output rate
2003 apr 10 43 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 30 description of register bits (address 01h) table 31 register address 02h table 32 description of register bits (address 02h) bit symbol description 15 to 9 - reserved 8 mute_dao digital mute setting. if this bit is logic 0, then the digital output is not muted; if this bit is logic 1, then the digital output is muted. 7 pon_digo power control digital output. if this bit is logic 0, then the digital output is in power-down mode; if this bit is logic 1, then the digital output is in power-on mode. the registers have their own clock, which means that there cannot be a dead-lock situation. 6 - reserved 5 and 4 digout[1:0] input selector for digital output. value to select the input signal for the digital output. the default input will be chosen if in an application an invalid data signal is selected: 00 = adc input 01 = digital input 10 = iec 60958 input 11 = interpolator mixer output 3 - reserved 2 to 0 sforo[2:0] digital output format. value to set the digital output format: 000 = i 2 s-bus 001 = lsb-justified; 16 bits 010 = lsb-justified; 18 bits 011 = lsb-justified; 20 bits 100 = lsb-justified; 24 bits 101 = msb-justified 110 = not used; output is default value 111 = not used; output is default value bit 15 14 13 12 11 10 9 8 symbol - ---- - - - default 0 0000 0 0 0 bit7 6543 2 1 0 symbol pon_digi ---- sfori2 sfori1 sfori0 default 1 0000 0 0 0 bit symbol description 15 to 8 - reserved 7 pon_digi power control digital input. if this bit is logic 0, then the digital input is in power-down mode; if this bit is logic 1, then the digital input is in power-on mode. the registers have their own clock, which means that there cannot be a dead-lock situation. 6to3 - reserved
2003 apr 10 44 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 33 register address 04h table 34 description of register bits (address 04h) 2 to 0 sfori[2:0] digital input format. value to set the digital input format: 000 = i 2 s-bus 001 = lsb-justified; 16 bits 010 = lsb-justified; 18 bits 011 = lsb-justified; 20 bits 100 = lsb-justified; 24 bits 101 = msb-justified 110 = not used; input is default value 111 = not used; input is default value bit 15 14 13 12 11 10 9 8 symbol pon_dac - --- pon_adcl pon_adcr pon_adc_bias default 1 0 0 0 0 1 1 1 bit 7654321 0 symbol daclk_off daclk_auto --- en_dec - en_int default 0 0 0 0 0 1 0 1 bit symbol description 15 pon_dac power control dac. if this bit is logic 0, then the dac is in power-down mode; if this bit is logic 1, then the dac is in power-on mode. this bit is only connected to the dac input and is not combined with mute status or other signals. 14 to 11 - reserved 10 pon_adcl power control adc left channel. value to set power on the adc left channel (see table 35). 9 pon_adcr power control adc right channel. value to set power on the adc right channel (see table 35). 8 pon_adc_bias power control adc bias. value to set power on the adcs (see table 35). 7 daclk_off dac clock enable. if this bit is logic 0, then the dac clock is disabled; if this bit is logic 1, then the dac clock is enabled. 6 daclk_auto dac clock auto function. if this bit is logic 0, then the dac clock auto function is disabled; if this bit is logic 1, then the dac clock auto function is enabled. if the fpll is unlocked, the interpolator will be muted and the dac clock is automatically disabled. 5to3 - reserved 2 en_dec decimator and adc clock enable. if this bit is logic 0, then the clock to decimator and adc is disabled; if this bit is logic 1, then the clock to decimator and adc is running. 1 - reserved 0 en_int interpolator clock enable. if this bit is logic 0, then the clock to interpolator and fsdac is disabled; if this bit is logic 1, then the clock to the interpolator and fsdac is running. bit symbol description
2003 apr 10 45 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 35 adc power control 12.2.2 i nterpolator table 36 register address 10h table 37 description of register bits (address 10h) table 38 master volume setting left and right channel pon_adc_bias pon_adcr pon_adcl description 0 x x no power on both adcs 1 0 0 no power on both adcs 1 1 0 only power on right channel adc 1 0 1 only power on left channel adc 1 1 1 power on both adcs bit 15 14 13 12 11 10 9 8 symbol mvcl_7 mvcl_6 mvcl_5 mvcl_4 mvcl_3 mvcl_2 mvcl_1 mvcl_0 default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol mvcr_7 mvcr_6 mvcr_5 mvcr_4 mvcr_3 mvcr_2 mvcr_1 mvcr_0 default 0 0 0 0 0 0 0 0 bit symbol description 15 to 8 mvcl_[7:0] master volume setting left channel. value to program the left channel master volume attenuation. the range is 0 db to - 78 db and db (see table 38). 7 to 0 mvcr_[7:0] master volume setting right channel. value to program the right channel master volume attenuation. the range is 0 db to - 78 db and db (see table 38). mvcl_7 mvcl_6 mvcl_5 mvcl_4 mvcl_3 mvcl_2 mvcl_1 mvcl_0 volume (db) mvcr_7 mvcr_6 mvcr_5 mvcr_4 mvcr_3 mvcr_2 mvcr_1 mvcr_0 000000000 00000001 - 0.25 00000010 - 0.5 00000011 - 0.75 00000100 - 1 ::::::::: 11001100 - 51 11001101 - 51.25 11001110 - 51.5 11001111 - 51.75 11010000 - 52
2003 apr 10 46 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 39 register address 11h table 40 description of register bits (address 11h) table 41 mixer volume setting channel 1 and 2 11010100 - 54 11011000 - 56 ::::::::: 11101100 - 66 11110000 - 69 11110100 - 72 11111000 - 78 11111100 - bit 15 14 13 12 11 10 9 8 symbol vc2_7 vc2_6 vc2_5 vc2_4 vc2_3 vc2_2 vc2_1 vc2_0 default 1 1 1 1 1 1 1 1 bit76543210 symbol vc1_7 vc1_6 vc1_5 vc1_4 vc1_3 vc1_2 vc1_1 vc1_0 default 0 0 0 0 0 0 0 0 bit symbol description 15 to 8 vc2_[7:0] mixer volume setting channel 2. value to program channel 2 mixer volume attenuation. the range is 0 db to - 72 db and db (see table 41). 7 to 0 vc1_[7:0] mixer volume setting channel 1. value to program channel 1 mixer volume attenuation. the range is 0 db to - 72 db and db (see table 41). vc2_7 vc2_6 vc2_5 vc2_4 vc2_3 vc2_2 vc2_1 vc2_0 volume (db) vc1_7 vc1_6 vc1_5 vc1_4 vc1_3 vc1_2 vc1_1 vc1_0 000000000 00000001 - 0.25 00000010 - 0.5 00000011 - 0.75 00000100 - 1 ::::::::: 10110100 - 45 10110101 - 45.25 10110110 - 45.5 10110111 - 45.75 10111000 - 46 mvcl_7 mvcl_6 mvcl_5 mvcl_4 mvcl_3 mvcl_2 mvcl_1 mvcl_0 volume (db) mvcr_7 mvcr_6 mvcr_5 mvcr_4 mvcr_3 mvcr_2 mvcr_1 mvcr_0
2003 apr 10 47 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 42 register address 12h table 43 description of register bits (address 12h) 10111100 - 48 11000000 - 50 ::::::::: 11010100 - 60 11011000 - 63 11011100 - 66 11100000 - 72 11100100 - ::::::::: 11111100 - bit 15 14 13 12 11 10 9 8 symbol m1 m0 trl1 trl0 bbl3 bbl2 bbl1 bbl0 default 00000000 bit76543210 symbol bb_off bb_fix trr1 trr0 bbr3 bbr2 bbr1 bbr0 default 00000000 bit symbol description 15 and 14 m[1:0] sound feature mode. value to program the sound processing ?lter sets (modes) of bass boost and treble: 00 = flat set 01 = minimum set 10 = minimum set 11 = maximum set 13 and 12 trl[1:0] treble settings left. value to program the left channel treble setting. both left and right channels will follow the left channel setting when bit bass_sel = 1. the used ?lter set is selected with the sound feature mode bits m1 and m2 (see table 44). 11 to 8 bbl[3:0] normal bass boost settings left. value to program the left bass boost settings. the used ?lter set is selected by the sound feature mode bits m1 and m2 (see table 45). 7 bb_off resonant bass boost. if this bit is logic 0 then the resonant bass boost is enabled; if this bit is logic 1 then the resonant bass boost is disabled. vc2_7 vc2_6 vc2_5 vc2_4 vc2_3 vc2_2 vc2_1 vc2_0 volume (db) vc1_7 vc1_6 vc1_5 vc1_4 vc1_3 vc1_2 vc1_1 vc1_0
2003 apr 10 48 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 44 treble settings table 45 normal bass boost settings; note 1 note 1. the bass boost setting is only effective when bit bass_sel = 0. 6 bb_fix resonant bass boost coef?cient. if this bit is logic 0 then the resonant bass boost coef?cient is ?nished loading; if this bit is logic 1 then the resonant bass boost coef?cient is loading to register. 5 and 4 trr[1:0] treble settings right. value to program the right treble setting. the used ?lter set is selected by the sound feature mode bits m1 and m2 (see table 44). 3 to 0 bbr[3:0] normal bass boost settings right. value to program the right bass boost settings. the used ?lter set is selected by the sound feature mode bits m1 and m2 (see table 45). trl1 trl0 flat set (db) min. set (db) max. set (db) trr1 trr0 00000 01022 10044 11066 bbl3 bbl2 bbl1 bbl0 flat set (db) min set (db) max set (db) bbr3 bbr2 bbr1 bbr0 0000 0 0 0 0001 0 2 2 0010 0 4 4 0011 0 6 6 0100 0 8 8 0101 0 1010 0110 0 1212 0111 0 1414 1000 0 1616 1001 0 1818 1010 0 1820 1011 0 1822 1100 0 1824 1101 0 1824 1110 0 1824 1111 0 1824 bit symbol description
2003 apr 10 49 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 46 register address 13h table 47 description of register bits (address 13h) table 48 dac gain setting notes 1. see table 52. 2. x = dont care bit 15 14 13 12 11 10 9 8 symbol - mtm gs mixgain mt2 de2_2 de2_1 de2_0 default 00001000 bit76543210 symbol mtns1 mtns0 ws_sel de_sw mt1 de1_2 de1_1 de1_0 default 00000000 bit symbol description 15 - reserved 14 mtm master mute. if this bit is logic 0 then there is no master mute or the master de-mute is in progress; if this bit is logic 1 then the master mute is in progress or muted. 13 gs gain select. see table 48. 12 mixgain mixer gain select. see tables 48 and 49. 11 mt2 channel 2 mute. if this bit is logic 0 then channel 2 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 2 is muted or the muting is in progress. 10 to 8 de2_[2:0] de-emphasis setting for channel 2. see table 50. 7 and 6 mtns[1:0] interpolator mute. selection: 00 = no mute 01 = if no ws signal is detected, the noise shaper of the interpolator mute 1x = the noise shaper of the interpolator mute 5 ws_sel ws signal select. if this bit is logic 0 then ws_det is selected for the ws detection; if this bit is logic 1 then fpll is selected for the ws detection. 4 de_sw de-emphasis select. if this bit is logic 0 then spdif pre-emphasis information is selected; if this bit is logic 1 then the de-emphasis setting is selected. 3 mt1 channel 1 mute. if this bit is logic 0 then channel 1 is not muted or the de-mute is in progress; if this bit is logic 1 then channel 1 is muted or the muting is in progress. 2 to 0 de1_[2:0] de-emphasis setting for channel 1. see table 50. gs mix (1) mix_gain dac gain (db) 0x (2) x (2) 0 1006 1100 1016 1116
2003 apr 10 50 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 49 mixer gain setting note 1. see table 52. table 50 de-emphasis setting for the incoming signal table 51 register address 14h table 52 description of register bits (address 14h) mix (1) mix_gain mixer output gain 1 0 dac output gain is set to 0 db and mixer signal output gain is set - 6db 1 1 dac output gain and mixer signal output gain are set to 0 db de2_2 de2_1 de2_0 function de1_2 de1_1 de1_0 0 0 0 off 0 0 1 32 khz 0 1 0 44.1 khz 0 1 1 48 khz 1 0 0 96 khz bit 15 14 13 12 11 10 9 8 symbol da_pol_ inv sel_ns mix_pos mix dac_ch2_ sel1 dac_ch2_ sel0 dac_ch1_ sel1 dac_ch1_ sel0 default 0 1 0 0 1101 bit76 5 4 3210 symbol silence sdet_on sd_ value1 sd_ value0 bass_sel bypass os_in1 os_in0 default 0 0 0 0 0000 bit symbol description 15 da_pol_inv dac polarity control. if this bit is logic 0 then the dac output is not inverted; if this bit is logic 1 then the dac output is inverted. 14 sel_ns select noise shaper. if this bit is logic 0 then the third order noise shaper is selected; if this bit is logic 1 then the ?fth order noise shaper is selected. 13 mix_pos mixer position. mixing is done before or after the sound processing unit (see table 53). 12 mix mixer. if this bit is logic 0 then the mixer is disabled; if this bit is logic 1 then the mixer is enabled (see tables 48, 49 and 53). 11 and 10 dac_ch2_sel[1:0] dac channel 2 input selection. value to select the input mode to channel 2 of the interpolator (see table 54). 9 and 8 dac_ch1_sel[1:0] dac channel 1 input selection. value to select the input mode to channel 1 of the interpolator (see table 54).
2003 apr 10 51 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 53 mixer signal control signals note 1. x = dont care 7 silence silence detector overrule. value to force the dac output to silence. this will give a plop at the output of the dac because of mismatch in offsets and the dc offset added to the signal in the interpolator itself. if this bit is logic 0 then there is no overruling and the fsdac silence switch setting depends on the silence detector circuit and on the status of bit mtm; if this bit is logic 1 then there is overruling and the fsdac silence switch is activated independent of the status of the digital silence detector circuit or the status of bit mtm. 6 sdet_on silence detector enable. if this bit is logic 0 then the silence detection circuit is disabled; if this bit is logic 1 then the silence detection circuit is enabled. 5 and 4 sd_value[1:0] silence detector setting. value to program the silence detector. the number of zero samples counted before the silence detector signals whether there has been digital silence: 00 = 3200 samples 01 = 4800 samples 10 = 9600 samples 11 = 19200 samples 3 bass_sel bass boost select. if this bit is logic 0 then the normal bass boost function is selected; if this bit is logic 1 then the resonant bass boost function is selected. 2 bypass mixer bypass mode. if this bit is logic 0 then the mixer is in mixer mode; if this bit is logic 1 then the mixer is in mixer bypass mode. 1 and 0 os_in[1:0] oversampling ratio select. value to select the oversampling input mode. this mode is only for i 2 s-bus input: 00 = single speed input; normal input; mixing possible 01 = double speed input; after first half-band filter; no mixing possible but volume and mute still possible 10 = quad speed input; in front of noise shaper; no mixing possible; no volume control possible 11 = reserved. mix mix_pos function 0x (1) this is the default setting: no mixing, volume of channel 1 is forced to 0 db and volume of channel 2 is forced to - db 1 0 mixing is done before the sound processing; input signals are automatically scaled by 6 db in order to prevent clipping during adding; after the addition, the 6 db scaling is compensated 1 1 mixing is done after the sound processing; input signals are automatically scaled in order to prevent clipping during adding bit symbol description
2003 apr 10 52 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 54 data source selector dac channel 1 and 2; note 1 note 1. the change of the data source will take place only when the mix mode is turned on (bit mix = 1). the channel 2 input selection is valid only when the channel 1 data source is correct. table 55 register addresses 19h, 1ah, 1bh, 1ch, 1dh and 1eh table 56 description of register bits (addresses 19h, 1ah, 1bh, 1ch, 1dh and 1eh) 12.2.3 d ecimator settings table 57 register address 20h dac_ch2_sel1 dac_ch2_sel0 data output dac dac_ch1_sel1 dac_ch1_sel0 0 0 adc input 01i 2 s-bus input 1 0 iec 60958 input 11i 2 s-bus input bit 15 14 13 12 11 10 9 8 symbol -- bass_x_13 bass_x_12 bass_x_11 bass_x_10 bass_x_9 bass_x_8 default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol bass_x_7 bass_x_6 bass_x_5 bass_x_4 bass_x_3 bass_x_2 bass_x_1 bass_x_0 default 0 0 0 0 0 0 0 0 bit symbol description 15 and 14 - reserved 13 to 0 bass_x_[13:0] resonant bass boost coef?cient x . six 14-bit registers are used as the ?lter coef?cients to specify the bass boost characteristics. the six coef?cients are k1, km, a1, a2, b1 and b2m. a software program is available for users to generate these six 14-bit coef?cients by entering the desired centre frequency, peak gain, sampling frequency and shape factor (default ?at response). bit 15 14 13 12 11 10 9 8 symbol ma_ decl7 ma_ decl6 ma_ decl5 ma_ decl4 ma_ decl3 ma_ decl2 ma_ decl1 ma_ decl0 default 0 0 0 0 0 0 0 0 bit76543210 symbol ma_ decr7 ma_ decr6 ma_ decr5 ma_ decr4 ma_ decr3 ma_ decr2 ma_ decr1 ma_ decr0 default 0 0 0 0 0 0 0 0
2003 apr 10 53 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 58 description of register bits (address 20h) table 59 adc volume control settings table 60 register address 21h bit symbol description 15 to 8 ma_decl[7:0] adc volume setting left channel. value to program the adc gain setting for the left channel. the range is from +24 to - 63 db and - db (see table 59). 7 to 0 ma_decr[7:0] adc volume setting right channel. value to program the adc gain setting for the right channel. the range is from +24 to - 63 db and - db (see table 59). ma_ decl7 ma_ decl6 ma_ decl5 ma_ decl4 ma_ decl3 ma_ decl2 ma_ decl1 ma_ decl0 gain (db) ma_ decr7 ma_ decr6 ma_ decr5 ma_ decr4 ma_ decr3 ma_ decr2 ma_ decr1 ma_ decr0 00110000 +24.0 00101111 +23.5 00101110 +23.0 ::::::::: 00000010 +1.0 00000001 +0.5 000000000 11111111 - 0.5 ::::::::: 10000100 - 62.0 10000011 - 62.5 10000010 - 63.0 10000001 - 63.5 10000000 - bit 15 14 13 12 11 10 9 8 symbol mt_adc --- pga_gain_ ctrll3 pga_gain_ ctrll2 pga_gain_ ctrll1 pga_gain_ ctrll0 default 0 0 0 0 0000 bit76543210 symbol ---- pga_gain_ ctrlr3 pga_gain_ ctrlr2 pga_gain_ ctrlr1 pga_gain_ ctrlr0 default 0 0 0 0 0000
2003 apr 10 54 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 61 description of register bits (address 21h) table 62 adc input amp pga gain settings table 63 register address 22h table 64 description of register bits (address 22h) bit symbol description 15 mt_adc mute adc. if this bit is logic 0 then the adc is not muted; if this bit is logic 1 then the adc is muted. 14 to 12 - reserved 11 to 8 pga_gain_ctrll[3:0] pga gain control left channel. value to program the gain of the left input ampli?er. there are nine settings (see table 62). 7to4 - reserved 3 to 0 pga_gain_ctrlr[3:0] pga gain control right channel. value to program the gain of the right input ampli?er. there are nine settings (see table 62). pga_gain_ ctrll3 pga_gain_ ctrll2 pga_gain_ ctrll1 pga_gain_ ctrll0 gain (db) pga_gain_ ctrlr3 pga_gain_ ctrlr2 pga_gain_ ctrlr1 pga_gain_ ctrlr0 0000 0 0001 3 0010 6 0011 9 0100 12 0101 15 0110 18 0111 21 1000 24 bit 15 14 13 12 11 10 9 8 symbol --- adcpol_inv --- - default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol ------ dc_skip hp_en_dec default 0 0 0 0 0 0 1 1 bit symbol description 15 to 13 - reserved 12 adcpol_inv adc polarity control. if this bit is logic 0 then the adc input is not inverted; if this bit is logic 1 then the adc input is inverted.
2003 apr 10 55 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12.2.4 spdif input settings table 65 register address 30h table 66 description of register bits (address 30h) 11 to 2 - reserved 1 dc_skip dc ?lter skip. if this bit is logic 0 then the dc ?lter is enabled; if this bit is logic 1 then the dc ?lter is disabled. the dc ?lter is at the output of the comb ?lter just before the decimator. this dc ?lter compensates for the dc offset added in the adc (to remove idle tones from the audio band). this dc offset must not be ampli?ed in order to prevent clipping. 0 hp_en_dec high-pass enable. if this bit is logic 0 then the high-pass is disabled; if this bit is logic 1 then the high-pass is enabled. the high-pass is a dc ?lter which is at the output of the decimation ?lter (running at f s ). bit 15 14 13 12 11 10 9 8 symbol ------ - - default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol --- pon_spdi -- slicer_sel1 slicer_sel0 default 0 0 0 1 0 0 0 0 bit symbol description 15 to 5 - reserved 4 pon_spdi power control spdif input. if this bit is logic 0 then the spdif input is switched to power-down mode; if this bit is logic 1 then the spdif input is switched to power-on mode. 3 and 2 - reserved 1 and 0 slicer_sel[1:0] spdif source select. value to select an iec 60958 input channel: 00 = iec 60958 input from pin spdif0 01 = iec 60958 input from pin spdif1 10 = iec 60958 input from pin spdif2 11 = iec 60958 input from pin spdif3 bit symbol description
2003 apr 10 56 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12.2.5 spdif output settings table 67 register address 50h table 68 description of register bits (address 50h) bit 15 14 13 12 11 10 9 8 symbol --- - - - - spdo_ valid default 0 0 0 0 0 0 0 0 bit 7 6 5 4 3 2 1 0 symbol - l_r_copy - pon_spdo dis_spdo spdout_sel2 spdout_sel1 spdout_sel0 default 0 1 0 1 0 1 0 0 bit symbol description 15 to 9 - reserved 8 spdo_valid sdpdif output valid. if this bit is logic 0 then the spdif output is invalid; if this bit is logic 1 then the spdif output is valid. 7 - reserved 6 l_r_copy spdif channel status copy. if this bit is logic 0 then the status bits of the left channel are not copied to the right channel; if this bit is logic 1 then the status bits of the left channel are copied to the right channel. 5 - reserved 4 pon_spdo power control of spdif output. if this bit is logic 0 then the spdif output is switched to power-down mode; if this bit is logic 1 then the spdif output is switched to power-on mode. 3 dis_spdo spdif encoder enable. if this bit is logic 0 then the spdif encoder is enabled; if this bit is logic 1 then the spdif encoder is disabled. 2 to 0 spdout_sel[2:0] spdif output source selector. value to select the input source for spdif output. the selection option to select the spdif input just after the slicer was already there. added is an independent selection of the input signals spdif0 to spdif3: 000 = adc 001 = i 2 s-bus input 010 = not used 011 = interpolator mix output 100 = spdif0 loop through 101 = spdif1 loop through 110 = spdif2 loop through 111 = spdif3 loop through
2003 apr 10 57 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 69 register addresses 51h (left) and 54h (right) table 70 register addresses 52h (left) and 55h (right) table 71 register addresses 53h (left) and 56h (right) table 72 description of register bits bit 15 14 13 12 11 10 9 8 symbol spdo_ bit39 spdo_ bit38 spdo_ bit37 spdo_ bit36 spdo_ bit35 spdo_ bit34 spdo_ bit33 spdo_ bit32 default 00000000 bit76543210 symbol spdo_ bit31 spdo_ bit30 spdo_ bit29 spdo_ bit28 spdo_ bit27 spdo_ bit26 spdo_ bit25 spdo_ bit24 default 00000000 bit 15 14 13 12 11 10 9 8 symbol spdo_ bit23 spdo_ bit22 spdo_ bit21 spdo_ bit20 spdo_ bit19 spdo_ bit18 spdo_ bit17 spdo_ bit16 default 00000000 bit76543210 symbol spdo_ bit15 spdo_ bit14 spdo_ bit13 spdo_ bit12 spdo_ bit11 spdo_ bit10 spdo_ bit9 spdo_ bit8 default 00000000 bit 15 14 13 12 11 10 9 8 symbol -------- default 00000000 bit76543210 symbol spdo_ bit7 spdo_ bit6 spdo_ bit5 spdo_ bit4 spdo_ bit3 spdo_ bit2 spdo_ bit1 spdo_ bit0 default 00000000 bit symbol description 39 to 36 spdo_bit[39:36] reserved 35 to 33 spdo_bit[35:33] word length. value indicating the word length (see table 73). 32 spdo_bit[32] audio sample word length. value to signal the maximum audio sample word length. if bit 32 is logic 0, then the maximum length is 20 bits; if bit 32 is logic 1, then the maximum length is 24 bits (see table 73). 31 to 30 spdo_bit[31:30] reserved
2003 apr 10 58 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 73 word length 29 to 28 spdo_bit[29:28] clock accuracy. value indicating the clock accuracy: 00 = level ii 01 = level i 10 = level iii 11 = reserved 27 to 24 spdo_bit[27:24] sample frequency. value indicating the sampling frequency: 0000 = 44.1 khz 0001 = 48 khz 0010 = 32 khz other states = reserved 23 to 20 spdo_bit[23:20] channel number. value indicating the channel number (see table 74). 19 to 16 spdo_bit[19:16] source number. value indicating the source number (see table 75). 15 to 8 spdo_bit[15:8] general information. value indicating general information (see table 76). 7 to 6 spdo_bit[7:6] mode. value indicating mode 0: 00 = mode 0 other states = reserved 5 to 3 spdo_bit[5:3] audio sampling. value indicating the type of audio sampling (linear pcm). for bit spdo_bit1 = 0: 000 = two audio samples without pre-emphasis 001 = two audio samples with 50/15 m s pre-emphasis 010 = reserved (two audio samples with pre-emphasis) 011 = reserved (two audio samples with pre-emphasis) other states = reserved 2 spdo_bit2 software copyright. value indicating software for which copyright is asserted or not. if this bit is logic 0, then copyright is asserted; if this bit is logic 1, then no copyright is asserted. 1 spdo_bit1 audio sample word. value indicating the type of audio sample word. if this bit is logic 0, then the audio sample word represents linear pcm samples; if this bit is logic 1, then the audio sample word is used for other purposes. 0 spdo_bit0 channel status. value indicating the consumer use of the status block. this bit is logic 0. spdo_bit32 spdo_bit35 spdo_bit34 spdo_bit33 word length 0000 not indicated 000116 bits 001018 bits 0011 reserved 010019 bits 010120 bits 011017 bits 0111 reserved bit symbol description
2003 apr 10 59 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 74 channel number table 75 source number 1000 indicated 100120 bits 101022 bits 1011 reserved 110023 bits 110124 bits 111021 bits 1111 reserved spdo_bit23 spdo_bit22 spdo_bit21 spdo_bit20 channel number 0000 dont care 0001a (left for stereo transmission) 0010b(r ight for stereo transmission) 0011c 0100d 0101e 0110f 0111g 1000h 1001i 1010j 1011k 1100l 1101m 1110n 1111o spdo_bit19 spdo_bit18 spdo_bit17 spdo_bit16 source number 0000 dont care 00011 00102 00113 01004 01015 01106 01117 10008 10019 101010 spdo_bit32 spdo_bit35 spdo_bit34 spdo_bit33 word length
2003 apr 10 60 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 76 general information 12.3 read registers mapping 12.3.1 i nterpolator table 77 register address 18h 101111 110012 110113 111014 111115 spdo_bit[15:8] function 00000 000 general lxxxx 001 laser optical products lxxxx 010 digital-to-digital converters and signal processing products lxxxx 011 magnetic tape or disc based products lxxxx 100 broadcast reception of digitally encoded audio signals with video signals lxxxx 110 broadcast reception of digitally encoded audio signals without video signals lxxxx 101 musical instruments, microphones and other sources without copyright information lxx00 110 analog-to-digital converters for analog signals without copyright information lxx10 110 analog-to-digital converters for analog signals which include copyright information in the form of cp- and l-bit status lxxx1 000 solid state memory based products l1000 000 experimental products not for commercial sale lxxxx 111 reserved lxxx0 000 reserved, except 000 0000 and 000 0001l bit 15 14 13 12 11 10 9 8 symbol -- - - - - - - bit 7 6 5 4 3 2 1 0 symbol - sdetr2 sdetl2 sdetr1 sdetl1 mute_state_m mute_state_ch2 mute_state_ch1 spdo_bit19 spdo_bit18 spdo_bit17 spdo_bit16 source number
2003 apr 10 61 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 78 description of register bits (address 18h) 12.3.2 d ecimator table 79 register address 28h table 80 description of register bits (address 28h) bit symbol description 15 to 7 - reserved 6 sdetr2 silence detector channel 2 right. if this bit is logic 0 then there is no silence detection for the right input of channel 2; if this bit is logic 1 then there is silence detection for the right input of channel 2. 5 sdetl2 silence detector channel 2 left. if this bit is logic 0 then there is no silence detection for the left input of channel 2; if this bit is logic 1 then there is silence detection for the left input of channel 2. 4 sdetr1 silence detector channel 1 right. if this bit is logic 0 then there is no silence detection for the right input of channel 1; if this bit is logic 1 then there is silence detection for the right input of channel 1. 3 sdetl1 silence detector channel 1 left. if this bit is logic 0 then there is no silence detection for the left input of channel 1; if this bit is logic 1 then there is silence detection for the left input of channel 1. 2 mute_state_m mute status interpolator. if this bit is logic 0 then the interpolator is not muted; if this bit is logic 1 then the interpolator is muted. 1 mute_state_ch2 mute status channel 2. if this bit is logic 0 then the interpolator channel 2 is not muted; if this bit is logic 1 then the interpolator channel 2 is muted. 0 mute_state_ch1 mute status channel 1. if this bit is logic 0 then the interpolator channel 1 is not muted; if this bit is logic 1 then the interpolator channel 1 is muted. bit 15 14 13 12 11 10 9 8 symbol ----- - - - bit76543 2 1 0 symbol ----- mt_adc_stat - overflow bit symbol description 15 to 3 - reserved 2 mt_adc_stat mute status decimator. if this bit is logic 0 then the decimator is not muted; if this bit is logic 1 then the decimator is muted. 1 - reserved 0 overflow over?ow decimator. if this bit is logic 0 then there is no over?ow in the decimator (digital level above - 1.16 db.); if this bit is logic 1 then there is an over?ow in the decimator.
2003 apr 10 62 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 12.3.3 spdif input table 81 register address 59h table 82 description of register bits (address 59h) table 83 register address 5ch (left) and 5fh (right); note 1 note 1. see for the description of the spdi bit the corresponding spdo bit description of table 72. table 84 register addresses 5bh (left) and 5eh (right); note 1 note 1. see for the description of the spdi bit the corresponding spdo bit description of table 72. bit 15 14 13 12 11 10 9 8 symbol ------- spdo_status bit7654321 0 symbol ------ b_err spdif_lock bit symbol description 15 to 9 - reserved 8 spdo_status spdif encoder output status. if this bit is logic 0 then the spdif encoder output is enabled; if this bit is logic 1 then the spdif encoder output is disabled. 7to2 - reserved 1 b_err bit error detection. if this bit is logic 0 then there is no biphase error; if this bit is logic 1 then there is a biphase error. 0 spdif_lock spdif lock indicator. if this bit is logic 0 then the spdif decoder block is not in lock; if this bit is logic 1 then the spdif decoder block is in lock. bit 15 14 13 12 11 10 9 8 symbol -------- bit76543210 symbol spdi_ bit39 spdi_ bit38 spdi_ bit37 spdi_ bit36 spdi_ bit35 spdi_ bit34 spdi_ bit33 spdi_ bit32 bit 15 14 13 12 11 10 9 8 symbol spdi_ bit31 spdi_ bit30 spdi_ bit29 spdi_ bit28 spdi_ bit27 spdi_ bit26 spdi_ bit25 spdi_ bit24 bit76543210 symbol spdi_ bit23 spdi_ bit22 spdi_ bit21 spdi_ bit20 spdi_ bit19 spdi_ bit18 spdi_ bit17 spdi_ bit16
2003 apr 10 63 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H table 85 register address 5ah (left) and 5dh (right); see note 1 note 1. see for the description of the spdi bit the corresponding spdo bit description of table 72. 13 limiting values in accordance with the absolute maximum rating system (iec 60134); all voltage referenced to ground. notes 1. all v dd and v ss connections must be made to the same power supply. 2. jedec class 2 compliant. 3. jedec class b compliant. 4. dac operation after short-circuiting cannot be guaranteed. 14 thermal characteristics bit 15 14 13 12 11 10 9 8 symbol spdi_ bit15 spdi_ bit14 spdi_ bit13 spdi_ bit12 spdi_ bit11 spdi_ bit10 spdi_ bit9 spdi_ bit8 bit76543210 symbol spdi_ bit7 spdi_ bit6 spdi_ bit5 spdi_ bit4 spdi_ bit3 spdi_ bit2 spdi_ bit1 spdi_ bit0 symbol parameter conditions min. max. unit v dd supply voltage note 1 2.7 5.0 v t stg storage temperature - 65 +125 c t amb ambient temperature - 40 +85 c v esd electrostatic discharge voltage human body model (hbm); note 2 - 3000 +3000 v machine model (mm); note 3 - 250 +250 v i lu(prot) latch-up protection current t amb = 125 c; v dd = 3.6 v - 100 ma i sc(dac) short-circuit current of dac t amb =0 c;v dd = 3 v; note 4 output short-circuit to v ssa1 - 20 ma output short-circuit to v dda1 - 100 ma symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 70 k/w
2003 apr 10 64 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 15 characteristics v dd = 3.0 v; t amb =25 c; r l =5k w ; all voltages referenced to ground; unless otherwise speci?ed; note 1. symbol parameter conditions min. typ. max. unit supplies v dda1 dac supply voltage 2.7 3.0 3.6 v v dda2 adc supply voltage 2.7 3.0 3.6 v v ddx crystal oscillator and pll supply voltage 2.7 3.0 3.6 v v ddi digital core supply voltage 2.7 3.0 3.6 v v dde digital pad supply voltage 2.7 3.0 3.6 v i dda1 dac supply current f s = 48 khz; power-on - 4.7 - ma f s = 96 khz; power-on - 4.7 - ma f s = 48 khz; power-down - 1.7 -m a f s = 96 khz; power-down - 1.7 -m a i dda2 adc supply current f s = 48 khz; power-on - 10.2 - ma f s = 96 khz; power-on - 10.4 - ma f s = 48 khz; power-down - 0.2 -m a f s = 96 khz; power-down - 0.2 -m a i ddx crystal oscillator and pll supply current f s = 48 khz; power-on - 0.9 - ma f s = 96 khz; power-on - 1.2 - ma i ddi digital core supply current f s = 48 khz; all on - 18.2 - ma f s = 96 khz; all on - 34.7 - ma i dde digital pad supply current f s = 48 khz; all on - 0.5 - ma f s = 96 khz; all on - 0.7 - ma digital input pins v ih high-level input voltage 0.8v dd - v dd + 0.5 v v il low-level input voltage - 0.5 - +0.2v dd v v hys(reset) hysteresis on pin reset - 0.8 - v | i li | input leakage current -- 2 m a c i input capacitance -- 10 pf digital output pins v oh high-level output voltage i oh = - 2 ma 0.85v dd -- v v ol low-level output voltage i ol =2ma -- 0.4 v i l(max) maximum output load (nominal) - 3 - ma r pu pull-up resistance 16 33 78 k w r pd pull-down resistance 16 33 78 k w 3-level input pins v ih high-level input voltage 0.9v dd - v dd v v im mid-level input voltage 0.4v dd - 0.6v dd v v il low-level input voltage 0 - 0.5 v
2003 apr 10 65 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H reference voltage v ref reference voltage on pin ref with respect to v ssa 0.45v dd 0.5v dd 0.55v dd v digital-to-analog converter v o(rms) output voltage (rms value) - 900 - mv d v o output voltage unbalance - 0.1 - db (thd+n)/s total harmonic distortion-plus-noise to signal ratio iec 60958 input; f s = 48 khz at 0 db -- 88 - db at - 20 db -- 75 - db at - 60 db; a-weighted -- 37 - db iec 60958 input; f s = 96 khz at 0 db -- 83 - db at - 60 db; a-weighted -- 37 - db s/n signal-to-noise ratio iec 60958 input; code = 0; a-weighted f s = 48 khz - 98 - db f s = 96 khz - 96 - db a cs channel separation f i = 1 khz tone - 100 - db r l load resistance 3 -- k w c l load capacitance note 2 -- 200 pf r o output resistance - 0.13 3.0 w i o(max) maximum output current (thd + n)/s < 0.1%; r l =5k w - tbf - ma analog-to-digital converter v adcp positive adc reference voltage - v dda2 - v v adcn negative adc reference voltage - 0.0 - v v i (rms) input voltage (rms value) v o = - 1.16 dbfs digital output - 1.0 - v d v i input voltage unbalance - 0.1 - db (thd+n)/s total harmonic distortion-plus-noise to signal ratio f s = 48 khz at 0 db -- 85 - db at - 60 db; a-weighted -- 35 - db f s = 96 khz at 0 db -- 85 - db at - 60 db; a-weighted -- 35 - db s/n signal-to-noise ratio code = 0; a-weighted f s = 48 khz - 97 - db f s = 96 khz - 95 - db a cs channel separation - 100 - db symbol parameter conditions min. typ. max. unit
2003 apr 10 66 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H notes 1. all power supply pins (v dd and v ss ) must be connected to the same external power supply unit. 2. when the dac must drive a higher capacitive load (above 50 pf), then a series resistor of 100 w must be used in order to prevent oscillations in the output. 16 timing characteristics v dd = 2.7 to 3.6 v; t amb = - 20 to +85 c; r l =5k w ; unless otherwise speci?ed. iec 60958 inputs v i(p-p) input voltage (peak-to-peak value) 0.2 0.5 3.3 v r i input resistance - 6 - k w v hys hysteresis voltage - 40 - mv i dd(diff) i dd(dac,input) /i dd(dac,no input) - tbf -- power consumption p tot total power consumption iec 60958 input; f s = 48 khz dac in playback mode - 74 - mw dac in power-down mode - 63 - mw symbol parameter conditions min. typ. max. unit device reset t rst reset time - 250 -m s pll lock time t lock time-to-lock f s = 32 khz - 85.0 - ms f s = 44.1 khz - 63.0 - ms f s = 48 khz - 60.0 - ms f s = 96 khz - 40.0 - ms i 2 s-bus interface (see fig.20) t cy(bck) bit clock period 1 / 128fs -- ms t bckh bit clock high time 30 -- ns t bckl bit clock low time 30 -- ns t r rise time -- 20 ns t f fall time -- 20 ns t su(datai) data input set-up time 10 -- ns t h(datai) data input hold time 10 -- ns t d(datao-bck) data output to bit clock delay -- 30 ns t d(datao-ws) data output to word select delay -- 30 ns t h(datao) data output hold time 0 -- ns t su(ws) word select set-up time 10 -- ns t h(ws) word select hold time 10 -- ns symbol parameter conditions min. typ. max. unit
2003 apr 10 67 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H l3-bus interface (see figs 21 and 22) t r rise time note 1 -- 10 ns/v t f fall time note 1 -- 10 ns/v t cy(clk)l3 l3clock cycle time note 2 500 -- ns t clk(l3)h l3clock high time note 2 250 -- ns t clk(l3)l l3clock low time note 2 250 -- ns t su(l3)a l3mode set-up time in address mode 190 -- ns t h(l3)a l3mode hold time in address mode 190 -- ns t su(l3)d l3mode set-up time in data transfer mode 190 -- ns t h(l3)d l3mode hold time in data transfer mode 190 -- ns t stp(l3) l3mode stop time in data transfer mode 190 -- ns t su(l3)da l3data set-up time in address and data transfer mode 190 -- ns t h(l3)da l3data hold time in address and data transfer mode 30 -- ns t d(l3)r l3data delay time in data transfer mode 0 - 50 ns t dis(l3)r l3data disable time for read data 0 - 50 ns i 2 c-bus interface (see fig.23) f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 --m s t high scl high time 0.6 --m s t r rise time sda and scl note 3 20 + 0.1c b - 300 ns t f fall time sda and scl note 3 20 + 0.1c b - 300 ns t hd;sta hold time start condition note 4 0.6 --m s t su;sta set-up time repeated start 0.6 --m s t su;sto set-up time stop condition 0.6 --m s t buf bus free time between a stop and start condition 1.3 --m s t su;dat data set-up time 100 -- ns symbol parameter conditions min. typ. max. unit
2003 apr 10 68 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H notes 1. in order to prevent digital noise interfering with the l3-bus communication, the rise and fall times should be as small as possible. 2. when the sampling frequency is below 32 khz, the l3clock cycle must be limited to 1 64fs cycle. 3. c b is the total capacitance of one bus line in pf. the maximum capacitive load for each bus line is 400 pf. 4. after this period, the first clock pulse is generated. 5. to be suppressed by the input filter. t hd;dat data hold time 0 --m s t sp pulse width of spikes note 5 0 - 50 ns c l load capacitance for each bus line -- 400 pf symbol parameter conditions min. typ. max. unit handbook, full pagewidth mgs756 ws bck datao datai t f t r t h(ws) t su(ws) t bckh t bckl t cy(bck) t h(datao) t su(datai) t h(datai) t d(datao-bck) t d(datao-ws) fig.20 i 2 s-bus interface timing.
2003 apr 10 69 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H handbook, full pagewidth t h(l3)a t h(l3)da t su(l3)da t cy(clk)(l3) bit 0 l3mode l3clock l3data bit 7 mgl723 t clk(l3)h t clk(l3)l t su(l3)a t su(l3)a t h(l3)a fig.21 l3-bus interface timing for address mode. handbook, full pagewidth t stp(l3) t su(l3)d t h(l3)da t su(l3)da t h(l3)d t cy(clk)l3 bit 0 l3mode l3clock l3data read l3data write bit 7 mbl566 t clk(l3)h t clk(l3)l t d(l3)r t dis(l3)r fig.22 l3-bus interface timing for data transfer mode (write and read).
2003 apr 10 70 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 2003 apr 10 70 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl fig.23 i 2 c-bus interface timing.
2003 apr 10 71 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 17 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 0.25 0.05 1.85 1.65 0.25 0.4 0.2 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 97-08-01 03-02-25 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.1
2003 apr 10 72 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 18 soldering 18.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering can still be used for certain surface mount ics, but it is not suitable for fine pitch smds. in these situations reflow soldering is recommended. 18.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferably be kept: below 220 c for all the bga packages and packages with a thickness 3 2.5mm and packages with a thickness <2.5 mm and a volume 3 350 mm 3 so called thick/large packages below 235 c for packages with a thickness <2.5 mm and a volume <350 mm 3 so called small/thin packages. 18.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 18.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2003 apr 10 73 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 18.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. for more detailed information on the bga packages refer to the (lf)bga application note (an01026); order a copy from your philips semiconductors sales office. 2. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 3. these packages are not suitable for wave soldering. on versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. on versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 5. wave soldering is suitable for lqfp, tqfp and qfp packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. wave soldering is suitable for ssop, tssop, vso and vssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package (1) soldering method wave reflow (2) bga, lbga, lfbga, sqfp, tfbga, vfbga not suitable suitable dhvqfn, hbcc, hbga, hlqfp, hsqfp, hsop, htqfp, htssop, hvqfn, hvson, sms not suitable (3) suitable plcc (4) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (4)(5) suitable ssop, tssop, vso, vssop not recommended (6) suitable
2003 apr 10 74 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 19 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). 20 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 21 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 apr 10 75 philips semiconductors preliminary speci?cation stereo audio codec with spdif interface UDA1355H 22 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands 753503/01/pp 76 date of release: 2003 apr 10 document order number: 9397 750 09925

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