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1 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel fea tures ? sync hro nous sram organized as 2meg words x 32bit ? continuous data transfer (cdt) architecture eliminates wait states between read and write operations ? supports 40mhz to 80mhz bus operations ? internally self-timed output buffer control eliminates the need for synchronous output enable ? registered inputs for flow-thru operations ? single 2.5v to 3.3v supply ? clock-to-output times - clk to q = 12ns ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self-timed writes ? three chip enables (cs0 , cs1, cs2 ) for simple depth expansion ? "zz" sleep mode option for partial power-down ? "shutdown" mode option for deep power-down ? four word burst capability--linear or interleaved ? operational environment - total dose: 100 krad(si) - sel immune: 100mev-cm 2 /mg - seu error rate: 1 x 10 -15 errors/bit-day with internal error correction ? package options: - 288-lead clga, ccga, and cbga ? standard microelectronics drawing (smd) 5962-15214 - qmlq and q+ pending introduction the ut8sf2m32 is a high performance 67,108,864-bit synchronous static random access memory (ssram) device that is organized as 2m words of 32 bits. this device is equipped with thr ee chip selects (cs0 , cs1, and cs2 ), a write enable (we ), and an output enable (oe ) pin, allowing for significant design flexibility without bus contention. the device supports a four word burst function using (adv_ld ). the device achieves a very lo w error rate by employing secded (single error correction double error detection) edac (error detection and correction) scheme during read/ write operations as well as additional autonomous data scrubbing. the data scrubbing is performed in the background and is invisible to the user. all synchronous inputs are registered on the rising edge of the clock provided the clock enable (cen ) input is enabled low. operations are suspended when cen is disabled high and the previous operation is extended. write operation control signals are we and flsh_pipe. all write operations are performed by internal self-timed circuitry. for easy bank selection, three synchronous chip enables (cs0 , cs1, cs2 ) and an asynchronous output enable (oe ) provide for output tri-state control. the output drivers are synchronously tri-stated during the data portion of a write sequence to avoid bus contention. standard products ut8sf2m32 64megabit flow-thru ssram preliminary datasheet www.aeroflex.com/memories april 2015
2 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel figure 1. ut8sf2m32 block diagram main memory array 2meg x 52 housekeeping, scrub and fault logic write data coherency logic write address and command queue user command interface logic addr cmd write data queue check bit generation logic write data steering logic error detections and correction logic read data steering and fault logic stall cycle registers clk d in q out
3 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel table 1: pin definitions name description type cs0 chip enable 0, in put, active low: sampled on the rising edge of clk. used in conjunction with cs1 and cs2 to select or deselect the device. input-synchronous cs1 chip enable 1 input, active high: sampled on the rising edge of clk. used in conjunction with cs0 and cs2 to select or deselect the device. input-synchronous cs2 chip enable 2 input, active low: sampled on the rising edge of clk. used in conjunction with cs0 and cs1 to select or deselect the device. input-synchronous a[20:0] address inputs: sampled at the rising edge of the clk. a[1:0] is fed to the two-bit burst counter. input-synchronous flsh_pipe flush pipeline input, active high: qualified with we to conduct dummy writes to flush pipeline. must be low during normal write operation. input-synchronous we write enable input, active low: sampled on the rising edge of clk if cen is active low. this signal must be enabled low to initiate a write sequence. input-synchronous adv_ld advance/load input: advances the on-chip address counter or loads a new address. when high (and cen is enabled low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after deselection, drive adv_ld low to load a new address. input-synchronous clk clock input: used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. input-clock oe output enable, asynchronous input, active low: combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are en abled to behave as outputs. when disabled high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a wr ite sequence, during the first clock when emerging from a deselected stat e and when the device is deselected. input-asynchronous cen clock enable input, active low: when enabled low, the clock signal is recognized by the ssram. when d easserted high, the clock signal is masked. because deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. input-synchronous dq[51:0] 1 bidirectional data i/os: as inputs, dq[51:0] feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, dq[51:0] delivers the data contained in the memo ry location specified by the addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is enabled low, the pins behave as outputs. when high, dqs are placed in a tri-state condition.the outputs are automatically tri-stated during the da ta portion of a write sequence, during the first clock when emerging from a dese lected state, and when the device is deselected, regardless of the state of oe . aeroflex recommends connecting all dq pins to either v ddq or v ss through a > 10k ? resistor. i/o-synchronous reset reset input, active low: resets device to known configuration. reset is required at initial power-up after exiting shutdown mode, or after any power interruption. input-asynchronous
4 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel name description type zz zz ?sleep? input, active high: when high, places the device in a non- time critical ?sleep? condition with da ta integrity preserved. during normal operation, this pin must be low. input-synchronous shutdown shutdown input, active high : when high, places device in shutdown mode. system clock can be stopped. memory contents are not retained. input-asynchronous ready 2 device ready output: ready outputs a high when device is available for normal operations. ready outputs a low when requesting an idle cycle or during power up initialization. output-synchronous mbe0 mbe1 mbec multiple bit error flags: when low data is valid, when high data is corrupt. users can monitor either mbe0 and mbe1 or mbec (combined). output-synchronous mode 3 mode input: established at power up. selects the burst order of the device. when tied to v ss selects linear burst sequence. when tied to v ddq selects interleaved burst sequence. input-dc edacen edac enable input: edac is enabled when high. when low, allows for simple package pin disable of ed ac. device pin internally connected through a 75k ? 10% resistor to v ddq . input-dc scruben scrub enable input: scrub mode is enabled when high. when low, scrub mode is externally disabled. de vice pin internally connected through 1 75k ? 10% resistor to v ddq . input-dc extres 3 input current reference: provided for external pr ecision current reference resister connection. input-dc v dd power supply inputs to the core of the device. power supply v ddq power supply for the i/o circuitry. i/o power supply v ss ground inputs to the core of the device. ground v ssq ground for i/o circuitry i/o ground table 1: pin definitions
5 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel note: 1. dq[51:32] are ignore during wr ite and tri-stated during read activities unless edacen is deselected. (see read access error correction and detection page 6.) 2. reference application note an-mem-004 for additional ready signal information. 3. dc inputs are established at power up and canno t be switched while power is applied to the device. 4. reference application note an-mem-05 for jtag operations. jtag operations are intended for terrestrial use and not guarantee d in radiation environment. nuil not used input low: pins designated as nuil need to be externally connected by user to v ss q through a > 10k ? 10% resistor. -- nuih not used input high: pins designated as nuih need to be externally connected by user to v ddq through a > 10k ? 10% resistor. -- nc no connects. not internally connected to the die. --- tdo 4 jtag circuit serial data output. p ackage pin requires a pull-up through > 10k ? 10% resistor to v ddq . jtag serial output synchronous tdi 4 jtag circuit serial data input. device pin internally connected through a 75k ? 10% resistor to v ddq . jtag serial input synchronous tms 4 jtag controller test mode select. de vice pin internally connected through a 75k ? 10% resistor to v ddq . test mode select synchronous tck 4 jtag circuit clock input. package pin requires a pull-up through > 10k ? 10% resistor to v ddq . jtag clock
6 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel device operation the u t8sf2m32 is synchronous flow-thru ssram designed specifically to eliminate wait stat es during write/read or read/ write transitions. all synchronous inputs are registered on the rising edge of clock. the clock signal is enabled by the clock enable input (cen ). when cen is high, the clock signal is disregarded and all internal states are maintained. all synchronous operations are qualified by cen . once power-up requirements have been satisfied, the input clock may only be stopped during sleep (zz is high) or shutdown mode (shutdown is high). maximum access delay from the rising edge of clock (t cqv ) is 11.5ns (80mhz device). access is initiated by asserting all three chip enables (cs0 , cs1, cs2 ) active at the rising edge of the clock with clock enable (cen ) and adv_ld asserted low. the address presented to the device will be registered. access can be either a read or write operation, depending on the status of the write enable (we ). write operations are initiate d by the write enable (we ) input. all write commands are controlled by built in synchronous self-timed circuitry. three synchronous chip enables (cs0 , cs1, cs2 ) and an asynchronous output enable (oe ) simplify memory depth expansion. all operations (read s, writes, and deselects) are registered. adv_ld must be driven low once the device has been deselected in order to load a new address and command for the next operation. single read accesses a read access is initiated when the following device inputs are present at rising clock edge: cen is enabled low, cs0 , cs1, and cs2 are all enabled, the write enable input signal we is disabled high and adv_ld is asserted low. the addresses present at the address inputs a[20:0] are registered and presented to the memory. data is available to the bus within 12ns provided oe is enabled low. after the first clock of the read access, the output bu ffers are controlled by oe and the internal control logic. oe must be enabled low to drive requested data. during the next rising clock, any operation (read/write/deselect) may be initiated. burst read accesses the ut8sf2m32 has an internal burst counter allowing up to four reads to be performed from a single address input. a new address can only be loaded when adv_ld is driven low. new addresses are loaded into the ssram, as described by the single read access section. the burst counter operates in either linear or interleave and is controlled by the mode input at power up. when mode pin is low, the burst sequence is linear. the burst sequence is interleaved when mode is high. a0 and a1 are controlled by the burst counter. burst counter will wrap around when needed. the burst counter increments an ytime adv_ld is high and cen is low. the operation selected by the state of we is latched at the beginning of the sequence and maintained throughout. read access error detection and correction the ut8sf2m32 device features an embedded single error correction double error det ection (secded) aeroflex proprietary error correction sc heme. single bit errors are corrected during read accesses. da ta corrections, to the core memory, occurs during a separate data scrubbing activities. double bit errors are detected and indicated by mbe0, mbe1 and mbec. the mbe0 output is the multibit error indictor for the 16 even dqs. the mbe1 ou tput is the multibit error indicator for 16 odd dqs. mbec is the combined ored result of mbe0 and mbe1. either mb ec or mbe0 and mbe1 can be monitored to validate data. if all mbex signals (mbec, mbe0, mbe1) remain low during a data output cycle, the data is valid. if any of the mbe signal pins go active high during a read activity, the data is invalid and contains an uncorrectable multibit error. aeroflex recommends that all dq pins be connected to either v ddq or v ssq through pull up/ down resistors as dq[51:0] must not be left floating. the upper 20 i/o pins dq[51:32] are used for error code data storage, and need to be individually connected to soft pull ups or downs (refer to table 4 ex ternal connections). when the edac is enabled via the edacen pin, the upper 20 data i/os are ignored during write operations and tri-stated during read operations. when the edac is disabled, the upper 20 data i/ os may be written and read the same as dq[31:0]. single write accesses a write access is initiated when the following device inputs are present at rising clock edge: cen is enabled low, cs0 , cs1, and cs2 are all enabled, the write enable input signal we , adv_ld , and flsh_pipe are asserted low. the addresses present at the address inputs a[20:0] are registered and presented to the memory core. data i/os are tri-stated after t cqz is satisfied regardless of the state of oe . during a write operation, data is qualified by the flsh_ pipe input. input data at dq[51:0] is registered when flsh_pipe is low in conjunction with an active we , but ignored when flsh_pipe is high with an active we . in either state of flsh_pipe, commands are shifted through the register pipeline.
7 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel to avoid bus contention data should not be driven to dqs when outputs are active. the output enable (oe ) may be disabled high before applying data to the dq lines. this will tri-state the dq output drivers. as an additional feature dq lines are automatically tri-stated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the ut8sf2m32 has an internal burst counter allowing up to four writes to be performed from a single address input. a new address can only be loaded when adv_ld is driven low. new addresses are loaded into the ssram, as described the single write access section. when adv_ld is driven high where cen is low on the subsequent clock rise, the chip enables (cs0 , cs1, cs2 ) and we inputs are ignored and the burst counter is incremented. the flsh_pipe input must be low in each cycle of the burst write in order to write the correct data. ready status the ut8sf2m32 device operates as a synchronous sram device. data integrity housekeeping activities are performed in the background during normal user activity. these housekeeping activities are performed on a regular basis. however, when a housekeeping activity sequence cannot be completed due to user conflict for memory space, the ready pin asserts signifying to the user that an idle cycle is required. please reference applications note an-mem-004 for more information. data scrubbing the ut8sf2m32 device employs internal autonomous data scrubbing. the scrub circuit cy cles through all address spaces typically once every 0.5 seconds . scrub cycles occur anytime power is applied provided scruben is high. when the edac circuit is disabled via edacen input low, dq[51:32] pins are available for read and write accesses. however if the scruben is not also disabled, data written to dq[51:32] could be changed by the internal data scrubbing activity. flsh_pipe the write operation consists of two register stages. writing data to the core memory requires three subsequent write operations. dummy write operations can be performed using the flsh_pipe inputs. because data coherency is always maintained and the seu error rate includes the pipeline registers, flushing the pi peline is not necessary. s leep mode the zz input lead is a synchronous input. asserting the zz pin high places the ssram into a power conservative "sleep" mode. to assure the completion of previous commands through the pipeline prior to entering sleep mode, a minimum of two full clock cycles (t zzs ) are required between the last operation command and asserting the zz input. while in sleep mode, data integrity is guaranteed. changing the input clock frequency or halting the input clock may be executed during sleep mode. the device must be deselected prior to entering sleep mode and remain deselected for the duration of t zzrec after the zz input returns low. shutdown mode the shutdown input pin is an asynchronous input. asserting shutdown places the device in a power saving shutdown mode. the system clock can be stopped. memory contents are not maintained in shutdown mode. the ssram requires a reset upon exiting shutdown mode. table 2. linear bu rst address table (mode= v ss ) starting address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 table 3. interleaved burst address table (mode=v ddq ) starting address second address third address fourth address a1, a0 a1, a0 a1, a0 a1, a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
8 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel power up/ down requirements the s sram requires that v dd < v ddq at all times. the ssram does require the user to pr ovide an external reset after initial power application, exiting shutdown mode, or any power interruption to the device input voltage outside the specified limit. performing a reset requires the assertion of the /reset device input lead (low) for a minimum of 1us (t rlrh ). after the /reset input is returned high, the device requires 50us (t shtdwnrec ) to complete the reset operation. once the reset operation is complete, the device requires an additional 20us (t cr ) to synchronize the clock input providing a stable input clock is present. the device ready output lead asserts high once t cr is satisfied at the next rising clock. the ready out lead high indicates the device is available for normal operations. for power down it is required that v dd and v ddq be powered down to < 0.5v for a minimum of 100ms. clock conditioning requirements the clk signal input requirements are given in the clock section of the ac characteri zations. ac characterization performances listed herein are based on providing a clock input signal meeting these requirements. changing clock frequencies the clk input frequency should be established at power on, and may only be changed while in sleep mode (reference table 5). external connections a precision 25kohm < + 0.2% low tcr < 25ppm/ o c resistor is required to be connected between device pin extres (r15) and v ss . in order to ensure proper operation in conjunction with jtag boundary (reference applications note mem-an-005) and edac bypass capabilities, aeroflex requires that specific package pins be biased through soft connections to either v dd , v ddq or v ss . table 4 below is a list of these required external biases. notes: 1. nuil = not used input low 2. nuih = not used input high 3. aeroflex recommends connecting all dq[51:0] to either v ddq or v ss through > 10k ? resistors. table 4. external bias conditions signal name package pin bias condition nuil 1 p13, r7, r8, r12, r13, r14, r16 > 10k? to v ssq nuih 2 p16 > 10k ? to v ddq tdo r5 > 10k ? to v ddq tck r9 > 10k ? to v ssq dq[51:0] 4 ref table 6 > 10k ? to v ddq orv ssq
9 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel notes: * all chip selects active when l, at least one chip select inactive when h 1. x = ?don't care?, h = logic high, l = logic low 2. write is defined by we and flsh_pipe. 3. when a write cycle is dete cted, all i/os are tri-stated. 4. the dq pins are controlled by the current cycle and the oe signal. 5. cen = h inserts wait states. 6. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dq s = tri-state when oe is inactive or when the de vice is deselected and dq s = data when oe is active. table 6. 288-lead flow-thru signal locations table 5: truth ta ble for ut8sf2m32 [1,2,3,4,5,6,7] operation address used csx* zz shut down adv_ld we flsh_ pipe oe cen clk dqs standby mode none h l l l x x x l l-h 3-state continue deselect none x l l h x x x l l-h 3-state read cycle (start burst) external l l l l h x l l l-h data out read cycle (cont. burst) next x l l h x x l l l-h data out nop/dummy read (start) external l l l l h x h l l-h 3-state nop/dummy read (cont.) next x l l h x x h l l-h 3-state write cycle (start burst) external l l l l l l x l l-h data in write cycle (cont. burst) next x l l h x l x l l-h data in dummy write (start) none l l l l l h x l l-h 3-state dummy write (cont. burst) next x l l h x h x l l-h 3-state clock inhibit (stall) n/a x l l x x x x h l-h n/a sleep mode n/a h h l x x x x x x 3-state shutdown mode none x x h x x x x x x 3-state
10 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel notes: 1. pin requires pull-up to v ddq of > 10k ? 10% . 2. pin requires pull-down to v ss of > 10k ? 10% . 3. nuil = not used input low. nuil pins requires > 10k ? 10% pull-down to v ssq . 4. nuih = not used input high. nuih pins requires > 10k ? + 10% pull-up to v ddq . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a vddq cs2 we vss a10 a8 a4 a18 a19 a14 a15 a2 a0 cs0 vss vss b vss vss oe vss a11 a9 a6 a17 vss a20 a16 a13 a12 a1 zz vss shut down vss c vddq vssq vss ready flsh_ pipe vss a7 a5 vss vdd vss vssq vdd vdd a3 adv_ld cs1 vss vssq vdd d dq33 dq35 vdd vss vss vddq vssq vdd vdd vss vdd vdd vssq vddq vdd vss vss vdd vddq dq32 e dq37 dq1 dq39 vdd vssq vss vssq vddq vss vss vss vssq vddq vss vss vssq vdd dq38 dq36 dq34 f dq3 dq5 dq7 vddq vddq vssq vss vss vdd vss vdd vss vss vddq vssq vddq vddq dq4 dq0 dq2 g dq9 dq11 dq13 vdd vssq vdd vddq vdd vss vdd vss vdd vddq vssq vdd vssq vdd dq10 dq6 dq8 h mbe1 dq15 cen vss vss vdd vdd vdd vss vss vss vdd vdd vss vss vss vss clk dq12 mbe0 j dq19 dq17 dq21 vdd vssq vdd vss vdd vss vdd vss vdd vss vssq vdd vssq vdd dq14 dq16 dq18 k dq27 dq25 dq23 vddq vddq vssq vss vddq vdd vss vdd vddq vss vddq vssq vddq vddq dq20 dq24 dq22 l dq31 dq41 dq29 vdd vssq vss vssq vddq vss vss vss vssq vddq vss vss vssq vdd dq26 dq30 dq28 m dq45 dq47 dq43 vdd vss vssq vddq vssq vdd vss vdd vdd vssq vddq vssq vss vdd dq40 dq44 dq42 n dq51 dq49 vss vss vdd vddq vssq vdd vss vdd vss vss vdd vssq vssq vdd vss dq46 dq48 dq50 p vss vss vdd scrub en vssq vssq vssq vss vss vddq mode nuil 3 edacen tms nuih 4 vssq vss vss r vdd tdi tdo 1 vdd nuil 3 nuil 3 tck 2 mbec reset nuil 3 nuil 3 nuil 3 extres nuil 3 vddq vdd
11 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel absolute maximum ratings 1 (referenced to v ss ) notes: 1. permanent device damage may occur if ab solute maximum ratings are ex ceeded. functional operation shou ld be restricted to rec ommended operating conditions. 2. all voltages are referenced to v ss . 3. per mil-std-883, method 1012, section 3.4.1 p d = (t j (max) - t c (max)) operational environments 1 notes: 1. adams 90% worst case environment, geosynchronous orbit, 100mils of aluminum 2. temperature = 105 o c; v dd and v ddq = 3.6v recommended operating conditions symbol parameter va l u e unit v dd /v ddq supply voltage 2 -0.5 to 4.0 v v in voltage on any pin 2 -0.3 to v ddq +0.3 v i io dc i/o current per pin @ t j = 135 o for 15 years + 10 ma p d package power dissipation permitted @ t c = 105c 3 15 w t j maximum junction temperature +150 o c jc thermal resistance junction to case 3 o c/w t stg storage temperature -65 to +150 o c parameter limit units total ionizing dose (tid) 100k rad(si) heavy ion error rate 1x10 -15 errors/bit-day single event latchup (sel) immune 2 100 mev-cm 2 /mg symbol parameter limits v dd core supply voltage 2.3v to v ddq v ddq i/o power supply voltage 2.3v to 3.6v t c case temperature range -55 c to +105 c v in dc input voltage 0v to v ddq t j junction temperature -55 c to +125 c jc
12 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel dc electrical charac teri s tics (pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v; unless otherwise noted, tc is per the temperature range ordered ) parameter description condition min max unit v dd core power supply vo l t a g e 2.3 v ddq v v ddq i/o power supply voltage 2.3 3.6 v v oh output high voltage for 3.0v i/o, i oh =-4ma 0.8 * v ddq v for 2.3v i/o, i oh =-1ma 2.0 v v ol output low voltage for 3.0v i/o, i ol =8ma 0.4 v for 2.3v i/o, i ol =1ma 0.4 v v ih input high voltage for 3.0v i/o 2.0 v for 2.3v i/o 1.7 v v il input low voltage for 3.0v i/o 0.8 v for 2.3v i/o 0.7 v i in1 input leakage current v in = v ddq and v ss except device pins edacen, scruben, tdi, tms -2 2 a i in2 input leakage current v in = v ddq device pins edacen, scruben, tdi, tms 2 a v in = v ss device pins edacen, scruben, tdi, tms -100 a i oz three-state output leakage current v dd , v ddq = (max), v o = v ddq and v ss, oe = v ddq (max) -2 2 a i os 1,2 short-circuit output current v dd , v ddq = (max), v o = v ddq and v ss -100 100 ma i dd 3 v dd supply current in active mode v dd , v ddq = (max), i out = 0ma, f = f max 105 o c 700 ma -55 o c and 25 o c 600 ma i ddq 3 v ddq supply current in active mode v dd , v ddq = (max) i out = 0ma, f = f max 105 o c 60 ma -55 o c and 25 o c 60 ma i shtdwn 3 v dd supply current in shutdown mode v dd , v ddq = (max), v in > v ih or v in < v il , shutdown > v ih 105 o c 250 ma -55 o c and 25 o c 200 ma
13 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel capacitance notes: * for devices procured with a total ionizing dose tolerance gu arantee, the post-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maxi mum tid level procured. 1. supplied as a design limit but not guaranteed nor tested. 2. not more than one output may be shorted at a time for maximum duration of one second. 3. post-irradiation limits are the 105 o c limits when specified. 4. measured only for initial qualificatio n and after process or design change s that could affect this parameter. i shtdwnq 3 v ddq supply current in shutdown mode v dd , v ddq = (max), v in > v ih or v in < v il , shutdown > v ih 105 o c 15 ma -55 o c and 25 o c 15 ma i stby 3 v dd supply current in standby mode v dd , v ddq = (max) v in > v ih or v in < v il , f = fmax, device deselected 105 o c 550 ma -55 o c and 25 o c 400 ma i stbyq 3 v ddq supply current in standby mode v dd , v ddq = (max) v in > v ih or v in < v il , f = fmax, device deselected 105 o c 60 ma -55 o c and 25 o c 60 ma i zz 3 v dd supply current in sleep mode v dd , v ddq = (max), v in > v ih or v in < v il , zz > v ih , shutdown < v il 105 o c 500 ma -55 o c and 25 o c 350 ma i zzq 3 v ddq supply current in sleep mode v dd , v ddq = (max), v in > v ih or v in < v il , zz > v ih , shutdown < v il 105 o c 55 ma -55 o c and 25 o c 55 ma symbol parameter min max unit c in 4 input capacitance 15 pf c i/o 4 i/o capacitance 15 pf
14 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel ac characteristics (pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v; unless otherwise noted, tc is per the temperature range ordered.) 1 parameter description min max unit t powerup 2 v dd to first valid command (read or write) 100 ms clock t cyc clock (clk) cycle time 12.5 25.0 ns t ch clk high time 0.4 * t cyc 0.6 * t cyc ns t cl clk low time 0.4 * t cyc 0.6 * t cyc ns t r, t f 2 input clock rise/fall time (10-90%) 2.25 v/ns t clkpj 3,5 input clock period jitter -100 100 ps t clkccj 3,5 input clock cycle to cycle jitter 150 ps setup times t as address setup time prior to clk 2.5 ns t ds data setup time prior to clk 1.5 ns t cens clock enable (cen ) setup time prior to clk 3 ns t wes write enable (we ) setup time prior to clk 3 ns t advlds advance load (adv_ld ) setup time prior to clk 2.5 ns t css chip select (csx) setup time prior to clk 3 ns hold times t ah address hold time after clk 1.2 ns t dh data hold time after clk 1.4 ns t cenh cen hold time after clk 1.2 ns t weh we hold time after clk 1.5 ns t advldh adv_ld hold time after clk 0.9 ns t csh csx hold time after clk 1.8 ns output times t cqv 4 data valid after rising clk 12 ns t oeqv 4 output enable (oe ) active to data valid 4.0 ns t cqoh data output hold time after rising clk 3.0 ns t cqz 5 rising clk to output three-state time 5.0 ns t cqx 5 rising clk to output enable time 1.3 ns
15 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel notes: * for devices procured with a total ionizing dose tolerance gu arantee, the post-irradiation pe rformance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured 1. ac characteristics based on comp liance with clock in put specifications 2. supplied as a design guidelin e, not tested or guaranteed. 3. period and cycle to cycle jitter is defined by jedec standard 65b 4. maximum data output valid times guaranteed up to 25pf load capacitance. for loads >25pf, a derating factor of parameter = [s pecification max(ns) + (c load - 25pf)(44.2ps/pf]. 5. guranteed by design. t oeqz 5 oe inactive to output three-state time 4.5 ns t oeqx 5 oe active to output enable time 0 ns t cmv1 4 multiple bit error (mbe0/mbe1) valid after rising clk 12 ns t cmv2 4 multiple bit error (mbec) valid after rising clk 13 ns t oemv1 4 oe active to mbe0/mbe1 valid 4.0 ns t oemv2 4 oe active to mbec valid 4.5 ns t cmz1 5 rising clk to mbe0/mbe 1 three-state time 4.5 ns t cmz2 5 rising clk to mbec three-state time 4.5 ns t cmx1 5 rising clk to mbe0/mbe1 enable time 1.4 ns t cmx2 5 rising clk to mbec enable time 1.4 ns t oemz1 5 oe inactive to mbe0/mbe 1 three-state time 4.5 ns t oemz2 5 oe inactive to mbec three-state time 5.5 ns t oemx1 5 oe active to mbe0/mbe1 enable time 0 ns t oemx2 5 oe active to mbec enable time 0 ns
16 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel shutdown and sleep mode characteris tics ( pre and post-radiation)* (v dd = 2.3v to v ddq , v ddq = 2.3 to 3.6v; unless otherwise noted t c is for temperature range ordered.) notes: * for devices procured with a total ionizing dose tolerance guarantee, the po st-irradiation performance is guaranteed at 25 o c per mil-std-883 method 1019, condition a up to the maximum tid level procured 1. the clock must start up prior to exiting sleep or shutdown modes. parameter is guaranteed by design. 2. t cr is necessary anytime the clock is stopped, af ter initial power on, or exiting shutdown mode. 3. tested functionally. 4. guaranteed by design. parameter description condition min max unit t zzs 3 device operation to sleep mode ? > v ih 1 t cyc ns t zzh 3 sleep high pulse width ? > v ih 100 s t zzl 3 sleep low pulse width ? < v ih 100 s t shtdwns 3 device operation to shutdown shutdown > v ih 2 t cyc ns t zzrec 3 sleep recovery time standby < v il 100 + (3*t cyc ) ns t shtdwnrec 1,3 shutdown recovery time shutdown < v il 50 s t zzi 4 active to sleep current ? > v ih 100 + (3*t cyc ) ns t shtdwni 4 active to shutdown current shutdown > v ih 250 ns t rzzi 4 time to exit sleep current mode standby < v ilnotes 0n s t rshtdwni 4 time to exit shudown current mode shutdown < v il 0n s t cr 1,2,3 clock recovery prior to exiting zz ? > v ih 20 s t rlrh reset low to high time shutdown < v il 1 s t pds 3 sleep setup time prior to clk 2.0 ns t pdh 3 sleep hold time after clk 0.5 ns
17 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel figure 3. switching waveform for internal housekeeping figure 4. switching waveform for sleep mode figure 5. switching wave form for shutdown mode figure 6. switching w aveform for power-up clk zz rd / wr rd / wr rd / wr deselect cycle t zzs t zzi t pdh t pds t zzh t cr t zzl t rzzi t zzrec command bus clk rd/ wr rd/ wr deselect cycle t shtdwns t shtdwni t rshtdwni t shtdwnrec t rlrh t cr reset command bus s hutdown clk shutdown rd/ wr rd/ wr deselect cycle power-up t rlrh t shtdwnrec t cr ready reset command bus clk t cl t ch t cyc 64 th non- idle cycle 65 th non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle non - idle cycle idle cycle any cycle any cycle command bus ready t cqv t cqv any cycle 16 cycles max
18 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel figure 7. switching waveforms for flow-thru cycle operations clk /cen addr /we s 0 , /cs2 ( 1 ) adv/ ldb /oe qout a 0 a 0 q(a 0 ) d(a 0 ) d(a 2 ) din a 1 a 2 d(a 0+1 ) flsh_pipe q(a 1 ) q(a 0 ) t cl t ch t cens t cenh t css t csh t as t ah t ds t dh t cqx t cqz t oeqv t wes t weh t advlds t advldh 12 34 5 6789101112 a 0 a 2 a 3 t cyc q(a 2 ) q(a 0 ) 13 d(a 3 ) mbe0 mbe1 mbec q( a 0 ) q( a 1 ) q( a 0 ) t oemv1,2 q( a 2 ) q( a 0 ) t oeqx t oemx1,2 t cmz1,2 t cmx1,2 t cqv t cmv1,2 t oemz1,2 t oeqz t cqoh read q(a 0 ) write d(a 0 ) burst write d(a 0+1 ) stall cycle read q(a 1 ) read q (a 0 ) stall cycle stall cycle write d(a 2 ) read q(a 2 ) stall cycle write d(a 3 ) c hip level command de- select cycle notes: 1. cs1 has timing transistions identical to /cs0 and /cs2 but is inverted logically. for example, when /cs0 and /cs2 are low cs1 is high.
19 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel v dd dut zo = 50ohm v dd c l = 40pf r term 100ohm test point r term 100ohm 90% cmos input pulses 10% > 2.25v/ns v ss v dd2 10% 90% > 2.25v/ns figure 8. ac test loads and input waveforms notes: 1. measurement of data output occurs at the low to high or high to low transition mid- point (i.e., cmos input = v dd2 /2
20 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel packaging figur e 9. 288-lead ccga
21 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel packaging figure 10. 288-lead clga
22 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel packaging figure 11. advanced 288-lead cbga, ball dimensions (a, a1 , a2) are subject to change
23 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel ordering information 2 m x 32 ssram package option associated lead finish option (z) 288-clga (c) gold (s) 288-ccga (a) hot solder dipped (c) 288-cbga (a) hot solder dipped ut ******* - * lead finish: (note 1) (c) = gold (a) = solder screening: (notes 2, 3) (f) = hirel flow (temperature range: -55 c to +105 c) (in development, contact factory) (p) = prototype flow (temperature range: 25 o c only) package type: (z) = 288-lead ceramic land grid array (clga) (s) = 288-lead ceramic column grid array (ccga) (c) = 288-lead ceramic ball grid array (cbga) access time: (m) = 80mhz maximum frequency device type: (8sf2m32) = 2mbit x 32 ssram device notes: 1. lead finish per the table below. 2. prototype flow per aeroflex manufacturing flows document. devices are tested at 25 o c only. radiation is neither tested nor guaranteed. 3. hirel flow per aeroflex manufacturing flows docu ment. radiation is neither tested nor guaranteed. * * *
24 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel 2m x 32 ssram: smd lead finish: (note 1) (c) = gold (f) = solder case outline: (x) = 288-lead ceramic land grid array (clga) (f) = 288-lead ceramic co lumn grid array (ccga) class designator: (q) = qml class q (in development, contact factory) device type: (note 2) (01) = fmax = 80mhz, qml q only (temperature range: -55 c to +105 c) (02) = fmax = 80mhz aeroflex q+ flow (temperature range -55 c to +105 c) drawing number: (15214) = 2m x 32 ssram total dose: (r) = 100 krad(si) federal stock class designator: no options notes: 1. lead finish per the table below. 2. aeroflex?s q+ assembly flow, as define d in section 4.2.2.d of the smd, provides qml-q product through the smd that is manufa ctured with aeroflex?s qml-v flow. 5962 * ***** ** *** package option associated lead finish option (x) 288-clga (c) gold (f) 288-ccga (f) hot solder dipped
25 www.aeroflex.com/hirel info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services described herein at any time without notice. consult aeroflex or an authorized sales representa tive to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, ex cept as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a product or service fro m aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties. this product is controlled for export under the u.s. department of commerce (doc). a license may be required prior to the export of this produc t from the united states. aeroflex colorado springs - datasheet definition advanced datasheet - product in development preliminary datasheet - shipping prototype datasheet - shipping qml & reduced hi-rel
26 36-00-01-006 ver. 1.9.4 aeroflex microelectronics solutions - hirel data sheet revision history revision date description of change page(s) author 9/16/13 release of preliminary data sheet all mjl 10/1/13 page 3: dq[51:0] added aerofl ex pull-up/down recommendation page 8: table 4 revised page 9: corrected csx state for sleep mode from x to h as noted mjl 11/4/13 page 3: added manual reset pin to table 1. page 10: pull-up/down requ irements changed from 75k ? to 10k ? r17 bias from v ssq to v ddq p16 from v ssq to nuih p11 bias from v 44 to v ddq p6 from nuil to v ssq r11 from v ddq to reset page 16: shutdown and sleep mode characterization table revised: t shtdwnrec corrected from 100ms max to 50us min t cr corrected from 10us to 20us max page 17: corrected figures 4-6 as noted mjl 1/10/14 page 8: added ssram requires v dd < v ddq . clarified clock conditioning paragraph. page 12, 14, 16: added v ddq voltage range to top of tables. page 12: changed iddq specification for al l modes. adjusted cu rrent specifications. page 13: added note 3 for 105 o c post-irradiation specifications. page 15: changed note 5 to guaranteed by design and added note reference to all x and z specifications. page 23, 24: corrected pin count for clga to 288 and corrected package designators to (z) (s). as noted mjl 1/23/14 page 1: edits to features bullets 2,3,5 and 13 as noted mjl 4/24/14 page 1: seu changed to 1x10 -15 page 6, 7: multiple wording typo corrections page 11: jc changed to 3 o c/w page 13: cin and ci/o change to 15pf. page 14,1 5: standardized signal names in descriptions and added note numbers to some parameters. reworded note 4. page 16: added notes 3 and 4. page 17: added shutdown to signal in figure 5. page 22: added advanced to figure 11 title. as noted mjl 8/19/14 page 12: added iddq parameters for stby, shutdown, and sleep modes. finalized all current limits per char acterization data. page 14, 15: finalized ac setup, hold, and output limits per characterization data. as noted mjl
27 36-00-01-006 ver. 1.9.4 aeroflex microe lectroni cs solutions - hirel 10/2/2014 page 11: added operational environment table. page 12: added i in paramter for edacen, tdi, and tms pins. dc electrical characteristics table page 16: corrected min t cyc in shutdown and sleep mode characteristics table page 23 and 24: updated smd and ordering info sections. as noted mjl 3/18/2015 ver. 1.8.0 page 1: clock-to-ouput time changed from 11.5ns to 12ns. added smd designator. page 8: added pinout r7 and r8 to table 4. page 10: changed pinout r7 and r8 from vss to nuil page 11: changed p d from 10 w to 15 w page 12: scruben device pin added to condition column of parameters i in1 and i in2 in the dc electrical characteristics table page 14: the minimum se tup times for parameters t cens, t wes, and t css have changed from 2.5ns to 3ns, and the maximum output time for t cqv and t cmv1 changed from 11.5ns to 12ns and t cmv2 changed from 12.5ns to 13ns in the ac electrical characteristics table. page 16: minimum number of t cyc changed from 1 t cyc to 2 t cyc for t shtdwns parameter in the shutdown an d sleep mode characteristics table pages 20 and 21: corrected bottom vi ew orientation of package diagram. page 24: a correction the lead finish sectio n of the smd ordering encoder page. the solder lead finish designator was ch anged from "a" to "f". added smd designator april 2015 ver. 1.9.4 page 8: added pinout r13, r14, and r16 to table 4. page 10: changed pinout r13, r14, and r16 from vss to nuil, and p8 from vss to vssq

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