a1 revisions 0 plc 1 plc 2 plc 3 plc 4 plc angles of scale sheet rev name size cage code drawing no dimensions: tolerances unless otherwise specified: dwn chk apvd material finish product spec application spec weight p ltr date apvd dwn description 5 6 7 8 3 4 2 1 d b a a b c c d all rights reserved. released for publication c copyright this drawing is unpublished. 4805 (3/13) restricted to this drawing is a controlled document. te connectivity -x- -y- 1.5 1 2 3 4 5 6 8 customer drawing 1469081 s.magaro 13may2002 n.schroll 13may2002 r.patterson 16may2007 8:1 1 1 f - - - - see mm - - - - - 1$ receptacle assembly, 3 pair, 25mm, hmzd - - 2002 - table 2002 00779 by - e revised per eco-14-005095 11apr2014 ap rp f revised per eco-16-008845 27sep2016 ap rp 24.95 max ref 12.18 16.85 0.08 ref 3.68 ref 8.7 ref 2 ref typ 1.5 10.70 0.16 11.17 0.05 ref 23.4 ref typ 2.5 ref typ 3 ref 0.75 14.85 0.08 12.70 0.14 ref typ 1.5 termination area 2.20 ref typ 1.5 1.00 0.10 2.5 9 x 2.5 = 22.5 1.50 0.20 bsc bsc all plated thru holes typ typ 6 6 part number finish 1469081-1 1469081-2 reference application spec 114-13059 for recommended plated thru hole diameter and plating thicknesses. material: shield - phosphor bronze contact - copper-nickel-silicon housing, chicklet and chicklet cover - glass filled polyester, ul 94v-o rated. finish: signal and ground contacts: mating area: meets the performance requirements of product specification 108-2055; based on telcordia gr-1217-core, applications in uncontrolled environments compliant pin area: 0.5m min bright tin-lead over base plating connector marked with part number and date code in approximate area shown. dimension applies to centerline of thru hole datums and basic dimensions established by customer 7. contact area lubricated with bellcore approved lubricant. technical referance: gr-1217-core, issue 1, november 1995. finish: contact and shield mating area - 1.27m min gold over 1.27m min nickel compliant pin area - 0.05m min bright tin-lead over 1.27m min nikcel row a row b row c row d row e row f row fg (ground) row f row e row dg (ground) row d row c row bg (ground) row b row a top surface of daughter card 1 5 6 10 row a row b row bg (ground) row c row d row dg (ground) row e row f row fg (ground) recommended pc board layout, daughter board, component side shown scale 4:1 row fg (ground) row f row e row dg (ground) row d row c row bg (ground) row b row a typ 6 6 typ 4 5 6 6 1 2 3 8 6 6 5 1
|
