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i ntegrated c ircuits d ivision ds-ix2113-r03 www.ixysic.com 1 driver characteristics features ? floating channel for bootst rap operation to +600v with absolute maximum rating of +700v ? outputs capable of sourcing and sinking 2a ? gate drive supply range from 10v to 20v ? enhanced robustness due to soi process ? tolerant to negative voltage transients: dv/dt immune ? 3.3v logic compatible ? undervoltage lockout for both high-side and low-side outputs ? matched propagation delays description the ix2113 is a high voltage integrated circuit that can drive high speed mosfets and igbts that operate at up to +600v. the ix2113 is configured with independent high-side and low-side referenced output channels, both of which can source and sink 2a. the floating high-side channel can drive an n-channel power mosfet or igbt 600v from the common reference. manufactured on ixys integrated circuits division's proprietary high-voltage bcdmos on soi (silicon on insulator) process, the ix2113 is extremely robust, and is virtually immune to negative transients. the uvlo circuit prevents the turn-on of the mosfet or igbt until there is sufficient v bs or v cc supply voltage. propagation delays are matched for use in high frequency applications. the ix2113 is available in a 14-pin dip package and in a 16-pin soic package. ordering information ix2113 functional block diagram parameter rating units v offset 600 v i o +/- (source/sink) 2/2 a v out 10-20 v t on /t off 113/100 ns delay matching (max) 20 ns part description ix2113g 14-pin dip (25/tube) IX2113B 16-pin soic (50/tube) IX2113Btr 16-pin soic (1000/reel) level shift v dd / v cc v ss / com ls delay control level shift v dd / v cc v ss / com uvlo high voltage level shift uvlo pulse generator r r s q buffer v dd hin sd lin v ss v b ho v s v cc lo com input control logic & cycle-by-cycle edge-triggered shutdown buffer ix2113 600v high and low side gate driver
i ntegrated c ircuits d ivision ix2113 2 www.ixysic.com r03 1. specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 package pino u t: 16-pin soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 pin description: 16-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 package pino u t: 14-pin dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 pin description: 14-pin dip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.5 a b sol u te maxim u m ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.7 dynamic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.8 static electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.9 test wa v eforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. typical performance data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3. manufacturing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 moist u re sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 esd sensiti v ity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 reflo w profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.4 board wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 mechanical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 3 1 specifications 1.1 package pinout: 16-pin soic package 1.2 pin description: 16-pin soic package 1.3 package pinout: 14-pin dip package 1.4 pin description: 14-pin dip package pin# name description 1lo low-side gate drive output 2com low-side return 3 v cc low-side supply 4- no connection 5- no connection 6 v s high-side floating supply return 7 v b high-side floating supply 8ho high-side gate drive output 9- no connection 10 - no connection 11 v dd logic supply 12 hi n logic input for high-side gate driver output (ho), in-phase 13 sd logic input for shutdown 14 li n logic input for low-side gate driver output (lo), in-phase 15 v ss logic ground 16 - no connection lo - 1 ho - 8 com - 2 v cc - 3 v s - 6 v b - 7 4 5 16 9 15 - v ss 14 - lin 11 - v dd 10 13 - sd 12 - hin pin# name description 1lo low-side gate drive output 2com low-side return 3 v cc low-side supply 4- no connection 5 v s high-side floating supply return 6 v b high-side floating supply 7ho high-side gate drive output 8- no connection 9 v dd logic supply 10 hi n logic input for high-side gate driver output (ho), in-phase 11 sd logic input for shutdown 12 li n logic input for low-side gate driver output (lo), in-phase 13 v ss logic ground 14 - no connection lo - 1 ho - 7 com - 2 v cc - 3 v s - 5 v b - 6 4 14 8 13 - v ss 12 - lin 10 - hin 9 - v dd 11 - sd
i ntegrated c ircuits d ivision 4 www.ixysic.com r03 ix2113 1.5 absolute maximum ratings absolute maximum ratings indicate sustained limits be yond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings are measured under board-mounted and still-air conditions. 1.6 recommended operating conditions for proper operation, the device should be used within the recommended conditions. the v s and v ss offset ratings are tested with all supplies biased at a 15v differential. parameter symbol min max units high-side floating s u pply v oltage v b -0.3 700 v high-side floating s u pply offset v oltage v s v b -20 v b +0.3 v high-side floating o u tp u t v oltage v ho v s -0.3 v b +0.3 v lo w -side fixed s u pply v oltage v cc -0.3 20 v lo w -side o u tp u t v oltage v lo -0.3 v cc +0.3 v logic s u pply v oltage v dd -0.3 v ss +20 v logic s u pply offset v oltage v ss v cc -20 v cc +0.3 v logic inp u t v oltage (hi n , li n , sd) v i n v ss -0.3 v dd +0.3 v allo w a b le offset s u pply v oltage transient d v s /dt -5 0v / n s package po w er dissipation @ t a ? 25c 16-pin soic pd -1.25 w 14-pin dip 1.6 thermal resistance, j u nction to am b ient 16-pin soic r ? ja -1 00 c/w 14-pin dip 75 j u nction temperat u re t j -1 50c storage temperat u re t s -55 150 c lead temperat u re (soldering, 10 seconds) t l -3 00c parameter symbol min max units high-side floating s u pply a b sol u te v oltage v b v s +10 v s +20 v high-side floating s u pply offset v oltage v s -6 00 high-side floating o u tp u t v oltage v ho v s v b lo w -side fixed s u pply v oltage v cc 10 20 lo w -side o u tp u t v oltage v lo 0 v cc logic s u pply v oltage v dd v ss +3 v ss +20 logic s u pply offset v oltage v ss -5 5 logic inp u t v oltage (hi n , li n , sd) v i n v ss v dd am b ient temperat u re t a -40 +125 c
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 5 1.7 dynamic electrical characteristics v bias (v cc , v bs , v dd )=15v, cl=1000 pf, t a =25c, and v ss =com unless otherwise specified. 1. 8 static electrical characteristics v bias (v cc , v bs , v dd )=15v, t a =25c and v ss =com unless otherwise specified. the v in , v th , and i in parameters are referenced to v ss and are applicable to all three logic input leads: hin, lin, and sd. the v o and i o parameters are referenced to com and are applicable to the respective output leads: ho or lo. parameter conditions symbol min typ max units t u rn-on propagation delay v s =0 v t on -113160 ns t u rn-off propagation delay v s =600 v t off -100150 sh u tdo w n propagation delay t sd -94160 t u rn-on rise time - t r -9.435 t u rn-off fall time - t f -9.725 delay matching, hs & ls t u rn-on/off - mt - - 20 parameter conditions symbol min typ max units logic ?1? inp u t v oltage v dd =15 v v ih 9.5 - - v logic ?0? inp u t v oltage v il --6 logic ?1? inp u t v oltage v dd =3 v v ih 2.5 - - v logic ?0? inp u t v oltage v il --0.8 high-le v el o u tp u t v oltage, v bias - v o i o =0a v oh -1.62.5 v lo w -le v el o u tp u t v oltage, v o i o =20ma v ol - - 0.15 offset s u pply leakage c u rrent v b = v s =600 v i lk --60 ? a q u iescent v bs s u pply c u rrent v i n =0 v or v dd i qbs -187310 q u iescent v cc s u pply c u rrent v i n =0 v or v dd i qcc -300420 q u iescent v dd s u pply c u rrent v i n =0 v or v dd i qdd --1 logic ?1? inp u t bias c u rrent v i n = v dd i in+ -2240 ? a logic ?0? inp u t bias c u rrent v i n =0 v i in- --5 v bb s u pply under v oltage positi v e going threshold - v bsuv+ 7.5 8.4 9.7 v v bb s u pply under v oltage n egati v e going threshold - v bsuv- 77.89.4 v cc s u pply under v oltage positi v e going threshold - v ccuv+ 7.4 8.4 9.6 v cc s u pply under v oltage n egati v e going threshold - v ccuv- 77.89.4 o u tp u t high short circ u it p u lsed c u rrent v o =0 v , v i n = v dd , pw ? 10 ? s i o+ 22.5 - a o u tp u t lo w short circ u it p u lsed c u rrent v o =15 v , v i n =0 v , pw ? 10 ? s i o- 22.5 -
i ntegrated c ircuits d ivision 6 www.ixysic.com r03 ix2113 1.9 test waveforms 1.9.1 s w itching time test circ u it 1.9.2 inp u t/o u tp u t timing diagram 1.9.3 s w itching time wa v eform definition 1.9.4 sh u tdo w n wa v eform definitions 1.9.5 delay matching wa v eform definitions hin sd lin v cc =15v 10 f 0.1f 10f 0.1f 10f c l c l ho lo (0 to 500v/600v) v b v s 15v + - 1 8 6 7311 12 13 14 15 2 n ote: pin n umbers sho wn are for the soic package. hin lin sd ho lo hin lin ho lo 50% 50% 90% 90% 10% 10% t on t r t off t f sd ho lo 50% 90% t sd hin lin lo ho 50% 50% 10% 90% mt lo ho mt
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 7 2 typical performance data temperature (oc) -50 -25 0 25 50 75 100 125 turn-on delay time (ns) 0 50 100 150 200 250 turn-on delay time vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 turn-off delay time (ns) 0 50 100 150 200 250 turn-off delay time vs. temperature supply volta g e (v) 9 111315171921 turn-on delay time (ns) 0 50 100 150 200 250 turn-on delay time vs. v bias supply volta g e supply volta g e (v) 9 111315171921 turn-off delay time (ns) 0 50 100 150 200 250 turn-off delay time vs. v bias supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 shutdown delay time (ns) 0 50 100 150 200 250 shutdown delay time vs. temperature v bias supply volta g e (v) 10 12 14 16 1 8 20 shutdown propa g ation delay (ns) 0 50 100 150 200 250 shutdown delay time vs. v bias supply volta g e v dd supply volta g e (v) 0 5 10 15 20 shutdown delay time (ns) 0 50 100 150 200 250 300 350 shutdown delay time vs. v dd supply volta g e temperature (oc) -50 -25 0 25 50 75 100 125 turn-on rise time (ns) 0 10 20 30 40 50 turn-on rise time vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 turn-off fall time (ns) 0 10 20 30 40 50 turn-off fall time vs. temperature
i ntegrated c ircuits d ivision 8 www.ixysic.com r03 ix2113 v bias supply volta g e (v) 10 12 14 16 1 8 20 turn-on rise time (ns) 0 5 10 15 20 25 30 35 turn-on rise time vs. volta g e v bias supply volta g e (v) 10 12 14 16 1 8 20 turn-off fall time (ns) 0 5 10 15 20 25 30 35 turn-off fall time vs. volta g e v dd (v) 0 3 6 9 12 15 1 8 21 log ic ?0? input threshold (v) 0 2 4 6 8 10 12 log ic ?0? input threshold vs. v dd v dd (v) 0 3 6 9 12 15 1 8 21 log ic ?1? input threshold (v) 0 2 4 6 8 10 12 log ic ?1? input threshold vs. v dd temperature (oc) -50 -25 0 25 50 75 100 125 log ic "0" input threshold (v) 0 3 6 9 12 15 log ic "0" input threshold vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 log ic "1" input threshold (v) 0 3 6 9 12 15 log ic "1" input threshold vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 logic "0" input current (a) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 logic "0" input current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 logic "1" input bias current (a) 0 20 40 60 80 100 logic "1" input bias current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v dd supply current ( a) 0 5 10 15 20 v dd supply current vs. temperature v dd log ic supply volta g e (v) 0 5 10 15 20 v dd supply current ( a) 0.0 0.2 0.4 0.6 0.8 1.0 v dd supply current vs. volta g e temperature (oc) -50 -25 0 25 50 75 100 125 v bs supply current ( a) 0 100 200 300 400 500 v bs supply current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v cc supply current ( a) 0 100 200 300 400 500 600 v cc supply current vs. temperature
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 9 temperature (oc) -50 -25 0 25 50 75 100 125 leaka g e current (a) 0 10 20 30 40 50 offset supply leaka g e current vs. temperature v b boost volta g e (v) 0 100 200 300 400 600 leaka g e current (a) 0 100 200 300 400 500 offset supply leaka g e current vs. v b boost volta g e 500 temperature (oc) -50 -25 0 25 50 75 100 125 hig h level output volta g e (v) 0 1 2 3 4 5 hig h level output volta g e vs. temperature (i o =0ma) temperature (oc) -50 -25 0 25 50 75 100 125 low level output volta g e (v) 0.0 0.2 0.4 0.6 0.8 1.0 low level output volta g e vs. temperature (i o =20ma) temperature (oc) -50 -25 0 25 50 75 100 125 output source current (a) 0 1 2 3 4 5 output source current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 output sink current (a) 0 1 2 3 4 5 output sink current vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v bs undervolta g e lockout+ (v) 6 7 8 9 10 11 v bs undervolta g e lockout (+) vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 6 7 8 9 10 11 v cc undervolta g e lockout (-) vs. temperature v cc undervolta g e lockout- (v) temperature (oc) -50 -25 0 25 50 75 100 125 v cc undervolta g e lockout+ (v) 6 7 8 9 10 11 v cc undervolta g e lockout (+) vs. temperature temperature (oc) -50 -25 0 25 50 75 100 125 v bs undervolta g e lockout- (v) 6 7 8 9 10 11 v bs undervolta g e lockout (-) vs. temperature v bs floating supply volta g e (v) 10 12 14 16 1 8 20 v bs supply current ( a) 0 100 200 300 400 500 v bs supply current vs. volta g e v cc fixed supply volta g e (v) 10 12 14 16 1 8 20 v cc supply current ( a) 0 100 200 300 400 500 v cc supply current vs. volta g e
i ntegrated c ircuits d ivision 10 www.ixysic.com r03 ix2113 figure 1. typical connection diagram v bias supply volta g e (v) 10 12 14 16 1 8 20 output source current (a) 0 1 2 3 4 5 output source current vs. volta g e v bias supply volta g e (v) 10 12 14 16 1 8 20 output sink current (a) 0 1 2 3 4 5 output sink current vs. volta g e v bias supply volta g e (v) 10 12 14 16 1 8 20 hig h level output volta g e (v) 0 1 2 3 4 5 hig h level output volta g e vs. supply volta g e v cc supply volta g e (v) 10 12 14 16 1 8 20 low level output volta g e (mv) 0 40 80 120 160 200 low level output volta g e vs. supply volta g e v dd v dd hin hin sd sd lin lin v ss v ss v cc v cc com lo v s v b ho load up to 600v
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 11 3 manufacturing information 3.1 moisture sensitivity all plastic encapsulated semiconductor packages are susc eptible to moisture ingression. ixys integrated circuits division clas sified all of its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, ipc/jedec j-std-020 , in force at the time of product evaluation. we test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. failure to adhere to the warnings or limitations as establ ished by the listed specificati ons could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. this product carries a moisture sensitivity level (msl) rating as shown below, and should be handled according to the requirements of the latest version of the joint industry standard ipc/jedec j-std-033 . 3.2 esd sensitivity this product is esd sensitive , and should be handled according to the industry standard jesd-625 . 3.3 reflow profile this product has a maximum body temperature and time rating as shown below. all other guidelines of j-std-020 must be observed. 3.4 board wash ixys integrated circuits division recommends the use of no-clean flux formulations. however, board washing to remove flux residue is acceptable, and the use of a short drying bake may be necessary. chlorine-based or fluorine-based solvents or fluxes should not be used. clean ing methods that employ ultrasonic energy should not be used. device moisture sensitivity level (msl) rating IX2113B, ix2113g msl 1 device maximum temperature x time IX2113B 260c for 30 seconds ix2113g 245c for 30 seconds
i ntegrated c ircuits d ivision 12 www.ixysic.com r03 ix2113 3.5 mechanical dimensions 3.5.1 IX2113B: 16-pin soic package 3.5.2 IX2113Btr: tape & reel packaging for 16-pin soic package (inches) mm dimensions notes: 1. coplanarity = 0.1016 (0.004) max. 2. leadframe thickness does not include solder plating (1000 microinch maximum). 0.406 0.076 (0.016 0.003) 10.211 0.254 (0.402 0.010) 7.493 0.127 (0.295 0.005) 10.312 0.381 (0.406 0.015) 1.270 typ (0.050 typ) 0.254 / +0.051 / -0.025 (0.010 / +0.002 / -0.001) 0.889 0.178 (0.035 0.007) 0.649 0.102 (0.026 0.004) pin 1 pin 16 2.337 0.051 (0.092 0.002) 0.203 0.102 (0.008 0.004) 45o 2.00 (0.079) 1.27 (0.050) 9.40 (0.370) 0.60 (0.024) recommended pcb land pattern dimensions mm (inches) embossment emb ossed carrier top co v er tape thickness 0.102 max. (0.004 max.) 330.2 dia. (13.00 dia.) k 0 =3.20 (0.126) k 1 =2.70 (0.106) a 0 =10.90 (0.429) w=16 (0.630) b 0 =10.70 (0.421) p=12.00 (0.472) notes: 1. all dimensions carry tolerances of eia standard 481-2 2. the tape complies with all ? notes? for constant dimensions listed on page 5 of eia-481-2
i ntegrated c ircuits d ivision ix2113 r03 www.ixysic.com 13 3.5.3 ix2113g: 14-pin dip thro u gh-hole package n otes: 1. jedec o u tline: ms-001 aa. 2. this dimension does not incl ude mold flash or protr u sions. mold flash or protr usions shall not exceed 0.254 (0.010). 3. meas ured at the lead tips with the leads u nconstrained. 4. pointed or ro u nded lead tips are preferred to ease insertion. 5. distance betw een leads including dam bar protr usions to be 0.127 (0.005). 6. dat um plane h coincident with the bottom of lead w here lead exits b ody. dimensions (min / max) mm (inches) pin 1 8.509 / 9.525 (0.335 / 0.375) see note 3 7.62 bsc (0.300 bsc) 18.542 / 19.050 (0.730 / 0.750) see note 2 2.921 / 3.810 (0.115 / 0.150) 0.381 min (0.015 min) 0.457 typ (0.018 typ) 2.542 (0.100) 3.175 / 3.429 (0.125 / 0.135) 1.524 typ (0.06 typ) 6.223 / 6.477 (0.245 / 0.255) see note 2 pcb hole pattern 7.62 (0.300) 2.54 (0.100) 1.35 (0.053) 0.85 (0.0335) hole size = 5.334 max (0.210 max) h seating plane 0o / 15o for additional information please visit our website at: www.ixysic.com ixys integrated circuits division makes no representations or wa rranties with respect to the a ccuracy or completeness of the co ntents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. neither circuit patent licenses nor indemnity ar e expressed or implied. except as set forth in ixys integrated circuits division?s standard terms and condit ions of sale, ixys integrated circuits division assumes no liability whatsoever, a nd disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringem ent of any intellectual property right. the products described in this document are not designed, intended, authorized or warranted for use as components in systems in tended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of ixys integrated circuits division?s product may resul t in direct physical harm, injury, or death to a person or severe property or environmental damage. ixys integrated circuits divisi on reserves the right to discontinue or make changes to its pr oducts at any time without notice. specification: ds-ix2113-r03 ?copyright 2014, ixys integrated circuits division all rights reserved. printed in usa. 6/9/2014

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