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cyw20706 embedded bluetooth 4.2 soc with mcu, bluetooth transceiver, and baseband processor cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-14790 rev. *a revised thursday, september 29, 2016 the cypress cyw20706 is a monolithic, sing le-chip, bluetooth 4.2 + hs compliant soc, comprising a baseband processor, an arm cortex-m3 processor, and an integrated tran sceiver. it is designed for use in embedded applications, with on-chip support for a n embedded stack. manufactured us ing the industry's most advanced 40 nm cmos low-power process, the cyw20706 employs the highest level of integration, eliminating all critical external components, and ther eby minimizing the device?s footprint and c osts associated with the implementa tion of bluetooth solutions. the cyw20706 is the optimal solution for voice, data, home auto mation, accessories and other appl ications that require a blueto oth sig standards-compliant interface. the cyw20706 supports a hos t command interface (hci) through usb or uart and also supports pcm audio. the cyw20706 transceiver?s enhanced radio performance meets the most stringent industrial tem perature application requirements for compact integration into mobile handset and portable device s. the cyw20706 provides full r adio compatibility, enabling it t o operate simultaneously with gps and cellular radios. cypress part numbering scheme cypress is converting the acquired iot part nu mbers from broadcom to the cypress part numbering scheme. due to this conversion, there is no change in form, fit, or functi on as a result of offering the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. features complies with bluetooth core specification version 4.2+ hs with provisions for supporting future specifications bluetooth class 1 or class 2 transmitter operation supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets adaptive frequency hopping (afh) for reducing radio frequency interference interface support for usb or high-speed uart interface and pcm for audio data usb2.0 full-speed (12 mbps) supports broadcom proprietary 2 mbps low energy mode. ultra-low power consumption supports serial flash interfaces available in a 49-ball fcbga package supports mobile and pc applications without external memory 125-bump wlcsp available december 2014 applications home automation gateways, audio streamin g, and other home automation use cases bluetooth 4.2 embedded peripheral devices and accessories personal digital assistants automotive telematic systems table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number bcm20706 cyw20706 BCM20706UA1KFFB1G cyw20706ua1kffb1g
document number: 002-14790 rev. *a page 2 of 49 cyw20706 figure 1. functi onal block diagram iot resources cypress provides a wealth of data at http://www.cypress.com /internet-things-iot to help you to select th e right iot device for your design, and quickly and effectively integrate the device into your design. cypress provides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and softwa re from the cypress support community website ( http:// community.cypress.com/ ) microprocessor and memory unit (pu) bluetooth baseband core (bbc) high-speed peripheral transport unit (ptu) radio transceiver pcm/i 2 s usb uart gpio spi master bsc cyw20706
document number: 002-14790 rev. *a page 3 of 50 cyw20706 contents 1. overview ........................................................................ 4 1.1 major features ...................................................... 4 1.2 block diagram ....................................................... 6 1.3 usage model ......................................................... 7 2. integrated radio transceiver ...................................... 8 2.1 transmit ................................................................ 8 2.2 receiver ................................................................ 8 2.3 local oscillator generation ................................... 8 2.4 calibration ............................................................. 8 2.5 internal ldo .......................................................... 9 3. bluetooth baseband core ... .............. .............. .......... 10 3.1 bluetooth low energy ......................................... 10 3.2 bluetooth 4.2 features ........................................ 10 3.3 bluetooth 4.0 features............................................. 10 3.4 link control layer ............................................... 11 3.5 test mode support ........... .............. .............. ....... 11 3.6 power management unit ..................................... 11 3.7 adaptive frequency hoppin g .............................. 13 3.8 collaborative coexistence ................................... 13 3.9 global coexistence interf ace .............................. 13 4. microprocessor unit ................................................... 14 4.1 overview ............................................................. 14 4.2 nvram configuration data and storage ............ 14 4.3 eeprom ...... ............... ........... ........... ........... ....... 14 4.4 external reset ..................................................... 14 4.5 one-time programmable memory ...................... 15 5. peripheral transport unit .......................................... 16 5.1 pcm interface ..................................................... 16 5.2 hci transport detection configuration ............... 17 5.3 usb interface ...................................................... 17 5.4 uart interface .................................................... 18 5.5 simultaneous uart transport and bridging ...... 19 6. frequency references ............................................... 20 6.1 crystal interface and clock generation .............. 20 6.2 crystal oscillator ................................................. 21 6.3 frequency selection ............................................ 21 6.4 frequency trimming ........................................... 21 7. pin-out and signal descriptions ............................... 22 7.1 pin descriptions .................................................. 22 8. ball grid arrays .......................................................... 24 9. electrical characteristics ........................................... 25 9.1 rf specifications ................................................ 29 9.2 timing and ac characteri stics ............................ 32 9.3 i 2 s interface............................................................... 40 10. mechanical information ........................................... 46 10.1 tape, reel, and packing specification .............. 47 11. ordering information ................................................ 48 document history .......................................................... 49
document number: 002-14790 rev. *a page 4 of 50 cyw20706 1. overview the broadcom cyw20706 complies with bluetooth core specification, version 4.2+ hs and is designed for use in embedded bt4.2 and uart/usb hci applications. the combinat ion of the bluetooth baseband core (bbc), a peripheral transport unit (ptu), and a cortex-m3 based microprocessor with on-chip rom provides a lo wer and upper layer bluetooth stack, including link controller (lc), link manager (lm), and hci. 1.1 major features major features of the cyw20706 include: bluetooth v4.2 + edr with integrated class 1 pa bt host digital interface (can be used concurrently with below interfaces): ? usb 2.0 full-speed (up to 12 mbps) ? uart (up to 4 mbps)42 integrated rf section ? single-ended, 50 ? rf interface ? built-in tx/rx switch functionality ? tx class 1 output power capability ? rx sensitivity basic rate of ?93.5 dbm ? rx sensitivity for low energy of ?96.5 dbm gci-enhanced coexistence support, ability to coor dinate bt sco transmissions around wlan receives supports maximum bluetooth data rates ov er hci uart, usb, and spi interfaces i 2 s/pcm for bt audio high-speed uart (h4, h4+) transport support wideband speech support (16 bits linear data, msb first, left-justif ied at 4k samples/s for trans parent air coding, both throug h i 2 s and pcm interface) bluetooth smartaudio ? technology improves voice and music quality to headsets bluetooth low-power inquiry and page scan bluetooth low energy (ble) support supports broadcom proprietary 2 mbps low energy mode maximum of 100 le connections supports tbfc (triggered broadcom [bluetooth] fast connect) bluetooth packet loss concealment (plc) bluetooth wide band speech (wbs)
document number: 002-14790 rev. *a page 5 of 50 cyw20706 high-speed uart transport support ? h4 five-wire uart (four signal wires, one ground wire) ? maximum uart baud rates of 4 mbps ? low-power out-of-band bt_w ake and host_wake signaling ? proprietary compression scheme (allows more than two simultaneous a2dp packets and up to five devices at a time) hci usb transport support ? usb version 2.0 full-speed compliant interface ? uhe (proprietary method for emulating a human interface device (hid) at system boot up) standard bluetooth test modes extended radio and production test mode features full support for po wer savings modes: ? bluetooth standard sniff ? deep sleep modes and regulator shutdown built-in lpo clock larger patch ram space to support future enhancements serial flash interface with native suppor t for devices from several manufacturers one-time programmable (otp) memory
document number: 002-14790 rev. *a page 6 of 50 cyw20706 1.2 block diagram figure 2 shows the interconnect of the ma jor cyw20706 physical blocks and associated external interfaces. figure 2. functi onal block diagram
document number: 002-14790 rev. *a page 7 of 50 cyw20706 1.3 usage model this section contains information on the product usage model. 1.3.1 pc product usage model the cyw20706 can be directly interfaced using the uart interf ace, providing full support for embedded applications. the cyw2070 6 also supports applications such as external usb dongle peripheral devices. figure 3 shows an example of a typical pc product usage model. figure 3. a typical product usage model host flash memory cyw20706 ieee 802.11? wlan usb (hci)/uart bt_gci_seci_in bt_gci_seci_out link_ind 20 mhz crystal oscillator serial interface 3.3v
document number: 002-14790 rev. *a page 8 of 50 cyw20706 2. integrated radio transceiver the cyw20706 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low-power, low-cost, robust communicati ons for applications operating in the globally available 2.4 ghz unlicensed ism band. the cyw20706 is fully compliant with th e bluetooth radio specificatio n and enhanced data rate (edr) specification and meets or exceeds the requirements to provide the highest communication link quality of service. 2.1 transmit the cyw20706 features a fully integrated ze ro-if transmitter. the baseband transmit da ta is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. the transmitter path consists of signal filtering, i/q upconve rsion, output power amplifier, an d rf filtering. the transmitter pa th also incorporates p/4 ? dqpsk for 2 mbps and 8 ? dpsk for 3 mbps to support edr. the transmitter section is compatible to the bluetoot h low energy specification. the transmitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. 2.1.1 digital modulator the digital modulator performs the data modulation a nd filtering required for the gfsk, pi/4 ? dqpsk, and 8 ? dpsk signal. the fully digita l modulator minimizes any frequen cy drift or anomalies in the modu lation characteristics of th e transmitted signal and is much more stab le than direct vco modulation schemes. 2.1.2 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. 2.1.3 power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this prov ides greater flexibility in front-end matching and filtering. due to th e linear nature of the pa combi ned with some integrated filte ring, external filtering is required to meet t he bluetooth and regulatory harmonic and spurious requirements. the transmitter features a sophi sticated on-chip transmit signal strength indicator (tssi) block to ke ep the absolute output power variation within a tight range across process, voltage, and temperature. 2.2 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz ism band. the front-end topology wi th built-in out-of-band attenuat ion enables the cyw20706 to be used in most appl ications with minimal off-chip filtering. for integrated handset operation, in whic h the bluetooth function is integrated close to the cellular transmitter, external filtering is requir ed to eliminate the desensitiza tion of the receiver by the cellular transmit signal. 2.2.1 digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. 2.2.2 receiver signal strength indicator the radio portion of the cyw20706 provides a receiver signal strength indicator (rssi) signal to the baseband, so that the cont roller can take part in a bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine wheth er the transmitter should increase or decrease its output power. 2.3 local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immu nity to lo pulling during pa operation. the cyw20706 uses an internal rf and if loop filter. 2.4 calibration the cyw20706 radio transceiver features an automated calibration sch eme that is fully self contained in the radio. no user inte raction is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the perfo r- mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this take s into account process variation and temperature variation. calibration occurs transparently during normal operation during t he settling time of the hops and calibrates for temperature va riations as the device cools and heats during normal operation in its environment.
document number: 002-14790 rev. *a page 9 of 50 cyw20706 2.5 internal ldo the cyw20706 uses two ldos?one for 1.2v and the other for 2.5v . the 1.2v ldo is used to provide the power supply to the baseband and the radio while the 2.5v ldo is used for the pa power supply. figure 4. ldo functional block vddc_in vdd2p5_in avss_gnd vdd2p5_out vddc_out 2.5v ldo (btldo2p5) 1.2v ldo (vddc_ldo) cyw20706 pmu
document number: 002-14790 rev. *a page 10 of 50 cyw20706 3. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time cr itical functions required for hi gh-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedul es sco/acl tx/rx transactions, monitors blueto oth slot usage, optimal ly segments and packages data into baseband packets, manages connection status indicators , and composes and decodes hci packets. in addition to these functions, it independently handles hci event types and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data before sending over the air: symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (cr c), data decryption, and data dewhitening in the receiver. data framing, fec generation, hec generatio n, crc generation, key generat ion, data encryption, and da ta whitening in the trans- mitter. 3.1 bluetooth low energy the cyw20706 supports dual-mode bluetooth low energy (bt and ble) operation. 3.2 bluetooth 4.2 features the cyw20706 supports the new featur es expected in bluetooth v4.2. secure connections (le/br/edr) fast advertising interval piconet clock adjust clock nudging connectionless broadcast le enhanced privacy low duty cycle directed advertising le dual mode topology 3.3 bluetooth 4.0 features the cyw20706 supports all bluetooth 4.0 features, with the following benefits: extended inquiry response (eir) encryption pause resume (epr) sniff subrating (ssr) secure simple pairing (ssp) link supervision time out (lsto) qos enhancements
document number: 002-14790 rev. *a page 11 of 50 cyw20706 3.4 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command contro ller that takes commands from the software, and other controllers that are activated o r configured by the command cont roller, to perform the link cont rol tasks. each task pe rforms a different state in the bluetooth link controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff 3.5 test mode support the cyw20706 fully supports bluetooth test mode as described in specification of the bluetooth core v4.2, which includes the transmitter tests, normal and delayed loopback tests, and reduced h opping sequence. in addition to the standard bluetooth test mode, the cyw20706 also supports enhanced testing features to simp lify rf debugging and qualificat ion and type-approval testing, including: fixed frequency carrier wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis fixed frequency constant receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant transmission ? 8-bit fixed pattern, prbs-9, or prbs-15 ? enables modulated signal measurements with standard rf test equipment 3.6 power management unit the power management unit (pmu) provides power management features that can be in voked through power management registers or packet handling in the baseband core. this section contains descriptions of the pmu features. 3.6.1 rf power management the bbc generates power-down control signals for the transmit path, receive path, pll, and power amplifier to the 2.4 ghz trans - ceiver. the transceiver then processes the power-down functions, accordingly. 3.6.2 soc power management the host can place the device in a sleep state, in which all nonessential blocks ar e powered off and all nonessential clocks ar e disabled. power to the digital core is maintained so that the state of the registers and ram is not lost. in addition, the cyw2 0706 internal lpo clock is applied to the internal sleep controller so that the chip can wake automatically at a specified time or b ased on signaling from the host. the goal is to limit the current cons umption to a minimum, while maintaining the ability to wake up an d resume a connection with minimal latency. if a scan or sniff session is enabled while the device is in sleep mode, the device automatically will wake up for the scan/sni ff event, then go back to sleep when the event is done. in this case, the device uses its internal lpo-based timers to trigger the period ic wake up. while in sleep mode, the transports are id le. however, the device can wake up at any time. if signaled to wake up while a s can or sniff session is in progress, the session continues but t he device will not sleep between scan/sniff events. once sleep mode is enabled, the wake signaling mechanism can also be thought of as a sleep signaling mechanism, since removing the wake status wil l often cause the device to sleep. in addition to a bluetooth device wake signaling mechanism, ther e is a host wake signaling mechanism. this feature provides a w ay for the bluetooth device to wake up a host that is in a reduced power state.
document number: 002-14790 rev. *a page 12 of 50 cyw20706 there are two mechanisms for the device and th e host to signal wake status to each other: 3.6.3 bluetooth baseband core power management the following are low-power operations fo r the bluetooth baseband core (bbc): physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection mode s: sniff, hold, and park. while in thes e modes, the cyw20706 runs on the low-power oscillator and wakes up after a predefined time period. usb when running in usb mode the device supports the usb version 2.0 full-speed specification, suspend/resume signaling, as well as remote wake-up signaling for power control. bluetooth device wake (bt_dev_wake) and host wake (and bt_host_wake) signaling the bt_dev_wake signal allows the ho st to wake the bt device, and bt_host_wake is an output that allows the bt device to wake the host. table 2. power control pin summary pin direction description bt_dev_wake host output bt input bluetooth device wake-up: signal from the host to the bluetooth device that the host requires attention. asserted = bluetooth device must wake up or remain awake. deasserted = bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software conf igurable and can be asserted high or low. by default, bt_dev_wake is active-low (if bt-w ake is low it requires the device to wake up or remain awake). for usb applications, this can be used for radio disable mode. bt_host_wake bt output host input host wake-up. signal from the bluetooth dev ice to the host indicating that bluetooth device requires attention. asserted = host device must wake up or remain awake. deasserted = host device may sleep when sleep criteria are met. the polarity of this signal is software conf igurable and can be asserted high or low. bt_clk_req bt output clock request asserted = external clock reference required deasserted = external clock reference may be powered down rst_n bt input used to place the chip in reset. rst_n is active-low.
document number: 002-14790 rev. *a page 13 of 50 cyw20706 3.7 adaptive frequency hopping the cyw20706 supports host channel classification and dynamic channel classification adaptive frequency hopping (afh) schemes, as defined in the bluetooth specification. host channel classification enables the host to se t a predefined hopping map for the device to follow. if dynamic channel classification is enabled, the device gathers link quality statistics on a channel-by-channel basis to facil itate channel assessment and channel map selection. to provide a more accura te frequency hop map, link quality is determined using both rf an d baseband signal processing. 3.8 collaborative coexistence the cyw20706 provides extensions and collaborative coexistence to the standard bluetooth afh fo r direct communication with wlan devices. collaborative coexistence enables wlan and bluet ooth to operate simultaneously in a single device. the device supports industry-standard coexistence si gnaling, including 802.15.2, and supports broadcom and third-party wlan solutions. 3.9 global coexistence interface the cyw20706 support the proprietary broadcom global co existence interface (gci) wh ich is a 2-wire interface. the following key features are associated with the interface: enhanced coexistence data can be exchanged over gci_seci_in and gci_seci_out a two-wire interface, one serial input (gci_seci_in), and one serial output (gci_seci_out). the pad c onfiguration registers must be pr ogrammed to choose the digital i/o pins that serve the gci_seci_in and gci_seci_out function. it supports generic uart communication between wlan and bluetooth devices. to conserve power, it is disabled when inactive. it supports automatic resynchroniza ton upon waking from sleep mode. it supports a baud rate of up to 4 mbps. 3.9.1 seci i/o the cyw20706 devices have dedicated gci_seci_in and gci_seci_ out pins. the two pin functions can be mapped to any of the broadcom global co-existence interface (gci) gpio. pin function mapping is c ontrolled by the configurat ion file that is sto red in either nvram or downloaded direct ly into on-chip ram from the host.
document number: 002-14790 rev. *a page 14 of 50 cyw20706 4. microprocessor unit 4.1 overview the cyw20706 microprocessor unit runs software from the link contro l (lc) layer up to the stack and application layer. in the h ci mode of operation the stack will be run on the external host. th e microprocessor is based on the cortex-m3 32-bit risc processo r with embedded ice-rt debug and jtag interface units. the mi croprocessor also includes 848 kb of rom memory for program storage and boot rom, 352 kb of ram fo r data scratch-pad, and patch ram code. the internal boot rom provides flexibility during power-on reset to enable the same device to be used in various configurations , including automatic host transport selection from uart and usb transports with or wit hout external nvram. at power-up, the lowe r layer protocol stack is executed from the internal rom. external patches can be applied to the rom-based firmware to pr ovide flexibility for bug fixes and features additions. these pa tches can be downloaded from the host to the device through the spi in terface or uart and usb transports, or using external nvram. the device can also support the integr ation of user applications and profiles using an external serial flash memory. 4.2 nvram configuration data and storage 4.2.1 serial interface the cyw20706 includes an spi master controller that can be used to access serial flash memory. the spi master contains an ahb slave interface, transmit and receive fifos, and the spi core phy logic. data is transferred to and from the module by the syst em cpu. dma operation is not supported. 4.3 eeprom the cyw20706 includes a broadcom serial control (bsc) master interface. the bsc interface su pports low-speed and fast mode devices and is compatible with i 2 c slave devices. multiple i 2 c master devices and flexible wait st ate insertion by the master interface or slave devices are not supported. the cyw 20706 provides 400 khz, full speed clock support. the bsc interface is programmed by the cpu to gene rate the following bsc transfer types on the bus: read-only write-only combined read/write combined write-read nvram may contain configuration information about the customer applicatio n, including the following: fractional-n information bd_addr uart baud rate usb enumeration information sdp service record file system information used for code, code patches, or data 4.4 external reset the cyw20706 has an integrated power-on reset circuit which complete ly resets all circuits to a kn own power on state. this acti on can also be driven by an external reset signal, which can be us ed to externally control the device, forcing it into a power-on reset state. the rst_n signal is an active-low signal, which is an input to the cyw20706 chip. the cyw20706 does not require an external pul l- up resistor on the rst_n input.
document number: 002-14790 rev. *a page 15 of 50 cyw20706 4.5 one-time programmable memory the cyw20706 includes a one-time programmable (otp) memory , allowing manufacturing customization and avoiding the need for an on-board nvram.if customization is not required, then the otp does not need to be programmed. whether the otp is programmed or not, it is disabled after th e boot process completes to save power. the otp size is 2048 bytes. the otp is designed to store a minimal amount of information. aside from otp data, most user configuration information will be downloaded into ram after the cyw20706 boots up and is ready for ho st transport communication. th e otp contents are limited to: parameters required prior to downloading user configuration to ram. parameters unique to each part and each customer (i.e., the bd_addr, software license key, and usb pid/vid). the otp memory is particularly useful in a pc design with usb transport capability because: some customer-specific in formation must be configured before enumerating the part on the usb transport. part or customer unique information (bd_addr, software license key, and usb pid/vid) do not need to be stored on the host syste m. 4.5.1 contents the following are typical parameters programmed into the otp memory: bd_addr software license key usb pid/vid usb bus/self-powered status output power calibration frequency trimming initial status led drive configuration the otp contents also include a static error correction table to improve yield during the programming process as well as forwar d error correction codes to eliminate any long-term reliability problems. the otp contents as sociated with error correction are not vis ible by customers. 4.5.2 programming otp memory programming takes place through a combination of br oadcom software integrated with the manufacturing test software and code embedded in cyw20706 firmware.
document number: 002-14790 rev. *a page 16 of 50 cyw20706 5. peripheral transport unit this section discusses the pcm, usb, uart, i 2 s, and spi peripheral interfaces. the cyw20706 has a 1040-byte transmit and receive fifo, which is large enough to hold the ent ire payload of the largest edr bt packet (3-dh5). 5.1 pcm interface the cyw20706 supports two independent pcm inte rfaces that share the pins with the i2s interfaces. the pcm interface on the cyw20706 can connect to linear pcm codec devices in master or slave mode. in master mo de, the cyw20706 generates the pcm_clk and pcm_sync signals, and in slave mode, these signal s are provided by another master on the pcm interface and are inputs to the cyw20706. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. 5.1.1 slot mapping the cyw20706 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of slots is dependent on the selected in terface rate of 128 khz, 512 k hz, or 1024 khz. the corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. t he pcm data output driver tristate s its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 5.1.2 frame synchronization the cyw20706 supports both short- and long- frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at th e next rising edge of the cl ock. in long-frame synchroni zation mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. 5.1.3 data formatting the cyw20706 may be configured to generate and accept several different data formats. for conventional narrowband speech mode, the cyw20706 uses 13 of the 16 bits in each pcm frame. the location and order of thes e 13 bits can be configured to support var ious data formats on the pcm interface. the remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2? s complement data, left justified, and clocked msb first. 5.1.4 wideband speech support when the host encodes wideband speech (wbs) packets in transpa rent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mode, the pcm bus is ty pically configured in master m ode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw20706 also supports slave transparent mode using a proprietary rate-matchi ng scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus. 5.1.5 burst pcm mode in this mode of operation, the pcm bus runs at a significantly higher rate of operati on to allow the host to duty cycle its ope ration and save current. in this mode of operation, the pcm bus can operate at a rate of up to 24 mhz. this mode of operation is initiated with an hci command from the host.
document number: 002-14790 rev. *a page 17 of 50 cyw20706 5.2 hci transport detection configuration note: hci transport detection is only valid for the hci operating mode. the cyw20706 supports the following interface types for the hci transport from the host: uart (h4) usb only one host interface can be active at a time. the firmware pe rforms a transport detect function at boot-time to determine wh ich host is the active transport. it can auto-detect uart and usb in terfaces, but the spi interface mu st be selected by strapping t he scl pin to 0. the complete algorithm is summarized as follows: 1. determine if any local nvram contains a valid configuration f ile. if it does and a transport co nfiguration entry is present, select the active transport according to entry, and t hen exit the transport detection routine. 2. look for start-of-frame (sof) on the usb interface. if it is present, select usb. 3. look for cts_n = 0 on the uart interfac e. if it is present, select uart. 4. repeat step 2 and step 3 until transport is determined. 5.3 usb interface 5.3.1 features the following usb interface features are supported: usb protocol, revision 2.0, full -speed compliant (up to 12 mbps) global and selective suspend and resume with remote wake-up optional bluetooth hci hid, dfu, uhe (proprietary method to emulate an hi d device at system boot) integrated detach resistor note: if the usb transport is not used, tie th e cyw20706 usb pins and vdd_usb to ground. 5.3.2 operation the cyw20706 can be configured to boot up as a single usb perip heral, and the host detects a single usb bluetooth device. this configuration is typically used in a standal one mode. other embedded mode applications ma y not be used at the same time as the uhe mode described below. the cyw20706 can boot up showing the independent interfaces con nected to logical usb devices internal to the cyw20706?a generic bluetooth device, a mouse, and a ke yboard. in this mode, the mouse and keyb oard are emulated devices, since they connec t to real hid devices via a bluetooth link. th e bluetooth link to these hid devices is hi dden from the usb host. to the host, the mouse and/or keyboard appear to be directly connec ted to the usb port. this broadcom propri etary architecture is called usb hid emula tion (uhe). the usb device, configuration, and string descriptors are fully programmable, allowing manufacturers to customize the descripto rs, including vendor and product ids, the cyw20706 uses to identify itself on the usb port. to make custom usb descriptor informati on available at boot time, stor ed it in external nvram. in the single usb peripheral operating mode, the bluetooth de vice is configured to include the following interfaces: interface 0 contains a control endpoint (endpoint 0x00) for hci commands, a bulk in endpoint (endpoint 0x82) for receiving acl data, a bulk out endpoint (endpoint 0x02) for tran smitting acl data, and an interrupt endpoint (endpoint 0x81) for hci events. interface 1 contains isochronous in and out endpoints (endpoints 0x83 and 0x03) for sco traffic. several alternate interface 1 settings are available for reserving the proper bandw idth of isochronous data (depending on the application). interface 2 contains bulk in and bulk out endpoints (endpoints 0x84 and 0x04) used for proprietary testing and debugging purposes. these endpoints can be ignored during normal operation.
document number: 002-14790 rev. *a page 18 of 50 cyw20706 5.3.3 uhe support the cyw20706 supports the usb device model (usb 2.0-compatible, fu ll-speed compliant). optional mouse and keyboard interfaces utilize broadcom?s proprietary usb hid emul ation (uhe) architecture, which allows th ese bluetooth devices appear as standalone hid devices even though connected through a bluetooth link. the presence of uhe devices requires the cyw20706 to be configured as a composite device (composite mode). in this mode, the bluetooth mouse and keyboard interfac es are independently controlled and ap pear as standalone logical devices. broadcom?s standard comp osite configuration uses the following layout: interface 0 ? keyboard interface 1 ? mouse interface 2/3/4 ? bluetooth (as described above) when operating in composite mode, every interface does not have to be enabled?each can be optionally enabled. the configuration record in nvram determines which devices are present. 5.4 uart interface the cyw20706 shares a single uart for bluetooth. the uart is a standard 4-wire interface (rx, tx , rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the in terface features an automatic baud rate det ection capability that returns a baud ra te selection. alternatively, the baud rate may be se lected through a vendor-specific uart hci command. uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or the cpu. the uart supports the bluetooth 4.2 ua rt hci specification: h4, and a custom extended h4. the default baud rate is 115.2 kbaud. the cyw20706 uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform wake-on activi ty. for example, activity on the rx or cts inputs can wake the chip from a sleep state. normally, the uart baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detectio n, and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is incl uded through a vendor-specific command that allo ws the host to adjust the contents of t he baud rate registers. the cyw20706 uarts operate correctly with the host uart as long as the co mbined baud rate error of the two devices is within 2%. table 3. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00
document number: 002-14790 rev. *a page 19 of 50 cyw20706 5.5 simultaneous uart transport and bridging note : simultaneous uart transport and bridging is only valid for the hci operating mode. the cyw20706 supports uart or usb interfaces that can function as the host controller interface (hci). typi cally, a customer application would choose one of the two interfaces and the other would be idle. the cyw20706 allows the uart transport to opera te simultaneously with the usb. to operate this way, the assumpti on is that the usb would function as the primary host transport, while the uart would function as a secondary communication channel th at can operate at the same ti me. this can enable the following applications: bridging primary hci transport traffic to another device via the uart generic communication to an external device fo r a vendor-supported application via the uart simultaneous uart transport and bridging is enabled by including: two dedicated 64-byte fifos, one for the input and one for the output additional dma channels additional vendor-supported commands over the hci transport
document number: 002-14790 rev. *a page 20 of 50 cyw20706 6. frequency references the cyw20706 uses an external crystal for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference can be used. 6.1 crystal interface and clock generation the cyw20706 uses a fractional-n synthesiz er to generate the radio frequencies, clo cks, and data/packet timing, enabling it to operate from any of a multitude of frequency sources. the source can be external, such as a crystal interfaced directly to the device or an external frequency reference can be used. typical crystal frequencies of 20 mhz and 40 mhz are support ed using the xtal_strap_1 pin on the cyw20706. the signal characteristics for the crystal interface are listed in table 4 on page 20 . table 4. crystal interface signal characteristics parameter crystal external frequency reference units acceptable frequencies 19.2?52 mhz in 2 ppm a steps a. the frequency step size is approximately 80 hz resolution. 12?52 mhz in 2 ppm a steps ? crystal load capacitance 12 (typical) n/a pf esr 100 (max) ? ? power dissipation 200 (max) ? w input signal amplitude n/a 400 to 1200 2000 to 3300 (requires a 10 pf dc blocking capacitor to attenuate the signal) mvp-p signal type n/a square-wave or sine-wave ? input impedance n/a 1 2 m ? pf phase noise @ 1 khz @ 10 khz @ 100 khz @ 1 mhz n/a n/a n/a n/a n/a ? < ?120 < ?130 < ?135 < ?136 ? dbc/hz dbc/hz dbc/hz dbc/hz tolerance without frequency trimming b b. at-cut crystal or txco recommended. 20 20 ppm initial frequency tolerance trimming range 50 50 ppm
document number: 002-14790 rev. *a page 21 of 50 cyw20706 6.2 crystal oscillator the cyw20706 can use an external crystal to provide a frequency reference. the reco mmended configuration for the crystal oscill ator, including all external components, is shown in figure 5 . figure 5. recommended oscillator configuration 6.3 frequency selection any frequency within the range specified for the crystal and freq uency reference can be used. since bit timing is derived from the reference frequency, the cyw20706 must have the reference freque ncy set correctly in order for any of the usb, uart, and pcm interfaces to function properly. the cyw20706 reference frequency can be selected by using bt _xtal_strap_1. the typical crys tal frequencies of 20 mhz and 40 mhz are supported. the gpio_2 needs to be tied to ground. clock (mhz): xtal_strap_1 (pin-f2) 40:low 20:high if the application requires a frequencies othe r than these, the value can be stored in an external nvram. programming the refer ence frequency in nvram provides the maximum flexibility in the sele ction of the reference frequenc y, since any frequency within the specified range for crystal and external frequency reference can be used. during power-on reset (por), the device downloads the parameter settings stored in nvram, wh ich can be programmed to include the reference frequency and frequency trim values. typically, this is how a pc bl uetooth application is configured. 6.4 frequency trimming the cyw20706 uses a fractional-n synthesizer to digitally fine -tune the frequency reference input to within 2 ppm tuning accura cy. this trimming function can be applied to either the crystal or an reference frequency source. unlike the typical crystal-trimmi ng methods used, the cyw20706 changes the frequency using a fully digital implementation and is much more stable and unaffected by crystal characteristics or temperature. input impedance and l oading characteristics remain unchanged on the crystal during t he trimming process and are unaffected by process and temperature variations. the option to use or not use fr equency trimming is ba sed on the system designer?s cost tr ade-off between bi ll-of-materials (bom ) cost of the crystal and the added manufacturing cost associated wi th frequency trimming. the frequency trimming value can either be stored in the host and written to the cyw20706 as a vendor-spe cific hci command or stored in nvram and subsequently recalled during por. frequency trimming is not a substitute for the poor use of tuning capacitors at an crystal oscillator (xtal). occasionally, tri mming can help alleviate hardware changes. 0 ? ~ ? 18 pf* 0 ? ~ ? 18 pf* xoin xoout crystal ? oscillator *capacitor ? value ? range ? depends ? on ? the ? manufacturer ? of ? the ? xtal ? as ? well ? as ? board ? layout.
document number: 002-14790 rev. *a page 22 of 50 cyw20706 7. pin-out and signal descriptions 7.1 pin descriptions table 5. cyw20706 signal descriptions signal fcbga pin (49-ball) i/o power domain description radio rfop a2 i/o vdd_rf rf i/o antenna port xo_in a4 i vdd_rf crystal or reference input xo_out a5 o vdd_rf crystal oscillator output voltage regulators vbat d1 i n/a vbat input pin vdd2p5_in e1 i n/a 2.5v ldo input vdd2p5_out e2 o n/a 2.5v ldo output vddc_out f1 o n/a 1.2v ldo output straps bt_xtal_strap_1 f2 i vddo this pin is us ed as strap for choosing the xtal frequencies. rst_n a6 i vddo active-low reset input bt_tm1 g7 i vddo reserved: connect to ground. digital i/o bt_gpio_0 f8 i vddo bt _gpio_0/bt_dev_wake a signal from the host to the cyw20706 device that the host requires attention. bt_gpio_1 f7 o vddo bt_g pio_1/bt_host_wake a signal from the cyw20706 device to the host indicating that the bluetoot h device requires attention. bt_gpio_2 e4 i vddo when high, this signal extends the xtal warm-up time for external clk requests. otherwise, it is typically connected to ground. bt_gpio_3 c5 i/o vddo general-purpose i/o. bt_gpio_4 d6 i/o vddo general-purpose i/o. it can also be configured as a gci pin. bt_gpio_5 b5 i/o vddo general-purpose i/o. it can also be configured as a gci pin. bt_gpio_6 b6 i/o vddo general-purpose i/o. it can also be configured as a gci pin. bt_gpio_7 c6 i/o vddo general-purpose i/o. it can also be configured as a gci pin. bt_uart_rxd f5 i/o vddo uart receive data bt_uart_txd f4 i/o vddo uart transmit data bt_uart_rts_n f3 i/o vddo uart request to send output bt_uart_cts_n g4 i/o vddo uart clear to send input bt_clk_req g8 o vddo this pin is used for shared-clock application. spi2_miso_i2s_scl d8 i/o vddo bsc clock
document number: 002-14790 rev. *a page 23 of 50 cyw20706 spi2_mosi_i2s_sda e8 i/o vddo bsc data spi2_clk e7 i/o vddo serial flash spi clock spi2_csn d7 i/o vddo serial flash active-low chip select i2s_di/pcm_in c7 i/o vddo pcm/i2s data input i2s_do/pcm_out a8 i/o vddo pcm/i2s data output i2s_clk/pcm_clk b7 i/o vddo pcm/i2s clock i2s_ws/pcm_sync c8 i/o vddo pcm sync/i2s word select usb bt_husb_dp g2 i/o vdd_usb usb d+ sign al. if not used, connect to gnd. bt_husb_dn g3 i/o vdd_usb usb d- signal. if not used, connect to gnd. jtag jtag_sel d5 i/o vddo used for debugging supplies bt_vdd_usb g1 i n/a 3.3v usb transceiver supply voltage. if the usb transport is not needed, connect this pin to gnd. bt_ifvdd1p2 b4 i n/a radio if pll supply bt_pavdd2p5 a1 i n/a radio pa supply bt_lnavdd1p2 b1 i n/a radio lna supply bt_vcovdd1p2 c1 i n/a radio vco supply bt_pllvdd1p2 a3 i n/a radio rf pll supply vddc b8, g6 i n/a core logic supply vddo g5 i n/a digital i/o supply voltage vss a7, b2, b3, c2, d2, f6 ? n/a ground table 5. cyw20706 signal descriptions (cont.) signal fcbga pin (49-ball) i/o power domain description
document number: 002-14790 rev. *a page 24 of 50 cyw20706 8. ball grid arrays figure 6 shows the top view of the 49-ball 4.5 mm x 4 mm x 0.8 mm (fcbga). figure 6. 4.5 mm x 4 mm x 0.8 mm (fcbga) array figure 7. ball-out for the 49-ball fcbga 12345678 a bt_ pavdd2p5 rfop bt_ pllvdd1p2 xo_in xo_out rst_n vssc i2s_do/ pcm_out b bt_lnavdd1 p2 vss vss bt_ ifvdd1p2 bt_gpio_5 bt_gpio_6 i2s_clk/ pcm_clk vddc c bt_ vcovdd1p2 vss bt_gpio_3 bt_gpio_7 i2s_di/ pcm_in i2s_ws/ pcm_sync d vbat vss jtag_sel bt_gpio_4 spi2_csn spi2_miso_ i2c_scl e vdd2p5_in vdd2p5_ out bt_gpio_2 spi2_clk spi2_mosi_ i2c_sda f vddc_out bt_xtal _strap_1 bt_uart _rst_n bt_uart _txd bt_uart _rxd vss bt_gpio_1/ bt_host_ wake bt_gpio_0/ bt_dev _wake g bt_vdd _usb bt_husb _dp bt_husb _dn bt_uart _cts_n vddo vddc bt_tm1 bt_clk _req
document number: 002-14790 rev. *a page 25 of 50 cyw20706 9. electrical characteristics note: all voltages listed in table 6 are referenced to vdd. table 6. absolute maximum voltages requirement parameter specification units minimum nominal maximum ambient temperature of operation ?30 25 85 c storage temperature ?40 ? 150 c esd tolerance hbm ?2000 ? 2000 v esd tolerance mm ?100 ? 100 v esd tolerance cdm ?500 ? 500 v latch-up tbd tbd tbd tbd vdd core 1.14 1.2 1.26 v vdd io 3 3.3 3.6 v vdd rf (excluding class 1 pa) 1.14 1.2 1.26 v vdd pa (class 1 mode) 2.25 2.5 2.75 v table 7. power supply specifications parameter conditions min. typ. max. units vbat input ? 1.62 3.3 3.6 v 2.5v ldo input ? 3.0 3.3 3.6 v table 8. vddc ldo electrical specifications parameter conditions min. typ. max. units input voltage ? 1.62 3.3 3.6 v nominal output voltage ??1.2?v dc accuracy accuracy at any step, including bandgap reference. ?5 ? 5 % output voltage programmability range 0.89 ? 1.34 v step size ? 30 ? mv load current ? ? ? 40 ma dropout voltage i load = 40 ma ? ? 200 mv line regulation vin from 1.62v to 3.6v, i load = 40ma ??0.2%vo/v load regulation i load = 1 ma to 40 ma, vout = 1.2v, package + pcb r = 0.3 ? ? 0.02 0.05 %vo/ma quiescent current no load @vin = 3.3v ? 18 23 a max load @vin = 3.3v ? ? 0.56 0.65 ma power down current vin = 3.3v @25c ? 0.2 ? a
document number: 002-14790 rev. *a page 26 of 50 cyw20706 psrr vin = 3.3, vout = 1.2v, i load = 40 ma 1 khz 65 ? ? db 10 khz 60 ? ? db 100 khz 55 ? ? db over current limit ? 100 ? ? ma turn-on time vbat = 3.3v, bg already on, ldo off to on, co = 1 f, 90% of vout ? ? 100 s external output capacitor ceramic cap with esr 0.5 ? 0.8 1 4.7 f external input capacitor ceramic, x5r, 0402, 20%, 10v. ? 1 ? f table 9. btldo_2p5 el ectrical specifications parameters conditions min typ max units input supply voltage, vin min = vo + 0.2v = 2.7v (for vo = 2.5v) dropout voltage requirement must be met under maximum load for performance specs. 3.0 3.3 3.6 v nominal output voltage, vo default = 2.5v ? 2.5 ? v output voltage programmability range accuracy at any step (including line/load regulation), load >0.1 ma 2.2 ?5 ?2.8 5 v % dropout voltage at max load ? ? 200 mv output current ? 0.1 ? 70 ma quiescent current no load; vin = vo + 0.2v max load @ 70 ma; vin = vo + 0.2v ?8 660 16 700 a leakage current power-down mode. at junction temperature 85c. ?1.55 a line regulation vin from (vo + 0.2v) to 3.6v, max load ? ? 3.5 mv/v load regulation load from 1 ma to 70 ma, vin = 3.6v ? ? 0.3 mv/ma psrr vin vo+0.2v, vo=2.5v, co=2.2 f, max load, 100 hz to 100 khz 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? ? 150 s external output capacitor, co ceramic, x5r, 0402, (esr: 5m-240 m ? ), 20%, 6.3v 0.7 2.2 2.64 f external input capacitor ceramic, x5r, 0402, 20%, 10v ? 1 ? f table 8. vddc ldo electrical specifications (cont.) parameter conditions min. typ. max. units
document number: 002-14790 rev. *a page 27 of 50 cyw20706 table 10. digital i/o characteristics characteristics symbol minimum typical maximum unit input low voltage (vddo = 3.3v) v il ??0.8v input high voltage (vddo = 3.3v) v ih 2.0 ? ? v output low voltage v ol ??0.4v output high voltage v oh vddo ? 0.4v ? ? v input low current i il ??1.0 a input high current i ih ??1.0 a output low current (vddo = 3.3v, v ol = 0.4v) i ol ??2.0ma output high current (vddo = 3.3v, v oh = 2.9v) i oh ??4.0ma input capacitance c in ??0.4pf table 11. usb interface level parameter symbol minimum typical maximum unit i/o supply voltage vdd_usb 3.0 ? 3.6 v supply current icchpf ? ? 500 ma input high voltage (driven) vih 2.0 ? ? v input high voltage (floating) vihz 2.7 ? 3.6 v input low voltage vil ? ? 0.8 v differential input sensitivity vdi 0.2 ? ? v differential common-mode range vcm 0.8 ? 2.5 v output low voltage vol 0.0 ? 0.3 v output high voltage (driven) voh 2.8 ? 3.6 v output signal crossover voltage vcrs 1.3 ? 2.0 v
document number: 002-14790 rev. *a page 28 of 50 cyw20706 table 12. current cons umption?common use cases condition current (ma) receive (1 mbps) current le vel when receiving a basic rate packet (tbd ma). 12.5 transmit (1 mbps) current level when transmitting a basic rate packet. 26.5 receive (edr) current level when receiving a 2 or 3 mbps rate packet. 12.5 transmit (edr) current level when transmitting a 2 or 3 mbps rate packet. 20.0 dm1/dh1 average current during a basic rate maximum throughp ut connection that includes only this packet type. 14.5 dm3/dh3 average current during a basic rate maximum throughp ut connection that includes only this packet type. 17.0 dm5/dh5 average current during a maximum basic rate throughput connection that includes only this packet type. 17.5 hv1 average current during an sco voice connection consisting of only this packet type. the acl channel is in 500 ms sniff. 14.0 hv2 average current during an sco voice connection consisting of only this packet type. the acl channel is in 500 ms sniff. 9.0 hv3 average current during an sco voice connection consisting of only this packet type. the acl channel is in 500 ms sniff. 7.0 sleep uart transport active. external lpo clock available (tbd a). 0.120 inquiry scan (1.28 sec.). periodic scan rate is 1.28 sec. 0.188 page scan (r1) periodic scan rate is r1 (1.28 sec). 0.188 inquiry scan + page scan (r1) both inquiry and page scans are interlaced toget her at a 1.28 seconds periodic scan rate. 0.286 sniff master (500 ms) attempt and timeout parameters set to 4. quality connection that rarely requires more than a minimum packet exchange. 0.415 sniff slave (500 ms) attempt and timeout parameters set to 4. quality connection that rarely requires more than a minimum packet exchange. 0.408 sniff (500 ms) + inquiry or page scan (r1) 0.700 sniff (500ms) + inquiry scan + page scan (r1) 0.800 note : the values in this table were calculated for a 90% efficient dc-dc at 3v in hci mode, and bas ed on a class i configuration bench-marked at class ii. lower values are expected for a cla ss ii configuration using an external lpo and corresponding pa configuration.
document number: 002-14790 rev. *a page 29 of 50 cyw20706 9.1 rf specifications table 13. receiver rf specifications a, b parameter conditions minimum typical c maximum unit general frequency range ? 2402 ? 2480 mhz rx sensitivity d gfsk, 0.1% ber, 1 mbps ? ?93.5 ? dbm ? /4-dqpsk, 0.01% ber, 2 mbps ? ?95.5 ? dbm 8-dpsk, 0.01% ber, 3 mbps ? ?89.5 ? dbm maximum input gfsk, 1 mbps ? ? ?20 dbm maximum input ? /4-dqpsk, 8-dpsk, 2/3 mbps ? ? ?20 dbm interference performance gfsk modulation e c/i cochannel gfsk, 0.1% ber ? 9.5 11 db c/i 1 mhz adjacent channel gfsk, 0.1% ber ? ?5 0 db c/i 2 mhz adjacent channel gfsk, 0.1% ber ? ?40 ?30.0 db c/i > 3 mhz adjacent channel gfsk, 0.1% ber ? ?49 ?40.0 db c/i image channel gfsk, 0.1% ber ? ?27 ?9.0 db c/i 1 mhz adjacent to image channel gfsk, 0.1% ber ? ?37 ?20.0 db qpsk modulation f c/i cochannel ? /4-dqpsk, 0.1% ber ? 11 13 db c/i 1 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ?8 0 db c/i 2 mhz adjacent channel ? /4-dqpsk, 0.1% ber ? ?40 ?30.0 db c/i > 3 mhz adjacent channel 8-dpsk, 0.1% ber ? ?50 ?40.0 db c/i image channel ? /4-dqpsk, 0.1% ber ? ?27 ?7.0 db c/i 1 mhz adjacent to image channel ? /4-dqpsk, 0.1% ber ? ?40 ?20.0 db 8psk modulation g c/i cochannel 8-dpsk, 0.1% ber ? 17 21 db c/i 1 mhz adjacent cha nnel 8-dpsk, 0.1% ber ? ?5 5 db c/i 2 mhz adjacent channel 8-dpsk, 0.1% ber ? ?40 ?25.0 db c/i > 3 mhz adjacent channel 8-dpsk, 0.1% ber ? ?47 ?33.0 db c/i image channel 8-dpsk, 0.1% ber ? ?20 0 db c/i 1 mhz adjacent to image channel 8-dpsk, 0.1% ber ? ?35 ?13.0 db out-of-band blocking performance (cw) h 30 mhz?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm
document number: 002-14790 rev. *a page 30 of 50 cyw20706 out-of-band blocking performance, modulated interferer 776?764 mhz cdma ? ?10 i ?dbm 824?849 mhz cdma ? ?10 i ?dbm 1850?1910 mhz cdma ? ?23 i ?dbm 824?849 mhz edge/gsm ? ?10 i ?dbm 880?915 mhz edge/gsm ? ?10 i ?dbm 1710?1785 mhz edge/gsm ? ?23 i ?dbm 1850?1910 mhz edge/gsm ? ?23 i ?dbm 1850?1910 mhz wcdma ? ?23 i ?dbm 1920?1980 mhz wcdma ? ?23 i ?dbm intermodulation performance j bt, df = 4 mhz ? ?39.0 ? ? dbm spurious emissions k 30 mhz to 1 ghz ? ? ? ?62 dbm 1?12.75 ghz ? ? ? ?47 dbm 65?108 mhz fm rx ? ?147 ? dbm/hz 746?764 mhz cdma ? ?147 ? dbm/hz 851?894 mhz cdma ? ?147 ? dbm/hz 925?960 mhz edge/gsm ? ?147 ? dbm/hz 1805?1880 mhz edge/gsm ? ?147 ? dbm/hz 1930?1990 mhz pcs ? ?147 ? dbm/hz 2110?2170 mhz wcdma ? ?147 ? dbm/hz a. all specifications are single ended. unused inputs are left open. b. all specifications, except typica l, are for industrial temperatures. c. typical operating conditions are 3. 3v vbat and 25c ambient temperature. d. the receiver sensitivity is measured at ber of 0.1% on the device interface. e. typical gfsk ci numbers at ?7 mhz, ?5 mhz, and ?3 mhz are ?45 db, ?42 db, and ?41 db, respectively. f. typical qpsk ci numbers at ?7 mhz, ?5 mhz, and ?3 mhz are ?46 db, ?43 db, and ?42 db, respectively. g. typical 8psk ci numbers at ?7 mhz, ?5 mhz, and ?3 mhz are ?50 db, ?45 db, and ?45 db, respectively. h. meets this specification usi ng front-end band pass filter. i. numbers are referred to the pin output with an external bpf filter. j. f0 = -64 dbm bluetooth-modulated signal, f1 = ?39 dbm sine wave, f2 = ?39 dbm bluetooth-modulated signal, f0 = 2f1 ? f2, and |f2 ? f1| = n*1 mhz, where n is 3, 4, or 5. for the typical case, n = 4. k. includes baseband radiated emissions. table 13. receiver rf specifications a, b (cont.) parameter conditions minimum typical c maximum unit
document number: 002-14790 rev. *a page 31 of 50 cyw20706 table 14. transmitter rf specifications a b parameter conditions minimum typical maximum unit general frequency range ? 2402 ? 2480 mhz class1: gfsk tx power c ??12?dbm class1: edr tx power d ? ?9?dbm class 2: gfsk tx power ? ? 2 ? dbm power control step ? 2 4 8 db modulation accuracy ? /4-dqpsk frequency stability ? ?10 ? 10 khz ? /4-dqpsk rms devm ? ? ? 20 % ? /4-qpsk peak devm ? ? ? 35 % ? /4-dqpsk 99% devm ? ? ? 30 % 8-dpsk frequency stability ? ?10 ? 10 khz 8-dpsk rms devm ? ? ? 13 % 8-dpsk peak devm ? ? ? 25 % 8-dpsk 99% devm ? ? ? 20 % in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz ? ? ? ?26 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ? ? ?20 dbm |m ? n| > 2.5 mhz ? ? ? ?40 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 e dbm 1?12.75 ghz ? ? ? ?30.0 e, f dbm 1.8?1.9 ghz ? ? ? ?47.0 dbm 5.15?5.3 ghz ? ? ? ?47.0 dbm gps band noise emission (without a front-end band pass filter) 1572.92 mhz to 1577.92 mhz ? ? ?150 ?127 dbm/hz out-of-band noise emissions (witho ut a front-end b and pass filter) 65?108 mhz fm rx ? ?145 ? dbm/hz 746?764 mhz cdma ? ?145 ? dbm/hz 869?960 mhz cdma ? ?145 ? dbm/hz 925?960 mhz edge/gsm ? ?145 ? dbm/hz 1805?1880 mhz edge/gsm ? ?145 ? dbm/hz 1930?1990 mhz pcs ? ?145 ? dbm/hz 2110?2170 mhz wcdma ? ?140 ? dbm/hz a. all specifications are for industrial temperatures. b. all specifications are single-ended. unused input are left open. c. +12 dbm output for gfsk measured with pa vdd = 2.5v. d. +9 dbm output for edr measured with pa vdd = 2.5v. e. maximum value is the value r equired for bluetooth qualification. f. meets this spec using a front-end bandpass filter.
document number: 002-14790 rev. *a page 32 of 50 cyw20706 9.2 timing and ac characteristics in this section, use the numbers listed in the re ference column to interp ret the timing diagrams. 9.2.1 startup timing the global reset signal in the cyw20706 is a logical or (actually a wired and, since the signals are active low) of the rst_n i nput and the internal por signals. the last signal to be released dete rmines the time at which the chip is released from reset. the por is typically asserted for 2.4 ms a fter the por threshold is crossed. the following two figures illustrate two startup timing scenarios. figure 8. startup timing table 15. ble rf specifications parameter conditions minimum typical maximum unit frequency range n/a 2402 ? 2480 mhz rx sense a gfsk, 0.1% ber, 1 mbps ? ?96.5 ? dbm tx power b n/a ?9?dbm mod char: delta f1 average n/a 225 255 275 khz mod char: delta f2 max c n/a 99.9 ? ? % mod char: ratio n/a 0.8 0.95 ? % a. dirty tx is off. b. the ble tx power can be increased to compensate for fr ont-end losses such as bpf, diplexer, switch, etc. the output is capped at 12 dbm out. the ble tx power at the antenna port cannot exceed the 10 dbm eirp specification limit. c. at least 99.9% of all delta f2 max frequency values recorded over 10 packets must be greater than 185 khz. vddio vddio por vddc vddc reset vddc reset/share xtal ? 3.96 ms ~ 2.4 ms 0.5 ms 7.5 ms
document number: 002-14790 rev. *a page 33 of 50 cyw20706 9.2.2 usb full-speed timing ta b l e 1 6 through figure 9 shows timing specifications for vdd_usb = 3.3v, v ss = 0v, and t a = 0c to 85c operating temperature range. figure 9. usb full-speed timing table 16. usb full-speed timing specifications reference characteristics minimum maximum unit 1 transition rise time 4 20 ns 2 transition fall time 4 20 ns 3 rise/fall timing matching 90 111 % 4 full-speed data rate 12 ? 0.25% 12 + 0.25% mb/s d+ d- v crs 90% 90% 10% 10% 1 2
document number: 002-14790 rev. *a page 34 of 50 cyw20706 9.2.3 uart timing figure 10. uart timing table 17. uart timi ng specifications ref no. characteristics minimum typical maximum unit 1 delay time uart_cts_n low to uart txd valid. ? ? 1.50 bit periods 2 setup time uart_cts_n high before midpoint of stop bit. ? ? 0.67 bit periods 3 delay time midpoint of stop bit to uart_rts_n high. ? ? 1.33 bit periods uart_cts_n uart_rxd uart_rts_n 1 2 midpoint ? of ? stop ? bit uart_txd midpoint ? of ? stop ? bit 3
document number: 002-14790 rev. *a page 35 of 50 cyw20706 9.2.4 pcm interface timing short frame sync, master mode figure 11. pcm timing diagram (short frame sync, master mode) table 18. pcm interface timing specifications (short frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 20.0 mhz 2 pcm bit clock low 20.0 ? ? ns 3 pcm bit clock high 20.0 ? ? ns 4 pcm_sync delay 0.0 ? 5.7 ns 5 pcm_out delay ?0.4 ? 5.6 ns 6 pcm_in setup 16.9 ? ? ns 7 pcm_in hold 25.0 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance ?0.4 ? 5.6 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high impedance 7
document number: 002-14790 rev. *a page 36 of 50 cyw20706 short frame sync, slave mode figure 12. pcm timing diagram (short frame sync, slave mode) table 19. pcm interface timing specifications (short frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24.0 mhz 2 pcm bit clock low 0.4 ? ? ns 3 pcm bit clock high 18.5 ? ? ns 4 pcm_sync setup 17.0 ? ? ns 5 pcm_sync hold ?0.3 ? ? ns 6 pcm_out delay 3.6 ? 9.5 ns 7 pcm_in setup 18.5 ? ? ns 8 pcm_in hold 0.4 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 3.6 ? 9.5 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high impedance 8
document number: 002-14790 rev. *a page 37 of 50 cyw20706 long frame sync, master mode figure 13. pcm timing diagram (long frame sync, master mode) table 20. pcm interface timing specifications (long frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 20.0 mhz 2 pcm bit clock low 20.0 ? ? ns 3 pcm bit clock high 20.0 ? ? ns 4 pcm_sync delay 0.0 ? 5.7 ns 5 pcm_out delay ?0.4 ? 5.6 ns 6 pcm_in setup 16.9 ? ? ns 7 pcm_in hold 25.0 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance ?0.4 ? 5.6 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high impedance 7 bit 0 bit 0 bit 1 bit 1
document number: 002-14790 rev. *a page 38 of 50 cyw20706 long frame sync, slave mode figure 14. pcm timing diagram (long frame sync, slave mode) table 21. pcm interface timing specifications (long frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24.0 mhz 2 pcm bit clock low 0.4 ? ? ns 3 pcm bit clock high 18.5 ? ? ns 4 pcm_sync setup 17.0 ? ? ns 5 pcm_sync hold don?t care ? ? ns 6 pcm_out delay 3.6 ? 9.5 ns 7 pcm_in setup 18.5 ? ? ns 8 pcm_in hold 0.4 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 3.6 ? 9.5 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high impedance 8 bit 0 bit 0 bit 1 bit 1
document number: 002-14790 rev. *a page 39 of 50 cyw20706 short frame sync, burst mode figure 15. pcm burst mode timing (receive only, short frame sync) table 22. pcm burst mode (receive only, short frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24.0 mhz 2 pcm bit clock low 0.4 ? ? ns 3 pcm bit clock high 18.5 ? ? ns 4 pcm_sync setup 17.0 ? ? ns 5 pcm_sync hold ?0.3 ? ? ns 6 pcm_in setup 18.5 ? ? ns 7 pcm_in hold 25.0 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7
document number: 002-14790 rev. *a page 40 of 50 cyw20706 long frame sync, burst mode figure 16. pcm burst mode timing (receive only, long frame sync) 9.3 i 2 s interface the cyw20706 supports two independent i 2 s digital audio ports. the i 2 s interface supports both master and slave modes. the i 2 s signals are: i 2 s clock: i 2 s sck i 2 s word select: i 2 s ws i 2 s data out: i 2 s sdo i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo always stays as an output. the channel word length is 16 bits and the data is justified so that the msb of the left-channel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the m sb of each data word is transmitt ed one bit clock cycle after the i 2 s ws transition, synchronous with the falling edge of bit clock. left-channel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the cyw20706 are synchronized with the falli ng edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz. table 23. pcm burst mode (receive only, long frame sync) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 24.0 mhz 2 pcm bit clock low 0.4 ? ? ns 3 pcm bit clock high 18.5 ? ? ns 4 pcm_sync setup 17.0 ? ? ns 5 pcm_sync hold don?t care ? ? ns 6 pcm_in setup 18.5 ? ? ns 7 pcm_in hold 25.0 ? ? ns pcm_bclk pcm_sync 1 2 3 4 5 pcm_in 6 7 bit 0 bit 1
document number: 002-14790 rev. *a page 41 of 50 cyw20706 9.3.1 i 2 s timing note: timing values specified in table 24 are relative to high and low threshold levels. note: the time periods specified in figure 17 and figure 18 are defined by the transmitter speed. the receiver specifications must match transmitter performance. table 24. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min max min max min max min max clock period t t tr ???t r ??? a a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. master mode: clock generated by transmitter or receiver high t hc 0.35t tr ? ? ? 0.35t tr ??? b b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for this reason, t hc and t lc are specified with respect to t. lowt lc 0.35t tr ? ? ? 0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ?0.35t tr ???0.35t tr ?? c c. in slave mode, the transmitter and receiver need a clock signal with minimum high and lo w periods so that they can detect the signal. so long as the mi nimum periods are greater than 0.35t r , any clock that meets the requirements can be used. low t lc ?0.35t tr ???0.35t tr ?? c rise time t rc ??0.15t tr ????? d d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . transmitter delay t dtr ???0.8t???? e e. to allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and t, always giving the receiver sufficient setup time. hold time t htr 0??????? d receiver setup time t sr ?????0.2t r ?? f f. the data setup and hold time must not be less than the specified receiver setup and hold time. hold time t hr ?????0?? f
document number: 002-14790 rev. *a page 42 of 50 cyw20706 figure 17. i 2 s transmitter timing figure 18. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t otr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-14790 rev. *a page 43 of 50 cyw20706 9.3.2 bsc interface timing figure 19. bsc interface timing diagram table 25. bsc interface timing specifications reference characteristics minimum maximum unit 1 clock frequency ? 100 400 800 1000 khz 2 start condition setup time 650 ? ns 3 start condition hold time 280 ? ns 4 clock low time 650 ? ns 5 clock high time 280 ? ns 6 data input hold time a a. as a transmitter, 300 ns of delay is provided to bridge th e undefined region of the falling edge of scl to avoid unintended g eneration of start or stop conditions 0?ns 7 data input setup time 100 ? ns 8 stop condition setup time 280 ? ns 9 output valid from clock ? 400 ns 10 bus free time b b. time that the cbus must be free before a new transaction can start. 650 ? ns 2 3 4 5 6 78 9 10 scl sda in sda out 1
document number: 002-14790 rev. *a page 44 of 50 cyw20706 9.3.3 spi timing the spi interface can be clocked up to 12 mhz. ta b l e 2 6 and figure 20 show the timing requirements when operating in spi mode 0 and 2. figure 20. spi timing, mode 0 and 2 table 26. spi mode 0 and 2 reference characteristics minimum maximum unit 1 time from master assert sp i_csn to first clock edge 45 ? ns 2 hold time for mosi data lines 12 ? sck ns 3 time from last sample on mosi/mis o to slave deassert spi_int 0 100 ns 4 time from slave deassert spi_int to master deassert spi_csn 0 ? ns 5 idle time between subsequent spi transactions 1 sck ? ns 2 spi_csn spi_int (directwrite) spi_clk (mode ? 0) spi_mosi first ? bit spi_miso not ? driven first ? bit second ? bit second ? bit last ? bit last ? bit 1 3 4 5 spi_clk (mode ? 2) spi_int (directread) not ? driven
document number: 002-14790 rev. *a page 45 of 50 cyw20706 ta b l e 2 7 and figure 21 show the timing requirements when operating in spi mode 0 and 2. figure 21. spi timing, mode 1 and 3 table 27. spi mode 1 and 3 reference characteristics minimum maximum unit 1 time from master assert spi_csn to first clock edge 45 ? ns 2 hold time for mosi data lines 12 ? sck ns 3 time from last sample on mosi/miso to slave deassert spi_int 0100ns 4 time from slave deassert spi_int to master deassert spi_csn 0?ns 5 idle time between subsequent spi transactions 1 sck ? ns 2 spi_csn spi_int (directwrite) spi_clk (mode ? 1) spi_mosi invalid ? bit spi_miso not ? driven invalid ? bit first ? bit first ? bit last ? bit last ? bit 1 3 4 5 not ? driven spi_clk (mode ? 3) spi_int (directread)
document number: 002-14790 rev. *a page 46 of 50 cyw20706 10. mechanical information figure 22. 49-ball fcbg a mechanical drawing
document number: 002-14790 rev. *a page 47 of 50 cyw20706 10.1 tape, reel, and packing specification figure 23. reel, labeling , and packing specification ? ? ? ? c y p r e s s ? b a r c o d e esd ? warning device ? orientation/mix ? lot ? number each ? reel ? may ? contain ? up ? to ? three ? lot ? numbers, ? independent ? of ? the ? date ? code. individual ? lots ? must ? be ? labeled ? on ? the ? box, ? moisture ? barrier ? bag, ? and ? the ? reel. moisture ? barrier ? bag ? contents/label desiccant ? pouch ? (minimum ? 1) humidity ? indicator ? (minimum ? 1) reel ? (maximum ? 1) pin ? 1 top \ right ? corner ? toward ? sprocket ? holes.
document number: 002-14790 rev. *a page 48 of 50 cyw20706 11. ordering information ta b l e 2 8 provides the available part number and its ordering information. this package is rated from ?30c to +85c. table 28. ordering information part number package type cyw20706ua1kffb1g commercial 49-ball fcbga, 4.5 mm x 4.0 mm x 0.8 mm.
document number: 002-14790 rev. *a page 49 of 49 cyw20706 document history document title: cyw20706 embedded bluetooth 4.2 soc wi th mcu, bluetooth transceiver, and baseband processor document number: 002-14790 revision ecn orig. of change submission date description of change ** ? ? 10/09/2015 20706-ds300-r initial release *a 5451097 utsv 09/29/2016 updated to cypress template
document number: 002-14790 rev. *a revised september 29, 2016 page 50 of 50 cyw20706 ? cypress semiconductor corporation, 2015-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support 50

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