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MB9B160R series 32 - b it arm ? cortex ? - m4f fm4 microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04918 rev.*a revised march 7, 2016 the MB9B160R series are a highly integrated 32 - bit microcontrollers dedicated for embedded controllers with high - performance and competitive cost. these series are based on the arm ? cortex ? - m4f processor with on - chip flash memory and sram, and has peripheral functions such as motor control timers, adcs and communication interfaces (uart, csio, i 2 c, lin). f eatures 32 - bit arm ? cortex ? - m4f core ? processor version: r2p1 ? up to 160 mhz frequency operation ? fpu built - in ? support dsp instruction ? memory protection unit (mpu): improves the reliability of an embedded system ? integrated nested vectored interrupt controller (nvic): 1 nmi (non - maskable interrupt) and 128 peripheral interrupts and 16 priority levels ? 24 - bit system timer (sys tick): system timer for os task management on - chip memories [flash memor y] these series are based on two independent on - chip flash memories. ? mainflash memory ? up to 1024 kbytes ? built - in flash accelerator system with 16 kbytes trace buffer memory ? the read access to flash memory can be achieved without wait - cycle up to operation frequency of 72 mhz. even at the operation frequency more than 72 mhz, an equivalent access to flash memory can be obtained by flash accelerator system. ? security function for code protection ? workfl ash memory ? 32 kbytes ? read cycle: ? 6wait - cycle: the operation frequency more than 120 mhz, and up to 160 mhz ? 4wait - cycle: the operation frequency more than 72 mhz, and up to 120 mhz ? 2wait - cycle: the operation frequency more than 40 mhz, and up to 72 mhz ? 0wai t - cycle: the operation frequency up to 40mhz ? security function is shared with code protection [sram] this is composed of three independent srams (sram0, sram1 and sram2). sram0 is connected to i - code bus or d - code bus of cortex - m4f core. sram1 and sram2 a re connected to system bus of cortex - m4f core. ? sram0: up to 64 kbytes ? sram1: up to 32 kbytes ? sram2: up to 32 kbytes external bus interface ? supports sram, nor, nand flash and sdram device ? up to 9 chip selects cs0 to cs8 (cs8 is only for sdram) ? 8/16 - bit data width ? up to 25 - bit address bit ? supports address/data multiplex ? supports external rdy function ? supports scramble function ? possible to set the validity/invalidity of the scramble function for the external areas 0x6000_0000 to 0xdfff_ffff in 4 mbytes units. ? possible to set two kinds of the scramble key ? note: it is necessary to prepare the dedicated software library to use the scramble function. multi - function serial interface (max 8 channels) ? 64 bytes with fifo (the fifo step numbers are variable depending o n the settings of the communication mode or bit length.) ? operation mode is selectable from the followings for each channel. ? uart ? csio ? lin ? i 2 c
document number: 002 - 04918 rev.*a page 2 of 158 MB9B160R series [uart] ? full - duplex double buffer ? selection with or without parity supported ? built - in dedicated baud rate generat or ? external clock available as a serial clock ? hardware flow control : automatically control the transmission by cts/rts (only ch.4) ? various error detect functions available (parity errors, framing errors, and overrun errors) [csio] ? full - duplex double buffe r ? built - in dedicated baud rate generator ? overrun error detect function available ? serial chip select function (ch.6 and ch.7 only) ? supports high - speed spi (ch.4 and ch.6 only) ? data length 5 to 16 - bit [lin] ? lin protocol rev.2.1 supported ? full - duplex double buffer ? master/slave mode supported ? lin break field generation (can change to 13 to 16 - bit length) ? lin break delimiter generation (can change to 1 to 4 - bit length) ? various error detect functions available (parity errors, framing errors, and overrun errors) [i 2 c] ? standard mode (max 100 kbps) / high - speed mode (max 400 kbps) supported ? fast mode plus (fm+) (max 1000 kbps, only for ch.3 = ch.a and ch.7 = ch.b) supported dma controller (8 channels) dma controller has an independent bus for cpu, so cpu and dma con troller can process simultaneously. ? 8 independently configured and operated channels ? transfer can be started by software or request from the built - in peripherals ? transfer address area: 32 - bit (4 gbytes) ? transfer mode: block transfer/burst transfer/demand t ransfer ? transfer data type: bytes/half - word/word ? transfer block count: 1 to 16 ? number of transfers: 1 to 65536 dstc (descriptor system data transfer controller) (128 channels) the dstc can transfer data at high - speed without going via the cpu. the dstc ado pts the descriptor system and, following the specified contents of the descriptor which has already been constructed on the memory, can access directly the memory /peripheral device and performs the data transfer operation. it supports the software activat ion, the hardware activation and the chain activation functions. a/d converter (max 24 channels) [12 - bit a/d converter] ? successive approximation type ? built - in 3 units ? conversion time: 0.5s @ 5v ? priority conversion available (priority at 2levels) ? scanning conversion mode ? built - in fifo for conversion data storage (for scan conversion: 16steps, for priority conversion: 4steps) da converter (max 2 channels) ? r - 2r type ? 12 - bit resolution base timer (max 8 channels) operation mode is selectable from the followings for each channel. ? 16 - bit pwm timer ? 16 - bit ppg timer ? 16/32 - bit reload timer ? 16/32 - bit pwc timer general purpose i/o port this series can use its pins as general purpose i/o ports when they are not used for external bus or peripherals. moreover, the port r elocate function is built in. it can set which i/o port the peripheral function can be allocated. ? capable of pull - up control per pin ? capable of reading pin level directly ? built - in the port relocate function ? up to 100 high - speed general - purpose i/o ports @ 120pin package ? some pin is 5v tolerant i/o. ? see pin description and i/o circuit type for the corresponding pins.
document number: 002 - 04918 rev.*a page 3 of 158 MB9B160R series multi - function timer (max 2 units) the multi - function timer is composed of the following blocks. minimum resolution : 6.25 ns ? 16 - bit free - run timer 3ch./unit ? input capture 4ch./unit ? output compare 6ch./unit ? a/d activation compare 6ch./unit ? waveform generator 3ch./unit ? 16 - bit ppg timer 3ch./unit the following function can be used to achieve the motor control. ? pwm signal output function ? dc chopper waveform output function ? dead time function ? input capture function ? a/d convertor activate function ? dtif (motor emergency stop) interrupt function real - time clock (rtc) the real - time clock can count year/month/day/hour/minute/second/a da y of the week from 01 to 99. ? interrupt function with specifying date and time (year/month/day/hour/minute/second/a day of the week.) is available. this function is also available by specifying only year, month, day, hour or minute. ? timer interrupt function after set time or each set time . ? capable of rewriting the time with continuing the time count. ? leap year automatic count is available. quadrature position/revolution counter (qprc) (max 2 channels) the quadrature position/revolution counter (qprc) is used to measure the position of the position encoder. moreover, it is possible to use up/down counter. ? the detection edge of the three external event input pins ain, bin and zin is configurable. ? 16 - bit position counter ? 16 - bit revolution counter ? two 16 - bit comp are registers dual timer (32/16 - bit down counter) the dual timer consists of two programmable 32/16 - bit down counters. operation mode is selectable from the followings for each channel. ? free - running ? periodic ( = reload) ? one - shot watch counter the watch counter is used for wake up from the low - power consumption mode. it is possible to select the main clock, sub clock, built - in high - speed cr clock or built - in low - speed cr clock as the clock source. interval timer: up to 64s (max) @ sub clock : 3 2.768 khz external interrupt controller unit ? external interrupt input pin: max 16 pins ? include one non - maskable interrupt (nmi) watchdog timer (2 channels) a watchdog timer can generate interrupts or a reset when a time - out value is reached. this series co nsists of two different watchdogs, a "hardware" watchdog and a "software" watchdog. "hardware" watchdog timer is clocked by low - speed internal cr oscillator. therefore, "hardware" watchdog is active in any power saving mode except stop. crc (cyclic redunda ncy check) accelerator the crc accelerator helps a verify data transmission or storage integrity. ccitt crc16 and ieee - 802.3 crc32 are supported. ? ccitt crc16 generator polynomial: 0x1021 ? ieee - 802.3 crc32 generator polynomial: 0x04c11db7 sd card interface it is possible to use the sd ca r d that conforms to the following standards. ? part 1 physical layer specification version 3.01 ? part e1 sdio specification version 3.00 ? part a2 sd host controller standard specification version 3.00 ? 1 - bit or 4 - bit data bus
document number: 002 - 04918 rev.*a page 4 of 158 MB9B160R series clock and reset [clocks] five clock sources (2 external oscillators, 2 internal cr oscillator, and main pll) that are dynamically selectable. ? main clock : 4 mhz to 48 mhz ? sub clock : 32.768 khz ? high - speed internal cr clock : 4 mhz ? low - speed interna l cr clock : 100 khz ? main pll clock [resets] ? reset requests from initx pin ? power on reset ? software reset ? watchdog timers reset ? low voltage detector reset ? clock supervisor reset clock super visor (csv) clocks generated by internal cr oscillators are used t o supervise abnormality of the external clocks. ? external osc clock failure (clock stop) is detected, reset is asserted. ? external osc frequency anomaly is detected, interrupt or reset is asserted. low - voltage detector (lvd) this series include 2 - stage monit oring of voltage on the vcc pins. when the voltage falls below the voltage has been set, low - voltage detector generates an interrupt or reset. ? lvd1: error reporting via interrupt ? lvd2: auto - reset operation low - power consumption mode six low - power consumption modes are supported. ? sleep ? timer ? rtc ? stop ? deep standby rtc (selectable from with/without ram retention) ? deep standby stop (selectable from with/without ram retention) vbat the consumption power during the rtc operation can be reduced by supplyi ng the power supply independent from the rtc (calendar circuit)/32 khz oscillation circuit. the following circuits can also be used. ? rtc ? 32 khz oscillation circuit ? power - on circuit ? back up register : 32 bytes ? port circuit debug ? serial wire jtag debug port (swj - dp) ? embedded trace macrocells (etm) provide comprehensive debug and trace facilities. unique id unique value of the device (41 - bit) is set. power supply three power supplies ? wide range voltage : vcc = 2.7v to 5.5v ? power supply for vbat : vbat = 2 .7v to 5.5v
document number: 002 - 04918 rev.*a page 5 of 158 MB9B160R series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 7 2. packages ................................ ................................ ................................ ................................ ................................ ........... 8 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 9 4. pin description ................................ ................................ ................................ ................................ ................................ 15 5. i/o circuit type ................................ ................................ ................................ ................................ ............................... 43 6. handling precautions ................................ ................................ ................................ ................................ ..................... 50 6.1 precautions for product design ................................ ................................ ................................ ................................ ... 50 6.2 precautions for package mounting ................................ ................................ ................................ .............................. 51 6.3 precautions for use environment ................................ ................................ ................................ ................................ 52 7. handling devices ................................ ................................ ................................ ................................ ............................ 53 8. block diagram ................................ ................................ ................................ ................................ ................................ . 56 9. memory size ................................ ................................ ................................ ................................ ................................ .... 57 10. memory map ................................ ................................ ................................ ................................ ................................ .... 57 11. pin status in each cpu state ................................ ................................ ................................ ................................ ........ 60 12. electrical characteristics ................................ ................................ ................................ ................................ ............... 67 12.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 67 12.2 recommended operating conditions ................................ ................................ ................................ ......................... 68 12.3 dc characteristics ................................ ................................ ................................ ................................ ...................... 71 12.3.1 current rating ................................ ................................ ................................ ................................ .............................. 71 12.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 78 12.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 80 12.4.1 m ain clock input characteristics ................................ ................................ ................................ ................................ .. 80 12.4.2 sub clock input characteristics ................................ ................................ ................................ ................................ ... 81 12.4.3 built - in cr oscillation characteristics ................................ ................................ ................................ .......................... 81 12.4.4 operating conditions of main pll (in the case of using main clock for input clock of pll) ................................ ......... 82 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr clock for input clock of main pll) .... 82 12.4.6 reset input characteristics ................................ ................................ ................................ ................................ .......... 82 12.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 83 12.4.8 gpio output characteristics ................................ ................................ ................................ ................................ ........ 83 12.4.9 external bus timing ................................ ................................ ................................ ................................ ..................... 84 12.4.10 base timer input timing ................................ ................................ ................................ ................................ ........... 95 12.4.11 uart timing ................................ ................................ ................................ ................................ ............................ 96 12.4.12 external input timing ................................ ................................ ................................ ................................ .............. 129 12.4.13 quadrature position/revolution counter timing ................................ ................................ ................................ .... 130 12.4.14 i 2 c timing ................................ ................................ ................................ ................................ ............................... 132 12.4.15 sd card interface timing ................................ ................................ ................................ ................................ ....... 134 12.4.16 etm timing ................................ ................................ ................................ ................................ ............................ 136 12.4.17 jtag timing ................................ ................................ ................................ ................................ ........................... 137 12.5 12 - bit a/d converter ................................ ................................ ................................ ................................ .................. 138 12.6 12 - bit d/a converter ................................ ................................ ................................ ................................ .................. 141 12.7 l ow - voltage detection characteristics ................................ ................................ ................................ ...................... 142 12.7.1 low - voltage detection reset ................................ ................................ ................................ ................................ ..... 142 12.7.2 interrupt of low - voltage detection ................................ ................................ ................................ ............................. 142 12.8 mainflash memory write/erase characteristics ................................ ................................ ................................ ........ 143 12.9 workflash memory write/erase characteristics ................................ ................................ ................................ ....... 143 12.10 standby recovery time ................................ ................................ ................................ ................................ ............ 144
document number: 002 - 04918 rev.*a page 6 of 158 MB9B160R series 12.10.1 recovery cause: interrupt/wkup ................................ ................................ ................................ ........................... 144 12.10.2 recovery cause: reset ................................ ................................ ................................ ................................ ........... 146 13 . ordering information ................................ ................................ ................................ ................................ .................... 148 14. package dimensions ................................ ................................ ................................ ................................ .................... 149 15. major changes ................................ ................................ ................................ ................................ .............................. 156 document histo ry ................................ ................................ ................................ ................................ ............................... 157
document number: 002 - 04918 rev.*a page 7 of 158 MB9B160R series 1. p roduct l ineup memory s ize product name mb9bf166m/n/r mb9bf167m/n/r mb9bf168m/n/r mainflash memory 512 kbytes 768 kbytes 1024 kbytes workflash memory 32 kbytes 32 kbytes 32 kbytes on - chip sram 64 kbytes 96 kbytes 128 kbytes sram0 32 kbytes 48 kbytes 64 kbytes sram1 16 kbytes 24 kbytes 32 kbytes sram1 16 kbytes 24 kbytes 32 kbytes function product name mb9bf166m mb9bf167m mb9bf168m mb9bf166n mb9bf167n mb9bf168n mb9bf166r mb9bf167r mb9bf168r pin count 80 100/112 120/144 cpu cortex - m4f, mpu, nvic 128ch. freq. 160 mhz power supply voltage range 2.7v to 5.5v dmac 8ch. dstc 128ch. external bus interface addr:19 - bit (max), r/w data: 8 - bit (max), cs:5 (max), sram, nor flash addr:25 - bit (max), r/w data: 8/16 - bit (max), cs:9 (max), sram, nor flash, sdram addr:25 - bit (max), r/w data: 8/16 - bit (max), cs:9 (max), sram, nor flash, nand flash, sdram multi - function serial interface (uart/csio/lin/i 2 c) 8ch. (max) base timer (pwc/reload timer/pwm/ppg) 8ch. (max) mf timer a/d activation compare 6ch. 2 units (max) input capture 4ch. free - run timer 3ch. output compare 6ch. waveform generator 3ch. ppg 3ch. sd card interface 1 unit qprc 2ch. (max) dual timer 1 unit real - time clock 1 unit watch counter 1 unit crc accelerator yes watchdog timer 1ch. (sw) + 1ch. (hw) external interrupts 16pins (max) + nmi 1 i/o ports 63pins (max) 80pins (max) 100pins (max) 12 - bit a/d converter 16ch. (3 units) 24ch. (3 units) 12 - bit d/a converter 2 units (max) csv (clock super visor) yes lvd (low - voltage detector) 2ch. built - in cr high - speed 4 mhz (2%) low - speed 100 khz (typ) debug function swj - dp/etm unique id yes note: all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the i/o port according to your function use.
document number: 002 - 04918 rev.*a page 8 of 158 MB9B160R series 2. packages product name package mb9bf166m mb9bf167m mb9bf168m mb9bf166n mb9bf167n mb9bf168n mb9bf166r mb9bf167r mb9bf168r lqfp: fpt - 80p - m 37 (0.5mm pitch) ? - - lqfp: fpt - 80p - m 40 (0.65mm pitch) ? - - qfp: fpt - 100p - m36 (0.65mm pitch) - ? - lqfp: fpt - 100p - m23 (0.5mm pitch) - ? - lqfp: fpt - 120p - m 37 (0.5mm pitch) - - ? bga: bga - 112p - m05 (0.5mm pitch) - ? - bga: bga - 144p - m09 (0.5mm pitch) - - ? ? : supported note : see "package dimensions" for detailed information on each package.
document number: 002 - 04918 rev.*a page 9 of 158 MB9B160R series 3. pin assignment fpt - 80p - m37/m40 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function regis ter (epfr) to select the pin. vss p81 p80 vcc p60/tioa2_2/sck5_0/nmix/wkup0/mrdy_0 p61/tiob2_2/sot5_0/rtcco_0/subout_0 p62/adtg_3/sin5_0/int04_1/s_wp_0/moex_0 p63/crout_1/int03_0/s_cd_0/mwex_0 p00/trstx/mcsx7_0 p01/tck/swclk p02/tdi/mcsx6_0 p03/tms/swdio p04/tdo/swo p09/an19/tioa3_2/sot1_0/s_data2_0/mcsx5_0 p0a/sin1_0/frck1_0/int12_2/s_data3_0/mcsx1_0 p0b/tiob6_1/sin6_1/ic10_0/int00_1/s_data0_0/mcsx0_0 p0c/tioa6_1/sot6_1/ic11_0/s_data1_0/male_0 p0d/tioa5_2/sck6_1/ic12_0/s_cmd_0/mdqm0_0 p0e/tiob5_2/scs6_1/ic13_0/s_clk_0/mdqm1_0 vcc 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 vcc 1 60 vss p50/cts4_0/ain0_2/rto10_0/int00_0/madata00_0 2 59 p21/an17/sin0_0/int06_1 p51/rts4_0/bin0_2/rto11_0/int01_0/madata01_0 3 58 p22/crout_0/an16/tiob7_1/sot0_0 p52/sck4_0/zin0_2/rto12_0/madata02_0 4 57 p23/an15/tioa7_1/sck0_0/rto00_1 p53/tioa1_2/sot4_0/rto13_0/madata03_0 5 56 p1b/an11/sck4_1/ic02_1/mad18_0 p54/tiob1_2/sin4_0/rto14_0/int02_0/madata04_0 6 55 p1a/an10/sot4_1/ic01_1/mad17_0 p55/adtg_1/sin6_0/rto15_0/int07_2/madata05_0 7 54 p19/an09/sin4_1/ic00_1/int05_1/mad16_0 p56/sot6_0/dtti1x_0/int08_2/madata06_0 8 53 p18/an08/sck2_2/mad15_0 p30/tiob0_1/rts4_2/int15_2/wkup1/madata07_0 9 52 avrh p31/tiob1_1/sin3_1/int09_2/madata08_0 10 51 avrl p32/tiob2_1/sot3_1/int10_1/madata09_0 11 50 avss p33/adtg_6/tiob3_1/sck3_1/int04_0/madata10_0 12 49 avcc p39/adtg_2/dtti0x_0/rtcco_2/subout_2 13 48 p17/an07/sot2_2/wkup3/mad14_0 p3a/tioa0_1/ain0_0/rto00_0 14 47 p16/an06/sin2_2/int14_1/mad13_0 p3b/tioa1_1/bin0_0/rto01_0 15 46 p15/an05/sck0_1/mad12_0 p3c/tioa2_1/zin0_0/rto02_0 16 45 p14/an04/sot0_1/ic03_2/mad11_0 p3d/tioa3_1/rto03_0/mad00_0 17 44 p13/an03/sin0_1/ic02_2/int03_1/mad10_0 p3e/tioa4_1/rto04_0/mad01_0 18 43 p12/an02/sck1_1/ic01_2/rtcco_1/subout_1/mad09_0 p3f/tioa5_1/rto05_0/mad02_0 19 42 p11/an01/sot1_1/ic00_2/mad08_0 vss 20 41 p10/an00/sin1_1/frck0_2/int02_1/mad07_0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 p44/tioa4_0/rto14_1/da0 p45/tiob0_0/rto15_1/da1 initx p46/x0a p47/x1a p48/vregctl p49/vwakeup vbat c vss vcc p4b/tiob1_0/scs7_1/mad03_0 p4c/tiob2_0/sck7_1/ain1_2/mad04_0 p4d/tiob3_0/sot7_1/bin1_2/int13_2/mad05_0 p4e/tiob4_0/sin7_1/zin1_2/frck1_1/int11_1/wkup2/mad06_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 80
document number: 002 - 04918 rev.*a page 10 of 158 MB9B160R series fpt - 100p - m23 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81 p80 vcc p60/tioa2_2/sck5_0/nmix/wkup0/mrdy_0 p61/tiob2_2/sot5_0/rtcco_0/subout_0 p62/adtg_3/sin5_0/int04_1/s_wp_0/moex_0 p63/crout_1/int03_0/s_cd_0/mwex_0 vss p00/trstx/mcsx7_0 p01/tck/swclk p02/tdi/mcsx6_0 p03/tms/swdio p04/tdo/swo p05/an23/adtg_0/traceclk/sin7_0/int01_1/mcsx2_0 p06/an22/traced3/tiob0_2/sot7_0/mcsx3_0 p07/an21/traced2/tioa0_2/sck7_0/mclkout_0 p08/an20/traced1/tiob3_2/sck1_0/mcsx4_0 p09/an19/traced0/tioa3_2/sot1_0/s_data2_0/mcsx5_0 p0a/sin1_0/frck1_0/int12_2/s_data3_0/mcsx1_0 p0b/tiob6_1/sin6_1/ic10_0/int00_1/s_data0_0/mcsx0_0 p0c/tioa6_1/sot6_1/ic11_0/s_data1_0/male_0 p0d/tioa5_2/sck6_1/ic12_0/s_cmd_0/mdqm0_0 p0e/tiob5_2/scs6_1/ic13_0/s_clk_0/mdqm1_0 vcc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 vcc 1 75 vss p50/cts4_0/ain0_2/rto10_0/int00_0/madata00_0 2 74 p20/an18/ain1_1/int05_0/mad24_0 p51/rts4_0/bin0_2/rto11_0/int01_0/madata01_0 3 73 p21/an17/sin0_0/bin1_1/int06_1/mad23_0 p52/sck4_0/zin0_2/rto12_0/madata02_0 4 72 p22/crout_0/an16/tiob7_1/sot0_0/zin1_1 p53/tioa1_2/sot4_0/rto13_0/madata03_0 5 71 p23/an15/tioa7_1/sck0_0/rto00_1/mad22_0 p54/tiob1_2/sin4_0/rto14_0/int02_0/madata04_0 6 70 p1e/an14/adtg_5/frck0_1/mad21_0 p55/adtg_1/sin6_0/rto15_0/int07_2/madata05_0 7 69 p1d/an13/rts4_1/dtti0x_1/mad20_0 p56/sot6_0/dtti1x_0/int08_2/madata06_0 8 68 p1c/an12/cts4_1/ic03_1/mad19_0 p30/tiob0_1/rts4_2/int15_2/wkup1/madata07_0 9 67 p1b/an11/sck4_1/ic02_1/mad18_0 p31/tiob1_1/sin3_1/int09_2/madata08_0 10 66 p1a/an10/sot4_1/ic01_1/mad17_0 p32/tiob2_1/sot3_1/int10_1/madata09_0 11 65 p19/an09/sin4_1/ic00_1/int05_1/mad16_0 p33/adtg_6/tiob3_1/sck3_1/int04_0/madata10_0 12 64 p18/an08/sck2_2/mad15_0 p34/tiob4_1/frck0_0/madata11_0 13 63 avrh p35/tiob5_1/ic03_0/int08_1/madata12_0 14 62 avrl p36/sin5_2/ic02_0/int09_1/madata13_0 15 61 avss p37/sot5_2/ic01_0/int05_2/madata14_0 16 60 avcc p38/sck5_2/ic00_0/int06_2/madata15_0 17 59 p17/an07/sot2_2/wkup3/mad14_0 p39/adtg_2/dtti0x_0/rtcco_2/subout_2/msdclk_0 18 58 p16/an06/sin2_2/int14_1/mad13_0 p3a/tioa0_1/ain0_0/rto00_0/msdcke_0 19 57 p15/an05/sck0_1/mad12_0 p3b/tioa1_1/bin0_0/rto01_0/mrasx_0 20 56 p14/an04/sot0_1/ic03_2/mad11_0 p3c/tioa2_1/zin0_0/rto02_0/mcasx_0 21 55 p13/an03/sin0_1/ic02_2/int03_1/mad10_0 p3d/tioa3_1/rto03_0/mad00_0 22 54 p12/an02/sck1_1/ic01_2/rtcco_1/subout_1/mad09_0 p3e/tioa4_1/rto04_0/mad01_0 23 53 p11/an01/sot1_1/ic00_2/mad08_0 p3f/tioa5_1/rto05_0/mad02_0 24 52 p10/an00/sin1_1/frck0_2/int02_1/mad07_0 vss 25 51 vcc 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1/msdwex_0 p43/adtg_7/tioa3_0/rto13_1/mcsx8_0 p44/tioa4_0/rto14_1/da0 p45/tiob0_0/rto15_1/da1 initx p46/x0a p47/x1a p48/vregctl p49/vwakeup vbat c vss vcc p4b/tiob1_0/scs7_1/mad03_0 p4c/tiob2_0/sck7_1/ain1_2/mad04_0 p4d/tiob3_0/sot7_1/bin1_2/int13_2/mad05_0 p4e/tiob4_0/sin7_1/zin1_2/frck1_1/int11_1/wkup2/mad06_0 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 100
document number: 002 - 04918 rev.*a page 11 of 158 MB9B160R series fpt - 120p - m37 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are mu ltiple pins that provide the same function for the same channel. use the extended port function register (epfr) to select the pin. vss p81 p80 vcc p60/tioa2_2/sck5_0/nmix/wkup0/mrdy_0 p61/tiob2_2/sot5_0/rtcco_0/subout_0 p62/adtg_3/sin5_0/int04_1/s_wp_0/moex_0 p63/crout_1/sin5_1/int03_0/s_cd_0/mwex_0 p64/tioa7_0/sot5_1/int10_2 p65/tiob7_0/sck5_1 p66/adtg_8/sin3_0/int11_2 p67/tioa7_2/sot3_0 p68/tiob7_2/sck3_0/int00_2 vss p00/trstx/mcsx7_0 p01/tck/swclk p02/tdi/mcsx6_0 p03/tms/swdio p04/tdo/swo p05/an23/adtg_0/traceclk/sin7_0/int01_1/mcsx2_0 p06/an22/traced3/tiob0_2/sot7_0/mcsx3_0 p07/an21/traced2/tioa0_2/sck7_0/mclkout_0 p08/an20/traced1/tiob3_2/sck1_0/mcsx4_0 p09/an19/traced0/tioa3_2/sot1_0/s_data2_0/mcsx5_0 p0a/sin1_0/frck1_0/int12_2/s_data3_0/mcsx1_0 p0b/tiob6_1/sin6_1/ic10_0/int00_1/s_data0_0/mcsx0_0 p0c/tioa6_1/sot6_1/ic11_0/s_data1_0/male_0 p0d/tioa5_2/sck6_1/ic12_0/s_cmd_0/mdqm0_0 p0e/tiob5_2/scs6_1/ic13_0/s_clk_0/mdqm1_0 vcc 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 vcc 1 90 vss p50/cts4_0/ain0_2/rto10_0/int00_0/madata00_0 2 89 p20/an18/ain1_1/int05_0/mad24_0 p51/rts4_0/bin0_2/rto11_0/int01_0/madata01_0 3 88 p21/an17/sin0_0/bin1_1/int06_1/mad23_0 p52/sck4_0/zin0_2/rto12_0/madata02_0 4 87 p22/crout_0/an16/tiob7_1/sot0_0/zin1_1 p53/tioa1_2/sot4_0/rto13_0/madata03_0 5 86 p23/an15/tioa7_1/sck0_0/rto00_1/mad22_0 p54/tiob1_2/sin4_0/rto14_0/int02_0/madata04_0 6 85 p24/sin2_1/rto01_1/int01_2 p55/adtg_1/sin6_0/rto15_0/int07_2/madata05_0 7 84 p25/tioa5_0/sot2_1/rto02_1 p56/sot6_0/dtti1x_0/int08_2/madata06_0 8 83 p26/tiob5_0/sck2_1/rto03_1 p57/sck6_0/madata07_0 9 82 p27/tioa6_2/rto04_1/int02_2 p58/sin4_2/ain1_0/int04_2/madata08_0 10 81 p1f/adtg_4/tiob6_2/rto05_1 p59/sot4_2/bin1_0/int07_1/madata09_0 11 80 p1e/an14/adtg_5/frck0_1/mad21_0 p5a/sck4_2/zin1_0/madata10_0 12 79 p1d/an13/rts4_1/dtti0x_1/mad20_0 p5b/cts4_2/madata11_0 13 78 p1c/an12/cts4_1/ic03_1/mad19_0 p30/tiob0_1/rts4_2/int15_2/wkup1/madata12_0 14 77 p1b/an11/sck4_1/ic02_1/mad18_0 p31/tiob1_1/sin3_1/int09_2/madata13_0 15 76 p1a/an10/sot4_1/ic01_1/mad17_0 p32/tiob2_1/sot3_1/int10_1/madata14_0 16 75 p19/an09/sin4_1/ic00_1/int05_1/mad16_0 p33/adtg_6/tiob3_1/sck3_1/int04_0/madata15_0 17 74 p18/an08/sck2_2/mad15_0 p34/tiob4_1/frck0_0/mnale_0 18 73 avrh p35/tiob5_1/ic03_0/int08_1/mncle_0 19 72 avrl p36/sin5_2/ic02_0/int09_1/mnwex_0 20 71 avss p37/sot5_2/ic01_0/int05_2/mnrex_0 21 70 avcc p38/sck5_2/ic00_0/int06_2 22 69 p17/an07/sot2_2/wkup3/mad14_0 p39/adtg_2/dtti0x_0/rtcco_2/subout_2/msdclk_0 23 68 p16/an06/sin2_2/int14_1/mad13_0 p3a/tioa0_1/ain0_0/rto00_0/msdcke_0 24 67 p15/an05/sck0_1/mad12_0 p3b/tioa1_1/bin0_0/rto01_0/mrasx_0 25 66 p14/an04/sot0_1/ic03_2/mad11_0 p3c/tioa2_1/zin0_0/rto02_0/mcasx_0 26 65 p13/an03/sin0_1/ic02_2/int03_1/mad10_0 p3d/tioa3_1/rto03_0/mad00_0 27 64 p12/an02/sck1_1/ic01_2/rtcco_1/subout_1/mad09_0 p3e/tioa4_1/rto04_0/mad01_0 28 63 p11/an01/sot1_1/ic00_2/mad08_0 p3f/tioa5_1/rto05_0/mad02_0 29 62 p10/an00/sin1_1/frck0_2/int02_1/mad07_0 vss 30 61 vcc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1/msdwex_0 p43/adtg_7/tioa3_0/rto13_1/mcsx8_0 p44/tioa4_0/rto14_1/da0 p45/tiob0_0/rto15_1/da1 initx p46/x0a p47/x1a p48/vregctl p49/vwakeup vbat c vss vcc p4b/tiob1_0/scs7_1/mad03_0 p4c/tiob2_0/sck7_1/ain1_2/mad04_0 p4d/tiob3_0/sot7_1/bin1_2/int13_2/mad05_0 p4e/tiob4_0/sin7_1/zin1_2/frck1_1/int11_1/wkup2/mad06_0 p70/tioa4_2/ain0_1/ic13_1 p71/tiob4_2/bin0_1/ic12_1/int15_1 p72/tioa6_0/sin2_0/zin0_1/ic11_1/int14_2 p73/tiob6_0/sot2_0/ic10_1/int03_2 p74/sck2_0/dtti1x_1 pe0/md1 md0 pe2/x0 pe3/x1 vss lqfp - 120
document number: 002 - 04918 rev.*a page 12 of 158 MB9B160R series fpt - 100p - m36 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the r elocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) t o select the pin. p50/cts4_0/ain0_2/rto10_0/int00_0/madata00_0 vcc vss p81 p80 vcc p60/tioa2_2/sck5_0/nmix/wkup0/mrdy_0 p61/tiob2_2/sot5_0/rtcco_0/subout_0 p62/adtg_3/sin5_0/int04_1/s_wp_0/moex_0 p63/crout_1/int03_0/s_cd_0/mwex_0 vss p00/trstx/mcsx7_0 p01/tck/swclk p02/tdi/mcsx6_0 p03/tms/swdio p04/tdo/swo p05/an23/adtg_0/traceclk/sin7_0/int01_1/mcsx2_0 p06/an22/traced3/tiob0_2/sot7_0/mcsx3_0 p07/an21/traced2/tioa0_2/sck7_0/mclkout_0 p08/an20/traced1/tiob3_2/sck1_0/mcsx4_0 p09/an19/traced0/tioa3_2/sot1_0/s_data2_0/mcsx5_0 p0a/sin1_0/frck1_0/int12_2/s_data3_0/mcsx1_0 p0b/tiob6_1/sin6_1/ic10_0/int00_1/s_data0_0/mcsx0_0 p0c/tioa6_1/sot6_1/ic11_0/s_data1_0/male_0 p0d/tioa5_2/sck6_1/ic12_0/s_cmd_0/mdqm0_0 p0e/tiob5_2/scs6_1/ic13_0/s_clk_0/mdqm1_0 vcc vss p20/an18/ain1_1/int05_0/mad24_0 p21/an17/sin0_0/bin1_1/int06_1/mad23_0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p51/rts4_0/bin0_2/rto11_0/int01_0/madata01_0 81 50 p22/crout_0/an16/tiob7_1/sot0_0/zin1_1 p52/sck4_0/zin0_2/rto12_0/madata02_0 82 49 p23/an15/tioa7_1/sck0_0/rto00_1/mad22_0 p53/tioa1_2/sot4_0/rto13_0/madata03_0 83 48 p1e/an14/adtg_5/frck0_1/mad21_0 p54/tiob1_2/sin4_0/rto14_0/int02_0/madata04_0 84 47 p1d/an13/rts4_1/dtti0x_1/mad20_0 p55/adtg_1/sin6_0/rto15_0/int07_2/madata05_0 85 46 p1c/an12/cts4_1/ic03_1/mad19_0 p56/sot6_0/dtti1x_0/int08_2/madata06_0 86 45 p1b/an11/sck4_1/ic02_1/mad18_0 p30/tiob0_1/rts4_2/int15_2/wkup1/madata07_0 87 44 p1a/an10/sot4_1/ic01_1/mad17_0 p31/tiob1_1/sin3_1/int09_2/madata08_0 88 43 p19/an09/sin4_1/ic00_1/int05_1/mad16_0 p32/tiob2_1/sot3_1/int10_1/madata09_0 89 42 p18/an08/sck2_2/mad15_0 p33/adtg_6/tiob3_1/sck3_1/int04_0/madata10_0 90 41 avrh p34/tiob4_1/frck0_0/madata11_0 91 40 avrl p35/tiob5_1/ic03_0/int08_1/madata12_0 92 39 avss p36/sin5_2/ic02_0/int09_1/madata13_0 93 38 avcc p37/sot5_2/ic01_0/int05_2/madata14_0 94 37 p17/an07/sot2_2/wkup3/mad14_0 p38/sck5_2/ic00_0/int06_2/madata15_0 95 36 p16/an06/sin2_2/int14_1/mad13_0 p39/adtg_2/dtti0x_0/rtcco_2/subout_2/msdclk_0 96 35 p15/an05/sck0_1/mad12_0 p3a/tioa0_1/ain0_0/rto00_0/msdcke_0 97 34 p14/an04/sot0_1/ic03_2/mad11_0 p3b/tioa1_1/bin0_0/rto01_0/mrasx_0 98 33 p13/an03/sin0_1/ic02_2/int03_1/mad10_0 p3c/tioa2_1/zin0_0/rto02_0/mcasx_0 99 32 p12/an02/sck1_1/ic01_2/rtcco_1/subout_1/mad09_0 p3d/tioa3_1/rto03_0/mad00_0 100 31 p11/an01/sot1_1/ic00_2/mad08_0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 p3e/tioa4_1/rto04_0/mad01_0 p3f/tioa5_1/rto05_0/mad02_0 vss vcc p40/tioa0_0/rto10_1/int12_1 p41/tioa1_0/rto11_1/int13_1 p42/tioa2_0/rto12_1/msdwex_0 p43/adtg_7/tioa3_0/rto13_1/mcsx8_0 p44/tioa4_0/rto14_1/da0 p45/tiob0_0/rto15_1/da1 initx p46/x0a p47/x1a p48/vregctl p49/vwakeup vbat c vss vcc p4b/tiob1_0/scs7_1/mad03_0 p4c/tiob2_0/sck7_1/ain1_2/mad04_0 p4d/tiob3_0/sot7_1/bin1_2/int13_2/mad05_0 p4e/tiob4_0/sin7_1/zin1_2/frck1_1/int11_1/wkup2/mad06_0 pe0/md1 md0 pe2/x0 pe3/x1 vss vcc p10/an00/sin1_1/frck0_2/int02_1/mad07_0 qfp - 100
document number: 002 - 04918 rev.*a page 13 of 158 MB9B160R series bga - 112p - m05 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) t o select the pin. vss x0 x1 vss vcc md1 md0 vss n vss p40 p41 vss x0a x1a vss vbat p49 vcc p4d c vss an01 an00 m vcc vss p42 p44 vss initx p45 p48 p4b p4c p4e an03 an02 l p3e p3f p43 an04 k p3c p3d an06 an05 an08 an07 avcc j p39 p3a p3b an10 an09 avss h vss p37 p38 g p34 p35 p36 an12 an11 avrl an14 an13 avrh f p31 p32 p33 an16 an15 e p55 p56 p30 an20 vss an18 an17 d p53 p54 vcc c p50 p51 p52 p63 tdi tdo/ swo an23 tms/ swdio an22 an19 p0c p0d vss p0e vss b vcc vss p60 p61 p62 trstx tck/ swclk vss an21 p0a p0b vss a vss p81 p80 vcc vss 8 9 10 11 12 13 1 2 3 4 5 6 7 index
document number: 002 - 04918 rev.*a page 14 of 158 MB9B160R series bga - 144p - m09 (top view) note: the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the same channel. use the extended port function register ( epfr) to select the pin. md1 x0 x1 vss vcc p73 md0 vss n vss p40 p42 initx x0a vss vbat c vss p4d vcc vss vss an00 vss m vcc vss p43 vss x1a vss vss p48 p4b p4e p71 p74 p72 vss an02 an01 avcc l p3f p41 vss p44 avss k vss p3d p3e vss p45 p49 p4c p70 an05 an04 an03 an07 an06 avrl j p39 p3a p3b p3c an08 an11 an10 an09 avrh h p35 p36 p37 p38 g p31 p32 p33 p34 p1f an14 an13 an12 p24 p25 p26 p27 f p59 p5a p5b p30 an17 an16 an15 e p55 p56 p57 p58 p65 trstx tms/ swdio an22 p0a vss an19 p0d vss an18 vss d p52 p53 p54 vss p0e c p50 p51 vss p62 p64 p68 tdi an23 tck/ swclk tdo/ swo an20 p0b vss vss vcc vss b vcc vss p60 p61 p63 p67 p66 vss vss an21 vss p0c a vss p81 p80 vcc vss 8 9 10 11 12 13 7 1 2 3 4 5 6 index
document number: 002 - 04918 rev.*a page 15 of 158 MB9B160R series 4. pin description list of pin numbers the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pin s, there are multiple pins that provide the same function for the sa me channel. use the extended port function register (epfr) to select the pin. pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 1 1 1 79 b1 b1 vcc - - 2 2 2 80 c1 c1 p50 e k cts4_0 ain0_2 rto10_0 (ppg10_0) int00_0 madata00_0 3 3 3 81 c2 c2 p51 e k rts4_0 bin0_2 rto11_0 (ppg10_0) int01_0 madata01_0 4 4 4 82 c3 d1 p52 e i sck4_0 (scl4_0) zin0_2 rto12_0 (ppg12_0) madata02_0 5 5 5 83 d1 d2 p53 e i tioa1_2 sot4_0 (sda4_0) rto13_0 (ppg12_0) madata03_0 6 6 6 84 d2 d3 p54 e k tiob1_2 sin4_0 rto14_0 (ppg14_0) int02_0 madata04_0 7 7 7 85 e1 e1 p55 e k adtg_1 sin6_0 rto15_0 (ppg14_0) int07_2 madata05_0
document number: 002 - 04918 rev.*a page 16 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 8 8 8 86 e2 e2 p56 e k sot6_0 (sda6_0) dtti1x_0 int08_2 madata06_0 9 - - - - e3 p57 e i sck6_0 (scl6_0) madata07_0 10 - - - - e4 p58 e k sin4_2 ain1_0 int04_2 madata08_0 11 - - - - f1 p59 e k sot4_2 (sda4_2) bin1_0 int07_1 madata09_0 12 - - - - f2 p5a e i sck4_2 (scl4_2) zin1_0 madata10_0 13 - - - - f3 p5b e i cts4_2 madata11_0 14 9 9 87 e3 f4 p30 e q tiob0_1 rts4_2 int15_2 wkup1 - - madata07_0 14 - - - - f4 madata12_0 15 10 10 88 f1 g1 p31 i k tiob1_1 sin3_1 int09_2 - - madata08_0 15 - - - - g1 madata13_0
document number: 002 - 04918 rev.*a page 17 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 16 11 11 89 f2 g2 p32 n k tiob2_1 sot3_1 (sda3_1) int10_1 - - madata09_0 16 - - - - g2 madata14_0 17 12 12 90 f3 g3 p33 n k adtg_6 tiob3_1 sck3_1 (scl3_1) int04_0 - - madata10_0 17 - - - - g3 madata15_0 18 13 - 91 g1 g4 p34 e i tiob4_1 frck0_0 - - madata11_0 18 - - - - g4 mnale_0 19 14 - 92 g2 h1 p35 e k tiob5_1 ic03_0 int08_1 - - madata12_0 19 - - - - h1 mncle_0
document number: 002 - 04918 rev.*a page 18 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 20 15 - 93 g3 h2 p36 e k sin5_2 ic02_0 int09_1 - - madata13_0 20 - - - - h2 mnwex_0 21 16 - 94 h2 h3 p37 e k sot5_2 (sda5_2) ic01_0 int05_2 - - madata14_0 21 - - - - h3 mnrex_0 22 17 - 95 h3 h4 p38 e k sck5_2 (scl5_2) ic00_0 int06_2 - - madata15_0 23 18 13 96 j1 j1 p39 l i adtg_2 dtti0x_0 rtcco_2 subout_2 - msdclk_0 24 19 14 97 j2 j2 p3a g i tioa0_1 ain0_0 rto00_0 (ppg00_0) - msdcke_0 25 20 15 98 j3 j3 p3b g i tioa1_1 bin0_0 rto01_0 (ppg00_0) - mrasx_0
document number: 002 - 04918 rev.*a page 19 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 26 21 16 99 k1 j4 p3c g i tioa2_1 zin0_0 rto02_0 (ppg02_0) - mcasx_0 27 22 17 100 k2 k2 p3d g i tioa3_1 rto03_0 (ppg02_0) mad00_0 28 23 18 1 l1 k3 p3e g i tioa4_1 rto04_0 (ppg04_0) mad01_0 29 24 19 2 l2 l1 p3f g i tioa5_1 rto05_0 (ppg04_0) mad02_0 30 25 20 3 n1 n1 vss - - 31 26 - 4 m1 m1 vcc - - 32 27 - 5 n2 n2 p40 g k tioa0_0 rto10_1 (ppg10_1) int12_1 33 28 - 6 n3 l2 p41 g k tioa1_0 rto11_1 (ppg10_1) int13_1 34 29 - 7 m3 n3 p42 g i tioa2_0 rto12_1 (ppg12_1) msdwex_0 35 30 - 8 l3 m3 p43 g i adtg_7 tioa3_0 rto13_1 (ppg12_1) mcsx8_0
document number: 002 - 04918 rev.*a page 20 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 36 31 21 9 m4 l4 p44 r j tioa4_0 rto14_1 (ppg14_1) da0 37 32 22 10 l5 k5 p45 r j tiob0_0 rto15_1 (ppg14_1) da1 38 33 23 11 m6 n4 initx b c 39 34 24 12 n5 n5 p46 p s x0a 40 35 25 13 n6 m5 p47 q t x1a 41 36 26 14 l6 l6 p48 o u vregctl 42 37 27 15 m7 k6 p49 o u vwakeup 43 38 28 16 n8 n7 vbat - - 44 39 29 17 n9 n8 c - - 45 40 30 18 n10 n9 vss - - 46 41 31 19 m8 m9 vcc - - 47 42 32 20 l7 l7 p4b e i tiob1_0 scs7_1 mad03_0 48 43 33 21 l8 k7 p4c n i tiob2_0 sck7_1 (scl7_1) ain1_2 mad04_0 49 44 34 22 m9 m8 p4d n k tiob3_0 sot7_1 (sda7_1) bin1_2 int13_2 mad05_0 50 45 35 23 l9 l8 p4e i q tiob4_0 sin7_1 zin1_2 frck1_1 int11_1 wkup2 mad06_0
document number: 002 - 04918 rev.*a page 21 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 51 - - - - k8 p70 e i tioa4_2 ain0_1 ic13_1 52 - - - - l9 p71 e k tiob4_2 bin0_1 ic12_1 int15_1 53 - - - - k9 p72 e k tioa6_0 sin2_0 zin0_1 ic11_1 int14_2 54 - - - - m10 p73 e k tiob6_0 sot2_0 (sda2_0) ic10_1 int03_2 55 - - - - l10 p74 e i sck2_0 (scl2_0) dtti1x_1 56 46 36 24 m10 n10 pe0 c e md1 57 47 37 25 m11 m11 md0 j d 58 48 38 26 n11 n11 pe2 a a x0 59 49 39 27 n12 n12 pe3 a b x1 60 50 40 28 n13 n13 vss - - 61 51 - 29 m13 m13 vcc - - 62 52 41 30 l13 l12 p10 f m an00 sin1_1 frck0_2 int02_1 mad07_0 63 53 42 31 l12 k12 p11 f l an01 sot1_1 (sda1_1) ic00_2 mad08_0
document number: 002 - 04918 rev.*a page 22 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 64 54 43 32 k13 k11 p12 f l an02 sck1_1 (scl1_1) ic01_2 rtcco_1 subout_1 mad09_0 65 55 44 33 k12 j12 p13 f m an03 sin0_1 ic02_2 int03_1 mad10_0 66 56 45 34 j13 j11 p14 f l an04 sot0_1 (sda0_1) ic03_2 mad11_0 67 57 46 35 j12 j10 p15 f l an05 sck0_1 (scl0_1) mad12_0 68 58 47 36 j11 h12 p16 f m an06 sin2_2 int14_1 mad13_0 69 59 48 37 h12 h11 p17 f p an07 sot2_2 (sda2_2) wkup3 mad14_0 70 60 49 38 h13 k13 avcc - - 71 61 50 39 g13 j13 avss - - 72 62 51 40 f13 h13 avrl - - 73 63 52 41 e13 g13 avrh - - 74 64 53 42 h11 h10 p18 f l an08 sck2_2 (scl2_2) mad15_0
document number: 002 - 04918 rev.*a page 23 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 75 65 54 43 g12 g12 p19 f m an09 sin4_1 ic00_1 int05_1 mad16_0 76 66 55 44 g11 g11 p1a m l an10 sot4_1 (sda4_1) ic01_1 mad17_0 77 67 56 45 f12 g10 p1b m l an11 sck4_1 (scl4_1) ic02_1 mad18_0 78 68 - 46 f11 f13 p1c f l an12 cts4_1 ic03_1 mad19_0 79 69 - 47 e12 f12 p1d f l an13 rts4_1 dtti0x_1 mad20_0 80 70 - 48 e11 f11 p1e f l an14 adtg_5 frck0_1 mad21_0 81 - - - - f10 p1f e i adtg_4 tiob6_2 rto05_1 (ppg04_1) 82 - - - - e13 p27 e k tioa6_2 rto04_1 (ppg04_1) int02_2
document number: 002 - 04918 rev.*a page 24 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 83 - - - - e12 p26 e i tiob5_0 sck2_1 (scl2_1) rto03_1 (ppg02_1) 84 - - - - e11 p25 e i tioa5_0 sot2_1 (sda2_1) rto02_1 (ppg02_1) 85 - - - - e10 p24 e k sin2_1 rto01_1 (ppg00_1) int01_2 86 71 57 49 d13 d13 p23 f l an15 tioa7_1 sck0_0 (scl0_0) rto00_1 (ppg00_1) - mad22_0 87 72 58 50 d12 d12 p22 f l crout_0 an16 tiob7_1 sot0_0 (sda0_0) - zin1_1 88 73 59 51 c13 d11 p21 f m an17 sin0_0 - bin1_1 59 int06_1 - mad23_0 89 74 - 52 c12 c12 p20 f m an18 ain1_1 int05_0 mad24_0 90 75 60 53 a13 a13 vss - - 91 76 61 54 b13 a12 vcc - -
document number: 002 - 04918 rev.*a page 25 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 92 77 62 55 a12 b13 p0e l i tiob5_2 scs6_1 ic13_0 s_clk_0 mdqm1_0 93 78 63 56 b11 c10 p0d l i tioa5_2 sck6_1 (scl6_1) ic12_0 s_cmd_0 mdqm0_0 94 79 64 57 b10 a11 p0c l i tioa6_1 sot6_1 (sda6_1) ic11_0 s_data1_0 male_0 95 80 65 58 a10 b10 p0b l k tiob6_1 sin6_1 ic10_0 int00_1 s_data0_0 mcsx0_0 96 81 66 59 a9 d9 p0a l k sin1_0 frck1_0 int12_2 s_data3_0 mcsx1_0 97 82 67 60 b9 c9 p09 m n an19 - traced0 67 tioa3_2 sot1_0 (sda1_0) s_data2_0 mcsx5_0 98 83 - 61 c9 b9 p08 f n an20 traced1 tiob3_2 sck1_0 (scl1_0) mcsx4_0
document number: 002 - 04918 rev.*a page 26 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 99 84 - 62 a8 a9 p07 f n an21 traced2 tioa0_2 sck7_0 (scl7_0) mclkout_0 100 85 - 63 b8 d8 p06 f n an22 traced3 tiob0_2 sot7_0 (sda7_0) mcsx3_0 101 86 - 64 c8 c8 p05 f o an23 adtg_0 traceclk sin7_0 int01_1 mcsx2_0 102 87 68 65 c7 b8 p04 e g tdo swo 103 88 69 66 b7 d7 p03 e g tms swdio 104 89 70 67 c6 c7 p02 e h tdi mcsx6_0 105 90 71 68 a6 b7 p01 e g tck swclk 106 91 72 69 b6 d6 p00 e h trstx mcsx7_0 107 92 - 70 a5 a7 vss - - 108 - - - - c6 p68 e k tiob7_2 sck3_0 (scl3_0) int00_2 109 - - - - b6 p67 e i tioa7_2 sot3_0 (sda3_0)
document number: 002 - 04918 rev.*a page 27 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 110 - - - - a6 p66 e k adtg_8 sin3_0 int11_2 111 - - - - d5 p65 e i tiob7_0 sck5_1 (scl5_1) 112 - - - - c5 p64 e k tioa7_0 sot5_1 (sda5_1) int10_2 113 93 73 71 c5 b5 p63 e k crout_1 - - - - sin5_1 93 73 71 c5 int03_0 s_cd_0 mwex_0 114 94 74 72 b5 c4 p62 i k adtg_3 sin5_0 int04_1 s_wp_0 moex_0 115 95 75 73 b4 b4 p61 e i tiob2_2 sot5_0 (sda5_0) rtcco_0 subout_0 116 96 76 74 b3 b3 p60 i f tioa2_2 sck5_0 (scl5_0) nmix wkup0 mrdy_0 117 97 77 75 a4 a4 vcc - - 118 98 78 76 a3 a3 p80 h r 119 99 79 77 a2 a2 p81 h r
document number: 002 - 04918 rev.*a page 28 of 158 MB9B160R series pin no pin name i/o circuit type pin state type lqfp120 lqfp100 lqfp80 qfp100 bga112 bga144 120 100 80 78 a1 a1 vss - - - - - - a7 a5 - - - - - - b2 a8 - - - - - - b12 a10 - - - - - - c11 b2 - - - - - - h1 b11 - - - - - - n4 b12 - - - - - - m5 c3 - - - - - - n7 c11 - - - - - - l11 c13 - - - - - - a11 d4 - - - - - - m12 d10 - - - - - - m2 k1 - - - - - - - k4 - - - - - - - k10 - - - - - - - l3 - - - - - - - l5 - - - - - - - l11 - - - - - - - l13 - - - - - - - m2 - - - - - - - m4 - - - - - - - m6 - - - - - - - m7 - - - - - - - m12 - - - - - - - n6 - -
document number: 002 - 04918 rev.*a page 29 of 158 MB9B160R series list of pin functions the number after the underscore ("_") in pin names such as xxx_1 and xxx_2 indicates the relocated port number. for these pins, there are multiple pins that provide the same function for the same channel. use the extended port function register (epfr) t o select the pin. pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 adc adtg_0 a/d converter external trigger input pin 101 86 - 64 c8 c8 adtg_1 7 7 7 85 e1 e1 adtg_2 23 18 13 96 j1 j1 adtg_3 114 94 74 72 b5 c4 adtg_4 81 - - - - f10 adtg_5 80 70 - 48 e11 f11 adtg_6 17 12 12 90 f3 g3 adtg_7 35 30 - 8 l3 m3 adtg_8 110 - - - - a6 an00 a/d converter analog input pin. anxx describes adc ch.xx. 62 52 41 30 l13 l12 an01 63 53 42 31 l12 k12 an02 64 54 43 32 k13 k11 an03 65 55 44 33 k12 j12 an04 66 56 45 34 j13 j11 an05 67 57 46 35 j12 j10 an06 68 58 47 36 j11 h12 an07 69 59 48 37 h12 h11 an08 74 64 53 42 h11 h10 an09 75 65 54 43 g12 g12 an10 76 66 55 44 g11 g11 an11 77 67 56 45 f12 g10 an12 78 68 - 46 f11 f13 an13 79 69 - 47 e12 f12 an14 80 70 - 48 e11 f11 an15 86 71 57 49 d13 d13 an16 87 72 58 50 d12 d12 an17 88 73 59 51 c13 d11 an18 89 74 - 52 c12 c12 an19 97 82 67 60 b9 c9 an20 98 83 - 61 c9 b9 an21 99 84 - 62 a8 a9 an22 100 85 - 63 b8 d8 an23 101 86 - 64 c8 c8 base timer 0 tioa0_0 base timer ch.0 tioa pin 32 27 - 5 n2 n2 tioa0_1 24 19 14 97 j2 j2 tioa0_2 99 84 - 62 a8 a9 tiob0_0 base timer ch.0 tiob pin 37 32 22 10 l5 k5 tiob0_1 14 9 9 87 e3 f4 tiob0_2 100 85 - 63 b8 d8 base timer 1 tioa1_0 base timer ch.1 tioa pin 33 28 - 6 n3 l2 tioa1_1 25 20 15 98 j3 j3 tioa1_2 5 5 5 83 d1 d2 tiob1_0 base timer ch.1 tiob pin 47 42 32 20 l7 l7 tiob1_1 15 10 10 88 f1 g1 tiob1_2 6 6 6 84 d2 d3 base timer 2 tioa2_0 base timer ch.2 tioa pin 34 29 - 7 m3 n3 tioa2_1 26 21 16 99 k1 j4 tioa2_2 116 96 76 74 b3 b3 tiob2_0 base timer ch.2 tiob pin 48 43 33 21 l8 k7 tiob2_1 16 11 11 89 f2 g2 tiob2_2 115 95 75 73 b4 b4
document number: 002 - 04918 rev.*a page 30 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 base timer 3 tioa3_0 base timer ch.3 tioa pin 35 30 - 8 l3 m3 tioa3_1 27 22 17 100 k2 k2 tioa3_2 97 82 67 60 b9 c9 tiob3_0 base timer ch.3 tiob pin 49 44 34 22 m9 m8 tiob3_1 17 12 12 90 f3 g3 tiob3_2 98 83 - 61 c9 b9 base timer 4 tioa4_0 base timer ch.4 tioa pin 36 31 21 9 m4 l4 tioa4_1 28 23 18 1 l1 k3 tioa4_2 51 - - - - k8 tiob4_0 base timer ch.4 tiob pin 50 45 35 23 l9 l8 tiob4_1 18 13 - 91 g1 g4 tiob4_2 52 - - - - l9 base timer 5 tioa5_0 base timer ch.5 tioa pin 84 - - - - e11 tioa5_1 29 24 19 2 l2 l1 tioa5_2 93 78 63 56 b11 c10 tiob5_0 base timer ch.5 tiob pin 83 - - - - e12 tiob5_1 19 14 - 92 g2 h1 tiob5_2 92 77 62 55 a12 b13 base timer 6 tioa6_0 base timer ch.6 tioa pin 53 - - - - k9 tioa6_1 94 79 64 57 b10 a11 tioa6_2 82 - - - - e13 tiob6_0 base timer ch.6 tiob pin 54 - - - - m10 tiob6_1 95 80 65 58 a10 b10 tiob6_2 81 - - - - f10 base timer 7 tioa7_0 base timer ch.7 tioa pin 112 - - - - c5 tioa7_1 86 71 57 49 d13 d13 tioa7_2 109 - - - - b6 tiob7_0 base timer ch.7 tiob pin 111 - - - - d5 tiob7_1 87 72 58 50 d12 d12 tiob7_2 108 - - - - c6 debugger swclk serial wire debug interface clock input pin 105 90 71 68 a6 b7 swdio serial wire debug interface data input / output pin 103 88 69 66 b7 d7 swo serial wire viewer output pin 102 87 68 65 c7 b8 tck j - tag test clock input pin 105 90 71 68 a6 b7 tdi j - tag test data input pin 104 89 70 67 c6 c7 tdo j - tag debug data output pin 102 87 68 65 c7 b8 tms j - tag test mode state input/output pin 103 88 69 66 b7 d7 traceclk trace clk output pin of etm 101 86 - 64 c8 c8 traced0 trace data output pin of etm 97 82 - 60 b9 c9 traced1 98 83 - 61 c9 b9 traced2 99 84 - 62 a8 a9 traced3 100 85 - 63 b8 d8 trstx j - tag test reset input pin 106 91 72 69 b6 d6
document number: 002 - 04918 rev.*a page 31 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 external bus mad00_0 external bus interface address bus 27 22 17 100 k2 k2 mad01_0 28 23 18 1 l1 k3 mad02_0 29 24 19 2 l2 l1 mad03_0 47 42 32 20 l7 l7 mad04_0 48 43 33 21 l8 k7 mad05_0 49 44 34 22 m9 m8 mad06_0 50 45 35 23 l9 l8 mad07_0 62 52 41 30 l13 l12 mad08_0 63 53 42 31 l12 k12 mad09_0 64 54 43 32 k13 k11 mad10_0 65 55 44 33 k12 j12 mad11_0 66 56 45 34 j13 j11 mad12_0 67 57 46 35 j12 j10 mad13_0 68 58 47 36 j11 h12 mad14_0 69 59 48 37 h12 h11 mad15_0 74 64 53 42 h11 h10 mad16_0 75 65 54 43 g12 g12 mad17_0 76 66 55 44 g11 g11 mad18_0 77 67 56 45 f12 g10 mad19_0 78 68 - 46 f11 f13 mad20_0 79 69 - 47 e12 f12 mad21_0 80 70 - 48 e11 f11 mad22_0 86 71 - 49 d13 d13 mad23_0 88 73 - 51 c13 d11 mad24_0 89 74 - 52 c12 c12
document number: 002 - 04918 rev.*a page 32 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 external bus mcsx0_0 external bus interface chip select output pin 95 80 65 58 a10 b10 mcsx1_0 96 81 66 59 a9 d9 mcsx2_0 101 86 - 64 c8 c8 mcsx3_0 100 85 - 63 b8 d8 mcsx4_0 98 83 - 61 c9 b9 mcsx5_0 97 82 67 60 b9 c9 mcsx6_0 104 89 70 67 c6 c7 mcsx7_0 106 91 72 69 b6 d6 mcsx8_0 35 30 - 8 l3 m3 madata00_0 external bus interface data bus (address / data multiplex bus) 2 2 2 80 c1 c1 madata01_0 3 3 3 81 c2 c2 madata02_0 4 4 4 82 c3 d1 madata03_0 5 5 5 83 d1 d2 madata04_0 6 6 6 84 d2 d3 madata05_0 7 7 7 85 e1 e1 madata06_0 8 8 8 86 e2 e2 madata07_0 9 9 9 87 e3 e3 madata08_0 10 10 10 88 f1 e4 madata09_0 11 11 11 89 f2 f1 madata10_0 12 12 12 90 f3 f2 madata11_0 13 13 - 91 g1 f3 madata12_0 14 14 - 92 g2 f4 madata13_0 15 15 - 93 g3 g1 madata14_0 16 16 - 94 h2 g2 madata15_0 17 17 - 95 h3 g3 mdqm0_0 external bus interface byte mask signal output pin 93 78 63 56 b11 c10 mdqm1_0 92 77 62 55 a12 b13 male_0 external bus interface address latch enable output signal for multiplex 94 79 64 57 b10 a11 mrdy_0 external bus interface external rdy input signal 116 96 76 74 b3 b3 mclkout_0 external bus interface external clock output pin 99 84 - 62 a8 a9 mnale_0 external bus interface ale signal to control nand flash output pin 18 - - - - g4 mncle_0 external bus interface cle signal to control nand flash output pin 19 - - - - h1 mnrex_0 external bus interface read enable signal to control nand flash 21 - - - - h3 mnwex_0 external bus interface write enable signal to control nand flash 20 - - - - h2 moex_0 external bus interface read enable signal for sram 114 94 74 72 b5 c4 mwex_0 external bus interface write enable signal for sram 113 93 73 71 c5 b5 external bus msdclk_0 sdram interface sdram clock output pin 23 18 - 96 j1 j1 msdcke_0 sdram interface sdram clock enable pin 24 19 - 97 j2 j2 mrasx_0 sdram interface sdram row address strobe pin 25 20 - 98 j3 j3 mcasx_0 sdram interface sdram column address strobe pin 26 21 - 99 k1 j4 msdwex_0 sdram interface sdram write enable pin 34 29 - 7 m3 n3
document number: 002 - 04918 rev.*a page 33 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 external interrupt int00_0 external interrupt request 00 input pin 2 2 2 80 c1 c1 int00_1 95 80 65 58 a10 b10 int00_2 108 - - - - c6 int01_0 external interrupt request 01 input pin 3 3 3 81 c2 c2 int01_1 101 86 - 64 c8 c8 int01_2 85 - - - - e10 int02_0 external interrupt request 02 input pin 6 6 6 84 d2 d3 int02_1 62 52 41 30 l13 l12 int02_2 82 - - - - e13 int03_0 external interrupt request 03 input pin 113 93 73 71 c5 b5 int03_1 65 55 44 33 k12 j12 int03_2 54 - - - - m10 int04_0 external interrupt request 04 input pin 17 12 12 90 f3 g3 int04_1 114 94 74 72 b5 c4 int04_2 10 - - - - e4 int05_0 external interrupt request 05 input pin 89 74 - 52 c12 c12 int05_1 75 65 54 43 g12 g12 int05_2 21 16 - 94 h2 h3 int06_1 external interrupt request 06 input pin 88 73 59 51 c13 d11 int06_2 22 17 - 95 h3 h4 int07_1 external interrupt request 07 input pin 11 - - - - f1 int07_2 7 7 7 85 e1 e1 int08_1 external interrupt request 08 input pin 19 14 - 92 g2 h1 int08_2 8 8 8 86 e2 e2 int09_1 external interrupt request 09 input pin 20 15 - 93 g3 h2 int09_2 15 10 10 88 f1 g1 int10_1 external interrupt request 10 input pin 16 11 11 89 f2 g2 int10_2 112 - - - - c5 int11_1 external interrupt request 11 input pin 50 45 35 23 l9 l8 int11_2 110 - - - - a6 int12_1 external interrupt request 12 input pin 32 27 - 5 n2 n2 int12_2 96 81 66 59 a9 d9 int13_1 external interrupt request 13 input pin 33 28 - 6 n3 l2 int13_2 49 44 34 22 m9 m8 int14_1 external interrupt request 14 input pin 68 58 47 36 j11 h12 int14_2 53 - - - - k9 int15_1 external interrupt request 15 input pin 52 - - - - l9 int15_2 14 9 9 87 e3 f4 nmix non - maskable interrupt input pin 116 96 76 74 b3 b3
document number: 002 - 04918 rev.*a page 34 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 gpio p00 general - purpose i/o port 0 106 91 72 69 b6 d6 p01 105 90 71 68 a6 b7 p02 104 89 70 67 c6 c7 p03 103 88 69 66 b7 d7 p04 102 87 68 65 c7 b8 p05 101 86 - 64 c8 c8 p06 100 85 - 63 b8 d8 p07 99 84 - 62 a8 a9 p08 98 83 - 61 c9 b9 p09 97 82 67 60 b9 c9 p0a 96 81 66 59 a9 d9 p0b 95 80 65 58 a10 b10 p0c 94 79 64 57 b10 a11 p0d 93 78 63 56 b11 c10 p0e 92 77 62 55 a12 b13 p10 general - purpose i/o port 1 62 52 41 30 l13 l12 p11 63 53 42 31 l12 k12 p12 64 54 43 32 k13 k11 p13 65 55 44 33 k12 j12 p14 66 56 45 34 j13 j11 p15 67 57 46 35 j12 j10 p16 68 58 47 36 j11 h12 p17 69 59 48 37 h12 h11 p18 74 64 53 42 h11 h10 p19 75 65 54 43 g12 g12 p1a 76 66 55 44 g11 g11 p1b 77 67 56 45 f12 g10 p1c 78 68 - 46 f11 f13 p1d 79 69 - 47 e12 f12 p1e 80 70 - 48 e11 f11 p1f 81 - - - - f10 p20 general - purpose i/o port 2 89 74 - 52 c12 c12 p21 88 73 59 51 c13 d11 p22 87 72 58 50 d12 d12 p23 86 71 57 49 d13 d13 p24 85 - - - - e10 p25 84 - - - - e11 p26 83 - - - - e12 p27 82 - - - - e13
document number: 002 - 04918 rev.*a page 35 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 gpio p30 general - purpose i/o port 3 14 9 9 87 e3 f4 p31 15 10 10 88 f1 g1 p32 16 11 11 89 f2 g2 p33 17 12 12 90 f3 g3 p34 18 13 - 91 g1 g4 p35 19 14 - 92 g2 h1 p36 20 15 - 93 g3 h2 p37 21 16 - 94 h2 h3 p38 22 17 - 95 h3 h4 p39 23 18 13 96 j1 j1 p3a 24 19 14 97 j2 j2 p3b 25 20 15 98 j3 j3 p3c 26 21 16 99 k1 j4 p3d 27 22 17 100 k2 k2 p3e 28 23 18 1 l1 k3 p3f 29 24 19 2 l2 l1 p40 general - purpose i/o port 4 32 27 - 5 n2 n2 p41 33 28 - 6 n3 l2 p42 34 29 - 7 m3 n3 p43 35 30 - 8 l3 m3 p44 36 31 21 9 m4 l4 p45 37 32 22 10 l5 k5 p46 39 34 24 12 n5 n5 p47 40 35 25 13 n6 m5 p48 41 36 26 14 l6 l6 p49 42 37 27 15 m7 k6 p4b 47 42 32 20 l7 l7 p4c 48 43 33 21 l8 k7 p4d 49 44 34 22 m9 m8 p4e 50 45 35 23 l9 l8 p50 general - purpose i/o port 5 2 2 2 80 c1 c1 p51 3 3 3 81 c2 c2 p52 4 4 4 82 c3 d1 p53 5 5 5 83 d1 d2 p54 6 6 6 84 d2 d3 p55 7 7 7 85 e1 e1 p56 8 8 8 86 e2 e2 p57 9 - - - - e3 p58 10 - - - - e4 p59 11 - - - - f1 p5a 12 - - - - f2 p5b 13 - - - - f3
document number: 002 - 04918 rev.*a page 36 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 gpio p60 general - purpose i/o port 6 116 96 76 74 b3 b3 p61 115 95 75 73 b4 b4 p62 114 94 74 72 b5 c4 p63 113 93 73 71 c5 b5 p64 112 - - - - c5 p65 111 - - - - d5 p66 110 - - - - a6 p67 109 - - - - b6 p68 108 - - - - c6 p70 general - purpose i/o port 7 51 - - - - k8 p71 52 - - - - l9 p72 53 - - - - k9 p73 54 - - - - m10 p74 55 - - - - l10 p80 general - purpose i/o port 8 118 98 78 76 a3 a3 p81 119 99 79 77 a2 a2 pe0 general - purpose i/o port e 56 46 36 24 m10 n10 pe2 58 48 38 26 n11 n11 pe3 59 49 39 27 n12 n12 multi - function serial 0 sin0_0 multi - function serial interface ch.0 input pin 88 73 59 51 c13 d11 sin0_1 65 55 44 33 k12 j12 sot0_0 (sda0_0) multi - function serial interface ch.0 output pin. this pin operates as sot0 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda0 when it is used in an i 2 c (operation mode 4). 87 72 58 50 d12 d12 sot0_1 (sda0_1) 66 56 45 34 j13 j11 sck0_0 (scl0_0) multi - function serial interface ch.0 clock i/o pin. this pin operates as sck0 when it is used in a uart/csio/lin (operation modes 0 to 3) and as scl0 when it is used in an i 2 c (operation mode 4). 86 71 57 49 d13 d13 sck0_1 (scl0_1) 67 57 46 35 j12 j10 multi - function serial 1 sin1_0 multi - function serial interface ch.1 input pin 96 81 66 59 a9 d9 sin1_1 62 52 41 30 l13 l12 sot1_0 (sda1_0) multi - function serial interface ch.1 output pin. this pin operates as sot1 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda1 when it is used in an i 2 c (operation mode 4). 97 82 67 60 b9 c9 sot1_1 (sda1_1) 63 53 42 31 l12 k12 sck1_0 (scl1_0) multi - function serial interface ch.1 clock i/o pin. this pin operates as sck1 when it is used in a csio (operation modes 4) and as scl1 when it is used in an i 2 c (operation mode 4). 98 83 - 61 c9 b9 sck1_1 (scl1_1) 64 54 43 32 k13 k11
document number: 002 - 04918 rev.*a page 37 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 multi - function serial 2 sin2_0 multi - function serial interface ch.2 input pin 53 - - - - k9 sin2_1 85 - - - - e10 sin2_2 68 58 47 36 j11 h12 sot2_0 (sda2_0) multi - function serial interface ch.2 output pin. this pin operates as sot2 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda2 when it is used in an i 2 c (operation mode 4). 54 - - - - m10 sot2_1 (sda2_1) 84 - - - - e11 sot2_2 (sda2_2) 69 59 48 37 h12 h11 sck2_0 (scl2_0) multi - function serial interface ch.2 clock i/o pin. this pin operates as sck2 when it is used in a csio (operation modes 2) and as scl2 when it is used in an i 2 c (operation mode 4). 55 - - - - l10 sck2_1 (scl2_1) 83 - - - - e12 sck2_2 (scl2_2) 74 64 53 42 h11 h10 multi - function serial 3 sin3_0 multi - function serial interface ch.3 input pin 110 - - - - a6 sin3_1 15 10 10 88 f1 g1 sot3_0 (sda3_0) multi - function serial interface ch.3 output pin. this pin operates as sot3 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda3 when it is used in an i 2 c (operation mode 4). 109 - - - - b6 sot3_1 (sda3_1) 16 11 11 89 f2 g2 sck3_0 (scl3_0) multi - function serial interface ch.3 clock i/o pin. this pin operates as sck3 when it is used in a csio (operation modes 2) and as scl3 when it is used in an i 2 c (operation mode 4). 108 - - - - c6 sck3_1 (scl3_1) 17 12 12 90 f3 g3 multi - function serial 4 sin4_0 multi - function serial interface ch.4 input pin 6 6 6 84 d2 d3 sin4_1 75 65 54 43 g12 g12 sin4_2 10 - - - - e4 sot4_0 (sda4_0) multi - function serial interface ch.4 output pin. this pin operates as sot4 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda4 when it is used in an i 2 c (operation mode 4). 5 5 5 83 d1 d2 sot4_1 (sda4_1) 76 66 55 44 g11 g11 sot4_2 (sda4_2) 11 - - - - f1 sck4_0 (scl4_0) multi - function serial interface ch.4 clock i/o pin. this pin operates as sck4 when it is used in a csio (operation modes 2) and as scl4 when it is used in an i 2 c (operation mode 4). 4 4 4 82 c3 d1 sck4_1 (scl4_1) 77 67 56 45 f12 g10 sck4_2 (scl4_2) 12 - - - - f2 cts4_0 multi - function serial interface ch.4 cts input pin 2 2 2 80 c1 c1 cts4_1 78 68 - 46 f11 f13 cts4_2 13 - - - - f3 rts4_0 multi - function serial interface ch.4 rts output pin 3 3 3 81 c2 c2 rts4_1 79 69 - 47 e12 f12 rts4_2 14 9 9 87 e3 f4
document number: 002 - 04918 rev.*a page 38 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 multi - function serial 5 sin5_0 multi - function serial interface ch.5 input pin 114 94 74 72 b5 c4 sin5_1 113 - - - - b5 sin5_2 20 15 - 93 g3 h2 sot5_0 (sda5_0) multi - function serial interface ch.5 output pin. this pin operates as sot5 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda5 when it is used in an i 2 c (operation mode 4). 115 95 75 73 b4 b4 sot5_1 (sda5_1) 112 - - - - c5 sot5_2 (sda5_2) 21 16 - 94 h2 h3 sck5_0 (scl5_0) multi - function serial interface ch.5 clock i/o pin. this pin operates as sck5 when it is used in a csio (operation modes 2) and as scl5 when it is used in an i 2 c (operation mode 4). 116 96 76 74 b3 b3 sck5_1 (scl5_1) 111 - - - - d5 sck5_2 (scl5_2) 22 17 - 95 h3 h4 multi - function serial 6 sin6_0 multi - function serial interface ch.6 input pin 7 7 7 85 e1 e1 sin6_1 95 80 65 58 a10 b10 sot6_0 (sda6_0) multi - function serial interface ch.6 output pin. this pin operates as sot6 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda6 when it is used in an i 2 c (operation mode 4). 8 8 8 86 e2 e2 sot6_1 (sda6_1) 94 79 64 57 b10 a11 sck6_0 (scl6_0) multi - function serial interface ch.6 clock i/o pin. this pin operates as sck6 when it is used in a csio (operation modes 2) and as scl6 when it is used in an i 2 c (operation mode 4). 9 - - - - e3 sck6_1 (scl6_1) 93 78 63 56 b11 c10 scs6_1 multi - function serial interface ch.6 serial chip select pin 92 77 62 55 a12 b13 multi - function serial 7 sin7_0 multi - function serial interface ch.7 input pin 101 86 - 64 c8 c8 sin7_1 50 45 35 23 l9 l8 sot7_0 (sda7_0) multi - function serial interface ch.7 output pin. this pin operates as sot7 when it is used in a uart/csio/lin (operation modes 0 to 3) and as sda7 when it is used in an i 2 c (operation mode 4). 100 85 - 63 b8 d8 sot7_1 (sda7_1) 49 44 34 22 m9 m8 sck7_0 (scl7_0) multi - function serial interface ch.7 clock i/o pin. this pin operates as sck7 when it is used in a csio (operation modes 2) and as scl7 when it is used in an i 2 c (operation mode 4). 99 84 - 62 a8 a9 sck7_1 (scl7_1) 48 43 33 21 l8 k7 scs7_1 multi - function serial interface ch.7 serial chip select pin 47 42 32 20 l7 l7
document number: 002 - 04918 rev.*a page 39 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 multi - function timer 0 dtti0x_0 input signal controlling wave form generator outputs rto00 to rto05 of multi - function timer 0. 23 18 13 96 j1 j1 dtti0x_1 79 69 - 47 e12 f12 frck0_0 16 - bit free - run timer ch.0 external clock input pin 18 13 - 91 g1 g4 frck0_1 80 70 - 48 e11 f11 frck0_2 62 52 41 30 l13 l12 ic00_0 16 - bit input capture ch.0 input pin of multi - function timer 0. icxx describes channel number. 22 17 - 95 h3 h4 ic00_1 75 65 54 43 g12 g12 ic00_2 63 53 42 31 l12 k12 ic01_0 21 16 - 94 h2 h3 ic01_1 76 66 55 44 g11 g11 ic01_2 64 54 43 32 k13 k11 ic02_0 20 15 - 93 g3 h2 ic02_1 77 67 56 45 f12 g10 ic02_2 65 55 44 33 k12 j12 ic03_0 19 14 - 92 g2 h1 ic03_1 78 68 - 46 f11 f13 ic03_2 66 56 45 34 j13 j11 rto00_0 (ppg00_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg00 when it is used in ppg0 output modes. 24 19 14 97 j2 j2 rto00_1 (ppg00_1) 86 71 57 49 d13 d13 rto01_0 (ppg00_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg00 when it is used in ppg0 output modes. 25 20 15 98 j3 j3 rto01_1 (ppg00_1) 85 - - - - e10 rto02_0 (ppg02_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg02 when it is used in ppg0 output modes. 26 21 16 99 k1 j4 rto02_1 (ppg02_1) 84 - - - - e11 rto03_0 (ppg02_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg02 when it is used in ppg0 output modes. 27 22 17 100 k2 k2 rto03_1 (ppg02_1) 83 - - - - e12 rto04_0 (ppg04_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg04 when it is used in ppg0 output modes. 28 23 18 1 l1 k3 rto04_1 (ppg04_1) 82 - - - - e13 rto05_0 (ppg04_0) wave form generator output pin of multi - function timer 0. this pin operates as ppg04 when it is used in ppg0 output modes. 29 24 19 2 l2 l1 rto05_1 (ppg04_1) 81 - - - - f10
document number: 002 - 04918 rev.*a page 40 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 multi - function timer 1 dtti1x_0 input signal controlling wave form generator outputs rto10 to rto15 of multi - function timer 1. 8 8 8 86 e2 e2 dtti1x_1 55 - - - - l10 frck1_0 16 - bit free - run timer ch.1 external clock input pin 96 81 66 59 a9 d9 frck1_1 50 45 35 23 l9 l8 ic10_0 16 - bit input capture ch.1 input pin of multi - function timer 1. icxx describes channel number. 95 80 65 58 a10 b10 ic10_1 54 - - - - m10 ic11_0 94 79 64 57 b10 a11 ic11_1 53 - - - - k9 ic12_0 93 78 63 56 b11 c10 ic12_1 52 - - - - l9 ic13_0 92 77 62 55 a12 b13 ic13_1 51 - - - - k8 rto10_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 2 2 2 80 c1 c1 rto10_1 (ppg10_1) 32 27 - 5 n2 n2 rto11_0 (ppg10_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg10 when it is used in ppg1 output modes. 3 3 3 81 c2 c2 rto11_1 (ppg10_1) 33 28 - 6 n3 l2 rto12_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 4 4 4 82 c3 d1 rto12_1 (ppg12_1) 34 29 - 7 m3 n3 rto13_0 (ppg12_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg12 when it is used in ppg1 output modes. 5 5 5 83 d1 d2 rto13_1 (ppg12_1) 35 30 - 8 l3 m3 rto14_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 6 6 6 84 d2 d3 rto14_1 (ppg14_1) 36 31 21 9 m4 l4 rto15_0 (ppg14_0) wave form generator output pin of multi - function timer 1. this pin operates as ppg14 when it is used in ppg1 output modes. 7 7 7 85 e1 e1 rto15_1 (ppg14_1) 37 32 22 10 l5 k5 quadrature position/ revolution counter 0 ain0_0 qprc ch.0 ain input pin 24 19 14 97 j2 j2 ain0_1 51 - - - - k8 ain0_2 2 2 2 80 c1 c1 bin0_0 qprc ch.0 bin input pin 25 20 15 98 j3 j3 bin0_1 52 - - - - l9 bin0_2 3 3 3 81 c2 c2 zin0_0 qprc ch.0 zin input pin 26 21 16 99 k1 j4 zin0_1 53 - - - - k9 zin0_2 4 4 4 82 c3 d1 quadrature position/ revolution counter 1 ain1_0 qprc ch.1 ain input pin 10 - - - - e4 ain1_1 89 74 - 52 c12 c12 ain1_2 48 43 33 21 l8 k7 bin1_0 qprc ch.1 bin input pin 11 - - - - f1 bin1_1 88 73 - 51 c13 d11 bin1_2 49 44 34 22 m9 m8 zin1_0 qprc ch.1 zin input pin 12 - - - - f2 zin1_1 87 72 - 50 d12 d12 zin1_2 50 45 35 23 l9 l8
document number: 002 - 04918 rev.*a page 41 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 real - time clock rtcco_0 0.5 seconds pulse output pin of real - time clock 115 95 75 73 b4 b4 rtcco_1 64 54 43 32 k13 k11 rtcco_2 23 18 13 96 j1 j1 subout_0 sub clock output pin 115 95 75 73 b4 b4 subout_1 64 54 43 32 k13 k11 subout_2 23 18 13 96 j1 j1 low - power consumption mode wkup0 deep standby mode return signal input pin 0 116 96 76 74 b3 b3 wkup1 deep standby mode return signal input pin 1 14 9 9 87 e3 f4 wkup2 deep standby mode return signal input pin 2 50 45 35 23 l9 l8 wkup3 deep standby mode return signal input pin 3 69 59 48 37 h12 h11 dac da0 d/a converter ch.0 analog output pin 36 31 21 9 m4 l4 da1 d/a converter ch.1 analog output pin 37 32 22 10 l5 k5 vbat vregctl on - board regulator control pin 41 36 26 14 l6 l6 vwakeup the return signal input pin from a hibernation state 42 37 27 15 m7 k6 sd i/f s_clk_0 sd memory card interface sd memory card clock output pin 92 77 62 55 a12 b13 s_cmd_0 sd memory card interface sd memory card command output 93 78 63 56 b11 c10 s_data1_0 sd memory card interface sd memory card data bus 94 79 64 57 b10 a11 s_data0_0 95 80 65 58 a10 b10 s_data3_0 96 81 66 59 a9 d9 s_data2_0 97 82 67 60 b9 c9 s_cd_0 sd memory card interface sd memory card detection pin 113 93 73 71 c5 b5 s_wp_0 sd memory card interface sd memory card write protection 114 94 74 72 b5 c4 reset initx external reset input pin. a reset is valid when initx = "l". 38 33 23 11 m6 n4 mode md1 mode 1 pin. during serial programming to flash memory, md1 = "l" must be input. 56 46 36 24 m10 n10 md0 mode 0 pin. during normal operation, md0 = "l" must be input. during serial programming to flash memory, md0 = "h" must be input. 57 47 37 25 m11 m11 power vcc power supply pin 1 1 1 79 b1 b1 31 26 - 4 m1 m1 46 41 31 19 m8 m9 61 51 - 29 m13 m13 91 76 61 54 b13 a12 117 97 77 75 a4 a4
document number: 002 - 04918 rev.*a page 42 of 158 MB9B160R series pin function pin name function description pin no lqfp 120 lqfp 100 lqfp 80 qfp 100 bga 112 bga 144 gnd vss gnd pin 107 92 - 70 a5 a7 30 25 20 3 n1 n1 45 40 30 18 n10 n9 60 50 40 28 n13 n13 90 75 60 53 a13 a13 120 100 80 78 a1 a1 - - - - a7 a5 - - - - b2 a8 - - - - b12 a10 - - - - c11 b2 - - - - h1 b11 - - - - n4 b12 - - - - m5 c3 - - - - n7 c11 - - - - l11 c13 - - - - a11 d4 - - - - m12 d10 - - - - m2 k1 - - - - - k4 - - - - - k10 - - - - - l3 - - - - - l5 - - - - - l11 - - - - - l13 - - - - - m2 gnd vss gnd pin - - - - - m4 - - - - - m6 - - - - - m7 - - - - - m12 - - - - - n6 clock x0 main clock (oscillation) input pin 58 48 38 26 n11 n11 x1 main clock (oscillation) i/o pin 59 49 39 27 n12 n12 x0a sub clock (oscillation) input pin 39 34 24 12 n5 n5 x1a sub clock (oscillation) i/o pin 40 35 25 13 n6 m5 crout_0 built - in high - speed cr - osc clock output port 87 72 58 50 d12 d12 crout_1 113 93 73 71 c5 b5 adc power avcc a/d converter and d/a converter analog power supply pin 70 60 49 38 h13 k13 avrl a/d converter analog reference voltage input pin 72 62 51 40 f13 h13 avrh a/d converter analog reference voltage input pin 73 63 52 41 e13 g13 vbat power vbat vbat power supply pin. backup power supply (battery etc.) and system power supply. 43 38 28 16 n8 n7 adc gnd avss a/d converter and d/a converter gnd pin 71 61 50 39 g13 j13 c pin c power supply stabilization capacity pin 44 39 29 17 n9 n8
document number: 002 - 04918 rev.*a page 43 of 158 MB9B160R series 5. i/o circuit type type circuit remarks a it is possible to select the main oscillation / gpio function when the main oscillation is selected. ? oscillation feedback resistor : approximately 1m ? with standby mode control when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma b ? cmos level hysteresis input ? pull - up resistor : approximately 50k standby mode control digital input standby mode control digital output digital output clock input digital input standby mode control pull - up resistor control pull - up resistor control digital output digital output pull - up resistor digital in put p-ch p-ch n-ch r r p-ch p-ch n-ch x0 x1
document number: 002 - 04918 rev.*a page 44 of 158 MB9B160R series type circuit remarks c ? open drain output ? cmos level hysteresis input e ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma f ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma digital input digital out put digital output digital output pull - up resistor control digital input standby mode control digital output digital output pull - up resistor control digital input standby mode control analog input input control n-ch p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 04918 rev.*a page 45 of 158 MB9B160R series type circuit remarks g ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 12ma, i ol = 12ma h ? cmos level output ? cmos level hysteresis input ? with standby mode control standby mode control pull - up resistor control digital input digital output digital output digital output digital output digital input standby mode co ntrol p-ch p-ch n-ch r p-ch n-ch r
document number: 002 - 04918 rev.*a page 46 of 158 MB9B160R series type circuit remarks i ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with standby mode control ? i oh = - 4ma, i ol = 4ma ? available to control of pzr registers. j cmos level hysteresis input l ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 8ma, i ol = 8ma standby mode c ontrol pull - up resistor control digital input digital output digital output mode input digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 04918 rev.*a page 47 of 158 MB9B160R series type circuit remarks m ? cmos level output ? cmos level hysteresis input ? with input control ? analog input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 8ma, i ol = 8ma n ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma (gpio) ? i ol = 20ma ( fast mode plus ) digital output digital output pull - up resistor control digital input standby mode c ontrol analog input input control digital output digital output pull - up resistor control digital input standby mode c ontrol p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 04918 rev.*a page 48 of 158 MB9B160R series type circuit remarks o ? cmos level output ? cmos level hysteresis input ? 5v tolerant ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma ? for i/o setting, refer to vbat domain in the peripheral manual p ? cmos level output ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma, i ol = 4ma ? for i/o setting, refer to vbat domain in the peripheral manual digital output digital out put digital input pull - up resistor control standby mode control digital output digital out put digital input pull - up resistor control standby mode control osc x0 a p-ch p-ch n-ch r p-ch p-ch n-ch r
document number: 002 - 04918 rev.*a page 49 of 158 MB9B160R series type circuit remarks q it is possible to select the sub oscillation / gpio function when the sub oscillation is selected. ? oscillation feedback resistor : approximately 10m ? with standby mode control ? when the gpio is selected. ? cmos level output. ? cmos level hysteresis input ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 4ma , i ol = 4ma ? for i/o setting, refer to vbat domain in the peripheral manual r ? cmos level output ? cmos level hysteresis input ? analog output ? with pull - up resistor control ? with standby mode control ? pull - up resistor : approximately 50k ? i oh = - 12ma, i ol = 12ma (4.5v 5.5v) ? i oh = - 8ma, i ol = 8ma (2.7v 4.5v) x1 a digital output digital out put digital input pull - up resistor control standby mode c ontrol osc standby mode c ontrol clock input pull - up resistor control digital input standby mode c ontrol analog out put digital output digital output p-ch p-ch n-ch r rx p-ch n-ch r p-ch
document number: 002 - 04918 rev.*a page 50 of 158 MB9B160R series 6. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observ ed to minimize the chance of failure and to ob tain higher reliability from your cypress semiconductor devices. 6.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be perman ently damaged by application of stress (voltage, current, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may ad versely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to con tact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the dev ice, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large cap acitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can advers ely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjecte d to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuously at the power supply pin. this condition is called latch - up. caut ion: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not e xceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. observance of safety regulations and standards most countries in the worl d have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current level s and other abnormal operating conditions.
document number: 002 - 04918 rev.*a page 51 of 158 MB9B160R series precautions r e lated to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may direct ly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 6.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during s oldering, you should only mount under cypress recommended conditions. for detailed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done b y two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic lead s be verified before moun ting. surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased suscep tibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. lead - free packaging caution: when ball grid array (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced u nder some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorpt ion of moisture. during mounting, the application of heat to a packag e that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store produ cts in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures between 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relati ve humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they ar e exposed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress recommended conditions for baking. condition: 125 c /24 h
document number: 002 - 04918 rev.*a page 52 of 158 MB9B160R series static electricity because semicon ductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: 1. maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or bracelets connected to ground through high resistance (on the level of 1 m ). wearing of co nductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect with anti - static measures. 5. avoid the use of styrofoam or other highly static - prone material s for storage of completed board assemblies. 6.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge of static electricity when high - voltage charges exist close to semiconductor devices, dis charges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affe ct the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation . users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. cu stomers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04918 rev.*a page 53 of 158 MB9B160R series 7. handling devices power supply pins in products with multiple vcc and vss pins, respective pins at the same potential are interconnected within the device in order to prevent malfunctions such as latch - up. however, all of these pins should be connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels, to prevent abnormal operat ion of strobe signals caused by the rise in the ground level, and to conform to the total output current rating. moreover, connect the current supply source with each power pins and gnd pins of this device at low impedance. it is also advisable that a cera mic capacitor of approximately 0.1 f be connected as a bypass capacitor between v cc and v ss near this device. power supply pins a malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is within the guaranteed o perating range of the vcc power supply voltage. as a rule of voltage stabilization, suppress voltage fluctuation so that the fluctuation in vcc ripple (peak - to - peak value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard vcc va lue, and the transient fluctuation rate does not exceed 0.1 v/s at a momentary fluctuation such as switching the power supply. crystal oscillator circuit noise near the x0/x1 and x0a/x1a pins may cause the device to malfunction. design the printed circuit board so that x0/x1, x0a/x1a pins, the crystal oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as close to the device as possible. it is strongly recommended that the pc board artwork be designed such that the x0/x1 and x0a/x1a pins are surrounded by ground plane as this is expected to produce stable operation. evaluate oscillation of your using crystal oscillator by your mount board. sub crystal oscillator this series sub oscillator circuit is low gain to keep the low cu rrent consumption. the crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize the oscillatio n. ? surface mount type size : more than 3.2 mm 1.5 mm load capacitance : approximately 6 pf to 7 pf ? lea d type load capacitance : approximately 6 pf to 7 pf using an external clock when using an external clock as an input of the main clock, set x0/x1 to the external clock input, and input the clock to x0. x1(pe3) can be used as a general - purpose i/o port. similarly, when using an external clock as an input of the sub clock, set x0a/x1a to the external clock input, and input the clock to x0a. x1a (p47) can be used as a general - purpose i/o port. ? example of using an external clock device x0(x0a ) x1 ( pe3 ), x1a ( p47) can be used as general - purpose i/o ports. set as external clock input
document number: 002 - 04918 rev.*a page 54 of 158 MB9B160R series handling when using multi - function serial pin as i 2 c pin if it is using the multi - function serial pin as i 2 c pins, p - ch transistor of digital output is always disabled. however, i 2 c pins need to keep the electrical characteristic like other pins and not to connect to the external i 2 c bus system with power off. c pin this series contains the regulator. be sure to connect a smoothing capacitor (c s ) for the regulator between the c pin and the gnd pin. please use a ceram ic capacitor or a capacitor of equivalent frequency characteristics as a smoothing capacitor. however, some laminated ceramic capacitors have the characteristics of capacitance variation due to thermal fluctuation (f characteristics and y5v characteristic s). please select the capacitor that meets the specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor. a smoothing capacitor of about 4.7 f would be recommended for this series. mode pins (md0) connect the md pin (md0) directly to vcc or vss pins. design the printed circuit board such that the pull - up/down resistance stays low, as well as the distance between the mode pins and vcc pins or vss pi ns is as short as possible and the connection impedance is low, when the pins are pulled - up/down such as for switching the pin level and rewriting the flash memory data. it is because of preventing the device erroneously switching to test mode due to noise . notes on power - on turn power on/off in the following order or at the same time. if not using the a/d converter and d/a converter, connect avcc = vcc and avss = vss. turning on : vbat vcc vcc avcc avrh vcc vbat avrh avcc vcc serial communication there is a possibility to receive wrong data due to the noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end. if an error is detected, retransmit the data. differences in features among the products with different memory sizes and between flash products and mask products the electric chara cteristics including power consumption, esd, latch - up, noise characteristics, and oscillation characteristics among the products with different memory sizes and between flash products and mask products are different because chip layout and memory structure s are different. if you are switching to use a different product of the same series, please make sure to evaluate the electric characteristics . device c vss c s gnd
document number: 002 - 04918 rev.*a page 55 of 158 MB9B160R series pull - up function of 5v tolerant i/o please do not input the signal more than vcc voltage at the time of pull - up function use of 5v tolerant i/o. adjoining wiring on circuit board if wiring of the crystal oscillation circuit x1a adjoins and also runs in parallel with the wiring of p48/vregctl, there is a possibility that the oscillation erroneously counts because x1a has noise with the change of p48/vregctl. keep as much distance as possible between both wirings and insert the ground pattern between them in order to avoid this possibility. handling when using debug pins when debug pins(tdo/tms/tdi/tck/trstx or swo/swdio/swclk) are set to gpio or other peripheral functions, only set them as output, do not set them as input. p 4 7/ x1a p 4 8/ v r e g c t l ground p 4 6/ x0a p 4 9/ v w a k e u p not allowed to run both wirings in parallel insert the ground pattern device
document number: 002 - 04918 rev.*a page 56 of 158 MB9B160R series 8. block diagram *: for the mb9 bf166m , mb9bf167m and mb9 bf168m , etm is not available. c o r t e x - m 4 m a i n f l a s h i / f c l o c k r e s e t g e n e r a t o r d u a l - t i m e r w a t c h d o g t i m e r ( h a r d w a r e ) d m a c 8 c h . w a t c h c o u n t e r u n i t 0 c s v e x t e r n a l i n t e r r u p t c o n t r o l l e r 1 6 p i n + n m i p o w e r - o n r e s e t s r a m 0 3 2 / 4 8 / 6 4 k b y t e s a h b - a p b b r i d g e : a p b 1 ( m a x 1 6 0 m h z ) s r a m 1 1 6 / 2 4 / 3 2 k b y t e s a h b - a p b b r i d g e : a p b 0 ( m a x 8 0 m h z ) i d s y s c l k m b 9 b f 1 6 6 m / n / r , f 1 6 7 m / n / r , f 1 6 8 m / n / r a h b - a p b b r i d g e : a p b 2 ( m a x 8 0 m h z ) n v i c w a t c h d o g t i m e r ( s o f t w a r e ) s e c u r i t y u n i t 1 t r s t x , t c k , t d i , t m s t r a c e d x , t r a c e c l k x 0 a v c c , a v s s , a v r h a n x x t i o a x t i o b x c t d o x 1 x 0 a x 1 a s c k x s i n x s o t x i n t x n m i x p 0 x , p 1 x , . . . p e x i n i t x m o d e - c t r l i r q - m o n i t o r m d 0 , m d 1 r e g u l a t o r c r c a c c e l e r a t o r a h b - a h b b r i d g e a d t g x r t s 4 c t s 4 m a d x m a d a t a x m a i n f l a s h 1 m b y t e s / 7 6 8 k b y t e s / 5 1 2 k b y t e s m u l t i - f u n c t i o n s e r i a l i / f 8 c h . h w f l o w c o n t r o l ( c h . 4 ) e x t e r n a l b u s i / f g p i o p i n - f u n c t i o n - c t r l l v d m u l t i - l a y e r a h b ( m a x 1 6 0 m h z ) t p i u * r o m t a b l e e t m * s w j - d p m a i n o s c p l l c r 1 0 0 k h z l v d c t r l b a s e t i m e r 1 6 - b i t 1 6 c h . / 3 2 - b i t 8 c h . p e r i p h e r a l c l o c k g a t i n g l o w - s p e e d c r p r e s c a l e r r t c c o , s u b o u t d e e p s t a n d b y c t r l w k u p x 1 6 - b i t f r e e - r u n t i m e r 3 c h . 1 6 - b i t o u t p u t c o m p a r e 6 c h . 1 6 - b i t i n p u t c a p t u r e 4 c h . a / d a c t i v a t i o n c o m p a r e 6 c h . 1 6 - b i t p p g 3 c h . d t t i 0 x f r c k 0 q p r c 2 c h . b i n x z i n x i c 0 x r t o 0 x a i n x 1 2 - b i t a / d c o n v e r t e r m u l t i - f u n c t i o n t i m e r 2 m c s x x , m d q m x , m o e x , m w e x , m a l e , m r d y , m n a l e , m n c l e , m n w e x , m n r e x , m c l k o u t , m s d w e x , m s d c l k , m s d c k e , m r a s x , m c a s x w a v e f o r m g e n e r a t o r 3 c h . m p u f p u 1 2 - b i t d / a c o n v e r t e r 2 u n i t s s r a m 2 1 6 / 2 4 / 3 2 k b y t e s w o r k f l a s h 3 2 k b y t e s w o r k f l a s h i / f t r a c e b u f f e r ( 1 6 k b y t e s ) d s t c s d - c a r d i / f s _ c l k , s _ c m d s _ d a t a x s _ c d , s _ w p v r e g c t l v w a k e u p u n i t 2 d a x r e a l - t i m e c l o c k p o r t c t r l . s u b o s c v b a t d o m a i n v b a t d o m a i n c r 4 m h z c r o u t s o u r c e c l o c k
document number: 002 - 04918 rev.*a page 57 of 158 MB9B160R series 9. memory size see "memory size" in "product lineup" to confirm the memory size. 10. memory map memory map (1) peripherals area 0x41ff_ffff 0x4007_0000 0x4006_f000 gpio 0x4006_e000 sd-card i/f 0xffff_ffff 0x4006_2000 0xe010_0000 0x4006_1000 dstc 0x4006_0000 dmac 0xe000_0000 0x4004_0000 0x4003_f000 ext-bus i/f 0x4003_c800 0x4003_c100 peripheral clock gating 0x4003_c000 low speed cr prescaler 0x6000_0000 0x4003_b000 rtc/port ctrl 0x4003_a000 watch counter 0x4003_9000 crc 0x4400_0000 0x4003_8000 mfs reserved 0x4200_0000 0x4003_6000 0x4003_5000 lvd/ds mode 0x4003_4000 reserved 0x4000_0000 0x4003_3000 d/ac 0x4003_2000 reserved 0x4003_1000 int-req.read 0x2400_0000 0x4003_0000 exti 0x4002_f000 reserved 0x2200_0000 0x4002_e000 cr trim 0x4002_8000 0x2010_0000 0x4002_7000 a/dc 0x200e_0000 workflash i/f 0x4002_6000 qprc 0x200c_0000 workflash 0x4002_5000 base timer 0x4002_4000 ppg 0x2004_8000 0x2004_0000 sram2 0x4002_2000 0x2003_8000 sram1 0x4002_1000 mft unit1 0x2000_0000 reserved 0x4002_0000 mft unit0 0x1fff_0000 sram0 0x0050_0000 reserved 0x4001_6000 0x0040_0000 security/cr trim 0x4001_5000 dual timer 0x4001_3000 0x4001_2000 sw wdt 0x0000_0000 0x4001_1000 hw wdt 0x4001_0000 clock/reset 0x4000_1000 0x4000_0000 mainflash i/f reserved 32 mbytes bit band alias reserved reserved reserved reserved cortex-m4 private peripherals reserved reserved external device area reserved reserved reserved reserved 32 mbytes bit band alias reserved see " ? memory map (2)" for the memory size details. mainflash reserved reserved peripherals
document number: 002 - 04918 rev.*a page 58 of 158 MB9B160R series memory map (2) mb9bf168m/n/r mb9bf167m/n/r mb9bf166m/n/r 0x2008_0000 0x2008_0000 0x2008_0000 0x200c_8000 0x200c_8000 0x200c_8000 0x200c_0000 0x200c_0000 0x200c_0000 0x2004_8000 0x2004_6000 0x2004_4000 0x2004_0000 0x2004_0000 0x2004_0000 0x2003_c000 0x2003_a000 0x2003_8000 0x2000_0000 0x2000_0000 0x2000_0000 0x1fff_8000 0x1fff_4000 0x1fff_0000 0x0050_0000 0x0050_0000 0x0050_0000 0x0040_2000 cr trimming 0x0040_2000 cr trimming 0x0040_2000 cr trimming 0x0040_0000 security 0x0040_0000 security 0x0040_0000 security 0x0010_0000 0x000c_0000 0x0008_0000 0x0000_0000 0x0000_0000 0x0000_0000 sram2 16 kbytes reserved sram0 32 kbytes reserved reserved sram1 24 kbytes reserved sram1 16 kbytes reserved reserved mainflash 512 kbytes reserved mainflash 768 kbytes reserved reserved reserved sram0 48 kbytes reserved workflash 32 kbytes workflash 32 kbytes reserved reserved workflash 32 kbytes sram2 24 kbytes mainflash 1 mbytes reserved reserved sram0 64 kbytes sram1 32 kbytes sram2 32 kbytes
document number: 002 - 04918 rev.*a page 59 of 158 MB9B160R series peripheral address map start address end address bus peripherals 0x4000_0000 0x4000_0fff ahb mainflash i/f register 0x4000_1000 0x4000_ffff reserved 0x4001_0000 0x4001_0fff apb0 clock/reset control 0x4001_1000 0x4001_1fff hardware watchdog timer 0x4001_2000 0x4001_2fff software watchdog timer 0x4001_3000 0x4001_4fff reserved 0x4001_5000 0x4001_5fff dual - timer 0x4001_6000 0x4001_ffff reserved 0x4002_0000 0x4002_0fff apb1 multi - function timer unit 0 0x4002_1000 0x4002_1fff multi - function timer unit 1 0x4002_2000 0x4003_ffff reserved 0x4002_4000 0x4002_4fff ppg 0x4002_5000 0x4002_5fff base timer 0x4002_6000 0x4002_6fff quadrature position/revolution counter 0x4002_7000 0x4002_7fff a/d converter 0x4002_8000 0x4002_dfff reserved 0x4002_e000 0x4002_efff internal cr trimming 0x4002_f000 0x4002_ffff reserved 0x4003_0000 0x4003_0fff apb2 external interrupt controller 0x4003_1000 0x4003_1fff interrupt request batch - read function 0x4003_2000 0x4003_4fff reserved 0x4003_3000 0x4003_3fff d/a converter 0x4003_4000 0x4003_4fff reserved 0x4003_5000 0x4003_57ff low voltage detector 0x4003_5800 0x4003_5fff deep standby mode controller 0x4003_6000 0x4003_ 7 fff reserved 0x4003_8000 0x4003_8fff multi - function serial interface 0x4003_9000 0x4003_9fff crc 0x4003_a000 0x4003_afff watch counter 0x4003_b000 0x4003_bfff rtc/ port ctrl 0x4003_c000 0x4003_c0ff low - speed cr prescaler 0x4003_c100 0x4003_c7ff peripheral c l ock gating 0x4003_c800 0x4003_efff reserved 0x4003_f000 0x4003_ffff external memory interface 0x4004_0000 0x400 5 _ffff ahb reserved 0x4006_0000 0x4006_0fff dmac register 0x4006_1000 0x4006_ 3 fff dstc register 0x4006_4000 0x4006_dfff reserved 0x4006_e000 0x4006_efff sd - card i/f 0x4006_f000 0x4006_ffff gpio 0x4006_7000 0x41ff_ffff reserved 0x 2 00 e _0000 0x 2 00 e _ f fff work f lash i / f register
document number: 002 - 04918 rev.*a page 60 of 158 MB9B160R series 11. pin status in each cpu state the terms used for pin status have the following meanings. ? initx = 0 this is the period when the initx pin is the "l" level. ? initx = 1 this is the period when the initx pin is the "h" level. ? spl = 0 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "0". ? spl = 1 this is the status that the standby pin level setting bit (spl) in the standby mode control register (stb_ctl) is set to "1". ? input enabled indicates that the input function can be used. ? i nternal input fixed at "0" this is the status that the input function cannot be used. internal input is fixed at "l". ? hi - z indicates that the pin drive transistor is disabled and the pin is put in the hi - z state. ? setting disabled indicates that the setting is disabled. ? maintain previous state maintains the state that was immediately prior to entering the current mode. if a built - in peripheral function is operating, the output follows the peripheral function. if the pin is being used as a port, that output i s maintained. ? analog input is enabled indicates that the analog input is enabled. ? trace output indicates that the trace function can be used. ? gpio selected in deep standby mode, pins switch to the general - purpose i/o port. ? setting prohibition prohibition o f a setting by specification limitation.
document number: 002 - 04918 rev.*a page 61 of 158 MB9B160R series list of pin status pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 \ \ \ \ spl = 0 spl = 1 spl = 0 spl = 1 - a gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected main crystal oscillator input pin/ external main clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled b gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external main clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state main crystal oscillator output pin hi - z / internal input fixed at "0"/ or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state/when oscillation stops* 1 , hi - z / internal input fixed at "0" maintain prev ious state/when oscillation stops* 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stops* 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stops* 1 , hi - z / internal input fixed at "0" maintain pr evious state/when oscillation stops* 1 , hi - z / internal input fixed at "0" maintain previous state/when oscillation stops* 1 , hi - z / internal input fixed at "0" c initx input pin pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled pull - up / input enabled d mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled e mode input pin input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / input enabled gpio selected hi - z / input enabled gpio selected
document number: 002 - 04918 rev.*a page 62 of 158 MB9B160R series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \ f nmix selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected maintain previous state g jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state gpio selected setting disabled setting disabled setting disabled hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected h jtag selected hi - z pull - up / input enabled pull - up / input enabled maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state resource other than above selected setting disabled setting disabled setting disabled hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected i resource selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected j analog output selected setting disabled setting disabled setting disabled maintain previous state *2 *3 gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state hi - z / internal input fixed at "0" gpio selected
document number: 002 - 04918 rev.*a page 63 of 158 MB9B160R series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \ k external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected l analog input selected hi - z hi - z / internal input fixedat "0" / analog input enabled hi - z / internal input fixedat "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabl ed hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled resource other than above selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected gpio selected m analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / an alog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled external interrupt enabled selected setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z / internal input fixed at "0" gpio selected
document number: 002 - 04918 rev.*a page 64 of 158 MB9B160R series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \ n analog input selected hi - z hi - z / internal input fixed at"0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected resource other than above selected hi - z / internal input fixed at "0" gpio selected o analog input selected hi - z hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / int ernal input fixed at "0" / analog input enabled trace selected setting disabled setting disabled setting disabled maintain previous state maintain previous state trace output gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected external interrupt enabled selected maintain previous state resource other than above selected hi - z / internal input fixed at "0" gpio selected
document number: 002 - 04918 rev.*a page 65 of 158 MB9B160R series pin status type function group power - on reset or low - voltage detection state initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable \ \ \ \ \ p analog input selected hi - z hi - z / internal input fixedat "0" / analog input enabled hi - z / internal input fixedat "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled hi - z / internal input fixed at "0" / analog input enabled wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected resource other than above selected hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected q wkup enabled setting disabled setting disabled setting disabled maintain previous state maintain previous state maintain previous state wkup input enabled hi - z / wkup input enabled gpio selected external interrupt enabled selected gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" resource other than above selected hi - z hi - z / input enabled hi - z / input enabled hi - z / internal input fixed at "0" gpio selected r gpio selected hi - z hi - z / input enabled hi - z / input enabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected *1 : oscillation is stopped at sub timer mode, sub cr timer mode, rtc mode, stop mode, deep standby rtc mode, and deep standby stop mode. *2 : maintain previous state at timer mode. gpio selected internal input fixed at "0" at rtc mode, stop mode. *3 : maintain previous state at timer mode. hi - z/internal input fixed at "0" at rtc mode, stop mode.
document number: 002 - 04918 rev.*a page 66 of 158 MB9B160R series list of vbat domain pin status vbat pin status type function group vbat power - o n reset initx input state device internal reset state run mode or sleep mode state timer mode, rtc mode, or stop mode state deep standby rtc mode or deep standby stop mode state return from deep standby mode state vbat rtc mode state return from vbat rtc mode state power supply unstable power supply stable power supply stable power supply stable power supply stable power supply stable power supply stable power supply stable \ initx = 0 initx = 1 initx = 1 initx = 1 initx = 1 initx = 1 - - \ \ \ \ spl = 0 spl = 1 spl = 0 spl = 1 - - - s gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected setting prohibition - sub crystal oscillator input pin / external sub clock input selected input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled input enabled maintain previous state maintain previous state t gpio selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" gpio selected internal input fixed at "0" hi - z / internal input fixed at "0" gpio selected setting prohibition - external sub clock input selected setting disabled setting disabled setting disabled maintain previous state maintain previous state hi - z / internal input fixed at "0" maintain previous state hi - z / internal input fixed at "0" maintain previous state maintain previous state maintain previous state sub crystal oscillator output pin hi - z / internal input fixed at "0"/ or input enable hi - z / internal input fixed at "0" hi - z / internal input fixed at "0" maintain previous state maintain previous state/when oscillation stops*, hi - z / internal input fixed at "0" maintain previous state/when oscillation stops*, hi - z / internal input fixed at "0" maintain previous state/when oscillation stops*, hi - z/ internal input fixed at "0" maintain previous state/when oscillation stops*, hi - z/ internal input fixed at "0" maintain previous state/whe n oscillation stops*, hi - z/ internal input fixed at "0" maintain previous state maintain previous state u resource selected hi - z maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state maintain previous state gpio selected * : oscillation is stopped at stop mode and deep standby stop mode.
document number: 002 - 04918 rev.*a page 67 of 158 MB9B160R series 12. electrical characteristics 12.1 absolute maximum ratings parameter symbol rating unit remarks min max power supply voltage * 1, * 2 v cc v ss - 0.5 v ss + 6.5 v power supply voltage (vbat) * 1 , * 3 v bat v ss - 0.5 v ss + 6.5 v analog power supply voltage * 1 , * 4 av cc v ss - 0.5 v ss + 6.5 v analog reference voltage * 1 , * 4 avrh v ss - 0.5 v ss + 6.5 v input voltage * 1 v i v ss - 0.5 v cc + 0.5 ( 6.5v) v v ss - 0.5 v ss + 6.5 v 5v tolerant analog pin input voltage * 1 v ia v ss - 0.5 av cc + 0.5 ( 6.5v) v output voltage * 1 v o v ss - 0.5 v cc + 0.5 ( 6.5v) v "l" level maximum output current * 5 i ol - 10 ma 4ma type 20 ma 8ma type 20 ma 12ma type 22.4 ma i 2 c fm+ "l" level average output current * 6 i olav - 4 ma 4ma type 8 ma 8ma type 12 ma 12ma type 20 ma i 2 c fm+ "l" level total maximum output current i ol - 100 ma "l" level total maximum output current * 7 i olav - 50 ma "h" level maximum output current * 5 i oh - - 10 ma 4ma type 20 ma 8ma type - 20 ma 12ma type "h" level average output current * 6 i ohav - - 4 ma 4ma type 8 ma 8ma type - 12 ma 12ma type "h" level total maximum output current i oh - - 100 ma "h" level total average output current * 7 i ohav - - 50 ma storage temperature t stg - 55 + 150 c *1 : these parameters are based on the condition that v ss = av ss = 0.0v. *2 : v cc must not drop below v ss - 0.5v. *3 : v bat must not drop below v ss - 0.5v. *4 : ensure that the voltage does not exceed v cc + 0.5v, for example, when the power is turned on. *5 : the maximum output current is defined as the value of the peak current flowing through any one of the corresponding pins. *6 : the average output current is defined as the average c urrent value flowing through any one of the corresponding pins for a 100ms period. *7 : the total average output current is defined as the average current value flowing through all of corresponding pins for a 100m s. warning semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings.
document number: 002 - 04918 rev.*a page 68 of 158 MB9B160R series 12.2 recommended operating conditions parameter symbol conditions value unit remarks min max power supply voltage v cc - 2.7 5.5 v power supply voltage (vbat) v bat - 2.7 5.5 v analog power supply voltage av cc - 2.7 5.5 v av cc = v cc analog reference voltage avrh - av ss av cc v operating temperature junction temperature tj - - 40 + 125 c ambient temperature ta - - 40 * c * : the maximum temperature of the ambient temperature (ta) can guarantee a range that does not exceed the junction temperature (tj). the calculation formula of the ambient temperature (ta) is shown below. ta(max) = tj(max) - pd(max) ja pd : power dissipation (w) ja : package thermal resistance ( c/w) pd (max) = v cc i cc (max) + (i ol v ol ) + ((v cc - v oh ) ( - i oh )) i ol : "l" level output current i oh : "h" level output current v ol : "l" level output voltage v oh : "h" level output voltage package thermal resistance and maximum permissible power for each package are shown below. the operation is guaranteed maximum permissible power or les s for semiconductor devices. table for package thermal resistance and maximum permissible power package printed circuit board thermal resistance ja ( c/w) maximum permissible power (mw) ta = +85 c ta = +105 c fpt - 80p - m37 (0.5mm pitch) single - layered both sides 60 667 333 4 layers 39 1026 513 fpt - 80p - m40 (0.65mm pitch) single - layered both sides 58 690 335 4 layers 38 1053 526 fpt - 100p - m23 (0.5mm pitch) single - layered both sides 57 702 351 4 layers 38 1053 526 fpt - 100p - m36 (0.65mm pitch) single - layered both sides 48 833 417 4 layers 34 1177 588 fpt - 120p - m37 (0.5mm pitch) single - layered both sides 62 645 323 4 layers 43 930 465 bga - 112p - m05 (0.5mm pitch) single - layered both sides 60 667 333 4 layers 40 1000 500 bga - 144p - m09 (0.5mm pitch) single - layered both sides 55 727 364 4 layers 40 1000 500 warning the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliabil ity of device and could result in device failure. no warranty is made with respect to any use, operating conditions or combinations not represented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand.
document number: 002 - 04918 rev.*a page 69 of 158 MB9B160R series calculation method of power dissipation (pd) the power dissipation is shown in the following formula. pd = v cc i cc + (i ol v ol ) + ((v cc - v oh ) ( - i oh )) i ol : "l" level output current i oh : "h" level output current v ol : "l" level output voltage v oh : "h" level output voltage i cc is a current consumed in device. it can be analyzed as follows. i cc = i cc (int) + i cc (io) i cc (int) : current consumed in internal logic and memory, etc. through regulator i cc (io) : sum of current (i/o switching current) consumed in output pin for i cc (int), it can be anticipated by "(1) current rating" in "3. dc characteristics" (this rating value does not include i cc (io) for a value at pin fixed). for icc (io ), it depends on system used by customers. the calculation formula is shown below. i cc (io) = (c int + c ext ) v cc fsw c int : pin internal load capacitance c ext : external load capacitance of output pin f sw : pin switching frequency parameter symb ol conditions capacitance value pin internal load capacitance c int 4ma type 1.93pf 8ma type 3.45pf 12ma type 3.42pf calculate i cc (max) as follows when the power dissipation can be evaluated by yourself. 1. measure current value i cc (typ) at normal temperature (+25c). 2. add maximum leak current value i cc (leak_max) at operating on a value in (1). i cc (max) = i cc (typ) + i cc (leak_max) parameter symbol conditions current value maximum leak current at operating i cc (leak_max) tj = +125 c 45.5ma tj = +105 c 26.8ma tj = +85 c 16.2ma
document number: 002 - 04918 rev.*a page 70 of 158 MB9B160R series current explanation diagram a v ??? ??? ??? v a a regulator logic flash ram i cc i cc (int) i cc (io) i ol v ol v oh i oh i cc (io) chip v cc c ext pd = v cc i cc + (i ol v ol ) ((v cc - v oh )( oh )) i cc = i cc (int) i cc ( io )
document number: 002 - 04918 rev.*a page 71 of 158 MB9B160R series 12.3 dc characteristics 12.3.1 current rating parameter symbol pin name conditions frequency * 4 value unit remarks typ * 1 max * 2 power supply current i cc vcc normal operation* 5, * 6 (pll) 160mhz 54 103 ma *3 when all peripheral clocks are on 144mhz 49 98 120mhz 41 90 100mhz 35 84 80mhz 28 77 60mhz 22 71 40mhz 16 64 20mhz 8.9 58 8mhz 5.1 54 4mhz 3.8 53 160mhz 34 83 ma *3 when all peripheral clocks are off 144mhz 31 80 120mhz 26 75 100mhz 22 71 80mhz 18 67 60mhz 14 63 40mhz 10 59 20mhz 6.2 55 8mhz 3.8 53 4mhz 3.1 52 parameter symbol pin name conditions frequency * 7 value unit remarks typ * 1 max * 2 power supply current i cc vcc normal operation* 8 (pll) 160mhz 74 126 ma *3 when all peripheral clocks are on 144mhz 68 120 120mhz 59 112 100mhz 52 104 80mhz 44 97 60mhz 36 89 40mhz 27 79 20mhz 17 67 8mhz 8.3 58 4mhz 5.4 55 160mhz 51 103 ma *3 when all peripheral clocks are off 144mhz 47 100 120mhz 42 94 100mhz 37 90 80mhz 33 85 60mhz 28 80 40mhz 21 73 20mhz 13 64 8mhz 6.9 56 4mhz 4.6 54 *1: ta = +25 c , v cc = 3.3v *2: tj = +125 c , v cc = 5.5v *3: when all ports are fixed. *4: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk/2 *5: when operating flash accelerator mode and trace buffer function (frwtr.rwt = 10, fbfcr.be = 1) *6: data access is nothing to mainflash memory *7: frequency is a value of hclk. pclk0 = pclk2 = hclk/2, pclk1 = hclk *8: when stopping flash accelerator mode and trace buffer function (frwtr.rw t = 10, fbfcr.be = 0)
document number: 002 - 04918 rev.*a page 72 of 158 MB9B160R series parameter symbol pin name conditions frequency * 4 (mhz) value unit remarks typ * 1 max * 2 power supply current i cc vcc normal operation* 5 (pll) 72mhz 46 98 ma *3 when all peripheral clocks are on 60mhz 40 92 48mhz 33 85 36mhz 27 78 24mhz 19 70 12mhz 11 61 8mhz 8.5 58 4mhz 5.5 55 72mhz 33 85 ma *3 when all peripheral clocks are off 60mhz 29 81 48mhz 25 76 36mhz 20 71 24mhz 15 65 12mhz 9.2 59 8mhz 6.9 56 4mhz 4.6 54 *1: ta = +25 c , v cc = 3.3v *2: tj = +125 c , v cc = 5.5v *3: when all ports are fixed. *4: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk *5: when 0 wait - cycle mode (frwtr.rwt = 00, fsyndn.sd = 00) parameter symbol pin name conditions frequency * 4 value unit remarks typ * 1 max * 2 power supply current i cc vcc normal operation* 5 (built - in high - speed cr) 4mhz 3.3 51 ma *3 when all peripheral clocks are on 2.8 51 ma *3 when all peripheral clocks are off normal operation* 5 (sub oscillation) 32khz 0.64 48 ma *3 when all peripheral clocks are on 0.56 48 ma *3 when all peripheral clocks are off normal operation* 5 (built - in low - speed cr) 100khz 0.64 48 ma *3 when all peripheral clocks are on 0.58 48 ma *3 when all peripheral clocks are off *1: ta = +25 c , v cc = 3.3v *2: tj = +125 c , v cc = 5.5v *3: when all ports are fixed. *4: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk/2 *5: when 0 wait - cycle mode (frwtr.rwt = 00, fsyndn.sd = 000)
document number: 002 - 04918 rev.*a page 73 of 158 MB9B160R series parameter symbol pin name conditions frequency * 4 value unit remarks typ * 1 max * 2 power supply current i ccs vcc sleep operation (pll) 160mhz 35 84 ma *3 when all peripheral clocks are on 144mhz 32 81 120mhz 27 76 100mhz 23 72 80mhz 19 68 60mhz 15 64 40mhz 11 60 20mhz 6.5 55 8mhz 4.1 53 4mhz 3.3 52 160mhz 16 65 ma *3 when all peripheral clocks are off 144mhz 14 63 120mhz 12 61 100mhz 11 60 80mhz 9.0 58 60mhz 7.4 56 40mhz 5.6 54 20mhz 3.9 53 8mhz 2.9 52 4mhz 2.6 51 parameter symbol pin name conditions frequency * 5 value unit remarks typ * 1 max * 2 power supply current i ccs vcc sleep operation (pll) 72mhz 22 71 ma *3 when all peripheral clocks are on 60mhz 19 68 48mhz 16 64 36mhz 12 61 24mhz 9.0 58 12mhz 5.8 55 8mhz 4.6 54 4mhz 3.6 52 72mhz 9.5 58 ma *3 when all peripheral clocks are off 60mhz 8.3 57 48mhz 7.1 56 36mhz 5.8 55 24mhz 4.6 53 12mhz 3.5 52 8mhz 3.0 52 4mhz 2.7 51 *1: ta = +25 c , v cc = 3.3v *2: tj = +125 c , v cc = 5.5v *3: when all ports are fixed. *4: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk/2 *5: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk
document number: 002 - 04918 rev.*a page 74 of 158 MB9B160R series parameter symbol pin name conditions frequency * 4 value unit remarks typ * 1 max * 2 power supply current i ccs vcc sleep operation (built - in high - speed cr) 4mhz 1.5 49 ma *3 when all peripheral clocks are on 1.0 49 ma *3 when all peripheral clocks are off sleep operation (sub oscillation) 32khz 0.59 48 ma *3 when all peripheral clocks are on 0.51 48 ma *3 when all peripheral clocks are off sleep operation (built - in low - speed cr) 100khz 0.61 48 ma *3 when all peripheral clocks are on 0.53 48 ma *3 when all peripheral clocks are off *1: ta = +25 c , v cc = 3.3v *2: tj = +125 c , v cc = 5.5v *3: when all ports are fixed. *4: frequency is a value of hclk. pclk0 = pclk1 = pclk2 = hclk/2
document number: 002 - 04918 rev.*a page 75 of 158 MB9B160R series parameter symbol pin name conditions frequency value unit remarks typ* 1 max* 2 power supply current i cch vcc stop mode - 0.33 1.8 ma *3, *4 ta = +25 c - 15 ma *3, *4 ta = +85 c - 22 ma *3, *4 ta = +105 c i cct timer mode (built - in high - speed cr) 4mhz 0.70 2.2 ma *3, *4 ta = +25 c - 16 ma *3, *4 ta = +85 c - 22 ma *3, *4 ta = +105 c timer mode (sub oscillation) 32khz 0.33 1.8 ma *3, *4 ta = +25 c - 15 ma *3, *4 ta = +85 c - 22 ma *3, *4 ta = +105 c timer mode (built - in low - speed cr) 100khz 0.34 1.8 ma *3, *4 ta = +25 c - 15 ma *3, *4 ta = +85 c - 22 ma *3, *4 ta = +105 c i ccr rtc mode (sub oscillation) 32khz 0.33 1.8 ma *3, *4 ta = +25 c - 15 ma *3, *4 ta = +85 c - 22 ma *3, *4 ta = +105 c *1: v cc = 3.3v *2: v cc = 5.5v *3: when all ports are fixed. *4: when lvd is off
document number: 002 - 04918 rev.*a page 76 of 158 MB9B160R series parameter symbol pin name conditions frequency value unit remarks typ * 1 max * 2 power supply current i cchd vcc deep standby stop mode (when ram is off) - 29 140 a *3, *4 ta = +25 c - 644 a *3, *4 ta = +85 c - 1011 a *3, *4 ta = +105 c deep standby stop mode (when ram is on) 48 273 a *3, *4 ta = +25 c - 2676 a *3, *4 ta = +85 c - 4162 a *3, *4 ta = +105 c i ccrd deep standby rtc mode (when ram is off) 32khz 29 140 a *3, *4 ta = +25 c - 644 a *3, *4 ta = +85 c - 1011 a *3, *4 ta = +105 c deep standby rtc mode (when ram is on) 48 273 a *3, *4 ta = +25 c - 2676 a *3, *4 ta = +85 c - 4162 a *3, *4 ta = +105 c i ccvbat vbat rtc stop - 0.015 0.29 a *3, *4, *5 ta = +25 c - 5.77 a *3, *4, *5 ta = +85 c - 10.6 a *3, *4, *5 ta = +105 c rtc operation 1.53 22.6 a *3, *4 ta = +25 c - 35.2 a *3, *4 ta = +85 c - 41.8 a *3, *4 ta = +105 c *1: v cc = 3.3v *2: v cc = 5.5v *3: when all ports are fixed. *4: when lvd is off *5: when sub oscillation is off
document number: 002 - 04918 rev.*a page 77 of 158 MB9B160R series parameter symbol pin name conditions value unit remarks min typ max low - voltage detection circuit (lvd) power supply current i cclvd vcc at operation - 4 7 a for occurrence of interrupt main flash memory write/erase current i ccflash at write/erase - 13.4 15.9 ma work flash memory write/erase current i ccwflash at write/erase - 11.5 13.6 ma peripheral current dissipation clock system peripheral unit frequency (mhz) unit remarks 40 80 160 hclk gpio a ll ports 0.22 0.43 0.85 ma dmac - 0.74 1.48 2.88 dstc - 0.32 0.61 1.17 external bus i/f - 0.14 0.27 0.55 sd card i/f - 0.93 1.81 3.63 pclk1 base timer 4ch . 0.16 0.34 0.66 ma multi - functional timer /ppg 1unit/4ch . 0.55 1.09 2.17 quadrature p osition/revolution c ounter 1unit 0.04 0.09 0.17 a/dc 1unit 0.20 0.39 0.78 pclk2 muli - function serial 1ch . 0.31 0.62 - ma
document number: 002 - 04918 rev.*a page 78 of 158 MB9B160R series 12.3.2 pin characteristics (v cc = av cc = 2.7v to 5.5v, v ss = av ss = 0v) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage (hysteresis input) v ihs cmos hysteresis input pin, md0, md1 - v cc 0.8 - v cc + 0.3 v 5v tolerant input pin - v cc 0.8 - v ss + 5.5 v input pin doubled as i 2 c fm+ - v cc 0.7 - v ss + 5.5 v "l" level input voltage (hysteresis input) v ils cmos hysteresis input pin, md0, md1 - v ss - 0.3 - v cc 0.2 v 5v tolerant input pin - v ss - 0.3 - v cc 0.2 v input pin doubled as i 2 c fm+ - v ss - v cc 0.3 v "h" level output voltage v oh 4ma type v cc 4.5 v, i oh = - 4ma v cc - 0.5 - v cc v v cc < 4.5 v, i oh = - 2ma 8ma type v cc 4.5 v, i oh = - 8ma v cc - 0.5 - v cc v v cc < 4.5 v, i oh = - 4ma 12ma type v cc 4.5 v, i oh = - 12ma v cc - 0.5 - v cc v v cc < 4.5 v, i oh = - 8ma the pin doubled as i 2 c fm+ v cc 4.5 v, i oh = - 4ma v cc - 0.5 - v cc v at gpio v cc < 4.5 v, i oh = - 3ma
document number: 002 - 04918 rev.*a page 79 of 158 MB9B160R series parameter symbol pin name conditions value unit remarks min typ max "l" level output voltage v ol 4ma type v cc 4.5 v, i ol = 4ma v ss - 0.4 v v cc < 4.5 v, i ol = 2ma 8ma type v cc 4.5 v, i oh = 8ma v ss - 0.4 v v cc < 4.5 v, i oh = 4ma 12ma type v cc 4.5 v, i ol = 12ma v ss - 0.4 v v cc < 4.5 v, i ol = 8ma the pin doubled as i 2 c fm+ v cc 4.5 v, i oh = 4ma v ss - 0.4 v at gpio v cc < 4.5 v, i oh = 3ma v cc 5.5 v, i oh = 20ma at i 2 c fm+ input leak current i il - - - 5 - + 5 a pull - up resistor value r pu pull - up pin v cc 4.5 v 25 50 100 k v cc < 4.5 v 30 80 200 input capacitance c in other than vcc, vbat, vss, avcc, avss, avrh - - 5 15 pf
document number: 002 - 04918 rev.*a page 80 of 158 MB9B160R series 12.4 ac characteristics 12.4.1 main clock input characteristics (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max input frequency f ch x0, x1 v cc 4.5v 4 48 mhz when crystal oscillator is connected v cc < 4.5v 4 20 v cc 4.5v 4 48 mhz when using external clock v cc < 4.5v 4 20 input clock cycle t cylh v cc 4.5v 20.83 250 ns when using external clock v cc < 4.5v 50 250 input clock pulse width - pwh/tcylh, pwl/tcylh 45 55 % when using external clock input clock rising time and falling time t cf, t cr - - 5 ns when using external clock internal operating clock* 1 frequency f cc - - - 160 mhz base clock (hclk/fclk) f cp0 - - - 80 mhz apb0 bus clock* 2 f cp1 - - - 160 mhz apb1 bus clock* 2 f cp2 - - - 80 mhz apb2 bus clock* 2 internal operating clock* 1 cycle time t cycc - - 6.25 - ns base clock (hclk/fclk) t cycp0 - - 12.5 - ns apb0 bus clock* 2 t cycp1 - - 6.25 - ns apb1 bus clock* 2 t cycp2 - - 12.5 - ns apb2 bus clock* 2 *1: for more information about each internal operating clock, see chapter : clock in fm4 family peripheral manual . *2: for about each apb bus which each p eripheral is connected to, see block diagram in this data sheet. x0
document number: 002 - 04918 rev.*a page 81 of 158 MB9B160R series 12.4.2 sub clock input characteristics (v bat = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min typ max input frequency 1/ t cyll x0a, x1a - - 32.768 - khz when crystal oscillator is connected - 32 - 100 khz when using external clock input clock cycle t cyll - 10 - 31.25 s when using external clock input clock pulse width - p wh / t cyll , p wl / t cyll 45 - 55 % when using external clock 12.4.3 built - in cr oscillation characteristics built - in high - speed cr (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions value unit remarks min typ max clock frequency f crh tj = - 20c to + 105c 3.92 4 4.08 mhz when trimming* tj = - 40c to + 125c 3.88 4 4.12 clock frequency f crh tj = - 40c to + 125c 3 4 5 when not trimming *: in the case of using the values in cr trimming area of flash memory at shipment for frequency/temperature trimming. built - in low - speed cr (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol condition value unit remarks min typ max clock frequency f crl - 50 100 150 khz x0 a v bat v bat v bat v bat 0.8 v bat
document number: 002 - 04918 rev.*a page 82 of 158 MB9B160R series 12.4.4 operating conditions of main pll (in the case of using main clock for input clock of pll) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 200 - - s pll input clock frequency f plli 4 - 16 mhz pll multiplication rate - 13 - 80 multiplier pll macro oscillation clock frequency f pllo 200 - 320 mhz main pll clock frequency* 2 f clkpll - - 160 mhz *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information abou t main pll clock (clkpll), see chapter: clock in fm4 family peripheral manual . 12.4.5 operating conditions of main pll (in the case of using built - in high - speed cr clock for input clock of main pll) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time* 1 (lock up time) t lock 200 - - s pll input clock frequency f plli 3.8 4 4.2 mhz pll multiplication rate - 50 - 75 multiplier pll macro oscillation clock frequency f pllo 190 - 320 mhz main pll clock frequency* 2 f clkpll - - 160 mhz *1: time from when the pll starts operating until the oscillation stabilizes. *2: for more information about main pll clock (clkpll), see chapter: clock in fm4 family peripheral manual . note: make sure to input to the main pll source clock, the high - speed cr clock (clkhc) that the frequency and temperature has been trimmed. 12.4.6 reset input characteristics (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name condition value unit remarks min max reset input time t initx initx - 500 - ns
document number: 002 - 04918 rev.*a page 83 of 158 MB9B160R series 12.4.7 power - on reset timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name value unit remarks min max power supply rising time tr vcc 0 - ms power supply shut down time toff 1 - ms time until releasing power - on reset tprt 0.33 0.60 ms glossary vcc_minimum : minimum v cc of recommended operating conditions. vdl_minimum : minimum detection voltage of low - voltage detection reset. see " 12. 7 . low - voltage detection characteristics " . 12.4.8 gpio output characteristics (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max output frequency t pcycle pxx* v cc 4.5 v - 50 mhz v cc < 4.5 v - 32 mhz *: gpio is a target. 0 . 2 v v d l _ m i n i m u m v c c _ m i n i m u m t p r t i n t e r n a l r s t v c c c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e t r 0 . 2 v 0 . 2 v t o f f p x x t p c y c l e
document number: 002 - 04918 rev.*a page 84 of 158 MB9B160R series 12.4.9 external bus timing external bus clock output characteristics (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max output frequency t cycle mclkout* 1 v cc 4.5 v - 50* 2 mhz v cc < 4.5 v - 32* 3 mhz *1: the external bus clock (mclkout) is a divided clock of hclk. for more information about setting of clock divider, see chapter: external bus interface in fm4 family peripheral manual . *2: generate mclkout at setting more than 4 division when the ahb bus clock exceeds 100mhz. *3: generate mclkout at setting more than 4 division when the ahb bus clock exceeds 64mhz. external bus signal input/output characteristics (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions value unit remarks signal input characteristics v ih - 0.8 v cc v v il 0.2 v cc v signal output characteristics v oh 0.8 v cc v v ol 0.2 v cc v mclk signal input signal output 0.8 vcc 0.8 vcc t cycle v ih v il v il v ih v oh v ol v ol v oh
document number: 002 - 04918 rev.*a page 85 of 158 MB9B160R series separate bus access asynchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max moex mininum pulse width t oew moex v cc 4.5v mclkn - 3 - ns v cc < 4.5v mcsxaddress output delay time t csl C av mcsx[7:0], mad[24:0] v cc 4.5v - 9 +9 ns v cc < 4.5v - 12 +12 moexaddress hold time t oeh - ax moex, mad[24:0] v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 mcsx moex delay time t csl - oel moex, mcsx[7:0] v cc 4.5v mclkm - 9 mclkm+9 ns v cc < 4.5v mclkm - 12 mclkm+12 moex mcsx time t oeh - csh v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 mcsxmdqm delay time t csl - rdqml mcsx, mdqm[1:0] v cc 4.5v mclkm - 9 mclkm+9 ns v cc < 4.5v mclkm - 12 mclkm+12 data set upmoex time t ds - oe moex, madata[15:0] v cc 4.5v 20 - ns v cc < 4.5v 38 - moex data hold time t dh - oe moex, madata[15:0] v cc 4.5v 0 - ns v cc < 4.5v mwex mininum pulse width t wew mwex v cc 4.5v mclkn - 3 - ns v cc < 4.5v mwexaddress output delay time t weh - ax mwex, mad[24:0] v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 mcsxmwex delay time t csl - wel mwex, mcsx[7:0] v cc 4.5v mclkn - 9 mclkn+9 ns v cc < 4.5v mclkn - 12 mclkn+12 mwexmcsx delay time t weh - csh v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 mcsxmdqm delay time t csl - wdqml mcsx, mdqm[1:0] v cc 4.5v mclkn - 9 mclkn+9 ns v cc < 4.5v mclkn - 12 mclkn+12 mcsx data output time t csl - dx mcsx, madata[15:0] v cc 4.5v mclk - 9 mclk+9 ns v cc < 4.5v mclk - 12 mclk+12 mwex data hold time t weh - dx mwex, madata[15:0] v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 note: when the external load capacitance c l = 30pf (m = 0 to 15, n = 1 to 16)
document number: 002 - 04918 rev.*a page 86 of 158 MB9B160R series mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d a d d r e s s t c s l - o e l t c s l - a v r d a d d r e s s w d t d h - o e t d s - o e t w e h - d x t o e w t o e h - a x t o e h - c s h t w e w t c y c l e t c s l - w e l t c s l - a v t w e h - c s h t w e h - a x t c s l - w d q m l t c s l - r d q m l t c s l - d x
document number: 002 - 04918 rev.*a page 87 of 158 MB9B160R series separate bus access synchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max address delay time t av mclk, mad[24:0] v cc 4.5v 1 9 ns v cc < 4.5v 12 mcsx delay time t csl mclk, mcsx[7:0] v cc 4.5v 1 9 ns v cc < 4.5v 12 t csh v cc 4.5v 1 9 ns v cc < 4.5v 12 moex delay time t rel mclk, moex v cc 4.5v 1 9 ns v cc < 4.5v 12 t reh v cc 4.5v 1 9 ns v cc < 4.5v 12 data set up mclk time t ds mclk, madata[15:0] v cc 4.5v 19 - ns v cc < 4.5v 37 mclk data hold time t dh mclk, madata[15:0] v cc 4.5v 0 - ns v cc < 4.5v mwex delay time t wel mclk, mwex v cc 4.5v 1 9 ns v cc < 4.5v 12 t weh v cc 4.5v 1 9 ns v cc < 4.5v 12 mdqm[1:0] delay time t dqml mclk, mdqm[1:0] v cc 4.5v 1 9 ns v cc < 4.5v 12 t dqmh v cc 4.5v 1 9 ns v cc < 4.5v 12 mclk data output time t ods mclk, madata[15:0] v cc 4.5v mclk+1 mclk+18 ns v cc < 4.5v mclk+24 mclk data hold time t od mclk, madata[15:0] v cc 4.5v 1 18 ns v cc < 4.5v 24 note: when the external load capacitance c l = 30pf mclk mcsx[7:0] mad[24:0] mdqm[1:0] mwex madata[15:0] moex i n v a l i d t d q m l t r e h a d d r e s s t c s l t a v t r e l r d a d d r e s s w d t d q m h t w e h t w e l t d h t d s t o d t a v t c s h t c y c l e t d q m l t d q m h t o d s
document number: 002 - 04918 rev.*a page 88 of 158 MB9B160R series multiplexed bus access asynchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max multiplexed address delay time t ale - chmadv male, madata[15:0] v cc 4.5v 0 10 ns v cc < 4.5v 20 multiplexed address hold time t chmadh v cc 4.5v mclkn+0 mclkn+10 ns v cc < 4.5v mclkn+0 mclkn+20 note: when the external load capacitance c l = 30pf (m = 0 to 15, n = 1 to 16) mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04918 rev.*a page 89 of 158 MB9B160R series multiplexed bus access synchronous sram mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max male delay time t chal mclk, ale v cc 4.5v 1 9 ns v cc < 4.5v 12 ns t chah v cc 4.5v 1 9 ns v cc < 4.5v 12 ns mclk multiplexed address delay time t chmadv mclk, madata[15:0] v cc 4.5v 1 t od ns v cc < 4.5v mclk multiplexed data output time t chmadx v cc 4.5v 1 t od ns v cc < 4.5v note: when the external load capacitance c l = 30pf mclk mcsx[7:0] male moex mwex madata[15:0] mad [24:0] mdqm [1:0]
document number: 002 - 04918 rev.*a page 90 of 158 MB9B160R series nand flash mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit min max mnrex min pulse width t nrew mnrex v cc 4.5v mclkn - 3 - ns v cc < 4.5v data set up mnrex time t ds C nre mnrex, madata[15:0] v cc 4.5v 20 - ns v cc < 4.5v 38 - mnrex data hold time t dh C nre mnrex, madata[15:0] v cc 4.5v 0 - ns v cc < 4.5v mnale mnwex delay time t aleh - nwel mnale, mnwex v cc 4.5v mclkm - 9 mclkm+9 ns v cc < 4.5v mclkm - 12 mclkm+12 mnale mnwex delay time t alel - nwel mnale, mnwex v cc 4.5v mclkm - 9 mclkm+9 ns v cc < 4.5v mclkm - 12 mclkm+12 mncle mnwex delay time t cleh - nwel mncle, mnwex v cc 4.5v mclkm - 9 mclkm+9 ns v cc < 4.5v mclkm - 12 mclkm+12 mnwex mncle delay time t nweh - clel mncle, mnwex v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 mnwex min pulse width t nwew mnwex v cc 4.5v mclkn - 3 - ns v cc < 4.5v mnwex data output time t nwel C dv mnwex, madata[15:0] v cc 4.5v - 9 + 9 ns v cc < 4.5v - 12 +12 mnwex data hold time t nweh C dx mnwex, madata[15:0] v cc 4.5v 0 mclkm+9 ns v cc < 4.5v mclkm+12 note: when the external load capacitance c l = 30pf (m = 0 to 15, n = 1 to 16) nand flash read mclk mnrex madata [ 15 : 0 ] read
document number: 002 - 04918 rev.*a page 91 of 158 MB9B160R series nand flash address write nand flash command write mclk mnale mncle madata [ 15 : 0 ] mnwex w rite mclk mnale mncle madata [ 15 : 0 ] mnwex w rite
document number: 002 - 04918 rev.*a page 92 of 158 MB9B160R series external ready input timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max mclk mrdy input setup time t rdyi mclk, mrdy v cc 4.5v 19 - ns v cc < 4.5v 37 ? when rdy is input ? when rdy is released mclk original moex mwex mrdy mclk extended moex mwex mrdy over 2cycle t rdyi 2 cycle t rdyi 0.5vcc
document number: 002 - 04918 rev.*a page 93 of 158 MB9B160R series sdram mode (v cc = 2.7v to 3.6v, v ss = 0v) parameter symbol pin name value unit min max output frequency t cycsd msdclk - 32 mhz address delay time t aosd msdclk, mad[15:0] 2 12 ns msdclk data output delay time t dosd msdclk, madata[31:0] 2 12 ns msdclk data output hi - z time t dozsd msdclk, madata[31:0] 2 20 ns mdqm[1:0] delay time t wrosd msdclk, mdqm[1:0] 1 12 ns mcsx delay time t mcssd msdclk, mcsx8 2 12 ns mrasx delay time t rassd msdclk, mrasx 2 12 ns mcasx delay time t cassd msdclk, mcasx 2 12 ns msdwex delay time t mwesd msdclk, msdwex 2 12 ns msdcke delay time t ckesd msdclk, msdcke 2 12 ns data set up time t dssd msdclk, madata[31:0] 23 - ns data hold time t dhsd msdclk, madata[31:0] 0 - ns note: when the external load capacitance c l = 30pf
document number: 002 - 04918 rev.*a page 94 of 158 MB9B160R series sdram a ccess r d w d m s d c l k m d q m [ 1 : 0 ] m c s x m r a s x m c a s x m s d w e x m s d c k e m a d a t a [ 1 5 : 0 ] a d d r e s s m a d a t a [ 1 5 : 0 ] m a d [ 2 4 : 0 ] t c y c s d t a o s d t w r o s d t m c s s d t r a s s d t c a s s d t m w e s d t c k e s d t d o s d t d o z s d t d s s d t d h s d
document number: 002 - 04918 rev.*a page 95 of 158 MB9B160R series 12.4.10 base timer input timing timer input timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max input pulse width t tiwh , t tiwl tioan/tiobn (when using as eck, tin) - 2 t cycp - ns trigger input timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max input pulse width t trgh , t trgl tioan/tiobn (when using as tgin) - 2 t cycp - ns note: t cycp indicates the apb bus clock cycle time. about the apb bus number which the base timer is connected to, see block diagram in this datasheet. eck tin tgin t tiwh v ihs v ihs v ils v ils t tiw l t trgh v ihs v ihs v ils v ils t trg l
document number: 002 - 04918 rev.*a page 96 of 158 MB9B160R series 12.4.11 uart timing synchronous serial (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5 v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns scksot delay time t slovi sckx, sotx - 30 + 30 - 20 + 20 ns sinsck setup time t ivshi sckx, sinx 50 - 30 - ns scksin hold time t shixi sckx, sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns scksot delay time t slove sckx, sotx - 50 - 30 ns sinsck setup time t ivshe sckx, sinx 10 - 10 - ns scksin hold time t shixe sckx, sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is no t guaranteed. ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 97 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 04918 rev.*a page 98 of 158 MB9B160R series synchronous serial (spi = 0, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns scksot delay time t shovi sckx, sotx - 30 + 30 - 20 + 20 ns sinsck setup time t ivsli sckx, sinx 50 - 30 - ns scksin hold time t slixi sckx, sinx 0 - 0 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns scksot delay time t shove sckx, sotx - 50 - 30 ns sinsck setup time t ivsle sckx, sinx 10 - 10 - ns scksin hold time t slixe sckx, sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 99 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 04918 rev.*a page 100 of 158 MB9B160R series synchronous serial (spi = 1, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns scksot delay time t shovi sckx, sotx - 30 + 30 - 20 + 20 ns sinsck setup time t ivsli sckx, sinx 50 - 30 - ns scksin hold time t slixi sckx, sinx 0 - 0 - ns sotsck delay time t sovli sckx, sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns scksot delay time t shove sckx, sotx - 50 - 30 ns sinsck setup time t ivsle sckx, sinx 10 - 10 - ns scksin hold time t slixe sckx, sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. ? about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 101 of 158 MB9B160R series ms bit = 0 ms bit = 1 *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 04918 rev.*a page 102 of 158 MB9B160R series synchronous serial (spi = 1, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns scksot delay time t slovi sckx, sotx - 30 + 30 - 20 + 20 ns sinsck setup time t ivshi sckx, sinx 50 - 30 - ns scksin hold time t shixi sckx, sinx 0 - 0 - ns sotsck delay time t sovhi sckx, sotx 2t cycp - 30 - 2t cycp - 30 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp - 10 - 2t cycp - 10 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns scksot delay time t slove sckx, sotx - 50 - 30 ns sinsck setup time t ivshe sckx, sinx 10 - 10 - ns scksin hold time t shixe sckx, sinx 20 - 20 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the same relocate port number. for example, the combination of sclkx_0 and sotx_1 is not guaranteed. ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 103 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe
document number: 002 - 04918 rev.*a page 104 of 158 MB9B160R series when using synchronous serial chip select (spi = 1, scinv = 0, ms = 0, cslvl = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 50 (*1)+0 (*1) - 50 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns scs deselect time t csdi (*3) - 50 +5t cycp (*3)+50 +5t cycp (*3) - 50 +5t cycp (*3)+50 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +30 - 3t cycp +30 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +30 - 3t cycp +30 - ns scs sut delay time t dse - 40 - 40 ns scs sut delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 105 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 04918 rev.*a page 106 of 158 MB9B160R series when using synchronous serial chip select (spi = 1, scinv = 1, ms = 0, cslvl = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 50 (*1)+0 (*1) - 50 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns scs deselect time t csdi (*3) - 50 +5t cycp (*3)+50 +5t cycp (*3) - 50 +5t cycp (*3)+50 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +30 - 3t cycp +30 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +30 - 3t cycp +30 - ns scs sot delay time t dse - 40 - 40 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 107 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 04918 rev.*a page 108 of 158 MB9B160R series when using synchronous serial chip select (spi = 1, scinv = 0, ms = 0, cslvl = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 50 (*1)+0 (*1) - 50 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns scs deselect time t csdi (*3) - 50 +5t cycp (*3)+50 +5t cycp (*3) - 50 +5t cycp (*3)+50 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +30 - 3t cycp +30 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +30 - 3t cycp +30 - ns scs sot delay time t dse - 40 - 40 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 109 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 04918 rev.*a page 110 of 158 MB9B160R series when using synchronous serial chip select (spi = 1, scinv = 1, ms = 0, cslvl = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 50 (*1)+0 (*1) - 50 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+50 (*2)+0 (*2)+50 ns scs deselect time t csdi (*3) - 50 +5t cycp (*3)+50 +5t cycp (*3) - 50 +5t cycp (*3)+50 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +30 - 3t cycp +30 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +30 - 3t cycp +30 - ns scs sot delay time t dse - 40 - 40 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacita nce c l = 30pf.
document number: 002 - 04918 rev.*a page 111 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 04918 rev.*a page 112 of 158 MB9B160R series high - speed synchronous serial (spi = 0, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx, sotx - 10 +10 - 10 +10 ns sinsck setup time t ivshi sckx, sinx 14 - 12.5 - ns 12.5 * sck sin hold time t shixi sckx, sinx 5 - 5 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp C 5 - 2t cycp C 5 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx, sotx - 15 - 15 ns sinsck setup time t ivshe sckx, sinx 5 - 5 - ns sck sin hold time t shixe sckx, 5 - 5 - ns sinx sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the following pins. ? no chip select : sin4_1, sot4_1, sck4_1 ? chip select : sin6_1, sot6_1, sck6_1, scs6_1 ? when the external load capacitance c l = 30pf. (for *, when c l = 10pf)
document number: 002 - 04918 rev.*a page 113 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc v oh v oh v ol v ol v ol v ih v il v ih v il t slovi t ivshi t shixi t slsh t shsl v ih t f tr v ih v oh v ih v il v il v ol v ih v il v ih v il t slove t ivshe t shixe
document number: 002 - 04918 rev.*a page 114 of 158 MB9B160R series high - speed synchronous serial (spi = 0, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx, sotx - 10 +10 - 10 +10 ns sinsck setup time t ivsli sckx, sinx 14 - 12.5 - ns 12.5 * sck sin hold time t slixi sckx, sinx 5 - 5 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp C 5 - 2t cycp C 5 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx, sotx - 15 - 15 ns sinsck setup time t ivsle sckx, sinx 5 - 5 - ns sck sin hold time t slixe sckx, sinx 5 - 5 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the following pins. ? no chip select : sin4_1, sot4_1, sck4_1 ? chip select : sin6_1, sot6_1, sck6_1, scs6_1 ? when the external load capacitance c l = 30pf. (for *, when c l = 10pf)
document number: 002 - 04918 rev.*a page 115 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc v oh v oh v oh v ol v ol v ih v il v ih v il t shovi t ivsli t slixi t shsl t slsh v ih tf tr v ih v oh v il v il v il v ol v ih v il v ih v il t shove t ivsle t slixe
document number: 002 - 04918 rev.*a page 116 of 158 MB9B160R series high - speed synchronous serial (spi = 1, scinv = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max serial clock cycle time t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns sck sot delay time t shovi sckx, sotx - 10 +10 - 10 +10 ns sinsck setup time t ivsli sckx, sinx 14 - 12.5 - ns 12.5 * sck sin hold time t slixi sckx, sinx 5 - 5 - ns sot sck delay time t sovli sckx, sotx 2t cycp C 10 - 2t cycp C 10 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp C 5 - 2t cycp C 5 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t shove sckx, sotx - 15 - 15 ns sinsck setup time t ivsle sckx, sinx 5 - 5 - ns sck sin hold time t slixe sckx, sinx 5 - 5 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the following pins. ? no chip select : sin4_1, sot4_1, sck4_1 ? chip select : sin6_1, sot6_1, sck6_1, scs6_1 ? when the external load capacitance c l = 30pf. (for *, when c l = 10pf)
document number: 002 - 04918 rev.*a page 117 of 158 MB9B160R series ms bit = 0 ms bit = 1 *: changes when writing to tdr register sck sot sin sck sot sin t sovli t scyc t shovi v ol v ol v oh v oh v ol v oh v ol v ih v il v ih v il t ivsli t slixi tf tr t slsh t shsl t shove v il v il v ih v ih v ih v oh * v ol v oh v ol v ih v il v ih v il t ivsle t slixe
document number: 002 - 04918 rev.*a page 118 of 158 MB9B160R series high - speed synchronous serial (spi = 1, scinv = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions v cc < 4.5v v cc 4.5v unit min max min max internal shift clock operation t scyc sckx internal shift clock operation 4t cycp - 4t cycp - ns sck sot delay time t slovi sckx, sotx - 10 +10 - 10 +10 ns sinsck setup time t ivshi sckx, sinx 14 - 12.5 - ns 12.5 * sck sin hold time t shixi sckx, sinx 5 - 5 - ns sot sck delay time t sovhi sckx, sotx 2t cycp C 10 - 2t cycp C 10 - ns serial clock "l" pulse width t slsh sckx external shift clock operation 2t cycp C 5 - 2t cycp C 5 - ns serial clock "h" pulse width t shsl sckx t cycp + 10 - t cycp + 10 - ns sck sot delay time t slove sckx, sotx - 15 - 15 ns sinsck setup time t ivshe sckx, sinx 5 - 5 - ns sck sin hold time t shixe sckx, sinx 5 - 5 - ns sck falling time tf sckx - 5 - 5 ns sck rising time tr sckx - 5 - 5 ns notes: ? the above characteristics apply to clk synchronous mode. ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? these characteristics only guarantee the following pins. ? no chip select : sin4_1, sot4_1, sck4_1 ? chip select : sin6_1, sot6_1, sck6_1, scs6_1 ? when the external load capacitance c l = 30pf. (for *, when c l = 10pf)
document number: 002 - 04918 rev.*a page 119 of 158 MB9B160R series ms bit = 0 ms bit = 1 sck sot sin sck sot sin t scyc t slovi v ol v oh v oh v oh v ol v oh v ol v ih v il v ih v il t ivshi t shixi t sovhi t shsl tr t slsh tf t slove v il v il v il v ih v ih v ih v oh v ol v oh v ol v ih v il v ih v il t ivshe t shixe
document number: 002 - 04918 rev.*a page 120 of 158 MB9B160R series when using high - speed synchronous serial chip select (spi = 1, scinv = 0, ms = 0, cslvl = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 20 (*1)+0 (*1) - 20 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns scs deselect time t csdi (*3) - 20 +5t cycp (*3)+20 +5t cycp (*3) - 20 +5t cycp (*3)+20 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +15 - 3t cycp +15 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +15 - 3t cycp +15 - ns scs sot delay time t dse - 25 - 25 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip select timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 121 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 04918 rev.*a page 122 of 158 MB9B160R series when using high - speed synchronous serial chip select (spi = 1, scinv = 1, ms = 0, cslvl = 1) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 20 (*1)+0 (*1) - 20 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns scs deselect time t csdi (*3) - 20 +5t cycp (*3)+20 +5t cycp (*3) - 20 +5t cycp (*3)+20 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +15 - 3t cycp +15 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +15 - 3t cycp +15 - ns scs sot delay time t dse - 25 - 25 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 123 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t c ss e t c s h e t c s d e t d e e t d s e
document number: 002 - 04918 rev.*a page 124 of 158 MB9B160R series when using high - speed synchronous serial chip select (spi = 1, scinv = 0, ms = 0, cslvl = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 20 (*1)+0 (*1) - 20 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns scs deselect time t csdi (*3) - 20 +5t cycp (*3)+20 +5t cycp (*3) - 20 +5t cycp (*3)+20 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +15 - 3t cycp +15 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +15 - 3t cycp +15 - ns scs sot delay time t dse - 25 - 25 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 125 of 158 MB9B160R series scs output sck output sot (s pi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 04918 rev.*a page 126 of 158 MB9B160R series when using high - speed synchronous serial chip select (spi = 1, scinv = 1, ms = 0, cslvl = 0) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions v cc < 4.5v v cc 4.5v unit min max min max scs sck setup time t cssi internal shift clock operation (*1) - 20 (*1)+0 (*1) - 20 (*1)+0 ns sck scs hold time t cshi (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns scs deselect time t csdi (*3) - 20 +5t cycp (*3)+20 +5t cycp (*3) - 20 +5t cycp (*3)+20 +5t cycp ns scs sck setup time t csse external shift clock operation 3t cycp +15 - 3t cycp +15 - ns sck scs hold time t cshe 0 - 0 - ns scs deselect time t csde 3t cycp +15 - 3t cycp +15 - ns scs sot delay time t dse - 25 - 25 ns scs sot delay time t dee 0 - 0 - ns (*1): cssu bit valueserial chip select timing operating clock cycle [ns] (*2): cshd bit valueserial chip select timing operating clock cycle [ns] (*3): csds bit valueserial chip select timing operating clock cycle [ns] notes: ? t cycp indicates the apb bus clock cycle time. about the apb bus number which uart is connected to, see block diagram in this datasheet. ? about cssu, cshd, csds, serial chip sele ct timing operating clock, see fm4 family peripheral manual . ? when the external load capacitance c l = 30pf.
document number: 002 - 04918 rev.*a page 127 of 158 MB9B160R series scs output sck output sot (spi=0) sot (spi=1) scs input sck input sot (spi=0) sot (spi=1) t c ss i t c s h i t c s d i t csse t cshe t csde t dee t dse
document number: 002 - 04918 rev.*a page 128 of 158 MB9B160R series external clock (ext = 1) : when in asynchronous mode only (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol condition value unit remarks min max serial clock "l" pulse width t slsh c l = 30pf t cycp + 10 - ns serial clock "h" pulse width t shsl t cycp + 10 - ns sck falling time tf - 5 ns sck rising time tr - 5 ns s ck t shsl v i l v i l v i l v ih v ih v ih tr tf t slsh
document number: 002 - 04918 rev.*a page 129 of 158 MB9B160R series 12.4.12 external input timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max input pulse width t inh , t inl adtg - 2t cycp * 1 - ns a/d converter trigger input frckx free - run timer input clock icxx input capture dttixx - 2t cycp * 1 - ns waveform generator int00 to int31, nmix - 2t cycp + 100* 1 - ns external interrupt, nmi 500* 2 - ns wkupx - 500* 3 - ns deep standby wake up *1: t cycp indicates the apb bus clock cycle time except stop when in stop mode, in timer mode. about the apb bus number which the a/d converter, multi - function timer, external i nterrupt are connected to, see block diagram in this data sheet. *2: when in stop mode, in timer mode. *3: when in deep standby rtc mode, in deep standby stop mode.
document number: 002 - 04918 rev.*a page 130 of 158 MB9B160R series 12.4.13 quadrature position/revolution counter timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions value unit min max ain pin "h" width t ahl - 2t cycp * - ns ain pin "l" width t all - bin pin "h" width t bhl - bin pin "l" width t bll - bin rising time from ain pin "h" level t aubu pc_mode2 or pc_mode3 ain falling time from bin pin "h" level t buad pc_mode2 or pc_mode3 bin falling time from ain pin "l" level t adbd pc_mode2 or pc_mode3 ain rising time from bin pin "l" level t bdau pc_mode2 or pc_mode3 ain rising time from bin pin "h" level t buau pc_mode2 or pc_mode3 bin falling time from ain pin "h" level t aubd pc_mode2 or pc_mode3 ain falling time from bin pin "l" level t bdad pc_mode2 or pc_mode3 bin rising time from ain pin "l" level t adbu pc_mode2 or pc_mode3 zin pin "h" width t zhl qcr:cgsc = "0" zin pin "l" width t zll qcr:cgsc = "0" ain/bin rising and falling time from determined zin level t zabe qcr:cgsc = "1" determined zin level from ain/bin rising and falling time t abez qcr:cgsc = "1" * : t cycp indicates the apb bus clock cycle time except stop whe n in stop mode, in timer mode. about the apb bus number which quadrature position/revolution counter is connected to, see block diagram in this data sheet. ain bin t aubu t buad t adbd t bdau t ahl t all t bhl t bll
document number: 002 - 04918 rev.*a page 131 of 158 MB9B160R series zin zin ain/bin bin t buau t aubd t bdad t adbu t bhl t bll t ahl t all ain
document number: 002 - 04918 rev.*a page 132 of 158 MB9B160R series 12.4.14 i 2 c timing typical mode, high - speed mode (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions typical mode high - speed mode uni t remarks min max min max scl clock frequency f scl c l = 30pf, r = (vp/i ol ) * 1 0 100 0 400 khz (repeated) start condition hold time sda scl t hdsta 4.0 - 0.6 - s scl clock "l" width t low 4.7 - 1.3 - s scl clock "h" width t high 4.0 - 0.6 - s (repeated) start condition setup time scl sda t susta 4.7 - 0.6 - s data hold time scl sda t hddat 0 3.45* 2 0 0.9* 3 s data setup time sda scl t sudat 250 - 100 - ns stop condition setup time scl sda t susto 4.0 - 0.6 - s bus free time between "stop condition" and "start condition" t buf 4.7 - 1.3 - s noise filter t sp 2mhz t cycp <40mhz 2 t cycp * 4 - 2 t cycp * 4 - ns *5 40mhz t cycp < 60mhz 4 t cycp * 4 - 4 t cycp * 4 - ns 60mhz t cycp <80mhz 6 t cycp * 4 - 6 t cycp * 4 - ns 80mhz t cycp <100mhz 8 t cycp * 4 - 8 t cycp * 4 - ns 100mhz t cycp <120mhz 10 t cycp * 4 - 10 t cycp * 4 - ns 120mhz t cycp <140mhz 12 t cycp * 4 - 12 t cycp * 4 - ns 140mhz t cycp <160mhz 14 t cycp * 4 - 14 t cycp * 4 - ns 160mhz t cycp <180mhz 16 t cycp * 4 - 16 t cycp * 4 - ns *1 : r and c l represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it does not extend at least "l" period (t low ) of device's scl signal. *3 : a high - speed mode i 2 c bus device can be used on a typical mode i 2 c bus system as long as the device satisfies the requirement of t sudat 250 ns . *4 : t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see block diagram in this data sheet. *5 : the noise filter time can be changed by register settings. change the number of the noise filter steps according to apb bus clock frequency.
document number: 002 - 04918 rev.*a page 133 of 158 MB9B160R series fast mode plus (fm+) (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol conditions fast mode plus (fm+)* 6 unit remarks min max scl clock frequency f scl c l = 30pf, r = (vp/i ol ) * 1 0 1000 khz (repeated) start condition hold time sda scl t hdsta 0.26 - s scl clock "l" width t low 0.5 - s scl clock "h" width t high 0.26 - s scl clock frequency t susta 0.26 - s (repeated) start condition hold time sda scl t hddat 0 0.45* 2, * 3 s data setup time sda scl t sudat 50 - ns stop condition setup time scl sda t susto 0.26 - s bus free time between "stop condition" and "start condition" t buf 0.5 - s noise filter t sp 60mhz t cycp <80mhz 6 t cycp * 4 - ns *5 80mhz t cycp <100mhz 8 t cycp * 4 - ns 100mhz t cycp <120mhz 10 t cycp * 4 - ns 120mhz t cycp <140mhz 12 t cycp * 4 - ns 140mhz t cycp <160mhz 14 t cycp * 4 - ns 160mhz t cycp <180mhz 16 t cycp * 4 - ns *1 : r and c l represent the pull - up resistance and load capacitance of the scl and sda lines, respectively. vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2 : the maximum t hddat must satisfy that it does not extend at least "l" period (t low ) of device's scl signal. *3 : a high - speed mode i 2 c bus device can be used on a typical mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250 ns". *4 : t cycp is the apb bus clock cycle time. about the apb bus number that i 2 c is connected to, see block diagram in this data sheet. to use fast mode plus (fm+), set the peripheral bus clock at 64 mhz or more. *5 : the noise filter time can be changed by register settings. change the number of the noise filter steps according to apb bus clock frequency. *6 : when using fast mode plus (fm+), set the i/o pin to the mode corresponding to i 2 c fm+ in the epfr register. see chapter : i/o port in f m4 family peripheral manua l for the details. sda s cl
document number: 002 - 04918 rev.*a page 134 of 158 MB9B160R series 12.4.15 sd card interface timing default - speed mode ? clock clk (all values are referred to v ih and v il ) (v cc = 2.7v to 3.6v, v ss = 0v) parameter symbol pin name conditions value remarks min max clock frequency data transfer mode f pp s_clk c card 10pf (1card) 0 16 mhz clock frequency identification mode f od s_clk 0*/100 400 khz clock low time t wl s_clk 10 - ns clock high time t wh s_clk 10 - ns clock rising time t tlh s_clk - 10 ns clock falling time t thl s_clk - 10 ns *: 0hz means to stop the clock. the given minimum frequency range is for cases were continues clock is required. ? card inputs cmd, dat (referenced to clock clk) parameter symbol pin name conditions value remarks min max input set - up time t isu s_cmd, s_data3:0 c card 10pf (1card) 5 - ns input hold time t ih s_cmd, s_data3:0 5 - ns ? card outputs cmd, dat (referenced to clock clk) parameter symbol pin name conditions value remarks min max output delay time during data transfer mode t odly s_cmd, s_data3:0 c card 40pf (1card) 0 22 ns output delay time durinn identification mode t odly s_cmd, s_data3:0 0 50 ns defalt - speed mode note: the card input corresponds to the host output and the card output corresponds to the host input because this model is the host. v il v il t wl t wh v ih v ih v ih t thl t tlh t isu v ih v il v ih v il t ih v oh v ol v oh v ol t odly(max) t odly(min) s_clk (sd clock) s_cmd, s_data3:0 (card input) s_cmd, s_data3:0 (card output)
document number: 002 - 04918 rev.*a page 135 of 158 MB9B160R series high - speed mode ? cloc k clk (all values are referred to v ih and v il ) (v cc = 2.7v to 3.6v, v ss = 0v) parameter symbol pin name conditions value remarks min max clock frequency data transfer mode f pp s_clk c card 10pf (1card) 0 32 mhz clock low time t wl s_clk 7 - ns clock high time t wh s_clk 7 - ns clock rising time t tlh s_clk - 3 ns clock falling time t thl s_clk - 3 ns ? card inputs cmd, dat (referenced to clock clk) parameter symbol pin name conditions value remarks min max input set - up time t isu s_cmd, s_data3:0 c card 10pf (1card) 8 - ns input hold time t ih s_cmd, s_data3:0 2 - ns ? card outputs cmd, dat (referenced to clock clk) parameter symbol pin name conditions value remarks min max output delay time during data transfer mode t odly s_cmd, s_data3:0 c l 40pf (1card) - 22 ns output hold time t oh s_cmd, s_data3:0 c l 15pf (1card) 2.5 - ns total system capacitance for each line* c l - 1card - 40 pf *: in order to satisfy severe timing, host shall drive only one card. high - speed mode notes: ? the card input corresponds to the host output and the card output corresponds to the host input because this model is the host. ? in high - speed mode, set the clock frequency (f pp ) and the ahb bus clock frequency to the same values. v il v il t wl t wh v ih v ih v ih t thl t tlh t isu v ih v il v ih v il t ih v oh v ol v oh v ol t odly(max) t oh(min) 50%v cc 50%v cc s_clk (sd clock) s_cmd, s_data3:0 (card input) s_cmd, s_data3:0 (card output)
document number: 002 - 04918 rev.*a page 136 of 158 MB9B160R series 12.4.16 etm timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max data hold t etmh traceclk, traced[3:0] v cc 4.5v 2 9 ns v cc < 4.5v 2 15 traceclk frequency 1/ t trace traceclk v cc 4.5v - 50 mhz v cc < 4.5v - 32 mhz traceclk clock cycle t trace v cc 4.5v 20 - ns v cc < 4.5v 31.25 - ns note: when the external load capacitance c l = 30pf. hclk traceclk traced[3:0]
document number: 002 - 04918 rev.*a page 137 of 158 MB9B160R series 12.4.17 jtag timing (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol pin name conditions value unit remarks min max tms, tdi setup time t jtags tck, tms, tdi v cc 4.5v 15 - ns v cc < 4.5v tms, tdi hold time t jtagh tck, tms, tdi v cc 4.5v 15 - ns v cc < 4.5v tdo delay time t jtagd tck, tdo v cc 4.5v - 25 ns v cc < 4.5v - 45 note: when the external load capacitance c l = 30pf. tck tms/ tdi tdo
document number: 002 - 04918 rev.*a page 138 of 158 MB9B160R series 12.5 12 - bit a/d converter electrical characteristics for the a/d converter (v cc = av cc = 2.7v to 5.5v, v ss = av ss = avrl = 0v) parameter symbol pin name value unit remarks min typ max resolution - - - - 12 bit integral nonlinearity - - - 4.5 - + 4.5 lsb avrh = 2.7v to 5.5v differential nonlinearity - - - 2.5 - + 2.5 lsb zero transition voltage v zt an00 to an23 - 15 - + 15 mv full - scale transition voltage v fst an00 to an23 avrh - 15 - avrh + 15 mv conversion time - - 0.5* 1 - - s av cc 4.5v sampling time ts - *2 - 10 s av cc 4.5v *2 - av cc < 4.5v compare clock cycle* 3 tcck - 25 - 1000 ns av cc 4.5v 50 - 1000 av cc < 4.5v state transition time to operation permission tstt - 1.0 - - s power supply current (analog + digital) - avcc - 0.69 0.92 ma a/d 1unit operation - 1.0 18 a when a/d stop reference power supply current (between avrh and avss) - avrh - 1.1 1.97 ma a/d 1unit operation avrh = 5.5v 0.3 6.3 a when a/d stop analog input capacity c ain - - - 12.05 pf analog input resistance r ain - - - 1.2 k av cc 4.5v 1.8 av cc < 4.5v interchannel disparity - - - - 4 lsb analog port input current - an00 to an23 - - 5 a analog input voltage - an00 to an23 av ss - avrh v reference voltage - avrh 2.7 - av cc v *1: the conversion time is the value of sampling time (ts) + compare time (tc). the condition of the minimum conversion time is when the value of sampling time: 150ns, the value of compare time: 350ns (av cc 4.5v). ensure that it satisfies th e value of sampling time (ts) and compare clock cycle (tcck). for setting* 4 of sampling time and compare clock cycle, see "chapter: a/d converter" in "fm4 family peripheral manual analog macro part". the register setting of the a/d converter is r eflected by the peripheral clock timing. the sampling and compare clock are set at base clock (hclk). *2: a necessary sampling time changes by external impedance. ensure that it set the sampling time to satisfy (equation 1). *3: the compare time (tc) is the value of (equation 2). *4: the register setting of the a/d converter is reflected by the timing of the apb bus clock. the sampling clock and compare clo ck are set in base clock (hclk). about the apb bus number which the a/d converter is connect ed to, see block diagram in this data sheet.
document number: 002 - 04918 rev.*a page 139 of 158 MB9B160R series (equation 1) ts (r ain + rext ) c ain 9 ts : sampling time r ain : input resistance of a/d = 1.2k at 4.5v < av cc < 5.5v input resistance of a/d = 1.8k at 2.7v < av cc < 4.5v c ain : input capacity of a/d = 12.05pf at 2.7v < av cc < 5.5v rext : output impedance of external circuit (equation 2) tc = tcck 14 tc : compare time tcck : compare clock cycle r ain c ain analog signal source rext an0 0 ~ an 23 analog input pin c omparator
document number: 002 - 04918 rev.*a page 140 of 158 MB9B160R series definition of 12 - bit a/d converter terms ? resolution : analog variation that is recognized by an a/d converter. ? integral nonlinearity : deviation of the line between the zero - transition point (0b000000000000 0b000000000001) and the full - scale transition point (0b111111111110 0b111111111111) from the actual conversion characteristics. ? differential nonlinearity : deviation from the ideal value of the input voltage that is required to change the output code by 1 lsb. integral nonlinearity of digital output n = v nt - {1lsb (n - 1) + v zt } [lsb] 1lsb differential nonlinearity of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v zt 4094 n : a/d converter digital output value. v zt : voltage at which the digital output changes from 0x000 to 0x001. v fst : voltage at which the digital output changes from 0xffe to 0xfff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn. integral nonl inearity differential non linearity digital output digital output actual conversion characteristics actual conversion characteristics ideal characteristics (actually - measured value) actual conversion characteristics actual conversion characteristics (actually - measured value) (actually - measured value) ideal characteristics (actually - measured value) analog input analog input (actually - measured value) 0x001 0x002 0x003 0x004 0x f fd 0x f fe 0x f ff avss avrh avss avrh 0x(n - 2) 0x(n - 1) 0x(n+1) 0xn {1 lsb(n - 1) + v zt } v nt v fst v zt v nt v (n+1)t
document number: 002 - 04918 rev.*a page 141 of 158 MB9B160R series 12.6 12 - bit d/a converter electrical characteristics for the d/a converter (v cc = av cc = 2.7vto5.5v, v ss = av ss = 0v) parameter symbol pin name value unit remarks min typ max resolution - dax - - 12 bit integral nonlinearity* inl - 16 - + 16 lsb differential nonlinearity* dnl - 0.98 - + 1.5 lsb output voltage offset v off - - 10.0 mv when setting 0x000 - 20.0 - + 1.4 mv when setting 0xfff analog output impedance r o 3.10 3.80 4.50 k d/a operation 2.0 - - m when d/a stop power supply current* idda avcc 260 330 410 a d/a 1unit operation av cc = 3.3v 400 510 620 a d/a 1unit operation av cc = 5.0v idsa - - 14 a when d/a stop *: during no load
document number: 002 - 04918 rev.*a page 142 of 158 MB9B160R series 12.7 low - voltage detection characteristics 12.7.1 low - voltage detection reset parameter symbol conditions value unit remarks min typ max detected voltage vdl - 2.25 2.45 2.65 v when voltage drops released voltage vdh - 2.30 2.50 2.70 v when voltage rises 12.7.2 interrupt of low - voltage detection parameter symbol conditions value unit remarks min typ max detected voltage vdl svhi = 00111 2.58 2.8 3.02 v when voltage drops released voltage vdh 2.67 2.9 3.13 v when voltage rises detected voltage vdl svhi = 00100 2.76 3.0 3.24 v when voltage drops released voltage vdh 2.85 3.1 3.34 v when voltage rises detected voltage vdl svhi = 01100 2.94 3.2 3.45 v when voltage drops released voltage vdh 3.04 3.3 3.56 v when voltage rises detected voltage vdl svhi = 01111 3.31 3.6 3.88 v when voltage drops released voltage vdh 3.40 3.7 3.99 v when voltage rises detected voltage vdl svhi = 01110 3.40 3.7 3.99 v when voltage drops released voltage vdh 3.50 3.8 4.10 v when voltage rises detected voltage vdl svhi = 01001 3.68 4.0 4.32 v when voltage drops released voltage vdh 3.77 4.1 4.42 v when voltage rises detected voltage vdl svhi = 01000 3.77 4.1 4.42 v when voltage drops released voltage vdh 3.86 4.2 4.53 v when voltage rises detected voltage vdl svhi = 11000 3.86 4.2 4.53 v when voltage drops released voltage vdh 3.96 4.3 4.64 v when voltage rises lvd stabilization wait time t lvdw - - - 4480 t cycp * s *: t cycp indicates the apb2 bus clock cycle time.
document number: 002 - 04918 rev.*a page 143 of 158 MB9B160R series 12.8 mainflash memory write/erase characteristics ( v cc = 2.7v to 5.5v ) parameter value unit remarks min typ max sector erase time large sector - 0.7 3.7 s includes write time prior to internal erase small sector 0.3 1.1 half word (16 - bit) write time write cycles < 100 times - 12 100 s not including system - level overhead time write cycles > 100 times 200 chip erase time - 13.6 68 s includes write time prior to internal erase write cycles and data hold time erase/write cycles (cycle) data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * * : this value comes from the technology qualification (using arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85c) . 12.9 workflash memory write/erase characteristics ( v cc = 2.7v to 5.5v ) parameter value unit remarks min typ max sector erase time - 0.3 1.5 s includes write time prior to internal erase half word (16 - bit) write time - 20 200 s not including system - level overhead time chip erase time - 1.2 6 s includes write time prior to internal erase write cycles and data hold time erase/write cycles (cycle) data hold time (year) 1,000 20 * 10,000 10 * 100,000 5 * * : this value comes from the technology qualification (using arrhenius equation to translate high temperature acceleration test result into average temperature value at + 85c) .
document number: 002 - 04918 rev.*a page 144 of 158 MB9B160R series 12.10 standby recovery time 12.10.1 recovery cause: interrupt/wkup the ti me from recovery cause reception of the internal circuit to the program operation start is shown. recovery count time (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol value unit remarks typ max* sleep mode ticnt hclk1 s high - speed cr timer mode main timer mode pll timer mode 40 80 s low - speed cr timer mode 450 900 s sub timer mode 881 1136 s rtc mode stop mode (high - speed cr /main/pll run mode return) 270 581 s rtc mode stop mode (low - speed cr/sub run mode return) 240 480 deep standby rtc mode with ram retention deep standby stop mode with ram retention 308 667 s without ram retention 308 667 s with ram retention *: the maximum value depends on the built - in cr accuracy. example of standby recovery operation (when in external interrupt recovery*) *: external interrupt is set to detecting fall edge. e x t . i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04918 rev.*a page 145 of 158 MB9B160R series example of standby recovery operation (when in internal resource interrupt recovery*) *: depending on the standby mode, interrupt from the internal resource is not included in the recovery cause. notes: ? the return factor is different in each low - power consumption modes. see chapter: low power consumption mode and operations of standby modes in fm4 family peripheral manual. ? when interrupt recoveries, the operation mode that cpu recoveries depends on the state before the low - power co nsumption mode transition. see chapter: low power consumption mode in fm4 family peripheral manual . i n t e r n a l r e s o u r c e i n t t i c n t i n t e r r u p t f a c t o r a c c e p t c p u o p e r a t i o n s t a r t a c t i v e i n t e r r u p t f a c t o r c l e a r b y c p u
document number: 002 - 04918 rev.*a page 146 of 158 MB9B160R series 12.10.2 recovery cause: reset the time from reset release to the program operation start is shown. recovery count time (v cc = 2.7v to 5.5v, v ss = 0v) parameter symbol value unit remarks typ max* sleep mode trcnt 111 267 s high - speed cr timer mode main timer mode pll timer mode 111 267 s low - speed cr timer mode 258 569 s sub timer mode 258 569 s rtc mode stop mode 258 569 s deep standby rtc mode with ram retention deep standby stop mode with ram retention 308 669 s without ram retention s with ram retention * : the maximum value depends on the built - in cr accuracy. example of standby recovery operation (when in initx recovery) i n i t x t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04918 rev.*a page 147 of 158 MB9B160R series example of standby recovery operation (when in internal resource reset recovery*) *: depending on the standby mode, the reset issue from the internal resource is not included in the recovery cause. notes: ? the return factor is different in each low - power consumption modes. see chapter: low power consumptio n mode and operations of standby modes in fm4 family peripheral manual . ? the time during the power - on reset/low - voltage detection reset is excluded to the recovery source. see 12.4.7 power - on reset timing in 12. 4. ac characteristics in 12. electrical characteristics " for the detail on the time during the power - on reset/low - voltage detection reset. ? when in recovery from reset, cpu changes to the high - speed cr run mode. when using the main clock or the pll clock, it is necessary to add the main clock os cillation stabilization wait time or the main pll clock stabilization wait time. ? the internal resource reset means the watchdog reset and the csv reset. i n t e r n a l r e s o u r c e r s t t r c n t i n t e r n a l r s t c p u o p e r a t i o n s t a r t r s t a c t i v e r e l e a s e
document number: 002 - 04918 rev.*a page 148 of 158 MB9B160R series 13. ordering information part number package mb9bf 1 68mpmc plastic ? lqfp (0.5mm pitch ), 80 pin ( fpt - 80 p - m 37 ) mb9bf 1 67mpmc mb9bf 1 66mpmc mb9bf 1 68mpmc1 plastic ? lqfp (0. 6 5mm pitch ), 80 pin ( fpt - 80 p - m 40 ) mb9bf 1 67mpmc1 mb9bf 1 66mpmc1 mb9bf 168 npmc plastic ? lqfp (0. 5 mm pitch ), 100 pin ( fpt - 100p - m23) mb9bf 167 npmc mb9bf 166 npmc mb9bf 168r pmc plastic ? lqfp (0.5mm pitch ), 120 pin ( fpt - 120p - m37) mb9bf 167r pmc mb9bf 166r pmc mb9bf 168 nbgl plastic ? pfbga (0.5 mm pitch ), 1 12 pin (bga - 112p - m05 ) mb9bf 167 nbgl mb9bf 166 nbgl mb9bf 1 68rbgl plastic ? pfbga (0.5 mm pitch ), 1 44 pin (bga - 144p - m09 ) mb9bf 1 67rbgl mb9bf 1 66rbgl mb9bf 1 68npqc plastic ? qfp (0.65mm pitch ), 100 pin ( fpt - 100p - m36 ) mb9bf 1 6 7 npqc mb9bf 1 6 6 npqc
document number: 002 - 04918 rev.*a page 149 of 158 MB9B160R series 14. package dimensions 120-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 16.0 mm 16.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.88 g code (reference ) p-lfqfp120-16 16-0.50 120-pin plastic lqfp (fpt -120p-m37) (fpt-120p-m37) c 2010 fujitsu semiconductor limited f120037sc(1)-1-1 16.00 0.10(.630 .004) sq 18.00 0.20(.709 .008) sq 1 30 31 61 91 60 90 120 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) ( ) 0.08(.003) "a" index .059 C .004 +.008 C 0.10 +0.20 1.50 (mounting height) 0? ~8 ? (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.05 (.004 .002) details of "a" part (stand off) * lead no. C 0.03 +0.05 0.145 C .001 +.002 .006 dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 04918 rev.*a page 150 of 158 MB9B160R series 100-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 14.00 mm 14.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.65 g 100-pin plastic lqfp (fpt-100p-m23) (fpt-100p-m23) c 2009-2010 fujitsu semiconductor limited f100034s-c-3-4 16.000.20(.630.008)sq 1 25 51 76 75 100 0.50(.020) 0.220.05 m 0.08(.003) *14.000.10(.551.004)sq 26 50 0.1450.055 (.006.002) 0.08(.003) "a" index 0 ~8 0.500.20 0.100.10 (stand off) + .008 + 0.20 (mounting height) - 0.10 1.50 .059 - .004 ( ) 0.600.15 0.25(.010) dimensions in mm (inches). note:the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. details of "a" part (.004.004) (.009.002) (.020.008) (.024.006)
document number: 002 - 04918 rev.*a page 151 of 158 MB9B160R series 100-pin plastic qfp lead pitch 0.65 mm pa ck age width pa ck age length 14.00 mm 20.00 mm lead shape gullwing sealing method plastic mold mounting height 3.35 mm max code (reference ) p-qfp100-14 20-0.6 5 100-pin plastic qfp (fpt-100p-m36) (fpt-100p-m36) 2011 fujitsu semiconductor limited hmbf100-36sc-1-1 c 1 30 31 50 51 80 81 100 20.000.20(.787.008) 23.900.40(.941.016) (.551.008) 17.90 0.40 (.705.016) index 0.65(.026) 0.32 0.05 (.013.002) m 0.13(.005) "a" 0.17 0.06 (.007 . 002) 0.10(.004) details of "a" part (.035 . 006) 0.88 0.15 (.031 . 008) 0.80 0.20 0.25(.010) 3.00 +0.35 C0.20 +.014 C.008 .118 (mounting height) 0.25 0.20 (.010 . 008) (stand off) 0~8 * * 14.000.20 di mensions in mm (inches). no te: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 04918 rev.*a page 152 of 158 MB9B160R series 80-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 12.00 mm 12.00 mm lead shape gullwing lead bend direction no rm al bend sealing method plastic mold mounting height 1.70 mm max we ight 0.47 g 80-pin plastic lqfp (fpt-80p-m37) (fpt-80p-m37) 2009-2010 fujitsu semiconductor limited f80037s-c-1-2 1 20 40 21 60 41 80 61 index *12.00 0.10(.472 .004)sq 14.00 0.20(.551 .008)sq 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" (stand off) details of "a" part (.004 .002) 0.10 0.05 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) 0.50 0.20 (mounting height) .059 C .004 +.008 C 0.10 +0.20 1.50 0~8 c dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 04918 rev.*a page 153 of 158 MB9B160R series
document number: 002 - 04918 rev.*a page 154 of 158 MB9B160R series
document number: 002 - 04918 rev.*a page 155 of 158 MB9B160R series
document number: 002 - 04918 rev.*a page 156 of 158 MB9B160R series 15. major changes spansion p ublication number: ds709 - 00004 - 1v0 - e page section change results - - preliminary data sheet 1 description deleted the following description : the products which are described in this data sheet are placed into type4 product categories in "fm4 family peripheral manual". 3 features multi - function serial interface [i 2 c] revised the following description : fast mode plus (fm+) (max 1000 kbps, only for ch.3 and ch.7) supported fast mode plus (fm+) (max 1000 kbps, only for ch.3=ch.a and ch.7=ch.b) supported 7 features u nique id added new section 9 product lineup function added unique id 51, 52 i/o circuit type revised the remarks of type o, p, q 59 handling devices handling when using debug pins added new section 60 block diagram revised the block diagram 72 electrical characteristics 2. recommended operating conditions revised t able for package thermal resistance and maximum permissible power 75 to 80 electrical characteristics 3 . dc characteristics (1) current rating ? r evised the value of tbd ? added the note to iccvbat 85 electrical characteristics 4 . ac characteristics (2) sub clock input characteristics r evised the waveform chart 85 electrical characteristics 4 . ac characteristics (3) built - in cr oscillationcharacteristics ? r evised the value of tbd ? revised the table and the note of built - in high - speed cr 144 electrical characteristics 5. 12 - bit a/d converter electrical characteristics for the a/d converter ? r evised the value of tbd ? revised the condition of the electrical characteristics table 147 electrical characteristics 6. 1 2 - bit d/a converter electrical characteristics for the d/a converter ? r evised the value of tbd ? revised the condition and remarks of the electrical characteristics table 150 electrical characteristics 1 0 . standby recovery time (1) recovery cause : interrupt /wkup ? r evised the value of tbd ? revised the table of recovery count time 152 electrical characteristics 1 0 . standby recovery time ( 2 ) recovery cause :reset ? r evised the value of tbd ? revised the table of recovery count time note : please see document history about later revised information.
document number: 002 - 04918 rev.*a page 157 of 158 MB9B160R series document history document title: MB9B160R series 32 - bit arm ? cortex ? - m4f, fm4 microcontroller document number: 002 - 04918 revision ecn orig. of change submission date description of change ** C akih 06/27/2013 migrated to cypress and assigned document number 002 - 04918 . no change to document contents or format . *a 5162380 akih 0 3 / 0 7 /201 6 updated to cypress format .
document number: 002 - 04918 rev.*a march 7, 2016 page 158 of 158 MB9B160R series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com /clocks interface cypress.com/interface lighting & power control cypress.com /powerpsoc memory cypress.com /memory psoc cypress.com /psoc touch sensing cypress .com /touch usb controllers cypress.com /usb wireless/rf cypress.com /wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support arm and cortex are the registered trademarks of arm limited in the eu and other countries. ? cypress semiconductor corporation 201 3 - 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