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preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 ez-ble? proc? xr module cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-15631 rev.*b revised december 16, 2016 general description the cyble-2x20xx-x1 is a bluetooth ? low energy (ble) wireless module solution. the cyble-2x20xx-x1 is a turnkey solution and includes onboard crystal oscillators, passive components, and the cypress proc? ble. refer to the cybl1xx7x datasheet for additional details on the capabilities of the proc ble device used on this module. the cyble-2x20xx-x1 supports a number of peripheral functions (adc, timers, counters, pwm) and serial communication protocols (i 2 c, uart, spi) through its programmable architecture. the cyble-2x20xx-x1 includes a royalty-free ble stack compatib le with bluetooth 4.2 and provides up to 19 gpios in a 15.0 23.0 2.0 mm package. the cyble-2x20xx-x1 is offered in two fully certified versions (CYBLE-212006-01 and cyble-202007-01), as well as an uncertified version (cyble-202013-11). the CYBLE-212006-01 includes an integrated trace antenna. the cyble-202007-01 supports an external antenna via a u-fl connector. the cyble-202013-11 supports an external antenna through a rf solder pad output. the cyble-202013-11 does not include a rf shield and is not bluetooth sig or regulatory certified. module description module size: 15.00 mm 23.00 mm 2.00 mm extended range: ? up to 400 meters bidirectional communication [1,2] ? up to 450 meters in beacon only mode [1] bluetooth 4.2 qualified single-mode module ? qdid: 88957 ? declaration id: d032786 footprint compatible options for integrated antenna or antenna-less design options certified to fcc, ic, mic, kc, and ce regulations (CYBLE-212006-01 and cyble-202007-01 only) castelated solder pad connections for ease-of-use 256-kb flash memory, 32-kb sram memory up to 19 gpios industrial temperature range: ?40 c to +85 c 32-bit processor (0.9 dmips/mh z) operating up to 48 mhz watchdog timer with dedicated internal low-speed oscillator power consumption maximum tx output power: +7.5 dbm rx receive sensitivity: ?93 dbm received signal strength indicator (rssi) with 1-db resolution tx current consumption ? ble silicon: 15.6 ma (radio only, 0 dbm) ? rfx2401c: 27 ma (pa/lna only, +7.5 dbm) rx current consumption ? ble silicon: 16.4 ma (radio only, 0 dbm) ? rfx2401c: 8.0 ma (pa/lna only) cypress cybl1xx7x silicon low power mode support ? deep sleep: 1.3 ? a with watch crystal oscillator (wco) on ? hibernate: 150 na with sram retention ? stop: 60 na with xres wakeup functional capabilities up to 18 capacitive sensors for buttons or sliders 12-bit, 1-msps sar adc with internal reference, sample-and-hold (s/h), and channel sequencer two serial communication blocks (scbs) supporting i 2 c (master/slave), spi (ma ster/slave), or uart four dedicated 16-bit timer, counter, or pwm blocks (tcpwms) lcd drive supported on all gpios (common or segment) programmable low voltage detect (lvd) from 1.8 v to 4.5 v i 2 s master interface ble protocol stack supporting generic access profile (gap) central, peripheral, observer, or broadcaster roles switches between central and peripheral roles on-the-go standard ble profiles and se rvices for interoperability custom profile and service for specific use cases benefits cyble-2x20xx-x1 is provided as a turnkey solution, including all necessary hardware requir ed to use ble communication standards. proven hardware design ready to use cost optimized for applicati ons without space constraint reprogrammable architecture fully certified module eliminates the time needed for design, development and certification bluetooth sig qualified with qdid and declaration id flexible communication protocol support psoc creator? provides an ea sy-to-use integrated design environment (ide) to configure, develop, program, and test a ble application notes 1. connection range tested module-to-module in full line-of-sight en vironment, free of obstacles or interference sources with ou tput power of +7.5 dbm. 2. specified as ez-ble xr module to module range. mobile phon e connection range will decrease based on the pa/lna performance of the mobile phone used.
document number: 002-15631 rev.*b page 2 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 more information cypress provides a wealth of data at www.cypress.com to help you to select the right modu le for your design, and to help you to quickly and effectively integrate the module into your design. overview: ez-ble module portfolio , module roadmap ez-ble proc product overview proc ble silicon datasheet application notes: cypress offers a number of ble application notes covering a broad range of topics, from basic to advanced level. recommended application notes for getting started with ez-ble modules are: ? an96841 - getting started with ez-ble module ? an94020 - getting started with proc ble ? an97060 - psoc ? 4 ble and proc? ble - over-the-air (ota) device firmware upgrade (dfu) guide ? an91162 - creating a ble custom profile ? an91184 - psoc 4 ble - designing ble applications ? an92584 - designing for low power and estimating battery life for ble applications ? an85951 - psoc ? 4 capsense ? design guide ? an95089 - psoc ? 4/proc? ble crystal oscillator selec- tion and tuning techniques ? an91445 - antenna design and rf layout guidelines technical reference manual (trm): ? proc ? ble technical reference manual knowledge base articles ? kba216542 - pin mapping differences between the ez-ble? proc? evaluation boards (cy- ble-212006-eval/cybl e-202007-eval/cy- ble-202013-eval) and the ble pioneer kit (cy8ckit-042-ble) ? kba97095 - ez-ble? module placement ? kba216380 - rf regulatory certifications for cy- ble-212006-01 and cyble-202007-01 ez-ble? proc? xr modules ? kba213976 - faq for ble and regulato ry certifications with ez-ble modules ? kba210802 - queries on ble qualification and declaration processes development kits: ? cyble-212006-eval , CYBLE-212006-01 eval board ? cyble-202007-eval , cyble-202007-01 eval board ? cyble-202013-eval , cyble-202013-11 eval board ? cy8ckit-042-ble , bluetooth ? low energy pioneer kit ? cy8ckit-002 , psoc ? miniprog3 program and debug kit test and debug tools: ? cysmart , bluetooth ? le test and debug tool (windows) ? cysmart mobile , bluetooth ? le test and debug tool (android/ios mobile app) two design environments to get you started quickly psoc ? creator? integrated design environment (ide) psoc creator is an integrated design environment (i de) that enables concurrent hardware and firmware editing, compiling and debugging of psoc 3, psoc 4, psoc 5lp, psoc 4 ble, proc bl e and ez-ble module systems with no code size limitations. psoc peripherals are designed using schematic capture and simple graphical user inte rface (gui) with over 120 pre-verified, production-ready psoc components?. psoc components are analog and digital ?virtual chips,? represent ed by an icon that users can drag-and-drop into a design and configure to suit a broad array of application requirements. bluetooth low energy component the bluetooth low energy component inside psoc creator provides a comprehensive gui-based configuration window that lets you quickly design ble applications. the component incorporates a bluet ooth core specification v4.1 co mpliant ble protocol stack an d provides api functions to enable user applications to interfac e with the underlying bluetooth low energy sub-system (bless) hardware via the stack. ez-serial? ble firmware platform the ez-serial firmware platform provides a simple way to access the most common hardware and communication features needed in ble applications. ez-serial implements an intuitive api protoc ol over the uart interface and exposes various status and cont rol signals through the module?s gpios, making it easy to add ble fu nctionality quickly to existing designs. use a simple serial te rminal and evaluation kit to begin development wi thout requiring an ide. refer to the ez-serial webpage for user manuals and instructions for getting started as well as detailed reference materials. ez-ble modules are pre-flashed with the ez-s erial firmware platform. if you do not hav e ez-serial pre-loaded on your module, yo u can download each ez-ble module?s firmware images on the ez-serial webpage . technical support frequently asked questions (faqs) : learn more about our ble eco system. forum : see if your question is already answered by fello w developers on the psoc 4 ble and proc ble forums. visit our support page and create a technical support case or contact a local sales representatives . if you are in the united states, you can talk to our technical support team by calling our to ll-free number: +1-800-541-4736. se lect option 2 at the prompt.
document number: 002-15631 rev.*b page 3 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 contents overview............................................................................ 4 module description.................. .................................... 4 pad connection interface ................................................ 6 recommended host pcb layout ................................... 7 digital and analog capabilities and connections......... 9 power supply connections and recommended external components.................................................................... 10 connection options................................................... 10 external component recomm endation ......... ........... 10 critical components list ........................................... 13 antenna design......................................................... 13 qualified antenna for cyble-202007-01 and cy- ble-202013-11 ............. .............. .............. .............. ......... 13 power amplifier (pa) and low noise amplifier (lna) 13 enabling extended range featur e ................ ........... 14 low power operation................................................ 14 electrical specification .................................................. 15 gpio ......................................................................... 17 xres......................................................................... 18 digital peripherals ..................................................... 21 serial communication ............................................... 23 memory ..................................................................... 24 system resources .................................................... 24 environmental specifications ....................................... 30 environmental compliance ....................................... 30 rf certification.......................................................... 30 safety certification .................................................... 30 environmental conditions ........ ............... .............. .... 30 esd and emi protection ........................................... 30 regulatory information .................................................. 31 fcc ........................................................................... 31 industry canada (ic) certific ation ............................. 32 european r&tte declaration of conformity ............ 32 mic japan ................ .............. .............. .............. ....... 33 kc korea................................................................... 33 packaging........................................................................ 34 ordering information...................................................... 36 part numbering convention ..... ................................. 36 acronyms ........................................................................ 37 document conventions ................................................. 37 units of measure ....................................................... 37 document history page ................................................. 38 sales, solutions, and legal information ...................... 39 worldwide sales and design supp ort............. .......... 39 products .................................................................... 39 psoc? solutions ...................................................... 39 cypress developer community................................. 39 technical support .................. ................................... 39
document number: 002-15631 rev.*b page 4 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 overview module description the cyble-2x20xx-x1 module is a complete module designed to be soldered to the applications main board. module dimensions and drawing cypress reserves the right to select com ponents (including the appropriate ble device) from various vendors to achieve the ble module functionality. such selections will still guarantee that all height restrictions of the component area are maintained. d esigns should be held within the physical dimensio ns shown in the mechanical drawings in figure 1 on page 5 . all dimensions are in millimeters (mm). table 1. module design dimensions see figure 1 on page 5 for the mechanical reference drawing for cyble-2x20xx-x1. dimension item specification module dimensions length (x) 15.00 0.15 mm width (y) 23.00 0.15 mm antenna location dimensions length (x) 15.00 0.15 mm width (y) 4.65 0.15 mm pcb thickness height (h) 0.80 0.10 mm shield height height (h) 1.20 0.10 mm maximum component height height (h) 1.20 mm typical (shield) - CYBLE-212006-01 1.25 mm typical (connector) - cyble-202007-01 0.75mm typical (crystal) - cyble-202013-11 total module thickness (bottom of module to highest component) height (h) 2.00 mm typical - CYBLE-212006-01 2.05 mm typical - cyble-202007-01 1.55 mm typical - cyble-202013-11
document number: 002-15631 rev.*b page 5 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 figure 1. module mechanical drawing top view bottom view side view note 3. no metal or traces should be located beneath or above the an tenna area. only bare pcb material should be located beneath the antenna area. for more information on recommended host pcb layout, see figure 3 , figure 4 , figure 5 , and figure 6 and ta b l e 3 .
document number: 002-15631 rev.*b page 6 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 pad connection interface as shown in the bottom view of figure 1 on page 5 , the cyble-2x20xx-x1 connects to the host board via solder pads on the backside of the module. ta b l e 2 and figure 2 detail the solder pad length, width, and pitc h dimensions of the cyble-2x20xx-x1 module. figure 2. solder pad dimensions (seen from bottom) to maximize rf performance, the host la yout should follow these recommendations: 1. the ideal placement of the cypress ble m odule is in a corner of the host board wit h the trace antenna located at the far corn er. this placement minimizes the additional recommended keep out area stated in item 2. please refer to an96841 for module placement best practices. 2. to maximize rf performance, the area immediately around th e cypress ble module trace antenna should contain an additional keep out area, where no grounding or signal trace are contained. the keep out area applie s to all layers of the host board. the recommended dimensions of the hos t pcb keep out area are shown in figure 3 (dimensions are in mm). figure 3. recommended host pcb keep ou t area around the cy ble-2x20xx-x1 antenna table 2. solder pad connection description name connections connection type pad length dimension pad width dimension pad pitch sp 30 solder pads 1.02 mm 0.71 mm 1.27 mm host pcb keep out area around trace antenna
document number: 002-15631 rev.*b page 7 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 recommended host pcb layout figure 4 , figure 5 , figure 6 , and ta b l e 3 provide details that can be used for the recommended host pcb layout pattern for the CYBLE-212006-01. dimensions are in millimeter s unless otherwise noted. pad length of 1. 27 mm (0.635 mm from center of the pad on either side) shown in figure 6 is the minimum recommended host pad length. the host pcb layout pattern can be completed using either figure 4 , figure 5 , or figure 6 . it is not necessary to use all figures to complete the host pcb layout pattern. figure 4. host layout pattern for cyble-2x20xx-x1 figure 5. module pad location from origin top view (seen on host pcb) top view (seen on host pcb)
document number: 002-15631 rev.*b page 8 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 ta b l e 3 provides the center location for each solder pad on the c yble-2x20xx-x1. all dimensions ar e referenced to the center of the solder pad. refer to figure 6 for the location of each module solder pad. table 3. module solder pad location figure 6. solder pad reference location solder pad (center of pad) location (x,y) from orign (mm) dimension from orign (mils) 1 (0.38, 10.54) (14.96, 414.96) 2 (0.38, 11.81) (14.96, 464.96) 3 (0.38, 13.08) (14.96, 514.96) 4 (0.38, 14.35) (14.96, 564.96) 5 (0.38, 15.62) (14.96, 614.96) 6 (0.38, 16.89) (14.96, 664.96) 7 (0.38, 18.16) (14.96, 714.96) 8 (0.38, 19.43) (14.96, 764.96) 9 (0.38, 20.70) (14.96, 814.96) 10 (0.38, 21.97) (14.96, 864.96) 11 (2.32, 22.62) (91.34, 890.55) 12 (3.59, 22.62) (141.34, 890.55) 13 (4.86, 22.62) (191.34, 890.55) 14 (6.13, 22.62) (241.34, 890.55) 15 (7.40, 22.62) (291.34, 890.55) 16 (8.67, 22.62) (341.34, 890.55) 17 (9.94, 22.62) (391.34,8 90.55) 18 (11.21, 22.62) (441.34, 890.55) 19 (12.48, 22.62) (491.34, 890.55) 20 (13.75, 22.62) (541.34, 890.55 21 (14.62, 20.70) (575.59, 814.96) 22 (14.62, 19.43) (575.59, 764.96) 23 (14.62, 18.16) (575.59, 714.96) 24 (14.62, 16.89) (575.59, 664.96) 25 (14.62, 15.62) (575.59, 614.96) 26 (14.62, 14.35) (575.59, 564.96) 27 (14.62, 13.08) (575.59, 514.96) 28 (14.62, 11.81) (575.59, 464.96) 29 see figure 2 see figure 2 30 see figure 2 see figure 2 top view (seen on host pcb)
document number: 002-15631 rev.*b page 9 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 digital and analog capabilities and connections ta b l e 4 details the solder pad connection definitions and available functions for each connection pad. ta b l e 4 lists the solder pads on cyble-2x20xx-x1, the ble device port-pin, and denotes whether the function shown is available for each solder pad. each connection is configurable for a single option shown with a ? . table 4. solder pad connection definitions solder pad number device port pin uart spi i 2 c tcpwm [4,5] capsense wco out eco out lcd swd gpio 1 gnd ground connection 2 xres external reset hardware connection input 3p4.0 [6] ? (scb1_rts) ? (scb1_mosi) ? (tcpwm0_p) ? (c mod ) ?? 4p3.7 ? (scb1_cts) ? (tcpwm) ? (sensor) ?? ? 5p3.6 ? (scb1_rts) ? (tcpwm) ? (sensor) ?? 6p3.5 ? (scb1_tx) ? (scb1_scl) ? (tcpwm) ? (sensor) ?? 7p3.4 ? (scb1_rx) ? (scb1_sda) ? (tcpwm) ? (sensor) ?? 8v ref reference voltage input (optional) 9p2.6 ? (tcpwm) ? (sensor) ?? 10 p2.4 ? (tcpwm) ? (sensor) ?? 11 p2.3 ? (tcpwm) ? (sensor) ?? ? 12 p2.2 ? (scb0_ss3) ? (tcpwm) ? (sensor) ?? 13 p2.0 ? (scb0_ss1) ? (tcpwm) ? (sensor) ?? 14 p1.7 ? (scb0_cts) ? (scb0_sclk ? (tcpwm) ? (sensor) ?? 15 p1.6 ? ( scb0_rts ) ? (scb0_ss0) ? (tcpwm) ? (sensor) ?? 16 p1.5 ? (scb0_tx) ? (scb0_miso) ? (scb0_scl) ? (tcpwm) ? (sensor) ?? 17 p1.4 ? (scb0_rx) ? (scb0_mosi) ? (scb0_sda) ? (tcpwm) ? (sensor) ?? 18 p0.7 ? (scb0_cts) ? (scb0_sclk ? (tcpwm) ? (sensor) ? ? (swdclk) ? 19 p1.0 ? (tcpwm) ? (sensor) ?? 20 p0.4 ? (scb0_rx) ? (scb0_mosi) ? (scb0_sda) ? (tcpwm) ? (sensor) ?? ? 21 p0.5 ? (scb0_tx) ? (scb0_miso) ? (scb0_scl) ? (tcpwm) ? (sensor) ?? 22 v dd digital power supply input (1.8 to 5.5v) 23 p0.6 ? (scb0_rts) ? (scb0_ss0) ? (tcpwm) ? (sensor) ? ? (swdio) ? 24 gnd [7] ground connection 25 gnd ground connection 26 gnd ground connection 27 gnd ground connection 28 v ddr radio power supply (2v to 3.6v) 29 gnd rf ground connection for use with cyble-202013-11 only; no connect for CYBLE-212006-01 and cyble-202007-01 30 ant rf pin to external antenna for use with cyble-202013 -11 only; no connect for CYBLE-212006-01 and cyble-202007-01 notes 4. tcpwm: timer, counter, and pulse width modulator. if supported, the pad can be configured to any of these peripheral function s. 5. tcpwm connections on ports 0, 1, 2, and 3 can be routed through the digital signal interconnect (dsi) to any of the tcpwm blo cks and can be either positive or negative polarity. tcpwm connections on port 4 are direct and can only be used with the specified tcpwm block and polarity s pecified above. 6. when using the capacitive sensing functionality, pad 3 (p4.0) must be connected to a c mod capacitor (located off of cypress ble module). the value of this capacitor is 2.2 nf and should be placed as close to the module as possible. 7. the main board needs to connect all gnd connections (pad 24/25/26/27) on the module to the common ground of the system. 8. if the i 2 s feature is used in the design, the i 2 s pins shall be dynamically routed to the app ropriate available gpio by psoc creator.
document number: 002-15631 rev.*b page 10 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 power supply connections and re commended external components power connections the cyble-2x20xx-x1 contains two power supply connec- tions, vdd and vddr. the vdd connection supplies power for both digital and analog device operation. the vddr connection supplies power for the device radio. vdd accepts a supply range of 1.71 v to 5.5 v. vddr accepts a supply range of 2.0v to 3. 6v. these specifications can be found in ta b l e 1 2 . the maximum power supply ripple for both power connections on the module is 100 mv, as shown in ta b l e 1 0 . the power supply ramp rate of vdd must be equal to or greater than that of vddr. connection options two connection options are available for any application: 1. single supply: connect vdd and vddr to the same supply. 2. independent supply: power vdd and vddr separately. external component recommendation in either connection scenario, it is recommended to place an external ferrite bead between the supply and the module connection. the ferrite bead should be positioned as close as possible to the module pin connection. figure 7 details the recommended host schematic options for a single supply scenario. the use of one or two ferrite beads will depend on the specific application and configuration of the cyble-2x20xx-x1. figure 8 details the recommended host schematic for an independent supply scenario. the recommended ferrite bead value is 330 ? , 100 mhz. (murata blm21pg331sn1d). figure 7. recommended host schematic options for a single supply option two ferrite bead option (seen from bottom) single ferrite bead opti on (seen from bottom)
document number: 002-15631 rev.*b page 11 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 figure 8. recommended host schematic for an independent supply option independent power supply option (seen from bottom)
document number: 002-15631 rev.*b page 12 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 the cyble-2x20xx-x1 schematic is shown in figure 9 . figure 9. cyble-2x20 xx-x1 schematic diagram
document number: 002-15631 rev.*b page 13 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 critical components list ta b l e 5 details the critical components used in the cyble-2x20xx-x1 module. table 5. critical component list antenna design ta b l e 6 details trace antenna used in the CYBLE-212006-01 module. for more information, see ta b l e 11 . table 6. trace antenna specifications qualified antenna for cyble-202007-01 and cyble-202013-11 the cyble-202007-01 module has been designed to work with a st andard 2.2 dbi dipole antenna. any antenna of equivalent or less gain can be used without additional application and testing for fcc regulations. ta b l e 7 details the approved antennas for the cyble-202007-01 module for ble operation. these antennas may al so be used for the cyble-202013-11 module, however all fcc and other regulatory testing will be required. table 7. qualified antenna power amplifier (pa) and low noise amplifier (lna) ta b l e 8 details the pa/lna that is used on the cyble-2x20xx-x1 module. for more information, see table 11 . table 8. power amplifier/low noise amplifier details ta b l e 9 details the power consumption of the integrated pa/lna used on the cyble-2x20xx-x1 module. ta b l e 9 only details the current consumption of the rfx2401c pa/lna. vdd= 3.3 v, t a = +25 c, measured on the rfx 2401c evaluation board, unless otherwise noted. table 9. power amplifier/low noise amplifier current consumption specifications component reference designator description silicon u1 56-pin qfn programmable radio-on-chip (proc) with ble crystal y1 24.000 mhz, 12pf crystal y2 32.768 khz, 12.5pf item description frequency range 2402?2480 mhz peak gain -0.5-dbi typical return loss 10-db minimum manufacturer part number gain antenova b4844-01 2.2 dbi rflink rf21c01228a 2.0 dbi pulse w1030 2.0 dbi item description pa/lna manufacturer skyworks inc. pa/lna part number rfx2401c power supply range 2.0 v to 3.6 v parameter test condition min typical max unit tx high power current pout = +20dbm 90 ma tx quiescent current no rf applied 17 ma rx quiescent current no rf applied 8 ma
document number: 002-15631 rev.*b page 14 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 enabling extended range feature the cyble-2x20xx-x1 modules come with an integrated power amp lifier/low noise amplifier to a llow for extended communication range of up to 400 meters full line-of-sight. this section de scribes the firmware steps requir ed to enable extended range opera tion of the cyble-2x20xx-x1 modules. the skyworks rfx2401c pa/lna is controlled by proc ble and uses two gpios: 1.one gpio to control the pa enable (p3[2]). the pa enabl e gpio is controlled directly by the ble link layer. 2.one gpio to control the lna enable (p3[3]). the lna en able gpio is controlled directly by the ble link layer. ensure that the proc ? ble silicon device ?adv/scan tx power level (dbm)? and ?connection tx power level (dbm)? in the ble component are both set to -12 dbm [9] to enable the extended range functionality, follow the steps outlined below. 1.open your project's main.c file and write the belo w code to define the register at the top of the code.. 2.locate/add the event ?cyble_evt _stack_on" in the appication code and insert the below two lines of code to enable the skyworks rfx2401c. low-power operation the cyble-2x20xx-x1 module is already optimized for low power o peration when in high output pow er, high gain mode. the cypress ble link layer will automatically enable tx high power operation, as well as rx high gain oper ation. when the radio tx or rx operation is not in use (i.e. sleep), the pa/lna will be set to shutdown mode by the ble link layer. this will occur during sle ep modes of the cypress proc ble silicon device. to learn more about optimiz e the cypress proc ble power consumption, refer to an92584: designing for low power and estimating battery life for ble applications . /* define the test register to switch the pa/lna hardware control pins */ #define cyreg_srss_tst_ddft_ctrl 0x40030008 /* mandatory events to be handled by ble application code */ case cyble_evt_stack_on: /* configure the link layer to automatically switch pa control pin p3[2] and lna control pin p3[3] */ cy_set_xtnd_reg32((void cyfar * )(cyreg_ble_bless_rf_config), 0x0331); cy_set_xtnd_reg32((void cyfar *)(cyreg_srss_tst_ddft_ctrl), 0x80000302); note 9. the CYBLE-212006-01 module is certified for fcc, ic, ce, mic and kc regulations at an output power of +7.5 dbm. to achieve th is output power, rf o2 (proc ble silicon pa level) must be set to the -12 dbm setti ng in firmware. settings higher than this will result in higher out put power than specified in the CYBLE-212006-01 certifications.
document number: 002-15631 rev.*b page 15 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 electrical specification ta b l e 1 0 details the absolute maximum electrical characteristics for the cypress ble module. table 10. cyble-2x20xx-x1 absolute maximum ratings ta b l e 11 details the rf characteristics for the cypress ble module. table 11. cyble-2x20xx-x1 rf performance characteristics ta b l e 1 2 through table 51 list the module level electrical characteristics for the cyble-2x20xx-x1. all spec ifications are valid for ?40 c ? t a ? 85 c and t j ? 100 c, except where noted. specifications are valid for 1.71 v to 5.5 v, except where noted. parameter description min typ max units details/conditions v ddd_abs analog, digital, or radi o supply relative to v ss (v ssd = v ssa ) ?0.5 ? 6 v absolute maximum v ccd_abs direct digital core voltage input relative to v ssd ?0.5 ? 1.95 v absolute maximum v dd_ripple maximum power supply ripple for v dd and v ddr input voltage ? ? 100 mv 3.0-v supply ripple frequency of 100 khz to 750 khz v gpio_abs gpio voltage ?0.5 ? v dd +0.5 v absolute maximum i gpio_abs maximum current per gpio ?2 5 ? 25 ma absolute maximum i gpio_injection gpio injection curre nt: maximum for v ih > v dd and minimum for v il < v ss ?0.5 ? 0.5 ma absolute maximum current injected per pin lu pin current for latch up ?200 200 ma ? parameter description min typ max units details/conditions rf o rf output power on ant 1 7.5 dbm configurable via silicon register settings rx s rf receive sensitivity on ant ? ?93 ? dbm measured value (CYBLE-212006-01) f r module frequency range 2402 ? 2480 mhz ? g p peak gain ? ?0.5 ? dbi ? rl return loss ? ?10 ? db ? table 12. cyble-2x20xx-x1 dc specifications parameter description min typ max units details/conditions v dd1 power supply input voltage 1.8 ? 5.5 v with regulator enabled v dd2 power supply input voltage unregulated 1.71 1.8 1.89 v internally unregulated supply v ddr1 radio supply voltage (radio on) 2.0 ? 3.6 v restricted by rfx2401c v ddr2 radio supply voltage (radio off) 2.0 ? 3.6 v ? active mode, v dd = 1.71 v to 5.5 v i dd3 execute from flash; cpu at 3 mhz ? 1.7 ? ma t = 25 c, v dd = 3.3 v i dd4 execute from flash; cpu at 3 mhz ? ? ? ma t = ?40 c to 85 c i dd5 execute from flash; cpu at 6 mhz ? 2.5 ? ma t = 25 c, v dd = 3.3 v i dd6 execute from flash; cpu at 6 mhz ? ? ? ma t = ?40 c to 85 c i dd7 execute from flash; cpu at 12 mhz ? 4 ? ma t = 25 c, v dd = 3.3 v i dd8 execute from flash; cpu at 12 mhz ? ? ? ma t = ?40 c to 85 c
document number: 002-15631 rev.*b page 16 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 i dd9 execute from flash; cpu at 24 mhz ? 7.1 ? ma t = 25 c, v dd = 3.3 v i dd10 execute from flash; cpu at 24 mhz ? ? ? ma t = ?40 c to 85 c i dd11 execute from flash; cpu at 48 mhz ? 13.4 ? ma t = 25 c, v dd = 3.3 v i dd12 execute from flash; cpu at 48 mhz ? ? ? ma t = ?40 c to 85 c sleep mode, v dd = 1.8v to 5.5v i dd13 imo on ? ? ? ma t = 25 c, v dd = 3.3 v, sysclk = 3 mhz sleep mode, v dd and v ddr = 1.9v to 5.5v i dd14 eco on ? ? ? ma t = 25 c, v dd = 3.3 v, sysclk = 3 mhz deep-sleep mode, v dd = 1.8 v to 3.6 v i dd15 wdt with wco on ? 1.5 ? ? a t = 25 c, v dd = 3.3 v i dd16 wdt with wco on ? ? ? ? a t = ?40 c to 85 c i dd17 wdt with wco on ? ? ? ? a t = 25 c, v dd = 5 v i dd18 wdt with wco on ? ? ? ? a t = ?40 c to 85 c deep-sleep mode, v dd = 1.71 v to 1.89 v (regulator bypassed) i dd19 wdt with wco on ? ? ? ? at = 25 c i dd20 wdt with wco on ? ? ? ? a t = ?40 c to 85 c hibernate mode, v dd = 1.8 v to 3.6 v i dd27 gpio and reset active ? 150 ? na t = 25 c, v dd = 3.3 v i dd28 gpio and reset active ? ? ? na t = ?40 c to 85 c hibernate mode, v dd = 3.6 v to 5.5 v i dd29 gpio and reset active ? ? ? na t = 25 c, v dd = 5 v i dd30 gpio and reset active ? ? ? na t = ?40 c to 85 c stop mode, v dd = 1.8 v to 3.6 v i dd33 stop-mode current (v dd )?20?na t = 25 c, v dd = 3.3 v i dd34 stop-mode current (v ddr ) ? 40 ?- na t = 25 c, v ddr = 3.3 v i dd35 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c i dd36 stop-mode current (v ddr )???na t = ?40 c to 85 c, v ddr = 1.9 v to 3.6 v stop mode, v dd = 3.6 v to 5.5 v i dd37 stop-mode current (v dd )???na t = 25 c, v dd = 5 v i dd38 stop-mode current (v ddr )???na t = 25 c, v ddr = 5 v i dd39 stop-mode current (v dd ) ? ? ? na t = ?40 c to 85 c i dd40 stop-mode current (v ddr ) ? ? ? na t = ?40 c to 85 c table 12. cyble-2x20xx-x1 dc specifications (continued) parameter description min typ max units details/conditions
document number: 002-15631 rev.*b page 17 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 table 13. ac specifications gpio parameter description min typ max units details/conditions f cpu cpu frequency dc ? 48 mhz 1.71 v ?? v dd ?? 5.5 v t sleep wakeup from sleep mode ? 0 ? ? s guaranteed by characterization t deepsleep wakeup from deep-sleep mode ? ? 25 ? s 24-mhz imo. guaranteed by characterization t hibernate wakeup from hibernate mode ? ? 2 ms guaranteed by characterization t stop wakeup from stop mode ? ? 2 ms xres wakeup table 14. gpio dc specifications parameter description min typ max units details/conditions v ih [10] input voltage high threshold 0.7 v dd ? ? v cmos input lvttl input, v dd < 2.7 v 0.7 v dd ? ? v ? lvttl input, v dd ? 2.7 v 2.0 ? ? v ? v il input voltage low threshold ? ? 0.3 v dd vcmos input lvttl input, v dd < 2.7 v ? ? 0.3 v dd v? lvttl input, v dd ? 2.7 v ? ? 0.8 v ? v oh output voltage high level v dd ?0.6 ? ? v i oh = 4 ma at 3.3-v v dd output voltage high level v dd ?0.5 ? ? v i oh = 1 ma at 1.8-v v dd v ol output voltage low level ? ? 0.6 v i ol = 8 ma at 3.3-v v dd output voltage low level ? ? 0.6 v i ol = 4 ma at 1.8-v v dd output voltage low level ? ? 0.4 v i ol = 3 ma at 3.3-v v dd r pullup pull-up resistor 3.5 5.6 8.5 k ? ? r pulldown pull-down resistor 3.5 5.6 8.5 k ? ? i il input leakage current (absolute value) ? ? 2 na 25 c, v dd = 3.3 v i il_ctbm input leakage on ctbm input pins ? ? 4 na ? c in input capacitance ? ? 7 pf ? v hysttl input hysteresis lvttl 25 40 ? mv v dd > 2.7 v v hyscmos input hysteresis cmos 0.05 v dd ? ? 1 ? i diode current through protection diode to v dd /v ss ? ? 100 ? a? i tot_gpio maximum total source or sink chip current ? ? 200 ma ? note 10. v ih must not exceed v dd + 0.2 v.
document number: 002-15631 rev.*b page 18 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 table 15. gpio ac specifications xres parameter description min typ max units details/conditions t risef rise time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf t fallf fall time in fast-strong mode 2 ? 12 ns 3.3-v v ddd , c load = 25 pf t rises rise time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf t falls fall time in slow-strong mode 10 ? 60 ns 3.3-v v ddd , c load = 25 pf f gpiout1 gpio fout; 3.3 v ? v dd ?? 5.5 v fast-strong mode ??33mhz 90/10%, 25 pf load, 60/40 duty cycle f gpiout2 gpio fout; 1.7 v ?? v dd ?? 3.3 v fast-strong mode ? ? 16.7 mhz 90/10%, 25 pf load, 60/40 duty cycle f gpiout3 gpio fout; 3.3 v ?? v dd ?? 5.5 v slow-strong mode ?? 7 mhz 90/10%, 25 pf load, 60/40 duty cycle f gpiout4 gpio fout; 1.7 v ?? v dd ?? 3.3 v slow-strong mode ??3.5mhz 90/10%, 25 pf load, 60/40 duty cycle f gpioin gpio input operating frequency 1.71 v ?? v dd ?? 5.5 v ? ? 48 mhz 90/10% v io table 16. ovt gpio dc specifications (p5_0 and p5_1 only) parameter description min typ max units details/conditions i il input leakage (absolute value). v ih > v dd ??10 ? a 25c, v dd = 0 v, v ih = 3.0 v v ol output voltage low level ? ? 0.4 v i ol = 20 ma, v dd > 2.9 v table 17. ovt gpio ac specifications (p5_0 and p5_1 only) parameter description min typ max units details/conditions t rise_ovfs output rise time in fast-strong mode 1.5 ? 12 ns 25-pf load, 10%?90%, v dd = 3.3 v t fall_ovfs output fall time in fast-strong mo de 1.5 ? 12 ns 25-pf load, 10%?90%, v dd = 3.3 v t risess output rise time in slow-strong mode 10 ? 60 ns 25 pf load, 10%-90%, v dd = 3.3 v t fallss output fall time in slow-strong mode 10 ? 60 ns 25 pf load, 10%-90%, v dd = 3.3 v f gpiout1 gpio f out ; 3.3 v ?? v dd ?? 5.5 v fast-strong mode ??24mhz 90/10%, 25 pf load, 60/40 duty cycle f gpiout2 gpio f out ; 1.71 v ?? v dd ?? 3.3 v fast-strong mode ??16mhz 90/10%, 25 pf load, 60/40 duty cycle table 18. xres dc specifications parameter description min typ max units details/conditions v ih input voltage high threshold 0.7 v ddd ? ? v cmos input v il input voltage low threshold ? ? 0.3 v ddd v cmos input r pullup pull-up resistor 3.5 5.6 8.5 k ? ? c in input capacitance ? 3 ? pf ? v hysxres input voltage hysteresis ? 100 ? mv ? i diode current through protection diode to v dd /v ss ? ? 100 ? a?
document number: 002-15631 rev.*b page 19 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 temperature sensor sar adc table 19. xres ac specifications parameter description min typ max units details/conditions t resetwidth reset pulse width 1 ? ? ? s? table 20. temperature sensor specifications parameter description min typ max units details/conditions t sensacc temperature-sensor accuracy ?5 1 5 c ?40 c to +85 c note 11. a maximum of six single-ended adc channels can be accomplished only if the amux buses are not being used for other funcitona lity (such as capsense). if the amux buses are being used for other functions, then t he maximum number of single-ended adc channels is four. similarly, if the amux buses are being used for other functionality, then the maximum number of differential adc channels is two. table 21. sar adc dc specifications parameter description min typ max units details/conditions a_res resolution ? ? 12 bits a_chnis_s number of channels - single-ended ? ? 6 6 full-speed [11] a-chnks_d number of channels - differential ? ? 3 diff inputs use neighboring i/o [11] a-mono monotonicity ? ? ? yes a_gainerr gain error ? ? 0.1 % with external reference a_offset input offset voltage ? ? 2 mv measured with 1-v v ref a_isar current consumption ? ? 1 ma a_vins input voltage range - single-ended v ss ?v dda v a_vind input voltage range - differential v ss ? v dda v a_inres input resistance ? ? 2.2 k ? a_incap input capacitance ? ? 10 pf vrefsar trimmed internal reference to sar ?1 ? 1 % percentage of vbg (1.024 v) table 22. sar adc ac specifications parameter description min typ max units details/conditions a_psrr power-supply rejection ratio 70 ? ? db measured at 1-v reference a_cmrr common-mode rejection ratio 66 ? ? db a_samp sample rate ? ? 1 msps fsarintref sar operating speed without external ref. bypass ? ? 100 ksps 12-bit resolution a_snr signal-to-noise ratio (snr) 65 ? ? db f in = 10 khz a_bw input bandwidth without aliasing ? ? a_samp/2 khz a_inl integral nonlinearity. v dd = 1.71 v to 5.5 v, 1 msps ?1.7 ? 2 lsb v ref = 1 v to v dd a_inl integral nonlinearity. v ddd = 1.71 v to 3.6 v, 1 msps ?1.5 ? 1.7 lsb v ref = 1.71 v to v dd
document number: 002-15631 rev.*b page 20 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 csd a_inl integral nonlinearity. v dd = 1.71 v to 5.5 v, 500 ksps ?1.5 ? 1.7 lsb v ref = 1 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 5.5 v, 1 msps ?1 ? 2.2 lsb v ref = 1 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 3.6 v, 1 msps ?1 ? 2 lsb v ref = 1.71 v to v dd a_dnl differential nonlinearity. v dd = 1.71 v to 5.5 v, 500 ksps ?1 ? 2.2 lsb v ref = 1 v to v dd a_thd total harmonic distortion ? ? ?65 db f in = 10 khz table 22. sar adc ac specifications (continued) parameter description min typ max units details/conditions csd block specifications parameter description min typ max units details/conditions v csd voltage range of operation 1.71 ? 5.5 v ? idac1 dnl for 8-bit resolution ?1 ? 1 lsb ? idac1 inl for 8-bit resolution ?3 ? 3 lsb ? idac2 dnl for 7-bit resolution ?1 ? 1 lsb ? idac2 inl for 7-bit resolution ?3 ? 3 lsb ? snr ratio of counts of finger to noise 5 ? ? ratio capacitance range of 9 pf to 35 pf, 0.1-pf sensitivity. radio is not operating during the scan i dac1_crt1 output current of idac1 (8 bits) in high range ? 612 ? ? a ? i dac1_crt2 output current of idac1 (8 bits) in low range ? 306 ? ? a ? i dac2_crt1 output current of idac2 (7 bits) in high range ? 305 ? ? a ? i dac2_crt2 output current of idac2 (7 bits) in low range ? 153 ? ? a ?
document number: 002-15631 rev.*b page 21 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 digital peripherals timer counter table 23. timer dc specifications parameter description min typ max units details/conditions i tim1 block current consumption at 3 mhz ? ? 42 ? a 16-bit timer i tim2 block current consumption at 12 mhz ? ? 130 ? a 16-bit timer i tim3 block current consumption at 48 mhz ? ? 535 ? a 16-bit timer table 24. timer ac specifications parameter description min typ max units details/conditions t timfreq operating frequency f clk ?48mhz t capwint capture pulse width (internal) 2 t clk ??ns t capwext capture pulse width (external) 2 t clk ??ns t timres timer resolution t clk ??ns t tenwidint enable pulse width (internal) 2 t clk ??ns t tenwidext enable pulse width (external) 2 t clk ??ns t timreswint reset pulse width (internal) 2 t clk ??ns t timresext reset pulse width (external) 2 t clk ??ns table 25. counter dc specifications parameter description min typ max units details/conditions i ctr1 block current consumption at 3 mhz ? ? 42 ? a 16-bit counter i ctr2 block current consumption at 12 mhz ? ? 130 ? a 16-bit counter i ctr3 block current consumption at 48 mhz ? ? 535 ? a 16-bit counter table 26. counter ac specifications parameter description min typ max units details/conditions t ctrfreq operating frequency f clk ?48mhz ? t ctrpwint capture pulse width (internal) 2 t clk ??ns ? t ctrpwext capture pulse width (external) 2 t clk ??ns ? t ctres counter resolution t clk ??ns ? t cenwidint enable pulse width (internal) 2 t clk ??ns ? t cenwidext enable pulse width (external) 2 t clk ??ns ? t ctrreswint reset pulse width (internal) 2 t clk ??ns ? t ctrreswext reset pulse width (external) 2 t clk ?? ns ?
document number: 002-15631 rev.*b page 22 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 pulse width modulation (pwm) lcd direct drive table 27. pwm dc specifications parameter description min typ max units details/conditions i pwm1 block current consumption at 3 mhz ? ? 42 ? a 16-bit pwm i pwm2 block current consumption at 12 mhz ? ? 130 ? a 16-bit pwm i pwm3 block current consumption at 48 mhz ? ? 535 ? a 16-bit pwm table 28. pwm ac specifications parameter description min typ max units details/conditions t pwmfreq operating frequency f clk ?48mhz ? t pwmpwint pulse width (internal) 2 t clk ??ns ? t pwmext pulse width (external) 2 t clk ??ns ? t pwmkillint kill pulse width (internal) 2 t clk ??ns ? t pwmkillext kill pulse width (external) 2 t clk ??ns ? t pwmeint enable pulse width (internal) 2 t clk ??ns ? t pwmenext enable pulse width (external) 2 t clk ??ns ? t pwmreswint reset pulse width (internal) 2 t clk ??ns ? t pwmreswext reset pulse width (external) 2 t clk ??ns ? table 29. lcd direct drive dc specifications parameter description min typ max units details/conditions i lcdlow operating current in low-power mode ? 17.5 ? ? a 16 4 small segment display at 50 hz c lcdcap lcd capacitance per segment/common driver ? 500 5000 pf ? lcd offset long-term segment offset ? 20 ? mv ? i lcdop1 lcd system operating current, v bias = 5 v ? 2 ? ma 32 4 segments. 50 hz at 25 c i lcdop2 lcd system operating current, v bias = 3.3 v ? 2 ? ma 32 4 segments 50 hz at 25 c table 30. lcd direct drive ac specifications parameter description min typ max units details/conditions f lcd lcd frame rate 10 50 150 hz ?
document number: 002-15631 rev.*b page 23 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 serial communication table 31. fixed i 2 c dc specifications table 33. fixed uart dc specifications table 34. fixed uart ac specifications parameter description min typ max units details/conditions i i2c1 block current consumption at 100 khz ? ? 50 ? a? i i2c2 block current consumption at 400 khz ? ? 155 ? a? i i2c3 block current consumption at 1 mbps ? ? 390 ? a? i i2c4 i 2 c enabled in deep-sleep mode ? ? 1.4 ? a? table 32. fixed i 2 c ac specifications parameter description min typ max units details/conditions f i2c1 bit rate ? ? 400 khz parameter description min typ max units details/conditions i uart1 block current consumption at 100 kbps ? ? 55 ? a? i uart2 block current consumption at 1000 kbps ? ? 312 ? a? parameter description min typ max units details/conditions f uart bit rate ? ? 1 mbps ? table 35. fixed spi dc specifications parameter description min typ max units details/conditions i spi1 block current consumption at 1 mbps ? ? 360 ? a? i spi2 block current consumption at 4 mbps ? ? 560 ? a? i spi3 block current consumption at 8 mbps ? ? 600 ? a? table 36. fixed spi ac specifications parameter description min typ max units details/conditions f spi spi operating frequency (master; 6x over sampling) ??8mhz ? table 37. fixed spi master mode ac specifications parameter description min typ max units details/conditions t dmo mosi valid after sclk driving edge ? ? 18 ns ? t dsi miso valid before sclk capturing edge full clock, late miso sampling used 20 ? ? ns full clock, late miso sampling t hmo previous mosi data hold time 0 ? ? ns referred to slave capturing edge table 38. fixed spi slave mode ac specifications parameter description min typ max units details/conditions t dmi mosi valid before sclk capturing edge 40 ? ? ns t dso miso valid after sclk driving edge ? ? 42 + 3 t cpu ns t dso_ext miso valid after sclk driving edge in external clock mode. v dd < 3.0 v ? ? 50 ns t hso previous miso data hold time 0 ? ? ns t sselsck ssel valid to first sc k valid edge 100 ? ? ns
document number: 002-15631 rev.*b page 24 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 memory system resources power-on-reset (por) table 39. flash dc specifications parameter description min typ max units details/conditions v pe erase and program voltage 1.71 ? 5.5 v ? t ws48 number of wait states at 32?48 mhz 2 ? ? cpu execution from flash t ws32 number of wait states at 16?32 mhz 1 ? ? cpu execution from flash t ws16 number of wait states for 0?16 mhz 0 ? ? cpu execution from flash table 40. flash ac specifications parameter description min typ max units details/conditions t rowwrite [12] row (block) write time (erase and program) ? ? 20 ms row (block) = 256 bytes t rowerase [12] row erase time ? ? 13 ms ? t rowprogram [12] row program time after erase ? ? 7 ms ? t bulkerase [12] bulk erase time (256 kb) ? ? 35 ms ? t devprog [12] total device program time ? ? 25 seconds ? f end flash endurance 100 k ? ? cycles ? f ret flash retention. t a ? 55 c, 100 k p/e cycles 20 ? ? years ? f ret2 flash retention. t a ? 85 c, 10 k p/e cycles 10 ? ? years ? note 12. it can take as much as 20 ms to write to flash. during this time, the device should not be reset, or flash operations will b e interrupted and cannot be relied on to have completed. reset sources include the xres pin, software resets , cpu lockup states and privilege violations, improper power supp ly levels, and watchdogs. make certain that these are not inadvertently activated. table 41. por dc specifications parameter description min typ max units details/conditions v riseipor rising trip voltage 0.80 ? 1.45 v ? v fallipor falling trip voltage 0.75 ? 1.40 v ? v iporhyst hysteresis 15 ? 200 mv ? table 42. por ac specifications parameter description min typ max units details/conditions t ppor_tr precision power-on reset (ppor) response time in active and sleep modes ??1 ? s? table 43. brown-out detect parameter description min typ max units details/conditions v fallppor bod trip voltage in active and sleep modes 1.64 ? ? v ? v falldpslp bod trip voltage in deep sleep 1.4 ? ? v ? table 44. hibernate reset parameter description min typ max units details/conditions v hbrtrip bod trip voltage in hibernate 1.1 ? ? v ?
document number: 002-15631 rev.*b page 25 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 voltage monitors (lvd) swd interface table 45. voltage monitor dc specifications parameter description min typ max units details/conditions v lvi1 lvi_a/d_sel[3:0] = 0000b 1.71 1.75 1.79 v ? v lvi2 lvi_a/d_sel[3:0] = 0001b 1.76 1.80 1.85 v ? v lvi3 lvi_a/d_sel[3:0] = 0010b 1.85 1.90 1.95 v ? v lvi4 lvi_a/d_sel[3:0] = 0011b 1.95 2.00 2.05 v ? v lvi5 lvi_a/d_sel[3:0] = 0100b 2.05 2.10 2.15 v ? v lvi6 lvi_a/d_sel[3:0] = 0101b 2.15 2.20 2.26 v ? v lvi7 lvi_a/d_sel[3:0] = 0110b 2.24 2.30 2.36 v ? v lvi8 lvi_a/d_sel[3:0] = 0111b 2.34 2.40 2.46 v ? v lvi9 lvi_a/d_sel[3:0] = 1000b 2.44 2.50 2.56 v ? v lvi10 lvi_a/d_sel[3:0] = 1001b 2.54 2.60 2.67 v ? v lvi11 lvi_a/d_sel[3:0] = 1010b 2.63 2.70 2.77 v ? v lvi12 lvi_a/d_sel[3:0] = 1011b 2.73 2.80 2.87 v ? v lvi13 lvi_a/d_sel[3:0] = 1100b 2.83 2.90 2.97 v ? v lvi14 lvi_a/d_sel[3:0] = 1101b 2.93 3.00 3.08 v ? v lvi15 lvi_a/d_sel[3:0] = 1110b 3.12 3.20 3.28 v ? v lvi16 lvi_a/d_sel[3:0] = 1111b 4.39 4.50 4.61 v ? lvi_idd block current ? ? 100 ? a? table 46. voltage monitor ac specifications parameter description min typ max units details/conditions t montrip voltage monitor trip time ? ? 1 ? s? table 47. swd interface specifications parameter description min typ max units details/conditions f_swdclk1 3.3 v ? v dd ? 5.5 v ? ? 14 mhz swdclk ?? 1/3 cpu clock frequency f_swdclk2 1.71 v ? v dd ? 3.3 v ? ? 7 mhz swdclk ?? 1/3 cpu clock frequency t_swdi_setup t = 1/f swdclk 0.25 t ? ? ns ? t_swdi_hold t = 1/f swdclk 0.25 t ? ? ns ? t_swdo_valid t = 1/f swdclk ? ? 0.5 t ns ? t_swdo_hold t = 1/f swdclk 1 ? ? ns ?
document number: 002-15631 rev.*b page 26 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 internal main oscillator internal low-speed oscillator table 52. eco trim value specification ble subsystem table 48. imo dc specifications parameter description min typ max units details/conditions i imo1 imo operating current at 48 mhz ? ? 1000 ? a? i imo2 imo operating current at 24 mhz ? ? 325 ? a? i imo3 imo operating current at 12 mhz ? ? 225 ? a? i imo4 imo operating current at 6 mhz ? ? 180 ? a? i imo5 imo operating current at 3 mhz ? ? 150 ? a? table 49. imo ac specifications parameter description min typ max units details/conditions f imotol3 frequency variation from 3 to 48 mhz ? ? 2 % with api-called calibration f imotol3 imo startup time ? 12 ? ? s? table 50. ilo dc specifications parameter description min typ max units details/conditions i ilo2 ilo operating current at 32 khz ? 0.3 1.05 ? a? table 51. ilo ac specifications parameter description min typ max units details/conditions t startilo1 ilo startup time ? ? 2 ms ? f ilotrim1 32-khz trimmed frequency 15 32 50 khz ? parameter description value details/conditions eco trim 24-mhz trim value (firmware configuration) 0x0000d0d0 optimum trim value that needs to be loaded to register cy_sys_xtal_blerd_bb_xo_captrim_reg table 53. ble subsystem parameter description min typ max units details/conditions rf receiver specification rxs, idle rx sensitivity with idle transmitter ? ?89 ? dbm ? rx sensitivity with idle transmitter excluding balun loss ? ?91 ? dbm guaranteed by design simulation rxs, dirty rx sensitivity with dirty transmitter ? ?87 ?70 dbm rf-phy specification (rcv-le/ca/01/c) rxs, highgain rx sensitivity in high-gain mode with idle transmitter ? ?91 ? dbm ? prxmax maximum input power ?10 ?1 ? dbm rf-phy specification (rcv-le/ca/06/c) ci1 cochannel interference, wanted signal at ?67 dbm and inter- ferer at frx ?9 21 db rf-phy specification (rcv-le/ca/03/c)
document number: 002-15631 rev.*b page 27 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 ci2 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 1 mhz ?tbd 15 db rf-phy specification (rcv-le/ca/03/c) ci3 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at frx 2 mhz ?tbd ? db rf-phy specification (rcv-le/ca/03/c) ci4 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at ? frx 3 mhz ?tbd ? db rf-phy specification (rcv-le/ca/03/c) ci5 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at image frequency (f image ) ?tbd ? db rf-phy specification (rcv-le/ca/03/c) ci3 adjacent channel interference wanted signal at ?67 dbm and inter- ferer at image frequency (f image 1mhz) ?tbd ? db rf-phy specification (rcv-le/ca/03/c) obb1 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 30?2000 mhz ? tbd ? dbm rf-phy specification (rcv-le/ca/04/c) obb2 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2003?2399 mhz ? tbd ? dbm rf-phy specification (rcv-le/ca/04/c) obb3 out-of-band blocking, wanted signal at ?67 dbm and inter- ferer at f = 2484?2997 mhz ? tbd ? dbm rf-phy specification (rcv-le/ca/04/c) obb4 out-of-band blocking, wanted signal a ?67 dbm and interferer at f = 3000?12750 mhz ? tbd ? dbm rf-phy specification (rcv-le/ca/04/c) imd inter modulation performance wanted signal at ?64 dbm and 1-mbps ble, third, fourth, and fifth offset channel tbd ? ? dbm rf-phy specification (rcv-le/ca/05/c) rxse1 receiver spurious emission 30 mhz to 1.0 ghz ??tbddbm 100-khz measurement bandwidth etsi en300 328 v1.8.1 rxse2 receiver spurious emission 1.0 ghz to 12.75 ghz ??tbddbm 1-mhz measurement bandwidth etsi en300 328 v1.8.1 rf transmitter specifications txp, acc rf power accuracy ? 1 ? db ? txp, range rf power control range ? 20 ? db ? txp, 0dbm output power, 0-db gain setting (pa7) ? 0 ? dbm ? txp, max output power, maximum power setting (pa10) ?3 ? dbm ? txp, min output power, minimum power setting (pa1) ? ?18 ? dbm ? f2avg average frequency deviation for 10101010 pattern 185 ? ? khz rf-phy specification (trm-le/ca/05/c) table 53. ble subsystem (continued) parameter description min typ max units details/conditions
document number: 002-15631 rev.*b page 28 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 f1avg average frequency deviation for 11110000 pattern 225 250 275 khz rf-phy specification (trm-le/ca/05/c) eo eye opening = ? f2avg/ ? f1avg tbd ? ? rf-phy specification (trm-le/ca/05/c) ftx, acc frequency accuracy ?150 ? 150 khz rf-phy specification (trm-le/ca/06/c) ftx, maxdr maximum frequency drift ?50 ? 50 khz rf-phy specification (trm-le/ca/06/c) ftx, initdr initial frequency drift ?20 ? 20 khz rf-phy specification (trm-le/ca/06/c) ftx, dr maximum drift rate ?20 ? 20 khz/ 50 ? s rf-phy specification (trm-le/ca/06/c) ibse1 in-band spurious emission at 2-mhz offset ???20dbm rf-phy specification (trm-le/ca/03/c) ibse2 in-band spurious emission at ? 3-mhz offset ??-30dbm rf-phy specification (trm-le/ca/03/c) txse1 transmitter spurious emissions (average), <1.0 ghz ? ? -55.5 dbm fcc-15.247 txse2 transmitter spurious emissions (average), >1.0 ghz ? ? -41.5 dbm fcc-15.247 rf current specifications irx receive current in normal mode ? 18.7 ? ma silicon only irx_rf radio receive current in normal mode ? 16.4 ? ma measured at v ddr irx, highgain receive current in high-gain mode ? 21.5 ? ma silicon only irx, lna receive current, lna ? 8.0 ? ma lna only itx, 3dbm tx current at 3-dbm setting (pa10) ? 20 ? ma silicon only itx, 0dbm tx current at 0-dbm setting (pa7) ? 16.5 ? ma silicon only itx_rf, 0dbm radio tx current at 0 dbm setting (pa7) ?15.6 ? ma silicon only. measured at v ddr itx_rf, 0dbm radio tx current at 0 dbm excluding balun loss ?14.2 ? ma silicon only. guaranteed by design simulation itx,-3dbm tx current at ?3-dbm setting (pa4) ? 15.5 ? ma silicon only itx,-6dbm tx current at ?6-dbm setting (pa3) ? 14.5 ? ma silicon only itx,-12dbm tx current at ?12-dbm setting (pa2) ? 13.2 ? ma silicon only itx,-18dbm tx current at ?18-dbm setting (pa1) ? 12.5 ? ma silicon only itx, +7.5dbm pa tx current at +7.5 dbm module txp silicon txp set to ?12-dbm setting (pa2) ?7.0 ? ma pa only current packet length of 0x01 continuous transmit ?27.0 ? ma pa only current packet length of 0xff continuous transmit itxrx, pa/lna pa/lna set to shutdown mode ? 1.0 ? ? a pa/lna only current table 53. ble subsystem (continued) parameter description min typ max units details/conditions
document number: 002-15631 rev.*b page 29 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 iavg_1sec, 7.5dbm average current at 1-second ble connection interval ?tbd ? ? a module txp: +7.5 dbm; 20-ppm master and slave clock accuracy. for empty pdu exchange iavg_4sec, 7.5dbm average current at 4-second ble connection interval ?tbd ? ? a module txp: +7.5 dbm; 20-ppm master and slave clock accuracy. for empty pdu exchange general rf specifications freq rf operating frequency 2400 ? 2482 mhz ? chbw channel spacing ? 2 ? mhz ? dr on-air data rate ? 1000 ? kbps ? idle2tx ble.idle to ble. tx transition time ? 120 140 ? s? idle2rx ble.idle to ble. rx transition time ? 75 120 ? s? rssi specifications rssi, acc rssi accuracy ? 5 ? db ? rssi, res rssi resolution ? 1 ? db ? rssi, per rssi sample period ? 6 ? ? s? table 53. ble subsystem (continued) parameter description min typ max units details/conditions
document number: 002-15631 rev.*b page 30 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 environmental specifications environmental compliance this cypress ble module is built in compliance with the rest riction of hazardous substances (rohs) and halogen free (hf) directives. the cypress module and components used to produce this module are rohs and hf compliant. rf certification the CYBLE-212006-01 and cyble-202007-01 modules will be certifie d under the following rf certification standards at production release. fcc: wap2006 ce ic: 7922a-2006 mic: 203-jn0599 kc: msip-crm-cyp-2006 safety certification the CYBLE-212006-01 and cyble-202007-01 modules comply with the following regulations: underwriters laboratories, inc. (ul) - filing e331901 csa tuv environmental conditions ta b l e 5 4 describes the operating and storage conditions for the cypress ble module. table 54. environmental co nditions for cyble-2x20xx-x1 esd and emi protection exposed components require special attention to esd and electromagnetic interference (emi). a grounded conductive layer inside the device enclosure is sugge sted for emi and esd performance. any openings in the enclosure near the module should be surrounded by a grounded conductive la yer to provide esd protection and a low-impedance path to groun d. device handling : proper esd protocol must be followed in manu facturing to ensure component reliability. description minimum specification maximum specification operating temperature ?40 c 85 c operating humidity (relative, non-condensation) 5% 85% thermal ramp rate ? 3 c/minute storage temperature ?40 c 85 c storage temperature and humidity ? 85 c at 85% esd: module integrated into system components [13] ? 15 kv air 2.2 kv contact note 13. this does not apply to the rf pins (ant, xtali, and xtalo). rf pins (ant, xtali, and xtalo) are tested for 500-v hbm.
document number: 002-15631 rev.*b page 31 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 regulatory information fcc fcc notice: the devices CYBLE-212006-01 and cyble-202007-01 comply with part 15 of the fcc rules. the dev ice meet the requirements for modular transmitter approval as detailed in fcc public notice da 00-1407.transmitter oper ation is subject to the following two c ondi- tions: (1) this device may not cause harmful interference, and (2 ) this device must accept any interference received, including interference that may cause undesired operation. caution: the fcc requires the user to be notified that any changes or modi fications made to this device that are not expressly approved by cypress semiconductor may void the user 's authority to oper ate the equipment. this equipment has been tested and found to comply with the limits for a class b digital device, pursuant to part 15 of the fcc rules. these limits are designed to provide reasonable protection agains t harmful interference in a residential installation. this equ ipment generates uses and can radiate radio frequency energy and, if no t installed and used in accordance with the instructions, may cause harmful interference to radio communications. however, there is no guarantee that interference will not occur in a particular i nstallation. if this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equi pment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: reorient or relocate the receiving antenna. increase the separation between the equipment and receiver. connect the equipment into an outlet on a circuit diff erent from that to which th e receiver is connected. consult the dealer or an experienced radio/tv technician for help labeling requirements: the original equipment manufactur er (oem) must ensure that fcc labelling requirem ents are met. this includes a clearly visible label on the outside of the oem enclosure specifying the appropri ate cypress semiconductor fcc i dentifier for this product as w ell as the fcc notice above. the fcc identifier is fcc id: wap2006. in any case the end product must be labeled exterior with ?contains fcc id: wap2006?. antenna warning: this device is tested with a standard sma connector and with antennas meeting the characteristics shown in table 7 on page 13 . when integrated in the oems product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. any antenna not in the following table must be tested to comply with fcc section 15.203 for unique anten na connectors and section 15.247 for emissions. rf exposure: to comply with fcc rf exposure requirements, the original eq uipment manufacturer (oem) must ensure to install the approved antenna in the previous. the preceding statement must be included as a caution statem ent in manuals, for products opera ting with the approved antennas in table 6 and table 7 on page 13 , to alert users on fcc rf exposure compliance. any notification to the end user of installation or removal instructions about the inte grated radio module is not allowed. the radiated output power of cyble-21200 6-01 with the trace antenna is far below the fcc radio frequency exposure limits. nevertheless, use CYBLE-212006-01 in such a manner that minimi zes the potential for human cont act during normal operation. end users may not be provided with the module installation inst ructions. oem integrators and e nd users must be provided with transmitter operating conditions for satisfying rf exposure compliance.
document number: 002-15631 rev.*b page 32 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 industry canada (i c) certification CYBLE-212006-01 and cyble-202007-01 are licensed to meet the regulatory requirement s of industry canada (ic), license: ic: 7922a-2006 manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions an d ensure compliance for sar and/or rf exposure limits. users can obta in canadian information on rf exposure and compliance from www.ic.gc.ca. this device has been designed to op erate with the antennas listed in table 6 and table 7 on page 13 , having a maximum gain of 2.2 dbi. antennas not included in this list or having a gain greater than 2.2 dbi are strictly prohi bited for use with this device. the required antenna impedance is 50 ohms. the antenna used for this transmitter must not be co-located or o perating in conjunction with any other antenna or transmitter. ic notice: the device CYBLE-212006-01 including the built-in trace anten na complies with canada rss-gen rules. the device meets the requirements for modular transmitter approval as detailed in r ss-gen. operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference th at may cause undesired operation. ic radiation exposure statement for canada this device complies with industry canada licence-exempt rss st andard(s). operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, includi ng interference that may cause undesired operation of the device. for the cyble- 202007-01, the sar exemption distance is 15 mm. le prsent appareil est conforme aux cnr d'industrie canada applic ables aux appareils radio exempts de licence. l'exploitation est autorise aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radiolectrique subi, mme si le brouillage est susceptible d'en compromettre le fonctionnement. pour le cyble-202007-01, la sar distance l'exemption est 15 mm. labeling requirements: the original equipment manufacturer (oem) must ensure that ic labelling requirements are met. this includes a clearly visible l abel on the outside of the oem enclosure specif ying the appropriate cypress semiconductor ic identifier for this product as well as the ic notice above. the ic identifier is 7922a-2006. in any case, the end product must be labeled in its exterior with "contains ic: 7922a-2006" european r&tte declaration of conformity hereby, cypress semiconductor declares that the bluetooth module CYBLE-212006-01 and cyble-202007-01 comply with the essential requirements and other relevant provisions of directive 1999/5/ec. as a result of the conformity assessment procedure described in annex iii of the directive 1999/5/ec, the end-customer equipment should be labeled as follows: all versions of the CYBLE-212006-01 and cyble-202007-01 in the sp ecified reference design can be used in the following countrie s: austria, belgium, cyprus, czech republic, de nmark, estonia, finland, france, germany, greece, hungary, ireland, italy, latvia, lithuania, luxembourg, malta, poland, portugal, slovakia, sl ovenia, spain, sweden, the netherlands, the united kingdom, switzerland, and norway.
document number: 002-15631 rev.*b page 33 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 mic japan CYBLE-212006-01 and cyble-202007-01 are certified as a module with type certification number 203-jn0599. end products that integrate CYBLE-212006-01 and cyble-202007-01 do not need ad ditional mic japan certific ation for the end product. end product can display the certific ation label of the embedded module. kc korea CYBLE-212006-01 and cyble-202007-01 are certified for us e in korea with certificate number msip-crm-cyp-2006.
document number: 002-15631 rev.*b page 34 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 packaging the cyble-2x20xx-x1 is offered in tape and reel packaging. figure 10 details the tape dimensions used for the cyble-2x20xx-x1. figure 10. cyble-2x20xx-x1 tape dimensions figure 11 details the orientation of the cyble-2x20xx-x1 in the tape as well as the direction for unreeling. figure 11. component orientation in tape and unreeling direction (illustration only) table 55. solder reflow peak temperature module part number package maximum peak temperature maximum time at peak temperature no. of cycles cyble-2x20xx-x1 30-pad smt 260 c 30 seconds 2 table 56. package moisture sensitivity level (msl), ipc/jedec j-std-2 module part number package msl cyble-2x20xx-x1 30-pad smt msl 3
document number: 002-15631 rev.*b page 35 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 figure 12 details reel dimensions used for the cyble-2x20xx-x1. figure 12. reel dimensions the cyble-2x20xx-x1 is designed to be used with pick-and- place equipment in an smt manuf acturing environment. the center-of-mass for the cyble- 2x20xx-x1 is detailed in figure 13 . figure 13. cyble-2x20xx-x1 center of mass (seen from top) cyble-202007-01 center of mass cyble-202013-11 center of mass CYBLE-212006-01 center of mass
document number: 002-15631 rev.*b page 36 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 ordering information ta b l e 5 7 lists the cyble-2x20xx-x1 part numbers and features. table 58. tape and reel package quantity and minimum order amount the cyble-2x20xx-x1 is offered in tape and reel packaging. the cyble-2x20xx-x1 ships with a maximum of 500 units/reel. part numbering convention the part numbers are of the form cyble-abcdef- gh where the fields are defined as follows. for additional information and a complete list of cypress semiconductor ble products, contact your local cypress sales representative. to locate the nearest cypress office, visit our website. table 57. ordering information part number cpu speed (mhz) flash size (kb) capsense scb tcpwm 12-bit sar adc i 2 s lcd package packing certified CYBLE-212006-01 48 256 yes 2 4 1 msps yes yes 30-smt tape and reel yes cyble-202007-01 48 256 yes 2 4 1 msps yes yes 30-smt tape and reel yes cyble-202013-11 48 256 yes 2 4 1 msps yes yes 30-smt tape and reel no description minimum reel quantity maximum reel quantity comments reel quantity 500 500 ships in 500 unit reel quantities. minimum order quantity (moq) 500 ? order increment (oi) 500 ? u.s. cypress headquarters address 198 champion court, san jose, ca 95134 u.s. cypress headquarter contact info (408) 943-2600 cypress website address http://www.cypress.com
document number: 002-15631 rev.*b page 37 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 acronyms document conventions units of measure table 59. acronyms used in this document acronym description ble bluetooth low energy bluetooth sig bluetooth special interest group ce european conformity csa canadian standards association emi electromagnetic interference esd electrostatic discharge fcc federal communications commission gpio general-purpose input/output ic industry canada ide integrated design environment kc korea certification mic ministry of internal affairs and communications (japan) pcb printed circuit board rx receive qdid qualification design id smt surface-mount technology; a method for producing electronic circuitry in which the components are placed directly onto the surface of pcbs tcpwm timer, counter, pulse width modulator (pwm) tuv germany: technischer berwachungs-verein (technical inspection association) tx transmit table 60. units of measure symbol unit of measure c degree celsius kv kilovolt ma milliamperes mm millimeters mv millivolt ? a microamperes ? m micrometers mhz megahertz ghz gigahertz vvolt
document number: 002-15631 rev.*b page 38 of 39 preliminary CYBLE-212006-01 cyble-202007-01 cyble-202013-11 document history page document title: CYBLE-212006-01, cyble-202007-01, cyble-202013-11 ez-ble? proc? xr module document number: 002-15631 revision ecn orig. of change submission date description of change ** 5446955 dso 10/07/2016 preliminary datasheet for cyble-2x20xx-x1 modules. *a 5536076 dso 11/29/2016 updated more information : added ez-serial? ble firmware platform section. updated overview : added bluetooth declaration id and qdid under ? bluetooth 4.2 qualified single-mode module ? updated recommended host pcb layout : updated figure 4 , figure 5 , and figure 6 captions to specify that these as ?seen on host pcb?. updated power supply connections and recommended external components : updated figure 7 and figure 8 to specify that these are ?seen from bottom?. updated digital and analog capabilities and connections : updated ta b l e 4 : updated tcpwm column to add tcpwm capability on port 2 pins. added footnote 5. *b 5554670 dso 12/15/2016 updated more information : added hyperlinks for evaluation boar d listed under development kits updated enabling extended range feature : updated sar adc : updated table 21 to add note 10 to specify under what conditions the maximum number of adc channels can be achieved.
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