View MB95F614HPMC-G-SNE2_8724903.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary mb95f613h/f613k/f614h mb95f614k/f616h/f616k new 8fx mb95610h series 8-bit microcontrollers cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-04698 rev. *a revised april 8, 2016 the mb95610h series is a series of general-purpose, single-chip mi crocontrollers. in addition to a compact instruction set, the microcontrollers of these series contain a variety of peripheral resources. features f 2 mc-8fx cpu core instruction set opti mized for controllers multiplication and division instructions 16-bit arithmetic operations bit test branch instructions bit manipulation instructions, etc. clock selectable main clock source ? main oscillation clock (up to 16.25 mhz, maximum machine clock frequency: 8.125 mhz) ? external clock (up to 32.5 mhz, maximum machine clock frequency: 16.25 mhz) ? main cr clock (4 mhz ? 2%) ? main pll clock / main cr pll clock (main oscillation clock = 4 mhz, main cr clock = 4 mhz) ? both main oscillation clock and main cr clock can be mul- tiplied by a pll multiplication rate. ? the frequency of the main pll clock / main cr pll clock becomes 8 mhz when the pll multiplication rate is 2. ? he frequency of the main pll clock / main cr pll clock becomes 10 mhz when the pll multiplication rate is 2.5. ? he frequency of the main pll clock / main cr pll clock becomes 12 mhz when the pll multiplication rate is 3. ? he frequency of the main pll clock / main cr pll clock becomes 16 mhz when the pll multiplication rate is 4. selectable subclock source ? suboscillation clock (32.768 khz) ? external clock (32.768 khz) ? sub-cr clock (typ: 100 khz, min: 50 khz, max: 150 khz) timer 8/16-bit composite timer ? 2 channels 8/16-bit ppg ? 2 channels 16-bit reload timer ? 1 channel event counter ? 1 channel time-base timer ? 1 channel watch counter ? 1 channel watch prescaler ? 1 channel uart/sio ? 2 channels full duplex double buffer capable of clock asynchronous (uart) serial data transfer and clock synchronous (sio) serial data transfer i 2 c bus interface ? 1 channel built-in wake-up function external interrupt ? 8 channels interrupt by edge detection (rising edge, falling edge, and both edges can be selected) can be used to wake up the device from different low power consumption (standby) modes 8/10-bit a/d converter ? 4 channels 8-bit or 10-bit resolution can be selected. lcd controller (lcdc) lcd output can be selected from 52 seg ? 4 com or 48 seg ? 8 com. internal divider resistor whose resistance value can be selected from 10 k ? or 100 k ? through software interrupt in sync with the lcd module frame frequency blinking function inverted display function low power consumption (standby) modes there are four standby modes as follows: stop mode sleep mode watch mode time-base timer mode in standby mode, two further options can be selected: normal standby mode and deep standby mode. i/o port mb95f613h/f614h/f616h (no. of i/o ports: 40) ? general-purpose i/o ports (cmos i/o): 39 ? general-purpose i/o port s (n-ch open drain): 1 mb95f613k/f614k/f616k (no. of i/o ports: 41) ? general-purpose i/o ports (cmos i/o): 39 ? general-purpose i/o port s (n-ch open drain): 2 on-chip debug 1-wire serial control serial writing supported (asynchronous mode)
document number: 002-04698 rev. *a page 2 of 110 preliminary mb95610h series hardware/software watchdog timer built-in hardware watchdog timer built-in software watchdog timer power-on reset a power-on reset is generated when the power is switched on. low-voltage detection (lvd) reset circuit (only available on mb95f613k/f614k/f616k) built-in low-voltage detection function (the combination of detection voltage and release voltage can be selected from four options.) clock supervisor counter built-in clock supervisor counter dual operation flash memory the program/erase operation and the read operation can be executed in different banks (upper bank/lower bank) simultane- ously. flash memory security function protects the content of the flash memory.
document number: 002-04698 rev. *a page 3 of 110 preliminary mb95610h series contents product line-up ................................................................ 5 packages and corresponding products ........................ 8 differences among products and notes on product selection ....................................................... 8 pin assignment ................................................................ 9 pin functions .................................................................. 10 i/o circuit type ............................................................... 14 handling precautions ..................................................... 18 precautions for product design ................................. 18 precautions for package mount ing ............ ........... .... 19 precautions for use environment .............................. 21 notes on device handling ......................................... 22 pin connection ...... .............. .............. .............. .......... 22 block diagram ........................................................... 24 cpu core .................................................................. 25 memory space .......................................................... 26 areas for specific applications .................................. 28 i/o map ...................................................................... 29 i/o ports .................................................................... 34 port 0 ......................................................................... 34 port 0 configuration ................................................... 34 block diagrams of port 0 ............................................ 35 port 0 registers .......................................................... 38 port 0 operations ... .............. .............. .............. .......... 38 port 1 ......................................................................... 40 port 1 configuration ................................................... 40 block diagrams of port 1 ............................................ 40 port 1 registers .......................................................... 44 port 1 operations ... .............. .............. .............. .......... 45 port 2 ......................................................................... 46 port 2 configuration ................................................... 46 block diagrams of port 2 ............................................ 46 port 2 registers .......................................................... 49 port 2 operations ... .............. .............. .............. .......... 50 port 3 ......................................................................... 51 port 3 configuration ................................................... 51 block diagrams of port 3 ............................................ 51 port 3 registers .......................................................... 54 port 3 operations ... .............. .............. .............. .......... 54 port 5 ......................................................................... 57 port 5 configuration ................................................... 57 block diagrams of port 5 ............................................ 57 port 5 registers .......................................................... 59 port 5 operations ....................................................... 59 port 9 ......................................................................... 61 port 9 configuration ................................................... 61 block diagrams of port 9 ............................................ 61 port 9 registers .......................................................... 62 port 9 operations ....................................................... 63 port f ......................................................................... 64 port f configuration ................................................... 64 block diagrams of port f ........................................... 64 port f registers .......................................................... 66 port f operations ....................................................... 67 port g ........................................................................ 68 port g configuration .................................................. 68 block diagram of port g ............................................. 68 port g registers ......................................................... 69 port g operations ...................................................... 69 interrupt source table ................................................... 70 pin states in each mode ................................................ 71 electrical characteristics ............................................... 76 absolute maximum ratings ... .................................... 76 recommended operating conditions ....................... 78 dc characteristics .................................................... 79 ac characteristics ..................................................... 83 clock timing .............................................................. 83 source clock/machine clock .................................... 89 external reset ...... ..................................................... 91 power-on reset ......................................................... 92 peripheral input timing ............................................. 92 low-voltage detection ........... .................................... 93 i2c bus interface ti ming ........................................... 95 uart/sio, serial i/o timing ..................................... 99 a/d converter .......................................................... 101 a/d converter electrical characteristics ................. 101 notes on using a/d converter ................................ 102 definitions of a/d converter terms ......................... 104 flash memory program/erase characteristics ........ 106 mask options .............................................................. 107 ordering information .................................................... 108 package dimension ...................................................... 109 major changes ...............................................................110
document number: 002-04698 rev. *a page 4 of 110 preliminary mb95610h series 1. product line-up (continued) part number parameter mb95f613h mb95f614h mb95f616h mb95f613k mb95f614k mb95f616k type flash memory product clock supervisor counter it supervises the main clock oscillat ion and the subclock oscillation. flash memory capacity 12 kbyte 20 kbyte 36 kbyte 12 kbyte 20 kbyte 36 kbyte ram capacity 512 bytes 1024 bytes 1024 bytes 512 bytes 1024 bytes 1024 bytes power-on reset yes low-voltage detection reset no yes reset input with dedicated reset input selected through software cpu functions ? number of basic instructions : 136 ? instruction bit length : 8 bits ? instruction length : 1 to 3 bytes ? data bit length : 1, 8 and 16 bits ? minimum instruction execution time : 61. 5 ns (machine clock frequency = 16.25 mhz) ? interrupt processing time : 0.6 s (machine clock frequency = 16.25 mhz) general-purpose i/o ? i/o port : 40 ? cmos i/o : 39 ? n-ch open drain : 1 ? i/o port : 41 ? cmos i/o : 39 ? n-ch open drain : 2 time-base timer interval time: 0.256 ms to 8.3 s (external clock frequency = 4 mhz) hardware/ software watchdog timer ? reset generation cycle main oscillation clock at 10 mhz: 105 ms (min) ? the sub-cr clock can be used as the source clock of the software watchdog timer. wild register it can be used to replace 3 bytes of data. 8/10-bit a/d converter 4 channels 8-bit or 10-bit resolution can be selected. 8/16-bit composite timer 2 channels ? the timer can be configured as an ?8-bit timer 2 channels? or a ?16-bit timer 1 channel?. ? it has the following functions: inte rval timer function, pwc function, pw m function and input capture function. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? it can output square wave. external interrupt 8 channels ? interrupt by edge detection (the rising edge, falling edge, and both edges can be selected.) ? it can be used to wake up the dev ice from different standby modes. on-chip debug ? 1-wire serial control ? it supports serial writing (asynchronous mode).
document number: 002-04698 rev. *a page 5 of 110 preliminary mb95610h series (continued) part number parameter mb95f613h mb95f614h mb95f616h mb95f613k mb95f614k mb95f616k uart/sio 2 channels ? data transfer with uart/sio is enabled. ? it has a full duplex double buffer, variable data length (5/6/7/8 bits), an internal baud rate generator and an error detection function. ? it uses the nrz type transfer format. ? lsb-first data transfer and msb-first data transfer are available to use. ? both clock asynchronous (uart) seri al data transfer and clock synchronous (sio) serial data transfer are enabled. i 2 c bus interface 1 channel ? master/slave transmission and receiving ? it has the following functions: bus e rror function, arbitration function, tr ansmission directi on detection function, wake-up function, and functions of generat ing and detecting repeated start conditions. 8/16-bit ppg 2 channels ? each channel can be used as an ?8-bit timer ? 2 channels? or a ?16-bit timer ? 1 channel?. ? the counter operating clock can be selected from eight clock sources. 16-bit reload timer 1 channel ? two clock modes and two counter oper ating modes are available to use. ? it can output square wave. ? count clock: it can be selected from internal clocks (seven types) and external clocks. ? two counter operating modes: reload mode and one-shot mode event counter by configuring the 16-bit reload timer and 8/16-bit co mposite timer ch. 1, the event count function can be implemented. when the event counter function is used, the 16-bit reload timer and 8/16-bit composite timer ch. 1 become unavailable. lcdc controller (lcdc) ? com output: 4 or 8 (max) (selectable) ? seg output: 48 or 52 (max) (selectable) - if the number of com outputs is 4, the maximum num ber of seg outputs is 52, and the maximum number of pixels that can be displayed 208 (4 ? 52). - if the number of com outputs is 8, the maximum num ber of seg outputs is 48, and the maximum number of pixels that can be displayed 384 (8 ? 48). ? duty lcd mode ? lcd standby mode ? blinking function ? internal divider resistor whose resi stance value can be selected from 10 k ? or 100 k ? through software ? interrupt in sync with the lcd module frame frequency ? inverted display function watch counter ? count clock: four selectable clock sources (125 ms, 250 ms, 500 ms or 1 s) ? the counter value can be selected from 0 to 63. (the watch counter can count fo r one minute when the clock source is one second and the counter value is set to 60.) watch prescaler eight different time intervals can be selected.
document number: 002-04698 rev. *a page 6 of 110 preliminary mb95610h series (continued) part number parameter mb95f613h mb95f614h mb95f616h mb95f613k mb95f614k mb95f616k flash memory ? it supports automatic programming (embedded algorithm), and program/erase/erase-suspend/erase-resume commands. ? it has a flag indicating the completion of the operation of embedded algorithm. ? flash security feature for protecting the content of the flash memory standby mode there are four standby modes as follows: ? stop mode ? sleep mode ? watch mode ? time-base timer mode in standby mode, two further options can be selected: normal standby mode and deep standby mode. package fpt-80p-m37 number of program/erase cycles 1000 10000 100000 data retention time 20 years 10 years 5 years
document number: 002-04698 rev. *a page 7 of 110 preliminary mb95610h series 2. packages and corresponding products ? : available 3. differences amo ng products and notes on product selection current consumption when using the on-chip debug function, take account of the current consumption of flash program/erase. for details of current consumption, see ?electrical characteristics?. package for details of information on each package, see ?packages and corresponding products? and ?package dimension?. operating voltage the operating voltage varies, depending on whether the on-chip debug function is used or not. for details of operating voltage, see ?electrical characteristics?. on-chip debug function the on-chip debug function requires that v cc , v ss and one serial wire be connected to an ev aluation tool. for details of the connection method, refer to ?chapter 25 example of serial programming connectio n? in ?new 8fx mb95610h series hardware manual?. part number package mb95f613h mb95f614h mb95f616h mb95f613k mb95f614k mb95f616k fpt-80p-m37 ??????
document number: 002-04698 rev. *a page 8 of 110 preliminary mb95610h series 4. pin assignment p13/uo0 p14/uck0 p15/ui0 p52/to00 p51/ec0 p50/to01 pf2/rst p94/v0 p93/v1 p92/v2 p91/v3 (top view) lqfp80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 20 19 18 17 16 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p12/dbg v cc pg1/x0a pg2/x1a c pf0/x0 pf1/x1 v ss p90/v4 p01/int01/an01 p02/int02/an02 p03/int03/an03 com0 com1 com2 com3 com4/seg00 com5/seg01 com6/seg02 com7/seg03 p00/int00/an00 seg05 seg06 seg07 seg08 seg09 seg10 seg11 seg04 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 41 42 43 44 45 seg31 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg19 p26/seg50/scl p25/seg49/ppg01 p24/seg48/ppg00 p23/seg47/ui1 p22/seg46/uck1 p21/seg45/uo1 p20/seg44/ti0 p37/seg43/to0 p36/seg42/ec1 p35/seg41/to10 p34/seg40/to11 p27/seg51/sda p32/seg38/int06 p31/seg37/int05 p30/seg36/int04 p07/seg35/ppg11 p06/seg34/ppg10 p05/seg33/adtg p04/seg32 p33/seg39/int07 fpt-80p-m37
document number: 002-04698 rev. *a page 9 of 110 preliminary mb95610h series 5. pin functions (continued) pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 1 p12 a general-purpose i/o port hysteresis cmos ? ? dbg dbg input pin 2 p13 b general-purpose i/o port hysteresis cmos ? ? uo0 uart/sio ch. 0 data output pin 3 p14 b general-purpose i/o port hysteresis cmos ? ? uck0 uart/sio ch. 0 clock i/o pin 4 p15 b general-purpose i/o port hysteresis cmos ? ? ui0 uart/sio ch. 0 data input pin 5 p52 b general-purpose i/o port hysteresis cmos ? ? to00 8/16-bit composite timer ch. 0 output pin 6 p51 b general-purpose i/o port hysteresis cmos ? ? ec0 8/16-bit composite timer ch. 0 clock input pin 7 p50 b general-purpose i/o port hysteresis cmos ? ? to01 8/16-bit composite timer ch. 0 output pin 8 pf2 c general-purpose i/o port hysteresis cmos ? ? rst reset pin dedicated reset pin on mb95f613h/f614h/f616h 9 p94 d general-purpose i/o port hysteresis cmos ? ? v0 lcd drive power supply pin 10 p93 d general-purpose i/o port hysteresis cmos ? ? v1 lcd drive power supply pin 11 p92 d general-purpose i/o port hysteresis cmos ? ? v2 lcd drive power supply pin 12 p91 d general-purpose i/o port hysteresis cmos ? ? v3 lcd drive power supply pin 13 p90 d general-purpose i/o port hysteresis cmos ? ? v4 lcd drive power supply pin 14 v cc ? power supply pin ? ? ? ? 15 pg1 e general-purpose i/o port hysteresis cmos ? ? x0a subclock input oscillation pin (32 khz) 16 pg2 e general-purpose i/o port hysteresis cmos ? ? x1a subclock i/o oscillation pin (32 khz) 17 c ? decoupling capacitor connection pin ? ? ? ? 18 pf0 f general-purpose i/o port hysteresis cmos ? ? x0 main clock input oscillation pin 19 pf1 f general-purpose i/o port hysteresis cmos ? ? x1 main clock i/o oscillation pin 20 v ss ? power supply pin (gnd) ? ? ? ?
document number: 002-04698 rev. *a page 10 of 110 preliminary mb95610h series (continued) pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 21 p00 g general-purpose i/o port hysteresis/ analog cmos ? ? int00 external interrupt input pin an00 8/10-bit a/d converter analog input pin 22 p01 g general-purpose i/o port hysteresis/ analog cmos ? ? int01 external interrupt input pin an01 8/10-bit a/d converter analog input pin 23 p02 g general-purpose i/o port hysteresis/ analog cmos ? ? int02 external interrupt input pin an02 8/10-bit a/d converter analog input pin 24 p03 g general-purpose i/o port hysteresis/ analog cmos ? ? int03 external interrupt input pin an03 8/10-bit a/d converter analog input pin 25 com0 h lcdc com0 output pin hysteresis lcd ? ? 26 com1 h lcdc com1 output pin hysteresis lcd ? ? 27 com2 h lcdc com2 output pin hysteresis lcd ? ? 28 com3 h lcdc com3 output pin hysteresis lcd ? ? 29 com4 h lcdc com4 output pin hysteresis lcd ? ? seg00 lcdc seg00 output pin 30 com5 h lcdc com5 output pin hysteresis lcd ? ? seg01 lcdc seg01 output pin 31 com6 h lcdc com6 output pin hysteresis lcd ? ? seg02 lcdc seg02 output pin 32 com7 h lcdc com7 output pin hysteresis lcd ? ? seg03 lcdc seg03 output pin 33 seg04 h lcdc seg04 output pin hysteresis lcd ? ? 34 seg05 h lcdc seg05 output pin hysteresis lcd ? ? 35 seg06 h lcdc seg06 output pin hysteresis lcd ? ? 36 seg07 h lcdc seg07 output pin hysteresis lcd ? ? 37 seg08 h lcdc seg08 output pin hysteresis lcd ? ? 38 seg09 h lcdc seg09 output pin hysteresis lcd ? ? 39 seg10 h lcdc seg10 output pin hysteresis lcd ? ? 40 seg11 h lcdc seg11 output pin hysteresis lcd ? ? 41 seg12 h lcdc seg12 output pin hysteresis lcd ? ? 42 seg13 h lcdc seg13 output pin hysteresis lcd ? ? 43 seg14 h lcdc seg14 output pin hysteresis lcd ? ? 44 seg15 h lcdc seg15 output pin hysteresis lcd ? ? 45 seg16 h lcdc seg16 output pin hysteresis lcd ? ? 46 seg17 h lcdc seg17 output pin hysteresis lcd ? ? 47 seg18 h lcdc seg18 output pin hysteresis lcd ? ? 48 seg19 h lcdc seg19 output pin hysteresis lcd ? ?
document number: 002-04698 rev. *a page 11 of 110 preliminary mb95610h series (continued) pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 49 seg20 h lcdc seg20 output pin hysteresis lcd ? ? 50 seg21 h lcdc seg21 output pin hysteresis lcd ? ? 51 seg22 h lcdc seg22 output pin hysteresis lcd ? ? 52 seg23 h lcdc seg23 output pin hysteresis lcd ? ? 53 seg24 h lcdc seg24 output pin hysteresis lcd ? ? 54 seg25 h lcdc seg25 output pin hysteresis lcd ? ? 55 seg26 h lcdc seg26 output pin hysteresis lcd ? ? 56 seg27 h lcdc seg27 output pin hysteresis lcd ? ? 57 seg28 h lcdc seg28 output pin hysteresis lcd ? ? 58 seg29 h lcdc seg29 output pin hysteresis lcd ? ? 59 seg30 h lcdc seg30 output pin hysteresis lcd ? ? 60 seg31 h lcdc seg31 output pin hysteresis lcd ? ? 61 p04 i general-purpose i/o port hysteresis cmos/lc d ?? seg32 lcdc seg32 output pin 62 p05 i general-purpose i/o port hysteresis cmos/lc d ?? seg33 lcdc seg33 output pin adtg 8/10-bit a/d converter trigger input pin 63 p06 i general-purpose i/o port hysteresis cmos/lc d ?? seg34 lcdc seg34 output pin ppg10 8/16-bit ppg ch. 1 output pin 64 p07 i general-purpose i/o port hysteresis cmos/lc d ?? seg35 lcdc seg35 output pin ppg11 8/16-bit ppg ch. 1 output pin 65 p30 i general-purpose i/o port hysteresis cmos/lc d ?? seg36 lcdc seg36 output pin int04 external interrupt input pin 66 p31 i general-purpose i/o port hysteresis cmos/lc d ?? seg37 lcdc seg37 output pin int05 external interrupt input pin 67 p32 i general-purpose i/o port hysteresis cmos/lc d ?? seg38 lcdc seg38 output pin int06 external interrupt input pin 68 p33 i general-purpose i/o port hysteresis cmos/lc d ?? seg39 lcdc seg39 output pin int07 external interrupt input pin 69 p34 i general-purpose i/o port hysteresis cmos/lc d ?? seg40 lcdc seg40 output pin to11 8/16-bit composite timer ch. 1 output pin
document number: 002-04698 rev. *a page 12 of 110 preliminary mb95610h series (continued) ? : available 1:for the i/o circuit types, see ?i/o circuit type?. 2:n-ch open drain 3:pull-up pin no. pin name i/o circuit type* 1 function i/o type input output od* 2 pu* 3 70 p35 i general-purpose i/o port hysteresis cmos/lc d ?? seg41 lcdc seg41 output pin to10 8/16-bit composite timer ch. 1 output pin 71 p36 i general-purpose i/o port hysteresis cmos/lc d ?? seg42 lcdc seg42 output pin ec1 8/16-bit composite timer ch. 1 clock input pin 72 p37 i general-purpose i/o port hysteresis cmos/lc d ?? seg43 lcdc seg43 output pin to0 16-bit reload timer ch. 0 output pin 73 p20 i general-purpose i/o port hysteresis cmos/lc d ?? seg44 lcdc seg44 output pin ti0 16-bit reload timer ch. 0 input pin 74 p21 i general-purpose i/o port hysteresis cmos/lc d ?? seg45 lcdc seg45 output pin uo1 uart/sio ch. 1 data output pin 75 p22 i general-purpose i/o port hysteresis cmos/lc d ?? seg46 lcdc seg46 output pin uck1 uart/sio ch. 1 clock i/o pin 76 p23 i general-purpose i/o port hysteresis cmos/lc d ?? seg47 lcdc seg47 output pin ui1 uart/sio ch. 1 data input pin 77 p24 i general-purpose i/o port hysteresis cmos/lc d ?? seg48 lcdc seg48 output pin ppg00 8/16-bit ppg ch. 0 output pin 78 p25 i general-purpose i/o port hysteresis cmos/lc d ?? seg49 lcdc seg49 output pin ppg01 8/16-bit ppg ch. 0 output pin 79 p26 i general-purpose i/o port hysteresis cmos/lc d ?? seg50 lcdc seg50 output pin scl i 2 c bus interface ch. 0 clock i/o pin 80 p27 i general-purpose i/o port hysteresis cmos/lc d ?? seg51 lcdc seg51 output pin sda i 2 c bus interface ch. 0 data i/o pin
document number: 002-04698 rev. *a page 13 of 110 preliminary mb95610h series 6. i/o circuit type type circuit remarks a ? n-ch open drain output ? hysteresis input b ? cmos output ? hysteresis input ? pull-up control c ? n-ch open drain output ? hysteresis input ? reset output d ? cmos output ? lcd power supply ? hysteresis input n-ch standby control hysteresis input digital output n-ch p-ch r pull-up control digital output digital output standby control hysteresis input n-ch reset output / digital output reset input / hysteresis input n-ch p-ch digital output digital output lcd internal divider resistor i/o lcd control standby control hysteresis input
document number: 002-04698 rev. *a page 14 of 110 preliminary mb95610h series e ? oscillation circuit ? high-speed side feedback resistance: approx. 1 m ? ? cmos output ? hysteresis input type circuit remarks standby control / port select clock input port select digital output digital output standby control hysteresis input digital output digital output standby control hysteresis input port select x1 x0 n-ch p-ch n-ch p-ch
document number: 002-04698 rev. *a page 15 of 110 preliminary mb95610h series (continued) type circuit remarks f ? oscillation circuit ? low-speed side feedback resistance: approx. 10 m ? ? cmos output ? hysteresis input ? pull-up control g ? cmos output ? hysteresis input ? analog input h lcd output clock input x1a x0a standby control / port select n-ch p-ch port select digital output digital output standby control hysteresis input n-ch digital output digital output digital output standby control hysteresis input p-ch r pull-up control port select p-ch r pull-up control n-ch p-ch digital output digital output analog input a/d control standby control hysteresis input lcd output
document number: 002-04698 rev. *a page 16 of 110 preliminary mb95610h series i ? cmos output ? lcd output ? hysteresis input type circuit remarks n-ch p-ch digital output digital output lcd output lcd control standby control hysteresis input
document number: 002-04698 rev. *a page 17 of 110 preliminary mb95610h series 7. handling precautions any semiconductor devices have inherently a certain rate of failu re. the possibility of failure is greatly affected by the cond itions in which they are used (circuit conditions, envi ronmental conditions, etc.). this page de scribes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your cypress semiconductor devices. 7.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of ce rtain established limits, called absolute maximum ratings. do not exceed these ratings. recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor dev ice. all the device's electrical characte r- istics are warranted when operated within these ranges. always use semiconductor devices within the recommended operati ng conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represent ed on the data sheet. users consid ering application outside the listed conditions are advised to contact their sales representative beforehand. processing and protection of pins these precautions must be followed when handling the pins whic h connect semiconductor devices to power supply and input/output functions. 1. preventing over-voltage and over-current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the devic e, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over-current conditions at the design stage. 2. protection of output pins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pins unconnected input pins with very high impedance levels can adv ersely affect stability of operation. such pins should be connected through an appropriate resistanc e to a power supply pin or ground pin.
document number: 002-04698 rev. *a page 18 of 110 preliminary mb95610h series latch-up semiconductor devices are constructed by the formation of p-type and n-type areas on a substrat e. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristo r structures) may be formed, caus ing large current levels in e xcess of several hundred ma to flow continuously at the power supply pin. this condition is called latch-up. the occurrence of latch-up not only causes loss of reliability in the semiconductor device, but c an cause injury or damage from high heat, smoke or flame. to prevent th is from happening, do the following: (1) be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. (2) be sure that abnormal current flows do not occur during the power-on sequence. observance of safety regulations and standards most countries in the world have established standards and regu lations regarding safety, protection from electromagnetic interf erence, etc. customers are requested to observe applicable re gulations and standards in the design of products. fail-safe design any semiconductor devices have inherently a certain rate of failure . you must protect against injury, damage or loss from such failures by incorporating safety design measures in to your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communicatio ns, and measurement equipment, pers onal or household devices, etc.). customers considering the use of our product s in special applications where failure or abnormal operation may directly affect h uman lives or cause physical injury or property damage, or where extr emely high levels of reliability are demanded (such as aerospac e systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medi cal devices for life support, etc.) are r equested to consult with sales representatives before such use. the comp any will not be responsible for damages arising from such use wi thout prior approval. 7.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under cypress?s recommended conditions. for detail ed information about mount conditions, contact your sales representative. lead insertion type mounting of lead insertion type packages onto printed circuit boa rds may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for in serting leads into through-holes on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be sub jected to thermal stress in excess of th e absolute ratings for storage temperature. mount ing processes should c onform to cypress recom - mended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact de terio- ration after long periods. for this reason it is recommended that the surface treatment of socket contacts and ic leads be veri fied before mounting.
document number: 002-04698 rev. *a page 19 of 110 preliminary mb95610h series surface mount type surface mount packaging has longer and thinner leads than lead- insertion packaging, and therefor e leads are more easily deforme d or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connecti ons caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting technique s. cypress recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to moun t packages in accordance with fujitsu semiconductor ranking of recommended conditions. lead-free packaging when ball grid array (bga) packages with sn-ag-cu balls are mounted using sn-pb eutectic sold ering, junction strength may be reduced under some conditions of use. storage of semiconductor devices because plastic chip packages are formed from plastic resins, ex posure to natural environmental conditions will cause absorptio n of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause mois ture to condense inside the product. store products in locatio ns where temperature changes are slight. (2) use dry boxes for product storage. prod ucts should be stored below 70% relative humidity, and at temp eratures between 5 ? c and 30 ? c. when you open dry package that recommends humidity 40% to 70% relative humidity. (3) when necessary, cypress packages semiconductor devices in hi ghly moisture-resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. (4) avoid storing packages where they are expos ed to corrosive gases or high levels of dust. baking packages that have absorbed moisture may be de-moisturized by baking (heat drying). follow the fujitsu semiconductor recommended conditions for baking. condition: 125 ? c/24 h static electricity because semiconductor devices are particularly susceptible to dama ge by static electricity, you must take the following precaut ions: (1) maintain relative humidity in the working environment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. (2) electrically ground all conveyors, solder ve ssels, soldering irons and peripheral equipment. (3) eliminate static body electricity by th e use of rings or bracelets connected to ground through high resistance (on the leve l of 1 m ? ). wearing of conductive clothing and shoes, use of conductive floor mats and othe r measures to minimize shock loads is recommended. (4) ground all fixtures and instruments, or protect with anti-static measures. (5) avoid the use of styrofoam or other highly static-prone materials for storage of completed board assemblies.
document number: 002-04698 rev. *a page 20 of 110 preliminary mb95610h series 7.3 precautions for use environment reliability of semiconductor devices depends on ambien t temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti-humidity processing. (2) discharge of static electricity when high-voltage charges exist close to semiconductor devi ces, discharges can cause abnorm al operation. in such cases, use anti-static measures or proc essing to prevent discharges. (3) corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. i f you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4) radiation, including cosmic radiation most devices are not designed for environments involving exposur e to radiation or cosmic radiation. users should provide shielding as appropriate. (5) smoke, flame caution: plastic molded devices are flamma ble, and therefore should not be used n ear combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in ot her special environmental cond itions should consult with sales representatives.
document number: 002-04698 rev. *a page 21 of 110 preliminary mb95610h series 8. notes on device handling preventing latch-ups when using the device, ensure that the voltage applied does not exceed the maximum voltage rating. in a cmos ic, if a voltage higher than v cc or a voltage lower than v ss is applied to an input/output pin that is neither a medium-withstand voltage pin nor a high-withs tand voltage pin, or if a voltage out of the rating range of power supply voltage mentioned in ?18.1 absolute maximum rati ngs? of ?electrical characteristics? is applied to the v cc pin or the v ss pin, a latch-up may occur. when a latch-up occurs, power supply current increases significantly, which may cause a component to be thermally destroyed. stabilizing supply voltage supply voltage must be stabilized. a malfunction may occur when power supply voltage fluctuates ra pidly even though the fluctuation is within the guaranteed opera ting range of the v cc power supply voltage. as a rule of voltage stabilization, suppress vo ltage fluctuation so that the fluctuation in v cc ripple (p-p value) at the commercial frequency (50 hz/60 hz) does not exceed 10% of the standard v cc value, and the transient fluctuat ion rate does not exceed 0.1 v/ms at a momentary fluctuation such as switching the power supply. notes on using the external clock when an external clock is used, oscillation stabilization wait ti me is required for power-on reset, wake-up from subclock mode or stop mode. 9. pin connection treatment of unused pins if an unused input pin is left unconnected, a component may be pe rmanently damaged due to malfunctions or latch-ups. always pul l up or pull down an unused input pin through a resistor of at least 2 k ? . set an unused input/output pi n to the output state and leave it unconnected, or set it to the input stat e and treat it the same as an unused input pin. if there is an unused output pin, le ave it unconnected. power supply pins to reduce unnecessary electro-magnetic emission, prevent malfunct ions of strobe signals due to an increase in the ground level, and conform to the total output current standard, always connect the v cc pin and the v ss pin to the power supply and ground outside the device. in addition, connect the current supply source to the v cc pin and the v ss pin with low impedance. it is also advisable to connect a ceramic capacitor of app roximately 0.1 f as a decoupling capacitor between the v cc pin and the v ss pin at a location close to this device. dbg pin connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not st ay at ?l? level until the reset output is released. the dbg pin becomes a communication pin in debug mode. since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool do cument when selecting a pull-up resistor. rst pin connect the rst pin to an external pull-up resistor of 2 k ? or above. to prevent the device from unintentionally entering the reset mode due to noise, mi nimize the interconnection length between a pull-up resistor and the rst pin and that between a pull-up resistor and the v cc pin when designing the layout of the printed circuit board. the pf2/rst pin functions as the reset input/output pin after po wer-on. in addition, the reset output of the pf2/rst pin can be enabled by the rstoe bit in the sysc regi ster, and the reset input function and the genera l purpose i/o fu nction can be se lected by the rsten bit in the sysc register.
document number: 002-04698 rev. *a page 22 of 110 preliminary mb95610h series c pin use a ceramic capacitor or a capacitor with equivalent freq uency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering a mode to wh ich the device is not set to transit due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. note on serial communication in serial communication, reception of wrong data may occur due to noise or other causes. theref ore, design a printed circuit bo ard to prevent noise from occurring. taking a ccount of the reception of wrong data, take measures such as adding a checksum to the end of data in order to detect errors. if an error is detected, retransmit the data. c cs dbg rst dbg/rst /c pins connection diagram
document number: 002-04698 rev. *a page 23 of 110 preliminary mb95610h series 10. block diagram reset with lvd dual operation flash with security function (36/20/12 kbyte) f 2 mc-8fx cpu ram (1024/512 bytes) oscillator circuit cr oscillator clock control interrupt controller pll internal bus 8/16-bit composite timer ch. 0 8/10-bit a/d converter lcdc (4 com or 8 com) 16-bit reload timer ch. 0 8/16-bit composite timer ch. 1 uart/sio ch. 0 8/16-bit ppg ch. 0 8/16-bit ppg ch. 1 port port pf2 *1 /rst *2 pf1/x1 *2 pf0/x0 *2 pg2/x1a *2 pg1/x0a *2 watch counter c p14/uck0 p13/uo0 p15/ui0 uart/sio ch. 1 p22/uck1 p21/uo1 p23/ui1 p24/ppg00 p25/ppg01 p06/ppg10 p07/ppg11 on-chip debug wild register external interrupt p00/int00 to p03/int03, p30/int04 to p33/int07 p12 *1 /dbg p52/to00 p50/to01 p51/ec0 p00/an00 to p03/an03 p05/adtg p90/v4 to p94/v0 com0 to com3 p04/seg32 to p07/seg35 p20/seg44 to p27/seg51 seg00 to seg31 p30/seg36 to p37/seg43 p90/v4 to p94/v0 4 com mode: 8 com mode: com0 to com7 p04/seg32 to p07/seg35 p20/seg44 to p27/seg51 seg04 to seg31 p30/seg36 to p37/seg43 p34/to11 p35/to10 p36/ec1 i 2 c bus interface ch. 0 p27/sda p26/scl p20/ti0 *3 p37/to0 vcc vss *1: *2: *3: p12 and pf2 are n-ch open drain pins. software select when the event counter operating mode is enabled, 8/16-bit composite timer ch. 1 and the 16-bit reload timer ch. 0 can function as an event counter.
document number: 002-04698 rev. *a page 24 of 110 preliminary mb95610h series 11. cpu core memory space the memory space of the mb95610h series is 64 kbyte in size, a nd consists of an i/o area, an extended i/o area, a data area, an d a program area. the memory space includes areas intended for spec ific purposes such as general-purpose registers and a vector table. the memory maps of the mb95610h series are shown below. memory maps mb95f614h/f614k mb95f613h/f613k i/o area access prohibited ram 512 bytes registers access prohibited extended i/o area access prohibited flash memory 8 kbyte flash memory 4 kbyte 0x0000 0x0080 0x0090 0x0100 0x0200 0x0290 0x0f80 0x1000 0x2000 0xe000 0xffff i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 flash memory 4 kbyte 0x1000 0x2000 flash memory 4 kbyte extended i/o area 0x0f80 0x1000 access prohibited access prohibited 0x8000 0x2000 access prohibited 0xc000 ram 1024 bytes flash memory 16 kbyte 0x0490 0xffff mb95f616h/f616k i/o area access prohibited 0x0000 0x0080 0x0090 registers 0x0100 0x0200 extended i/o area 0x0f80 access prohibited ram 1024 bytes flash memory 32 kbyte 0x0490 0xffff
document number: 002-04698 rev. *a page 25 of 110 preliminary mb95610h series 12. memory space the memory space of the mb95610h series is 64 kbyte in size, a nd consists of an i/o area, an extended i/o area, a data area, an d a program area. the memory space includes areas for specific app lications such as general-purpose registers and a vector table. i/o area (addresses: 0x0000 to 0x007f) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the i/o area forms part of the memory space, it can be acce ssed in the same way as the memory. it can also be accessed at high-speed by using direct addressing instructions. extended i/o area (addresses: 0x0f80 to 0x0fff) ? this area contains the control registers and data registers for built-in peripheral functions. ? as the extended i/o area forms part of the memory spac e, it can be accessed in the same way as the memory. data area ? static ram is incorporated in the data area as the internal data area. ? the internal ram size vari es according to product. ? the ram area from 0x0090 to 0x00ff can be accessed at high-speed by using direct addressing instructions. ? in mb95f614h/f614k/f616h/f616k, the area from 0x0090 to 0x047f is an extended direct addressing area. it can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. ? in mb95f613h/f613k, the area from 0x0090 to 0x028f is an ext ended direct addressing area. it can be accessed at high-speed by direct addressing instructions with a direct bank pointer set. ? the area from 0x0100 to 0x01ff can be used as a general-purpose register area. program area ? the flash memory is incorporated in the program area as the internal program area. ? the flash memory size varies according to product. ? the area from 0xffc0 to 0xffff is used as the vector table. ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register.
document number: 002-04698 rev. *a page 26 of 110 preliminary mb95610h series memory space map direct addressing area extended direct addressing area i/o area access prohibited 0x0000 0x0080 0x0090 registers (general-purpose register area) 0x0100 0x0200 0x047f vector table area extended i/o area 0x0f80 0x0fff 0x1000 access prohibited program area data area 0x048f 0x0490 0xffff 0xffc0
document number: 002-04698 rev. *a page 27 of 110 preliminary mb95610h series 13. areas for specific applications the general-purpose register area and vector tabl e area are used for the specific applications. general-purpose register area (addresses: 0x0100 to 0x01ff*) ? this area contains the auxiliary registers used for 8-bit arithmetic operations, transfer, etc. ? as this area forms part of the ram area, it can also be used as conventional ram. ? when the area is used as general-purpose registers, general-purpose register addr essing enables high-speed access with short instructions. non-volatile register data area (addresses: 0xffbb to 0xffbf) ? the area from 0xffbb to 0xffbf is used to store data of the non-volatile register. for details, refer to ?chapter 27 non-vol- atile register (nvr) interface? in ?new 8fx mb95610h series hardware manual?. vector table area (addresses: 0xffc0 to 0xffff) ? this area is used as the vector table for vector call instructions (callv), interrupts, and resets. ? the top of the flash memory area is allocate d to the vector table area. the start addr ess of a service routine is set to an add ress in the vector table in the form of data. ? interrupt source table? lists the vector table addresses corresponding to vector call instructio ns, interrupts, and resets. for details, refer to ?chapter 4 reset?, ?chapt er 5 interrupts?, and ?a.2 special instruction special instruction callv #vct? in ?appendix? in ?new 8fx mb95610h series hardware manual?. direct bank pointer and access area *: due to the memory size limi t, the available access area is up to ?0x028f? in mb95f613h/f613k. direct bank pointer (dp[2:0]) operand-specified dir access area 0bxxx (it does not affect mapping.) 0x0000 to 0x007f 0x0000 to 0x007f 0b000 (initial value) 0x0090 to 0x00ff 0x0090 to 0x00ff 0b001 0x0080 to 0x00ff 0x0100 to 0x017f 0b010 0x0180 to 0x01ff 0b011 0x0200 to 0x027f 0b100 0x0280 to 0x02ff* 0b101 0x0300 to 0x037f 0b110 0x0380 to 0x03ff 0b111 0x0400 to 0x047f
document number: 002-04698 rev. *a page 28 of 110 preliminary mb95610h series 14. i/o map (continued) address register abbreviation register name r/w initial value 0x0000 pdr0 port 0 data register r/w 0b00000000 0x0001 ddr0 port 0 direction register r/w 0b00000000 0x0002 pdr1 port 1 data register r/w 0b00000000 0x0003 ddr1 port 1 direction register r/w 0b00000000 0x0004 ? (disabled) ? ? 0x0005 watr oscillation stabilization wait time setting register r/w 0b11111111 0x0006 pllc pll control register r/w 0b000x0000 0x0007 sycc system clock control register r/w 0bxxx11011 0x0008 stbc standby control register r/w 0b00000000 0x0009 rsrr reset source register r/w 0b000xxxxx 0x000a tbtc time-base timer control register r/w 0b00000000 0x000b wpcr watch prescaler control register r/w 0b00000000 0x000c wdtc watchdog timer control register r/w 0b00xx0000 0x000d sycc2 system clock control register 2 r/w 0bxxxx0011 0x000e pdr2 port 2 data register r/w 0b00000000 0x000f ddr2 port 2 direction register r/w 0b00000000 0x0010 pdr3 port 3 data register r/w 0b00000000 0x0011 ddr3 port 3 direction register r/w 0b00000000 0x0012, 0x0013 ? (disabled) ? ? 0x0014 pdr5 port 5 data register r/w 0b00000000 0x0015 ddr5 port 5 direction register r/w 0b00000000 0x0016 to 0x001b ? (disabled) ? ? 0x001c pdr9 port 9 data register r/w 0b00000000 0x001d ddr9 port 9 direction register r/w 0b00000000 0x001e stbc2 standby control register 2 r/w 0b00000000 0x001f to 0x0027 ? (disabled) ? ? 0x0028 pdrf port f data register r/w 0b00000000 0x0029 ddrf port f direction register r/w 0b00000000 0x002a pdrg port g data register r/w 0b00000000 0x002b ddrg port g direction register r/w 0b00000000 0x002c ? (disabled) ? ? 0x002d pul1 port 1 pull-up register r/w 0b00000000 0x002e to 0x0030 ? (disabled) ? ? 0x0031 pul5 port 5 pull-up register r/w 0b00000000
document number: 002-04698 rev. *a page 29 of 110 preliminary mb95610h series (continued) address register abbreviation register name r/w initial value 0x0032 to 0x0034 ? (disabled) ? ? 0x0035 pulg port g pull-up register r/w 0b00000000 0x0036 t01cr1 8/16-bit composite timer 01 status control register 1 r/w 0b00000000 0x0037 t00cr1 8/16-bit composite timer 00 status control register 1 r/w 0b00000000 0x0038 t11cr1 8/16-bit composite timer 11 status control register 1 r/w 0b00000000 0x0039 t10cr1 8/16-bit composite timer 10 status control register 1 r/w 0b00000000 0x003a pc01 8/16-bit ppg timer 01 control register r/w 0b00000000 0x003b pc00 8/16-bit ppg timer 00 control register r/w 0b00000000 0x003c pc11 8/16-bit ppg timer 11 control register r/w 0b00000000 0x003d pc10 8/16-bit ppg timer 10 control register r/w 0b00000000 0x003e tmcsrh0 16-bit reload timer control status register (upper) ch. 0 r/w 0b00000000 0x003f tmcsrl0 16-bit reload timer control status register (lower) ch. 0 r/w 0b00000000 0x0040 to 0x0047 ? (disabled) ? ? 0x0048 eic00 external interrupt circuit control register ch. 0/ch. 1 r/w 0b00000000 0x0049 eic10 external interrupt circuit control register ch. 2/ch. 3 r/w 0b00000000 0x004a eic20 external interrupt circuit control register ch. 4/ch. 5 r/w 0b00000000 0x004b eic30 external interrupt circuit control register ch. 6/ch. 7 r/w 0b00000000 0x004c, 0x004d ? (disabled) ? ? 0x004e lvdr lvd reset voltage selection id register r/w 0b00000000 0x004f lcdcc2 lcdc control register 2 r/w 0b00010100 0x0050 to 0x0055 ? (disabled) ? ? 0x0056 smc10 uart/sio serial mode control register 1 ch. 0 r/w 0b00000000 0x0057 smc20 uart/sio serial mode control register 2 ch. 0 r/w 0b00100000 0x0058 ssr0 uart/sio serial status and data register ch. 0 r/w 0b00000001 0x0059 tdr0 uart/sio serial output data register ch. 0 r/w 0b00000000 0x005a rdr0 uart/sio serial input data register ch. 0 r 0b00000000 0x005b smc11 uart/sio serial mode control register 1 ch. 1 r/w 0b00000000 0x005c smc21 uart/sio serial mode control register 2 ch. 1 r/w 0b00100000 0x005d ssr1 uart/sio serial status and data register ch. 1 r/w 0b00000001 0x005e tdr1 uart/sio serial output data register ch. 1 r/w 0b00000000 0x005f rdr1 uart/sio serial input data register ch. 1 r 0b00000000 0x0060 ibcr00 i 2 c bus control register 0 ch. 0 r/w 0b00000000 0x0061 ibcr10 i 2 c bus control register 1 ch. 0 r/w 0b00000000
document number: 002-04698 rev. *a page 30 of 110 preliminary mb95610h series (continued) address register abbreviation register name r/w initial value 0x0062 ibsr0 i 2 c bus status register ch. 0 r/w 0b00000000 0x0063 iddr0 i 2 c data register ch. 0 r/w 0b00000000 0x0064 iaar0 i 2 c address register ch. 0 r/w 0b00000000 0x0065 iccr0 i 2 c clock control register ch. 0 r/w 0b00000000 0x0066 to 0x006b ? (disabled) ? ? 0x006c adc1 8/10-bit a/d converter control register 1 r/w 0b00000000 0x006d adc2 8/10-bit a/d converter control register 2 r/w 0b00000000 0x006e addh 8/10-bit a/d converter data register (upper) r/w 0b00000000 0x006f addl 8/10-bit a/d converter data register (lower) r/w 0b00000000 0x0070 wcsr watch counter status register r/w 0b00000000 0x0071 fsr2 flash memory status register 2 r/w 0b00000000 0x0072 fsr flash memory status register r/w 0b000x0000 0x0073 swre0 flash memory sector write control register 0 r/w 0b00000000 0x0074 fsr3 flash memory status register 3 r 0b000xxxxx 0x0075 fsr4 flash memory status register 4 r/w 0b00000000 0x0076 wren wild register address compare enable register r/w 0b00000000 0x0077 wror wild register data test setting register r/w 0b00000000 0x0078 ? mirror of register bank pointer (rp) and direct bank pointer (dp) ? ? 0x0079 ilr0 interrupt level setting register 0 r/w 0b11111111 0x007a ilr1 interrupt level setting register 1 r/w 0b11111111 0x007b ilr2 interrupt level setting register 2 r/w 0b11111111 0x007c ilr3 interrupt level setting register 3 r/w 0b11111111 0x007d ilr4 interrupt level setting register 4 r/w 0b11111111 0x007e ilr5 interrupt level setting register 5 r/w 0b11111111 0x007f ? (disabled) ? ? 0x0f80 wrarh0 wild register address setting register (upper) ch. 0 r/w 0b00000000 0x0f81 wrarl0 wild register address setting register (lower) ch. 0 r/w 0b00000000 0x0f82 wrdr0 wild register data setting register ch. 0 r/w 0b00000000 0x0f83 wrarh1 wild register address setting register (upper) ch. 1 r/w 0b00000000 0x0f84 wrarl1 wild register address setting register (lower) ch. 1 r/w 0b00000000 0x0f85 wrdr1 wild register data setting register ch. 1 r/w 0b00000000 0x0f86 wrarh2 wild register address setting register (upper) ch. 2 r/w 0b00000000 0x0f87 wrarl2 wild register address setting register (lower) ch. 2 r/w 0b00000000 0x0f88 wrdr2 wild register data setting register ch. 2 r/w 0b00000000 0x0f89 to 0x0f91 ? (disabled) ? ? 0x0f92 t01cr0 8/16-bit composite timer 01 status control register 0 r/w 0b00000000 0x0f93 t00cr0 8/16-bit composite timer 00 status control register 0 r/w 0b00000000
document number: 002-04698 rev. *a page 31 of 110 preliminary mb95610h series (continued) address register abbreviation register name r/w initial value 0x0f94 t01dr 8/16-bit composite timer 01 data register r/w 0b00000000 0x0f95 t00dr 8/16-bit composite timer 00 data register r/w 0b00000000 0x0f96 tmcr0 8/16-bit composite timer 00/01 timer mode control register r/w 0b00000000 0x0f97 t11cr0 8/16-bit composite timer 11 status control register 0 r/w 0b00000000 0x0f98 t10cr0 8/16-bit composite timer 10 status control register 0 r/w 0b00000000 0x0f99 t11dr 8/16-bit composite timer 11 data register r/w 0b00000000 0x0f9a t10dr 8/16-bit composite timer 10 data register r/w 0b00000000 0x0f9b tmcr1 8/16-bit composite timer 10/11 timer mode control register r/w 0b00000000 0x0f9c pps01 8/16-bit ppg01 cycle setting buffer register r/w 0b11111111 0x0f9d pps00 8/16-bit ppg00 cycle setting buffer register r/w 0b11111111 0x0f9e pds01 8/16-bit ppg01 duty setting buffer register r/w 0b11111111 0x0f9f pds00 8/16-bit ppg00 duty setting buffer register r/w 0b11111111 0x0fa0 pps11 8/16-bit ppg11 cycle setting buffer register r/w 0b11111111 0x0fa1 pps10 8/16-bit ppg10 cycle setting buffer register r/w 0b11111111 0x0fa2 pds11 8/16-bit ppg11 duty setting buffer register r/w 0b11111111 0x0fa3 pds10 8/16-bit ppg10 duty setting buffer register r/w 0b11111111 0x0fa4 ppgs 8/16-bit ppg start register r/w 0b00000000 0x0fa5 revc 8/16-bit ppg output inversion register r/w 0b00000000 0x0fa6 tmrh0 16-bit reload timer timer register (upper) ch. 0 r/w 0b00000000 tmrlrh0 16-bit reload timer reload register (upper) ch. 0 0x0fa7 tmrl0 16-bit reload timer timer register (lower) ch. 0 r/w 0b00000000 tmrlrl0 16-bit reload timer re load register (lower) ch. 0 0x0fa8 pssr0 uart/sio dedicated baud rate generator prescaler select register ch. 0 r/w 0b00000000 0x0fa9 brsr0 uart/sio dedicated baud rate generator baud rate setting register ch. 0 r/w 0b00000000 0x0faa pssr1 uart/sio dedicated baud rate generator prescaler select register ch. 1 r/w 0b00000000 0x0fab brsr1 uart/sio dedicated baud rate generator baud rate setting register ch. 1 r/w 0b00000000 0x0fac to 0x0fae ? (disabled) ? ? 0x0faf aidrl a/d input disable register (lower) r/w 0b00000000 0x0fb0 lcdcc1 lcdc control register 1 r/w 0b00000000 0x0fb1 ? (disabled) ? ? 0x0fb2 lcdce1 lcdc enable register 1 r/w 0b00111110 0x0fb3 lcdce2 lcdc enable register 2 r/w 0b00000000 0x0fb4 lcdce3 lcdc enable register 3 r/w 0b00000000 0x0fb5 lcdce4 lcdc enable register 4 r/w 0b00000000 0x0fb6 lcdce5 lcdc enable register 5 r/w 0b00000000
document number: 002-04698 rev. *a page 32 of 110 preliminary mb95610h series (continued) r/w access symbols initial value symbols note: do not write to an address that is ?(disabled)?. if a ?(disabled)? address is read, an indeterminate value is returned. address register abbreviation register name r/w initial value 0x0fb7 lcdce6 lcdc enable register 6 r/w 0b00000000 0x0fb8 lcdce7 lcdc enable register 7 r/w 0b00000000 0x0fb9 lcdce8 lcdc enable register 8 r/w 0b00000000 0x0fba lcdce9 lcdc enable register 9 r/w 0b00000000 0x0fbb lcdcb1 lcdc blinking setting register 1 r/w 0b00000000 0x0fbc lcdcb2 lcdc blinking setting register 2 r/w 0b00000000 0x0fbd to 0x0fe0 lcdram lcdc display ram 4 com mode: 0x0fbd to 0x0fd6 (26 bytes) 8 com mode: 0x0fc1 to 0x0fe0 (32 bytes) r/w 0b00000000 0x0fe1 ? (disabled) ? ? 0x0fe2 evcr event counter control register r/w 0bxxxxxxx0 0x0fe3 wcdr watch counter data register r/w 0b00111111 0x0fe4 crth main cr clock trimming register (upper) r/w 0b000xxxxx 0x0fe5 crtl main cr clock trimming register (lower) r/w 0b000xxxxx 0x0fe6 ? (disabled) ? ? 0x0fe7 crtda main cr clock temperature dependent adjustment register r/w 0b000xxxxx 0x0fe8 sysc system configuration register r/w 0b11000011 0x0fe9 cmcr clock monitoring control register r/w 0b00000000 0x0fea cmdr clock monitoring data register r 0b00000000 0x0feb wdth watchdog timer select ion id register (upper) r 0bxxxxxxxx 0x0fec wdtl watchdog timer selecti on id register (lower) r 0bxxxxxxxx 0x0fed, 0x0fee ? (disabled) ? ? 0x0fef wicr interrupt pin selection circuit control register r/w 0b01000000 0x0ff0 to 0x0fff lcdram lcdc display ram 4 com mode: unused 8 com mode: 0x0ff0 to 0x0fff (16 bytes) r/w 0b00000000 r/w : readable/writable r : read only 0 : the initial value of this bit is ?0?. 1 : the initial value of this bit is ?1?. x : the initial value of this bit is undefined.
document number: 002-04698 rev. *a page 33 of 110 preliminary mb95610h series 15. i/o ports list of port registers r/w : readable/writable (the read value is the same as the write value.) r, rm/w : readable/writable (the read value is different from the write value. the writ e value is read by the read-modify-write (rmw) type of instruction.) 15.1 port 0 port 0 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.1.1 port 0 configuration port 0 is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port 0 data register (pdr0) port 0 direction register (ddr0) a/d input disable register (lower) (aidrl) register name read/write initial value port 0 data register pdr0 r, rm/w 0b00000000 port 0 direction register ddr0 r/w 0b00000000 port 1 data register pdr1 r, rm/w 0b00000000 port 1 direction register ddr1 r/w 0b00000000 port 2 data register pdr2 r, rm/w 0b00000000 port 2 direction register ddr2 r/w 0b00000000 port 3 data register pdr3 r, rm/w 0b00000000 port 3 direction register ddr3 r/w 0b00000000 port 5 data register pdr5 r, rm/w 0b00000000 port 5 direction register ddr5 r/w 0b00000000 port 9 data register pdr9 r, rm/w 0b00000000 port 9 direction register ddr9 r/w 0b00000000 port f data register pdrf r, rm/w 0b00000000 port f direction register ddrf r/w 0b00000000 port g data register pdrg r, rm/w 0b00000000 port g direction register ddrg r/w 0b00000000 port 1 pull-up register pul1 r/w 0b00000000 port 5 pull-up register pul5 r/w 0b00000000 port g pull-up register pulg r/w 0b00000000 a/d input disable register (lower) aidrl r/w 0b00000000
document number: 002-04698 rev. *a page 34 of 110 preliminary mb95610h series 15.1.2 block diagrams of port 0 p00/int00/an00 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int00) ? 8/10-bit a/d converter analog input pin (an00) p01/int01/an01 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int01) ? 8/10-bit a/d converter analog input pin (an01) p02/int02/an02 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int02) ? 8/10-bit a/d converter analog input pin (an02) p03/int03/an03 pin this pin has the following peripheral functions: ? external interrupt circuit input pin (int03) ? 8/10-bit a/d converter analog input pin (an03) block diagram of p00/int00/an00, p01/int 01/an01, p02/int02/an02 and p03/int03/an03 p04/seg32 pin this pin has the following peripheral function: ? lcdc seg32 output pin (seg32) pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write aidrl read aidrl write ddr0 aidrl 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int00, int01, int02 and int03) a/d analog input internal bus
document number: 002-04698 rev. *a page 35 of 110 preliminary mb95610h series block diagram of p04/seg32 p05/seg33/adtg pin this pin has the following peripheral functions: ? lcdc seg33 output pin (seg33) ? 8/10-bit a/d converter trigger input pin (adtg) block diagram of p05/seg33/adtg p06/seg34/ppg10 pin this pin has the following peripheral functions: ? lcdc seg34 output pin (seg34) ? 8/16-bit ppg ch. 1 output pin (ppg10) pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write ddr0 0 1 stop mode, watch mode (spl = 1) lcd output lcd output enable internal bus pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write ddr0 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable lcd output internal bus lcd output enable
document number: 002-04698 rev. *a page 36 of 110 preliminary mb95610h series p07/seg35/ppg11 pin this pin has the following peripheral functions: ? lcdc seg35 output pin (seg35) ? 8/16-bit ppg ch. 1 output pin (ppg11) block diagram of p06/seg34/ppg10 and p07/seg35/ppg11 pdr0 pin pdr0 read pdr0 write executing bit manipulation instruction ddr0 read ddr0 write ddr0 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output internal bus lcd output lcd output enable
document number: 002-04698 rev. *a page 37 of 110 preliminary mb95610h series 15.1.3 port 0 registers port 0 register functions correspondence between registers and pins for port 0 15.1.4 port 0 operations operation as an output port ? a pin becomes an output port if the bit in the ddr0 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr0 register to external pins. ? if data is written to the pdr0 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr0 register returns the pdr0 register value. ? to use a pin shared with the lcdc as an output port, set a co rresponding function select bit (seg[35:32]) in the lcdc enable register 7 (lcdce7) to ?0? to select the general-purpose i/o por t function, and then set the port input control bit (pictl) in the lcdc enable register 1 (lcdce1) to ?1?. operation as an input port ? a pin becomes an input port if the bit in the ddr0 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when using an analog input shared pin as an input port, set the co rresponding bit in the a/d input disable register (lower) (ai drl) to ?1?. ? if data is written to the pdr0 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr0 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr0 register, the pdr0 re gister value is returned. ? to use a pin shared with the lcdc as an input port, set a corresp onding function select bit (seg[3 5:32]) in the lcdce7 register to ?0? to select the general-purpose i/o port function, an d then set the pictl bit in the lcdce1 register to ?1?. operation as a peripheral function output pin ? a pin becomes a peripheral function output pin if the peripheral output function is ena bled by setting the output enable bit of a peripheral function corresponding to that pin. ? the pin value can be read from the pdr0 register even if the per ipheral function output is enabl ed. therefore, the output value of a peripheral function can be read by t he read operation on the pdr0 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr0 regi ster, the pdr0 register value is returned. register abbreviation data read read by read-modify-write (rmw) instruction write pdr0 0 pin state is ?l? level. pdr0 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr0 value is ?1?. as output port, outputs ?h? level. ddr0 0 port input enabled 1 port output enabled aidrl 0 analog input enabled 1 port input enabled correspondence between related register bits and pins pin name p07 p06 p05 p04 p03 p02 p01 p00 pdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr0 aidrl----
document number: 002-04698 rev. *a page 38 of 110 preliminary mb95610h series operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr0 register corresponding to the input pin of a peripheral function to ?0?. ? when using the analog input shared pin as an other peripheral function input pin, configure it as an input port, which is the sa me as the operation as an input port. ? reading the pdr0 register returns the pin value, regardless of w hether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the p dr0 register, the pdr0 register value is retur ned. operation as an lcdc segment output pin ? set the bit in the ddr0 register corresponding to a desired lcdc segment output pin to ?0?. ? select the segment pin by setting a corresponding function select bit (seg[35:32]) in the lcdce7 re gister to ?1?, and then set the pictl bit in the lcdce1 register to ?1?. operation at reset if the cpu is reset, all bits in the ddr0 register are initialized to ?0? and port input is enabled. as for a pin shared with a nalog input, its port input is disabled because the ai drl register is initialized to ?0?. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr0 register value. the input of that pin is locked to ?l? level and blocked in order to prevent lea ks due to input open. however, if the interrupt input is enabled for the external interrupt (int00 to int03), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation as an analog input pin ? set the bit in the ddr0 register bit corresponding to the analog input pin to ?0? and the bit corresponding to that pin in the aidrl register to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. operation as an external interrupt input pin ? set the bit in the ddr0 register corresponding to the external interrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt circuit. when using a pin for a function other than the interrupt, disa ble the external interrupt function corresponding to that pin.
document number: 002-04698 rev. *a page 39 of 110 preliminary mb95610h series 15.2 port 1 port 1 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.2.1 port 1 configuration port 1 is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port 1 data register (pdr1) port 1 direction register (ddr1) port 1 pull-up register (pul1) 15.2.2 block diagrams of port 1 p12/dbg pin this pin has the following peripheral function: ? dbg input pin (dbg) block diagram of p12/dbg pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write ddr1 0 1 stop mode, watch mode (spl = 1) od internal bus
document number: 002-04698 rev. *a page 40 of 110 preliminary mb95610h series p13/uo0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data output pin (uo0) block diagram of p13/uo0 p14/uck0 pin this pin has the following peripheral function: ? uart/sio ch. 0 clock i/o pin (uck0) pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
document number: 002-04698 rev. *a page 41 of 110 preliminary mb95610h series block diagram of p14/uck0 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output hysteresis pull-up internal bus
document number: 002-04698 rev. *a page 42 of 110 preliminary mb95610h series p15/ui0 pin this pin has the following peripheral function: ? uart/sio ch. 0 data input pin (ui0) block diagram of p15/ui0 pdr1 pin pdr1 read pdr1 write executing bit manipulation instruction ddr1 read ddr1 write pul1 read pul1 write ddr1 pul1 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable cmos pull-up internal bus
document number: 002-04698 rev. *a page 43 of 110 preliminary mb95610h series 15.2.3 port 1 registers port 1 register functions *: if the pin is an n-ch open drain pin, the pin state becomes hi-z. correspondence between registers and pins for port 1 *: though p12 has no pull-up function, bit2 in the pul1 register can still be accessed. th e operation of p12 is not affected by the setting of bit2 in the pul1 register. register abbreviation data read read by read-modify-write (rmw) instruction write pdr1 0 pin state is ?l? level. pdr1 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr1 value is ?1?. as output port, outputs ?h? level.* ddr1 0 port input enabled 1 port output enabled pul1 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - p15 p14 p13 p12 - - pdr1 - - bit5 bit4 bit3 bit2* - - ddr1 pul1
document number: 002-04698 rev. *a page 44 of 110 preliminary mb95610h series 15.2.4 port 1 operations operation as an output port ? a pin becomes an output port if the bit in the ddr1 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr1 register to external pins. ? if data is written to the pdr1 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr1 register returns the pdr1 register value. operation as an input port ? a pin becomes an input port if the bit in the ddr1 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr1 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr1 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr1 register, the pdr1 re gister value is returned. operation as a peripheral function output pin ? a pin becomes a peripheral function output pin if the peripheral output function is ena bled by setting the output enable bit of a peripheral function corresponding to that pin. ? the pin value can be read from the pdr1 register even if the per ipheral function output is enabl ed. therefore, the output value of a peripheral function can be read by t he read operation on the pdr1 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr1 regi ster, the pdr1 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr1 register corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr1 register returns the pin value, regardless of w hether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the p dr1 register, the pdr1 register value is retur ned. operation at reset if the cpu is reset, all bits in the ddr1 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr1 register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. however, if the interrupt input of p14/uck0 and p15/ui0 is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit and the interrupt pin selection circuit control register (wicr) of the interrupt pin selection circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation of the pull-up register setting the bit in the pul1 register to ?1? makes the pull-up re sistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected rega rdless of the value of the pul1 register.
document number: 002-04698 rev. *a page 45 of 110 preliminary mb95610h series 15.3 port 2 port 2 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.3.1 port 2 configuration port 2 is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port 2 data register (pdr2) port 2 direction register (ddr2) 15.3.2 block diagrams of port 2 p20/seg44/ti0 pin this pin has the following peripheral functions: ? lcdc seg44 output pin (seg44) ? 16-bit reload timer ch. 0 input pin (ti0) p23/seg47/ui1 pin this pin has the following peripheral functions: ? lcdc seg47 output pin (seg47) ? uart/sio ch. 1 data input pin (ui1) block diagram of p20/seg44/ti0 and p23/seg47/ui1 pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write ddr2 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable lcd output internal bus lcd output enable
document number: 002-04698 rev. *a page 46 of 110 preliminary mb95610h series p21/seg45/uo1 pin this pin has the following peripheral functions: ? lcdc seg45 output pin (seg45) ? uart/sio ch. 1 data output pin (uo1) p24/seg48/ppg00 pin this pin has the following peripheral functions: ? lcdc seg48 output pin (seg48) ? 8/16-bit ppg ch. 0 output pin (ppg00) p25/seg49/ppg01 pin this pin has the following peripheral functions: ? lcdc seg49 output pin (seg49) ? 8/16-bit ppg ch. 0 output pin (ppg01) block diagram of p21/seg45/uo1, p24/seg48/ppg00 and p25/seg49/ppg01 pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write ddr2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output internal bus lcd output lcd output enable
document number: 002-04698 rev. *a page 47 of 110 preliminary mb95610h series p22/seg46/uck1 pin this pin has the following peripheral functions: ? lcdc seg46 output pin (seg46) ? uart/sio ch. 1 clock i/o pin (uck1) p26/seg50/scl pin this pin has the following peripheral functions: ? lcdc seg50 output pin (seg50) ? i 2 c bus interface ch. 0 clock i/o pin (scl) p27/seg51/sda pin this pin has the following peripheral functions: ? lcdc seg51 output pin (seg51) ? i 2 c bus interface ch. 0 data i/o pin (sda) block diagram of p22/seg46/uck1, p26/seg50/scl and p27/seg51/sda pdr2 pin pdr2 read pdr2 write executing bit manipulation instruction ddr2 read ddr2 write ddr2 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable peripheral function output enable peripheral function output internal bus lcd output lcd output enable
document number: 002-04698 rev. *a page 48 of 110 preliminary mb95610h series 15.3.3 port 2 registers port 2 register functions correspondence between registers and pins for port 2 register abbreviation data read read by read-modify-write (rmw) instruction write pdr2 0 pin state is ?l? level. pdr2 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr2 value is ?1?. as output port, outputs ?h? level. ddr2 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name p27 p26 p25 p24 p23 p22 p21 p20 pdr2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr2
document number: 002-04698 rev. *a page 49 of 110 preliminary mb95610h series 15.3.4 port 2 operations operation as an output port ? a pin becomes an output port if the bit in the ddr2 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr2 register to external pins. ? if data is written to the pdr2 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr2 register returns the pdr2 register value. ? to use a pin shared with the lcdc as an output port, set a co rresponding function select bit in the lcdc enable register 9 (lcdce9:seg[51:48]) or in the lcdc enable register 8 (lcdce8: seg[47:44]) to ?0? to select the general-purpose i/o port function, and then set the port inpu t control bit (pictl) in the lcdc enable register 1 (lcdce1) to ?1?. operation as an input port ? a pin becomes an input port if the bit in the ddr2 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr2 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr2 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr2 register, the pdr2 re gister value is returned. ? to use a pin shared with the lcdc as an input port, set a corr esponding function select bit in the lcdc enable register 9 (lcdce9:seg[51:48]) or in the lcdc enable register 8 (lcdce8: seg[47:44]) to ?0? to select the general-purpose i/o port function, and then set the port inpu t control bit (pictl) in the lcdc enable register 1 (lcdce1) to ?1?. operation as a peripheral function output pin ? a pin becomes a peripheral function output pin if the peripheral output function is ena bled by setting the output enable bit of a peripheral function corresponding to that pin. ? the pin value can be read from the pdr2 register even if the per ipheral function output is enabl ed. therefore, the output value of a peripheral function can be read by t he read operation on the pdr2 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr2 regi ster, the pdr2 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr2 register corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr2 register returns the pin value, regardless of w hether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the p dr2 register, the pdr2 register value is retur ned. operation as an lcdc segment output pin ? set the bit in the ddr2 register corresponding to a desired lcdc segment output pin to ?0?. ? select the segment pin by setting a corresponding function select bit in the lcdc enable register 9 (lcdce9:seg[51:48]) or in the lcdc enable register 8 (lcdce8:seg[47:44]) to ?1?, and then set the pictl bit in the lcdce1 register to ?1?. operation at reset if the cpu is reset, all bits in the ddr2 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr2 register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained.
document number: 002-04698 rev. *a page 50 of 110 preliminary mb95610h series 15.4 port 3 port 3 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.4.1 port 3 configuration port 3 is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port 3 data register (pdr3) ? port 3 direction register (ddr3) 15.4.2 block diagrams of port 3 p30/seg36/int04 pin this pin has the following peripheral functions: ? lcdc seg36 output pin (seg36) ? external interrupt input pin (int04) p31/seg37/int05 pin this pin has the following peripheral functions: ? lcdc seg37 output pin (seg37) ? external interrupt input pin (int05) p32/seg38/int06 pin this pin has the following peripheral functions: ? lcdc seg38 output pin (seg38) ? external interrupt input pin (int06) p33/seg39/int07 pin this pin has the following peripheral functions: ? lcdc seg39 output pin (seg39) ? external interrupt input pin (int07)
document number: 002-04698 rev. *a page 51 of 110 preliminary mb95610h series block diagram of p30/seg36/int04, p31/seg37 /int05, p32/seg38/int 06 and p33/seg39/int07 pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction ddr3 read ddr3 write ddr3 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable (int04, int05, int06 and int07) lcd output internal bus lcd output enable
document number: 002-04698 rev. *a page 52 of 110 preliminary mb95610h series p34/seg40/to11 pin this pin has the following peripheral functions: ? lcdc seg40 output pin (seg40) ? 8/16-bit composite timer ch. 1 output pin (to11) p35/seg41/to10 pin this pin has the following peripheral functions: ? lcdc seg41 output pin (seg41) ? 8/16-bit composite timer ch. 1 output pin (to10) p37/seg43/to0 pin this pin has the following peripheral functions: ? lcdc seg43 output pin (seg43) ? 16-bit reload timer ch. 0 output pin (to0) block diagram of p34/seg40/to11, p35/seg41/to11 and p37/seg43/to0 pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction ddr3 read ddr3 write ddr3 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output internal bus lcd output lcd output enable
document number: 002-04698 rev. *a page 53 of 110 preliminary mb95610h series p36/seg42/ec1 pin this pin has the following peripheral functions: ? lcdc seg42 output pin (seg42) ? 8/16-bit composite timer ch. 1 clock input pin (ec1) block diagram of p36/seg42/ec1 15.4.3 port 3 registers port 3 register functions correspondence between registers and pins for port 3 15.4.4 port 3 operations operation as an output port ? a pin becomes an output port if the bit in the ddr3 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr3 register to external pins. ? if data is written to the pdr3 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr3 register returns the pdr3 register value. register abbreviation data read read by read-modify-write (rmw) instruction write pdr3 0 pin state is ?l? level. pdr3 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr3 value is ?1?. as output port, outputs ?h? level. ddr3 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name p37 p36 p35 p34 p33 p32 p31 p30 pdr3 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 ddr3 pdr3 pin pdr3 read pdr3 write executing bit manipulation instruction ddr3 read ddr3 write ddr3 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable lcd output internal bus lcd output enable
document number: 002-04698 rev. *a page 54 of 110 preliminary mb95610h series ? to use a pin shared with the lcdc as an output port, set a co rresponding function select bit in the lcdc enable register 8 (lcdce8:seg[43:40]) or in the lcdc enable register 7 (lcdce7: seg[39:36]) to ?0? to select the general-purpose i/o port function, and then set the port inpu t control bit (pictl) in the lcdc enable register 1 (lcdce1) to ?1?. operation as an input port ? a pin becomes an input port if the bit in the ddr3 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr3 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr3 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr3 register, the pdr3 re gister value is returned. ? to use a pin shared with the lcdc as an input port, set a corr esponding function select bit in the lcdc enable register 8 (lcdce8:seg[43:40]) or in the lcdc enable register 7 (lcdce7: seg[39:36]) to ?0? to select the general-purpose i/o port function, and then set the port inpu t control bit (pictl) in the lcdc enable register 1 (lcdce1) to ?1?. operation as a peripheral function output pin ? a pin becomes a peripheral function output pin if the peripheral output function is ena bled by setting the output enable bit of a peripheral function corresponding to that pin. ? the pin value can be read from the pdr3 register even if the per ipheral function output is enabl ed. therefore, the output value of a peripheral function can be read by t he read operation on the pdr3 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr3 regi ster, the pdr3 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr3 register corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr3 register returns the pin value, regardless of w hether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the p dr3 register, the pdr3 register value is retur ned.
document number: 002-04698 rev. *a page 55 of 110 preliminary mb95610h series operation as an lcdc segment output pin ? set the bit in the ddr3 register corresponding to a desired lcdc segment output pin to ?0?. ? select the segment pin by setting a corresponding function select bit in the lcdc enable register 8 (lcdce8:seg[43:40]) or in the lcdc enable register 7 (lcdce7:seg[39:36]) to ?1?, and then set the pictl bit in the lcdce1 register to ?1?. operation at reset if the cpu is reset, all bits in the ddr3 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr3 register value. the input of that pin is locked to ?l? level and blocked in order to prevent lea ks due to input open. however, if the interrupt input is enabled for the external interrupt (int04 to int07), the input is enabled and not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation as an external interrupt input pin ? set the bit in the ddr3 register corresponding to the external interrupt input pin to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? the pin value is always input to the external interrupt circuit. when using a pin for a function other than the interrupt, disa ble the external interrupt function corresponding to that pin.
document number: 002-04698 rev. *a page 56 of 110 preliminary mb95610h series 15.5 port 5 port 5 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.5.1 port 5 configuration port 5 is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port 5 data register (pdr5) port 5 direction register (ddr5) port 5 pull-up register (pul5) 15.5.2 block diagrams of port 5 p50/to01 pin this pin has the following peripheral function: ? 8/16-bit composite time ch. 0 output pin (to01) p52/to00 pin this pin has the following peripheral function: ? 8/16-bit composite time ch. 0 output pin (to00) block diagram of p50/to01 and p52/to00 p51/ec0 pin this pin has the following peripheral function: ? 8/16-bit composite time ch. 0 clock input pin (ec0) pdr5 pin pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write pul5 read pul5 write ddr5 pul5 0 1 1 0 stop mode, watch mode (spl = 1) peripheral function output enable peripheral function output hysteresis pull-up internal bus
document number: 002-04698 rev. *a page 57 of 110 preliminary mb95610h series block diagram of p51/ec0 pdr5 pin pdr5 read pdr5 write executing bit manipulation instruction ddr5 read ddr5 write pul5 read pul5 write ddr5 pul5 0 1 stop mode, watch mode (spl = 1) peripheral function input peripheral function input enable hysteresis pull-up internal bus
document number: 002-04698 rev. *a page 58 of 110 preliminary mb95610h series 15.5.3 port 5 registers port 5 register functions correspondence between registers and pins for port 5 15.5.4 port 5 operations operation as an output port ? a pin becomes an output port if the bit in the ddr5 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr5 register to external pins. ? if data is written to the pdr5 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr5 register returns the pdr5 register value. operation as an input port ? a pin becomes an input port if the bit in the ddr5 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr5 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr5 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr5 register, the pdr5 re gister value is returned. operation as a peripheral function output pin ? a pin becomes a peripheral function output pin if the peripheral output function is ena bled by setting the output enable bit of a peripheral function corresponding to that pin. ? the pin value can be read from the pdr5 register even if the per ipheral function output is enabl ed. therefore, the output value of a peripheral function can be read by t he read operation on the pdr5 register. however, if the read-modify-write (rmw) type of instruction is used to read the pdr5 regi ster, the pdr5 register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddr5 register corresponding to the input pin of a peripheral function to ?0?. ? reading the pdr5 register returns the pin value, regardless of w hether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the p dr5 register, the pdr5 register value is retur ned. operation at reset if the cpu is reset, all bits in the ddr5 register are initialized to ?0? and port input is enabled. register abbreviation data read read by read-modify-write (rmw) instruction write pdr5 0 pin state is ?l? level. pdr5 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr5 value is ?1?. as output port, outputs ?h? level. ddr5 0 port input enabled 1 port output enabled pul5 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - - - p52 p51 p50 pdr5 -----bit2bit1bit0 ddr5 pul5
document number: 002-04698 rev. *a page 59 of 110 preliminary mb95610h series operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr5 register value. the input of that pin is locked to ?l? level and blocked in order to prevent lea ks due to input open. however, if the interrupt input of p51/ec0 is enabled by the external interrupt control register ch. 0 (eic00) of the external interrupt circuit and the interrupt pin select ion circuit control register (wicr) of the interrupt pin select ion circuit, the input is enabled and is not blocked. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation of the pull-up register setting the bit in the pul5 register to ?1? makes the pull-up re sistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected rega rdless of the value of the pul5 register.
document number: 002-04698 rev. *a page 60 of 110 preliminary mb95610h series 15.6 port 9 port 9 is a general-purpose i/o port. this section focuses on its functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.6.1 port 9 configuration port 9 is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port 9 data register (pdr9) port 9 direction register (ddr9) 15.6.2 block diagrams of port 9 p90/v4 pin this pin has the following peripheral function: ? lcdc drive power supply pin (v4) p91/v3 pin this pin has the following peripheral function: ? lcdc drive power supply pin (v3) p92/v2 pin this pin has the following peripheral function: ? lcdc drive power supply pin (v2) p93/v1 pin this pin has the following peripheral function: ? lcdc drive power supply pin (v1) p94/v0 pin this pin has the following peripheral function: ? lcdc drive power supply pin (v0)
document number: 002-04698 rev. *a page 61 of 110 preliminary mb95610h series block diagram of p90/v4, p91/v3, p92/v2, p93/v1 and p94/v0 15.6.3 port 9 registers port 9 register functions correspondence between registers and pins for port 9 register abbreviation data read read by read-modify-write (rmw) instruction write pdr9 0 pin state is ?l? level. pdr9 value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdr9 value is ?1?. as output port, outputs ?h? level. ddr9 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name - - - p94 p93 p92 p91 p90 pdr9 - - - bit4 bit3 bit2 bit1 bit0 ddr9 pdr9 pin pdr9 read pdr9 write executing bit manipulation instruction ddr9 read ddr9 write ddr9 0 1 stop mode, watch mode (spl = 1) lcd power supply lcd power supply enable internal bus
document number: 002-04698 rev. *a page 62 of 110 preliminary mb95610h series 15.6.4 port 9 operations operation as an output port ? a pin becomes an output port if the bit in the ddr9 register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdr9 register to external pins. ? if data is written to the pdr9 register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdr9 register returns the pdr9 register value. ? to use a pin shared with the lcdc as an output port, set the bit corresponding to that pin in the ve[4:0] bits in the lcdc enab le register 1 (lcdce1) to ?0?. operation as an input port ? a pin becomes an input port if the bit in the ddr9 register corresponding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdr9 register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdr9 register returns the pin value. however, if t he read-modify-write (rmw) type of instruction is used to read th e pdr9 register, the pdr9 re gister value is returned. ? to use a pin shared with the lcdc as an input port, set the bit (ve[ 4:0]) corresponding to that pi n in the lcdce1 register to ? 0?. operation at reset if the cpu is reset, all bits in the ddr9 register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddr9 register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation as an lcdc drive power supply pin ? set the bit in the ddr9 register corresponding to a desired lcdc drive power supply pin to ?0?. ? select the lcdc drive power supply pin by setting the bit corresp onding to that pin in the ve[4:0] bits in the lcdce1 register to ?1?.
document number: 002-04698 rev. *a page 63 of 110 preliminary mb95610h series 15.7 port f port f is a general-purpose i/o port. this section focuses on it s functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.7.1 port f configuration port f is made up of the following elements. ? general-purpose i/o pins/peripheral function i/o pins ? port f data register (pdrf) ? port f direction register (ddrf) 15.7.2 block diagrams of port f pf0/x0 pin this pin has the following peripheral function: ? main clock input oscillation pin (x0) pf1/x1 pin this pin has the following peripheral function: ? main clock i/o oscillation pin (x1) block diagram of pf0/x0 and pf1/x1 pdrf pin pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 stop mode, watch mode (spl = 1) internal bus hysteresis
document number: 002-04698 rev. *a page 64 of 110 preliminary mb95610h series pf2/rst pin this pin has the following peripheral function: ? reset pin (rst ) block diagram of pf2/rst pdrf pdrf read pdrf write executing bit manipulation instruction ddrf read ddrf write ddrf 0 1 1 0 stop mode, watch mode (spl = 1) reset input reset input enable reset output enable reset output pin od internal bus hysteresis
document number: 002-04698 rev. *a page 65 of 110 preliminary mb95610h series 15.7.3 port f registers port f register functions *: if the pin is an n-ch open drain pin, the pin state becomes hi-z. correspondence between registers and pins for port f *: pf2/rst is the dedicated reset pin on mb95f613h/f614h/f616h. register abbreviation data read read by read-modify-write (rmw) instruction write pdrf 0 pin state is ?l? level. pdrf value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrf value is ?1?. as output port, outputs ?h? level.* ddrf 0 port input enabled 1 port output enabled correspondence between related register bits and pins pin name - - - - - pf2* pf1 pf0 pdrf -----bit2bit1bit0 ddrf
document number: 002-04698 rev. *a page 66 of 110 preliminary mb95610h series 15.7.4 port f operations operation as an output port ? a pin becomes an output port if the bit in the ddrf re gister corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdrf register to external pins. ? if data is written to the pdrf register, the value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrf register returns the pdrf register value. operation as an input port ? a pin becomes an input port if t he bit in the ddrf register correspon ding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrf register, th e value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdrf register returns the pin va lue. however, if the read-modify-write (rmw ) type of instruction is used to read th e pdrf register, the pdrf register value is returned. operation at reset if the cpu is reset, all bits in the ddrf register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrf register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained.
document number: 002-04698 rev. *a page 67 of 110 preliminary mb95610h series 15.8 port g port g is a general-purpose i/o port. this section focuses on it s functions as a general-purpose i/o port. for details of perip heral functions, refer to their respective chapters in ?new 8fx mb95610h series hardware manual?. 15.8.1 port g configuration port g is made up of the following elements. general-purpose i/o pins/peripheral function i/o pins port g data register (pdrg) port g direction register (ddrg) port g pull-up register (pulg) 15.8.2 block diagram of port g pg1/x0a pin this pin has the following peripheral function: subclock input oscillation pin (x0a) pg2/x1a pin this pin has the following peripheral function: ? subclock i/o oscillation pin (x1a) block diagram of pg 1/x0a and pg2/x1a pdrg pin pdrg read pdrg write executing bit manipulation instruction ddrg read ddrg write pulg read pulg write ddrg pulg 0 1 stop mode, watch mode (spl = 1) hysteresis pull-up internal bus
document number: 002-04698 rev. *a page 68 of 110 preliminary mb95610h series 15.8.3 port g registers port g register functions correspondence between registers and pins for port g 15.8.4 port g operations operation as an output port ? a pin becomes an output port if the bit in the ddrg register corresponding to that pin is set to ?1?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? when a pin is used as an output port, it outputs th e value of the pdrg register to external pins. ? if data is written to the pdrg register, t he value is stored in the output latch and is output to the pin set as an output port as it is. ? reading the pdrg register returns the pdrg register value. operation as an input port ? a pin becomes an input port if t he bit in the ddrg register correspon ding to that pin is set to ?0?. ? for a pin shared with other peripheral functions, disable the output of such peripheral functions. ? if data is written to the pdrg register, the value is stored in the output latch but is not output to the pin set as an input p ort. ? reading the pdrg register returns the pin value. however, if th e read-modify-write (rmw) type of instruction is used to read th e pdrg register, the pdrg register value is returned. operation as a peripheral function input pin ? to set a pin as an input port, set the bit in the ddrg register corresponding to the input pin of a peripheral function to ?0?. ? reading the pdrg register returns the pin value, regardless of whether the peripheral function uses that pin as its input pin. however, if the read-modify-write (rmw) type of instruction is used to read the pdrg re gister, the pdrg register value is retur ned. operation at reset if the cpu is reset, all bits in the ddrg register are initialized to ?0? and port input is enabled. operation in stop mode and watch mode ? if the pin state setting bit in the standby control register (stbc:spl) is set to ?1? and the device transits to stop mode or w atch mode, the pin is compulsorily made to enter the high impedance state regardless of the ddrg register value. the input of that pin is locked to ?l? level and blocked in order to prevent leaks due to input open. ? if the pin state setting bit is ?0?, the state of the port i/o or t hat of the peripheral function i/o remains unchanged and the output level is maintained. operation of the pull-up register setting the bit in the pulg register to ?1? makes the pull-up re sistor be internally connected to the pin. when the pin output is ?l? level, the pull-up resistor is disconnected regard less of the value of the pulg register. register abbreviation data read read by read-modify-write (rmw) instruction write pdrg 0 pin state is ?l? level. pdrg value is ?0?. as output port, outputs ?l? level. 1 pin state is ?h? level. pdrg value is ?1?. as output port, outputs ?h? level. ddrg 0 port input enabled 1 port output enabled pulg 0 pull-up disabled 1 pull-up enabled correspondence between related register bits and pins pin name - - - - - pg2 pg1 - pdrg -----bit2bit1- ddrg pulg
document number: 002-04698 rev. *a page 69 of 110 preliminary mb95610h series 16. interrupt source table interrupt source interrupt request number vector table address interrupt l evel setting register priority order of interrupt sources of the same level (occurring simultaneously) upper lower register bit external interrupt ch. 0 irq00 0xfffa 0xfffb ilr0 l00 [1:0] high low external interrupt ch. 4 external interrupt ch. 1 irq01 0xfff8 0xfff9 ilr0 l01 [1:0] external interrupt ch. 5 external interrupt ch. 2 irq02 0xfff6 0xfff7 ilr0 l02 [1:0] external interrupt ch. 6 external interrupt ch. 3 irq03 0xfff4 0xfff5 ilr0 l03 [1:0] external interrupt ch. 7 uart/sio ch. 0 irq04 0xfff2 0xfff3 ilr1 l04 [1:0] 8/16-bit composite timer ch. 0 (lower) irq05 0xfff0 0xfff1 ilr1 l05 [1:0] 8/16-bit composite timer ch. 0 (upper) irq06 0xffee 0xffef ilr1 l06 [1:0] ? irq07 0xffec 0xffed ilr1 l07 [1:0] lcdc irq08 0xffea 0xffeb ilr2 l08 [1:0] 8/16-bit ppg ch. 1 (lower) irq09 0xffe8 0xffe9 ilr2 l09 [1:0] uart/sio ch. 1 8/16-bit ppg ch. 1 (upper) irq10 0xffe6 0xffe7 ilr2 l10 [1:0] 16-bit reload timer ch. 0 irq11 0xffe4 0xffe5 ilr2 l11 [1:0] 8/16-bit ppg ch. 0 (upper) irq12 0xffe2 0xffe3 ilr3 l12 [1:0] 8/16-bit ppg ch. 0 (lower) irq13 0xffe0 0xffe1 ilr3 l13 [1:0] 8/16-bit composite timer ch. 1 (upper) irq14 0xffde 0xffdf ilr3 l14 [1:0] ? irq15 0xffdc 0xffdd ilr3 l15 [1:0] i 2 c bus interface ch. 0 irq16 0xffda 0xffdb ilr4 l16 [1:0] ? irq17 0xffd8 0xffd9 ilr4 l17 [1:0] 8/10-bit a/d converter irq18 0xffd6 0xffd7 ilr4 l18 [1:0] time-base timer irq19 0xffd4 0xffd5 ilr4 l19 [1:0] watch prescaler irq20 0xffd2 0xffd3 ilr5 l20 [1:0] watch counter ? irq21 0xffd0 0xffd1 ilr5 l21 [1:0] 8/16-bit composite timer ch. 1 (lower) irq22 0xffce 0xffcf ilr5 l22 [1:0] flash memory irq23 0xffcc 0xffcd ilr5 l23 [1:0]
document number: 002-04698 rev. *a page 70 of 110 preliminary mb95610h series 17. pin states in each mode (continued) pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 pf0/x0 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 -hi-z - input enabled* 3 (however, it does not function.) pf1/x1 oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 -hi-z - input enabled* 3 (however, it does not function.) pf2/rst reset input reset input reset input reset input reset input reset input reset input* 4 i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 -hi-z - input enabled* 3 (however, it does not function.) pg1/x0a oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 -hi-z - input enabled* 3 (however, it does not function.) pg2/x1a oscillation input oscillati on input hi-z hi-z hi-z hi-z ? i/o port* 1 i/o port* 1 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 - previous state kept - input blocked* 1, * 2 -hi-z - input blocked* 1, * 2 -hi-z - input enabled* 3 (however, it does not function.) p00/int00/ an00 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2, * 5 -hi-z - input blocked* 2, * 5 - previous state kept - input blocked* 2, * 5 -hi-z - input blocked* 2, * 5 -hi-z - input blocked* 2 p01/int01/ an01 p02/int02/ an02 p03/int03/ an03 p04/seg32 i/o port/ peripheral function i/o/ analog input i/o port/ peripheral function i/o/ analog input - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input blocked* 2 p05/seg33/ adtg p06/seg34/ ppg10 p07/seg35/ ppg11
document number: 002-04698 rev. *a page 71 of 110 preliminary mb95610h series pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 p12/dbg i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p13/uo0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 6 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 6 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p14/uck0 p15/ui0 p20/seg44/ ti0 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2, *7 -hi-z - input blocked* 2, *7 - previous state kept - input blocked* 2, *7 -hi-z - input blocked* 2, *7 -hi-z - input enabled* 3 (however, it does not function.) p21/seg45/ uo1 p22/seg46/ uck1 p23/seg47/ ui1 p24/seg48/ ppg00 p25/seg49/ ppg01 p26/seg50/ scl p27/seg51/ sda p30/seg36/ int04 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 * 5 -hi-z - input blocked* 2 * 5 - previous state kept - input blocked* 2 * 5 -hi-z - input blocked* 2 * 5 -hi-z - input enabled* 3 (however, it does not function.) p31/seg37/ int05 p32/seg38/ int06 p33/seg39/ int07 p34/seg40/ to11 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p35/seg41/ to10 p36/seg42/ ec1 p37/seg43/ to0 p50/to01 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z* 6 - input blocked* 2 - previous state kept - input blocked* 2 -hi-z* 6 - input blocked* 2 -hi-z - input enabled* 3 (however, it does not function.) p51/ec0 p52/to00
document number: 002-04698 rev. *a page 72 of 110 preliminary mb95610h series (continued) p90/v4 i/o port/ peripheral function i/o i/o port/ peripheral function i/o - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input blocked* 2 p91/v3 p92/v2 p93/v1 pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1
document number: 002-04698 rev. *a page 73 of 110 preliminary mb95610h series (continued) spl: pin state setting bit in the standby control register (stbc:spl) hi-z: high impedance *1: the pin stays at the state shown when configured as a general-purpose i/o port. *2: ?input blocked? means direct input gate operation from the pin is disabled. *3: ?input enabled? means that the input function is enabled. while the input function is enabled, execute a pull-up or pull-dow n op- eration to prevent leaks due to external inpu t. if a pin is used as an output port, it s pin state is the same as that of other ports. *4: the pf2/rst pin stays at the state shown when configured as a reset pin. *5: though input is blocked, an external interrupt can be input when the external interrupt request is enabled. *6: the pull-up control se tting is still effective. *7: the i 2 c bus interface can wake up the mcu in stop mode or watch mode when its mcu standby mode wakeup function is enabled. pin name normal operation sleep mode stop mode watch mode on reset spl=0 spl=1 spl=0 spl=1 com0 analog output analog output - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input blocked* 2 com1 com2 com3 com4/ seg00 com5/ seg01 com6/ seg02 com7/ seg03 seg04 analog output analog output - previous state kept - input blocked* 2 -hi-z - input blocked* 2 - previous state kept - input blocked* 2 -hi-z - input blocked* 2 -hi-z - input blocked* 2 seg05 seg06 seg07 seg08 seg09 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31
document number: 002-04698 rev. *a page 74 of 110 preliminary mb95610h series for details of the mcu standby mode wakeup function, refer to ?chapter 23 i 2 c bus interface? in ?new 8fx mb95610h series hardware manual?.
document number: 002-04698 rev. *a page 75 of 110 preliminary mb95610h series 18. electrical characteristics 18.1 absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ?? 0.3 v ss ? 6v input voltage* 1 v i v ss ?? 0.3 v ss ? 6v*2 output voltage* 1 v o v ss ?? 0.3 v ss ? 6v*2 maximum clamp current i clamp ? 2 ? 2 ma applicable to specific pins* 3 total maximum clamp current ? |i clamp | ? 20 ma applicable to specific pins* 3 ?l? level maximum output current i ol ?15ma ?l? level average current i olav ?4ma average output current = operating current ? operating ratio (1 pin) ?l? level total maximum output current ? i ol ? 100 ma ?l? level total average output current ? i olav ?50ma total average output current = operating current ? operating ratio (total number of pins) ?h? level maximum output current i oh ? ? 15 ma ?h? level average current i ohav ? ? 4ma average output current = operating current ? operating ratio (1 pin) ?h? level total maximum output current ? i oh ? ? 100 ma ?h? level total average output current ? i ohav ? ? 50 ma total average output current = operating current ? operating ratio (total number of pins) power consumption p d ? 320 mw operating temperature t a ? 40 ? 85 ? c storage temperature t stg ? 55 ? 150 ? c
document number: 002-04698 rev. *a page 76 of 110 preliminary mb95610h series (continued) *1: these parameters are based on the condition that v ss is 0.0 v. *2: v 1 and v 0 must not exceed v cc ? 0.3 v. v 1 must not exceed the rated voltage. however, if the maximum current to/from an input is limited by means of an external component, the i clamp rating is used instead of the v i rating *3: specific pins: p00 to p07, p12 to p15, p20 to p27, p30 to p37, p50 to p52, p90 to p94 ? use under recommended operating conditions. ? use with dc voltage (current). ? the hv (high voltage) signal is an input signal exceeding the v cc voltage. always connect a limiting resistor between the hv (high voltage) signal and the microcontroller before applying the hv (high voltage) signal. ? the value of the limiting resistor should be set to a value at which the current to be input to the microcontroller pin when t he hv (high voltage) signal is input is below the standard value, irre spective of whether the current is transient current or station ary current. ? when the microcontroller drive current is low, such as in low power consumption modes, the hv (high voltage) input potential may pass through the protective diode to increase the potential of the v cc pin, affecting other devices. ? if the hv (high voltage) signal is input when the microcontrolle r power supply is off (not fixed at 0 v), since power is suppl ied from the pins, incomplete operations may be executed. ? if the hv (high voltage) input is input after power-on, since po wer is supplied from the pins, the voltage of power supply may not be sufficient to enable a power-on reset. ? do not leave the hv (high voltage) input pin unconnected. ? example of a recommended circuit: warning: semiconductor devices may be permanently dam aged by application of stress (including, without limitation, voltage, current or temperature) in excess of absolute maximum ratings. do not exceed any of these ratings. hv(high voltage) input (0 v to 16 v) protective diode v cc n-ch p-ch r limiting resistor ? input/output equivalent circuit
document number: 002-04698 rev. *a page 77 of 110 preliminary mb95610h series 18.2 recommended operating conditions (v ss = 0.0 v) *1: the minimum power supply voltage becomes 2.88 v when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. *2: use a ceramic capacitor or a capaci tor with equivalent frequency characteristics. the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . for the connection to a decoupling capacitor c s , see the diagram below. to prevent the device from unintentionally entering an un known mode due to noise, minimize the distance between the c pin and c s and the distance between c s and the v ss pin when designing the layout of a printed circuit board. warning: the recommended operating conditi ons are required in order to ensure th e normal operation of the semiconductor device. all of the device 's electrical characteristics are warranted when the device is operated under these conditions. any use of semiconductor devices will be under their recommended operating condition. operation under any conditions other than these conditions may adversely affect reliability of device and could result in device failure. no warranty is made with respect to any use, operating condit ions or combinations not repr esented on this data sheet. if you are considering application under any conditions other than listed herein, please contact sales representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 2.4* 1 5.5 v in normal operation 2.3 5.5 v hold condition in stop mode decoupling capacitor c s 0.022 1 f *2 operating temperature t a ? 40 ? 85 ? c not in on-chip debug mode ? 5 ? 35 in on-chip debug mode c cs dbg * rst ? dbg / rst / c pins connection diagram *: connect the dbg pin to an external pull-up resistor of 2 k ? or above. after power-on, ensure that the dbg pin does not stay at ?l? level until the rese t output is released. the dbg pin becomes a com- munication pin in debug mode. since the actual pull-up resistance depends on the tool used and the interconnection length, refer to the tool document when selecting a pull-up resistor.
document number: 002-04698 rev. *a page 78 of 110 preliminary mb95610h series 18.3 dc characteristics (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ihi p15, p23, p26, p27 ? 0.7 v cc ?v cc ? 0.3 v hysteresis input v ihs p00 to p07, p12 to p14, p20 to p22, p24, p25, p30 to p37, p50 to p52, p90 to p94, pf0 to pf2, pg1, pg2 ?0.8 v cc ?v cc ? 0.3 v hysteresis input ?l? level input voltage v ili p15, p23, p26, p27 ? v ss ?? 0.3 ? 0.3 v cc v hysteresis input v ils p00 to p07, p12 to p14, p20 to p22, p24, p25, p30 to p37, p50 to p52, p90 to p94, pf0 to pf2, pg1, pg2, ?v ss ?? 0.3 ? 0.2 v cc v hysteresis input open-drain output application voltage v d p12, pf2 ? v ss ?? 0.3 ? vss ? 5.5 v ?h? level output voltage v oh p00 to p07, p13 to p15, p20 to p27, p30 to p37, p50 to p52, p90 to p94, pf0, pf1, pg1, pg2 i oh = ? 4 ma v cc ?? 0.5 ? ? v ?l? level output voltage v ol p00 to p07, p12 to p15, p20 to p27, p30 to p37, p50 to p52, p90 to p94, pf0 to pf2, pg1, pg2 i ol = 4 ma ? ? 0.4 v
document number: 002-04698 rev. *a page 79 of 110 preliminary mb95610h series (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max input leak current (hi-z output leak current) i li p00 to p07, p12 to p15, p20 to p27, p30 to p37, p50 to p52, p90 to p94, pf0 to pf2 pg1, pg2 0.0 v < v i < v cc ? 5? ? 5a when the internal pull-up resistor is disabled internal pull-up resistor r pull p13 to p15, p50 to p52, pg1, pg2* 1 v i = 0 v 25 50 100 k ? when the internal pull-up resistor is enabled input capacitance c in other than v cc and v ss f = 1 mhz ? 5 15 pf power supply current* 1 i cc v cc (external clock operation) f ch = 32 mhz f mp = 16 mhz main clock mode (divided by 2) ?4.55.8ma except during flash memory programming and erasing ? 10.0 13.8 ma during flash memory programming and erasing ? 6.3 9.1 ma at a/d conversion i ccs f ch = 32 mhz f mp = 16 mhz main sleep mode (divided by 2) ?2.03.0ma i ccl f cl = 32 khz f mpl = 16 khz subclock mode (divided by 2) t a = ? 25 c ?60100a i ccls * 2 f cl = 32 khz f mpl = 16 khz subsleep mode (divided by 2) t a = ? 25 c ?1015a i cct * 2 f cl = 32 khz watch mode main stop mode t a = ? 25 c ?813 a
document number: 002-04698 rev. *a page 80 of 110 preliminary mb95610h series (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c ) (continued) parameter symbol pin name condition value unit remarks min typ max power supply current* 1 i ccmpll v cc f mcrpll = 16 mhz f mp = 16 mhz main cr pll clock mode (multiplied by 4) t a = ? 25 c ?5.56.8ma i ccmcr f crh = 4 mhz f mp = 4 mhz main cr clock mode ?1.42.0ma i ccscr sub-cr clock mode (divided by 2) t a = ? 25 c ? 70 150 a i ccts v cc (external clock operation) f ch = 32 mhz time-base timer mode t a = ? 25 c ? 360 410 a i cch substop mode t a = ? 25 c ?711a i lvd v cc current consumption of the low-voltage detection reset circuit ?4 7a the low-voltage detection reset circuit operates only in on-chip debug mode. i crh current consumption of the main cr oscillator ? 240 320 a i crl current consumption of the sub-cr oscillator oscillating at 100 khz ?720a i nstby current consumption difference between normal standby mode and deep standby mode t a = ? 25 c ?2030a
document number: 002-04698 rev. *a page 81 of 110 preliminary mb95610h series (continued) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 ? c to ? 85 c) *1: ? the power supply current is determined by the external clo ck. when the low-voltage detectio n reset circuit is selected, the power supply current is the sum of adding the current cons umption of the low-voltage detection reset circuit (i lvd ) to one of the values from i cc to i cch . when both the low-voltage detection reset circuit a nd a cr oscillator are selected, the power supply current is the sum of adding up the cu rrent consumption of the low-voltage detection reset circuit (i lvd ), the current consumption of the cr oscillator (i crh or i crl ) and one of the values from i cc to i cch . in on-chip debug mode, the main cr oscillator (i crh ) and the low-voltage detection reset circuit are always in operati on, and current consumption therefore increases accordingly. ? see ?4. ac characteristics (1) clock timing? for f ch , f cl , f crh and f mcrpll . ? see ?4. ac characteristics (2) source clock/machine clock? for f mp and f mpl . ? the power supply current value in standby mode is measured in deep standby mode. the current consumption in normal stand- by is higher than that in deep standby mode. the power supply current value in normal standby can be found by adding the current consumption difference between normal standby mode and deep standby mode (i nstby ) to the power supply current value in deep standby mode. for details of normal standby and deep standby mode, refer to ?chapter 3 clock control- ler? in ?new 8fx mb95610h series hardware manual?. *2: in sub-cr clock mode, the power supply current is the sum of adding i ccls or i cct to i crh . parameter symbol pin name condition value unit remarks min typ max lcd internal division resistance r lcd ? between v4 and v ss ?20?k ? 1/2 bias, 10 k ? resistor ? 200 ? k ? 1/2 bias, 100 k ? resistor ?40?k ? 1/4 bias, 10 k ? resistor ? 400 ? k ? 1/4 bias, 100 k ? resistor com0 to com7 output impedance r vcom com0 to com7 v1 to v4 = 4.1 v ?? 5k ? seg00 to seg51 output impedance r vseg seg00 to seg51 ? ? 7 k ? lcd leakage current i lcdl v0 to v4, com0 to com7, seg00 to seg51 ? ? 1? ? 1k ?
document number: 002-04698 rev. *a page 82 of 110 preliminary mb95610h series 18.4 ac characteristics 18.4.1 clock timing (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 1 ? 16.25 mhz when the main oscillation circuit is used x0 x1: open 1 ? 12 mhz when the main external clock is used x0, x1 * 1 ? 32.5 mhz x0, x1 ? 4 ? 8.13 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 2 4?6.5mhz operating conditions ? the main clock is used. ? pll multiplication rate: 2.5 4 ? 5.41 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 3 4 ? 4.06 mhz operating conditions ? the main clock is used. ? pll multiplication rate: 4 f crh ?? 3.92 4 4.08 mhz operating conditions ? the main cr clock is used. ?0 ? c ?? t a ??? 70 ? c 3.9 4 4.1 mhz operating conditions ? the main cr clock is used. ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c
document number: 002-04698 rev. *a page 83 of 110 preliminary mb95610h series (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max clock frequency f mcrpll ?? 7.84 8 8.16 mhz operating conditions ? pll multiplication rate: 2 ?0 ? c ?? t a ??? 70 ? c 7.6 8 8.4 mhz operating conditions ? pll multiplication rate: 2 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 9.8 10 10.2 mhz operating conditions ? pll multiplication rate: 2.5 ?0 ? c ?? t a ??? 70 ? c 9.5 10 10.5 mhz operating conditions ? pll multiplication rate: 2.5 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 11.76 12 12.24 mhz operating conditions ? pll multiplication rate: 3 ?0 ? c ?? t a ??? 70 ? c 11.4 12 12.6 mhz operating conditions ? pll multiplication rate: 3 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c 15.68 16 16.32 mhz operating conditions ? pll multiplication rate: 4 ?0 ? c ?? t a ??? 70 ? c 15.2 16 16.8 mhz operating conditions ? pll multiplication rate: 4 ? ? 40 ? c ? t a ? 0 ? c, ? 70 ? c ? t a ? ? 85 ? c f cl x0a, x1a ? ? 32.768 ? khz when the suboscillation circuit is used ? 32.768 ? khz when the sub-external clock is used f crl ? ? 50 100 150 khz when the sub-cr clock is used
document number: 002-04698 rev. *a page 84 of 110 preliminary mb95610h series (continued) (v cc = 2.4 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: the external clock signal is input to x0 and the inverted external clock signal to x1. parameter symbol pin name condition value unit remarks min typ max clock cycle time t hcyl x0, x1 ? 61.5 ? 1000 ns when the main oscillation circuit is used x0 x1: open 83.4 ? 1000 ns when an external clock is used x0, x1 * 30.8 ? 1000 ns t lcyl x0a, x1a ? ? 30.5 ? s when the subclock is used input clock pulse width t wh1 , t wl1 x0 x1: open 33.4 ? ? ns when an external clock is used, the duty ratio should range between 40% and 60%. x0, x1 * 14.4 15.2 ? ns t wh2 , t wl2 x0a ? ? 30.5 ? s input clock rising time and falling time t cr , t cf x0, x0a x1: open ? ? 5 ns when an external clock is used x0, x1, x0a, x1a *??5ns cr oscillation start time t crhwk ? ? ? ? 50 s when the main cr clock is used t crlwk ? ? ? ? 30 s when the sub-cr clock is used pll oscillation start time t mcrpllw k ? ? ? ? 100 s when the main cr pll clock is used
document number: 002-04698 rev. *a page 85 of 110 preliminary mb95610h series x0, x1 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh1 t wl1 0.2 v cc t hcyl t cr t cf ? input waveform generated when an external clock (main clock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0 x1 x0 x1 f ch f ch when an external clock is used (x1 is open) x0 x1 open f ch ? figure of main clock inpu t port external connection x0a 0.8 v cc 0.2 v cc 0.2 v cc 0.8 v cc t wh2 t wl2 0.2 v cc t lcyl t cr t cf ? input waveform generated when an external clock (subclock) is used when a crystal oscillator or a ceramic oscillator is used when an external cloc k is used x0a x1a x0a x1a open f cl f cl ? figure of subclock input port external connection
document number: 002-04698 rev. *a page 86 of 110 preliminary mb95610h series t crhwk 1/f crh main cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr clock) is used
document number: 002-04698 rev. *a page 87 of 110 preliminary mb95610h series t crlwk 1/f crl sub-cr clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (sub-cr clock) is used t mcrpllwk 1/f mcrpll main cr pll clock oscillation starts oscillation stabilizes ? input waveform generated when an internal clock (main cr pll clock) is used
document number: 002-04698 rev. *a page 88 of 110 preliminary mb95610h series 18.4.2 source clock/machine clock (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: this is the clock before it is divided according to the division ratio set by the machine clock division ratio select bits (sycc:div[1:0]). this source clock is divided to become a machin e clock according to the division ratio set by the machine cloc k division ratio select bits (sycc:di v[1:0]). in addition, a source clock can be selected from the following. ? main clock divided by 2 ? main cr clock ? pll multiplication of main clock or main cr clock (select a multiplication rate from 2, 2.5, 3 and 4.) ? subclock divided by 2 ? sub-cr clock divided by 2 *2: this is the operating clock of the microcontroller. a machine clock can be selected from the following. ? source clock (no division) ? source clock divided by 4 ? source clock divided by 8 ? source clock divided by 16 parameter symbol pin name value unit remarks min typ max source clock cycle time* 1 t sclk ? 61.5 ? 2000 ns when the main external clock is used min: f ch = 32.5 mhz, divided by 2 max: f ch = 1 mhz, divided by 2 62.5 ? 1000 ns when the main cr clock is used min: f crh = 4 mhz, multiplied by 4 max: f crh = 4 mhz, divided by 4 ?61?s when the suboscillation clock is used f cl = 32.768 khz, divided by 2 ?20?s when the sub-cr clock is used f crl = 100 khz, divided by 2 source clock frequency f sp ? 0.5 ? 16.25 mhz when the main oscillation clock is used ? 4 12.5 mhz when the main cr clock is used f spl ? 16.384 ? khz when the suboscillation clock is used ? 50 ? khz when the sub-cr clock is used f crl = 100 khz, divided by 2 machine clock cycle time* 2 (minimum instruction execution time) t mclk ? 61.5 ? 32000 ns when the main oscillation clock is used min: f sp = 16.25 mhz, no division max: f sp = 0.5 mhz, divided by 16 250 ? 4000 ns when the main cr clock is used min: f sp = 4 mhz, no division max: f sp = 4 mhz, divided by 16 61 ? 976.5 s when the suboscillation clock is used min: f spl = 16.384 khz, no division max: f spl = 16.384 khz, divided by 16 20 ? 320 s when the sub-cr clock is used min: f spl = 50 khz, no division max: f spl = 50 khz, divided by 16 machine clock frequency f mp ? 0.031 ? 16.25 mhz when the main oscillation clock is used 0.25 ? 16 mhz when the main cr clock is used f mpl 1.024 ? 16.384 khz when the suboscillation clock is used 3.125 ? 50 khz when the sub-cr clock is used f crl = 100 khz
document number: 002-04698 rev. *a page 89 of 110 preliminary mb95610h series f ch (main oscillation clock) divided by 2 divided by 2 divided by 2 f mcrpll (main pll clock, main cr pll clock) f crh (main cr clock) f cl (suboscillation clock) f crl (sub-cr clock) sclk (source clock) mclk (machine clock) machine clock divide ratio select bits (sycc:div[1:0]) clock mode select bits (sycc:scs[2:0]) division circuit 1 1/4 1/8 1/16 ? schematic diagram of the clock generation block operating voltage (v) a/d converter operation range 5.5 5.0 4.0 3.5 3.0 2.7 2.4 16 khz 3 mhz 10 mhz 16.25 mhz source clock frequency (f sp /f spl ) ? operating voltage - operating frequency (t a = ? 40 c to ? 85 c)
document number: 002-04698 rev. *a page 90 of 110 preliminary mb95610h series 18.4.3 external reset (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c ) *: see ?source clock/machine clock? for t mclk . parameter symbol value unit remarks min max rst ?l? level pulse width t rstl 2 t mclk *?ns 0.2 v cc rst 0.2 v cc t rstl
document number: 002-04698 rev. *a page 91 of 110 preliminary mb95610h series 18.4.4 power-on reset (v ss = 0.0 v, t a = ? 40 c to ? 85 c ) note: a sudden change of power supply voltage may activate the power-on reset function. when changing the power supply voltage during the operation, set the slope of rising to a value below within 30 mv/ms as shown below. 18.4.5 peripheral input timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?source clock/machine clock? for t mclk . parameter symbol condition value unit remarks min max power supply rising time t r ?? 50 ms power supply cutoff time t off ? 1 ? ms wait time until power-on parameter symbol pin name value unit min max peripheral input ?h? pulse width t ilih int00 to int07, ec0, ec1, adtg, ti0 2 t mclk * ? ns peripheral input ?l? pulse width t ihil 2 t mclk * ? ns 0.2 v 0.2 v t off t r 2.5 v 0.2 v v cc v cc 2.3 v v ss hold condition in stop mode set the slope of rising to a value below 30 mv/ms. int00 to int07, ec0, ec1, adtg, ti0 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ilih t ihil
document number: 002-04698 rev. *a page 92 of 110 preliminary mb95610h series 18.4.6 low-voltage detection (v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: the release voltage and the detection voltage can be selected by using the lvd reset voltage selection id register (lvdr) in the low-voltage detection reset ci rcuit. for details of the lvdr register, refe r to ?chapter 16 low-voltage detection reset circuit? in ?new 8fx mb95610h series hardware manual?. (continued) parameter symbol value unit remarks min typ max release voltage* v dl ? 2.52 2.7 2.88 v at power supply rise 2.61 2.8 2.99 2.89 3.1 3.31 3.08 3.3 3.52 detection voltage* v dl ? 2.43 2.6 2.77 v at power supply fall 2.52 2.7 2.88 2.80 3 3.20 2.99 3.2 3.41 hysteresis width v hys ??100mv power supply start voltage v off ??2.3v power supply end voltage v on 4.9 ? ? v power supply voltage change time (at power supply rise) t r 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl+ ) power supply voltage change time (at power supply fall) t f 650 ? ? s slope of power supply that the reset release signal generates within the rating (v dl- ) reset release delay time t d1 ??30s reset detection delay time t d2 ??30s lvd reset threshold voltage transition stabilization time t stb 10 ? ? s
document number: 002-04698 rev. *a page 93 of 110 preliminary mb95610h series (continued) v hys t d2 t d1 t r t f v cc v on v off v dl+ v dl- time time internal reset signal
document number: 002-04698 rev. *a page 94 of 110 preliminary mb95610h series 18.4.7 i 2 c bus interface timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: the maximum t hd;dat in the standard-mode is applicable only when the time during which the device is holding the scl signal at ?l? (t low ) does not extend. *3: a fast-mode i 2 c-bus device can be used in a standard-mode i 2 c-bus system, provided that the condition of t su;dat ? 250 ns is fulfilled. parameter symbol pin name condition value unit standard-mod e fast-mode min max min max scl clock frequency f scl scl r = 1.7 k ? , c = 50 pf* 1 0 100 0 400 khz (repeated) start condition hold time sda ??? scl ? t hd;sta scl, sda 4.0 ? 0.6 ? s scl clock ?l? width t low scl 4.7 ? 1.3 ? s scl clock ?h? width t high scl 4.0 ? 0.6 ? s (repeated) start condition setup time scl ??? sda ? t su;sta scl, sda 4.7 ? 0.6 ? s data hold time scl ??? sda ?? t hd;dat scl, sda 0 3.45 *2 00.9 *3 s data setup time sda ???? scl ? t su;dat scl, sda 0.25 ? 0.1 ? s stop condition setup time scl ? ? sda ? t su;sto scl, sda 4 ? 0.6 ? s bus free time between stop condition and start condition t buf scl, sda 4.7 ? 1.3 ? s
document number: 002-04698 rev. *a page 95 of 110 preliminary mb95610h series (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol pin name condition value* 2 unit remarks min max scl clock ?l? width t low scl r = 1.7 k ? , c = 50 pf* 1 (2 ? nm/2)t mclk ? 20 ? ns master mode scl clock ?h? width t high scl (nm/2)t mclk ? 20 (nm/2)t mclk ? 20 ns master mode start condition hold time t hd;sta scl, sda (-1 ? nm/2)t mclk ? 20 (-1 ? nm)t mclk ? 20 ns master mode maximum value is applied when m, n = 1, 8. otherwise, the minimum value is applied. stop condition setup time t su;sto scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode start condition setup time t su;sta scl, sda (1 ? nm/2)t mclk ? 20 (1 ? nm/2)t mclk ? 20 ns master mode bus free time between stop condition and start condition t buf scl, sda (2 nm ? 4) t mclk ? 20 ? ns data hold time t hd;dat scl, sda 3 t mclk ? 20 ? ns master mode data setup time t su;dat scl, sda (-2 ? nm/2) t mclk ? 20 (-1 ? nm/2) t mclk ? 20 ns master mode it is assumed that ?l? of scl is not extended. the minimum value is applied to the first bit of continuous data. otherwise, the maximum value is applied. setup time between clearing interrupt and scl rising t su;int scl (nm/2) t mclk ? 20 (1 ? nm/2) t mclk ? 20 ns the minimum value is applied to the interrupt at the ninth scl ? . the maximum value is applied to the interrupt at the eighth scl ? . scl clock ?l? width t low scl 4 t mclk ? 20 ? ns at reception scl clock ?h? width t high scl 4 t mclk ? 20 ? ns at reception sda scl t wakeup t hd;sta t su;dat f scl t hd;sta t su;sta t low t hd;dat t high t su;sto t buf
document number: 002-04698 rev. *a page 96 of 110 preliminary mb95610h series (continued) (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *1: r represents the pull-up resistor of the scl and sda lines, and c the load capacitor of the scl and sda lines. *2: ? see ?(2) source clock/machine clock? for t mclk . ? m represents the cs[4:3] bits in the i 2 c clock control register ch. 0 (iccr0). ? n represents the cs[2:0] bits in the i 2 c clock contro l register ch. 0 (iccr0). ? the actual timing of the i 2 c bus interface is determined by the values of m and n set by the machine clock (t mclk ) and the cs[4:0] bits in the iccr0 register. ? standard-mode: m and n can be set to values in the following range: 0.9 mhz ? t mclk (machine clock) ? 16.25 mhz. the usable frequencies of the machine clock are dete rmined by the settings of m and n as shown below. (m, n) = (1, 8) : 0.9 mhz < t mclk ? 1 mhz (m, n) = (1, 22), (5, 4), (6, 4), (7, 4), (8, 4) : 0.9 mhz < t mclk ? 2 mhz (m, n) = (1, 38), (5, 8), (6, 8), (7, 8), (8, 8) : 0.9 mhz < t mclk ? 4 mhz (m, n) = (1, 98), (5, 22), (6, 22), (7, 22) : 0.9 mhz < t mclk ? 10 mhz (m, n) = (8, 22) : 0.9 mhz < t mclk ? 16.25 mhz ? fast-mode: m and n can be set to values in the following range: 3.3 mhz < t mclk (machine clock) < 16.25 mhz. the usable frequencies of the machine clock are dete rmined by the settings of m and n as shown below. (m, n) = (1, 8) : 3.3 mhz < t mclk ? 4 mhz (m, n) = (1, 22), (5, 4) : 3.3 mhz < t mclk ? 8 mhz (m, n) = (1, 38), (6, 4), (7, 4), (8, 4) : 3.3 mhz < t mclk ? 10 mhz (m, n) = (5, 8) : 3.3 mhz < t mclk ? 16.25 mhz parameter symbol pin name condition value* 2 unit remarks min max start condition detection t hd;sta scl, sda r = 1.7 k ? , c = 50 pf* 1 2 t mclk ? 20 ? ns no start condition is detected when 1 t mclk is used at reception. stop condition detection t su;sto scl, sda 2 t mclk ? 20 ? ns no stop condition is detected when 1 t mclk is used at reception. restart condition detection condition t su;sta scl, sda 2 t mclk ? 20 ? ns no restart condition is detected when 1 t mclk is used at reception. bus free time t buf scl, sda 2 t mclk ? 20 ? ns at reception data hold time t hd;dat scl, sda 2 t mclk ? 20 ? ns at slave transmission mode data setup time t su;dat scl, sda t low ? 3 t mclk ? 20 ? ns at slave transmission mode data hold time t hd;dat scl, sda 0 ? ns at reception data setup time t su;dat scl, sda t mclk ? 20 ? ns at reception sda ? ? scl ? (with wakeup function in use) t wakeup scl, sda oscillation stabi lization wait time ? 2 t mclk ? 20 ?ns
document number: 002-04698 rev. *a page 97 of 110 preliminary mb95610h series 18.4.8 uart/sio, serial i/o timing (v cc = 5.0 v ? 10%, v ss = 0.0 v, t a = ? 40 c to ? 85 c) *: see ?source clock/machine clock? for t mclk . parameter symbol pin name condition value unit min max serial clock cycle time t scyc uck0, uck1 internal clock operation: c l = 80 pf + 1 ttl 4 t mclk *? ns uck ??? uo time t slov uck0, uck1, uo0, uo1 ? 190 ? 190 ns valid ui ? uck ? t ivsh uck0, uck1, ui0, ui1 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, uck1, ui0, ui1 2 t mclk *? ns serial clock ?h? pulse width t shsl uck0, uck1 external clock operation: c l = 80 pf + 1 ttl 4 t mclk *? ns serial clock ?l? pulse width t slsh uck0, uck1 4 t mclk *? ns uck ??? uo time t slov uck0, uck1, uo0, uo1 ? 190 ns valid ui ? uck ? t ivsh uck0, uck1, ui0, ui1 2 t mclk *? ns uck ??? valid ui hold time t shix uck0, uck1, ui0, ui1 2 t mclk *? ns 0.2 v cc 0.2 v cc 0.8 v cc t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0, uck1 uo0, uo1 ui0, ui1 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc t scyc ? internal shift clock mode
document number: 002-04698 rev. *a page 98 of 110 preliminary mb95610h series t slov t ivsh t shix 0.8 v cc 0.2 v cc uck0, uck1 uo0, uo1 ui0, ui1 0.7 v cc 0.3 v cc 0.7 v cc 0.3 v cc 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slsh t shsl ? external shift clock mode
document number: 002-04698 rev. *a page 99 of 110 preliminary mb95610h series 18.5 a/d converter 18.5.1 a/d converter electrical characteristics (v cc = 2.7 v to 5.5 v, v ss = 0.0 v, t a = ? 40 c to ? 85 c) parameter symbol value unit remarks min typ max resolution ? ? ? 10 bit to ta l e r r o r ? 3? ? 3lsb linearity error ? 2.5 ? ? 2.5 lsb differential linearity error ? 1.9 ? ? 1.9 lsb zero transition voltage v 0t v ss ?? 7.2 lsb v ss ? 0.5 lsb v ss ? 8.2 lsb v full-scale transition voltage v fst v cc ?? 6.2 lsb v cc ?? 1.5 lsb v cc ? 9.2 lsb v compare time ? 3 ? 10 s 2.7 v ? v cc ? 5.5 v sampling time ? 0.941 ? ? s 2.7 v ? v cc ? 5.5 v, with external impedance ? 3.3 k ? and external capacitance = 10 pf analog input current i ain ? 0.3 ? ? 0.3 a analog input voltage v ain v ss ?v cc v
document number: 002-04698 rev. *a page 100 of 110 preliminary mb95610h series 18.5.2 notes on using a/d converter external impedance of analog input and its sampling time the a/d converter of the mb95610h series has a sample and hold ci rcuit. if the external impedance is too high to keep sufficien t sampling time, the analog voltage charged to the capacitor of the internal sample and hold circuit is insufficient, adversely a ffecting a/d conversion precision. therefore, to sa tisfy the a/d conversion precision standard, considering the relationship between the external impedance and minimum sampling time, either adjust th e register value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum va lue. in addition, if sufficient sampling time cannot be secure d, connect a capacitor of about 0.1 f to the analog input pin. note: the values are reference values. 4.5 v v cc 5.5 v 2.7 v v cc < 4.5 v 1.45 k (max) 2.7 k (max) 14.89 pf (max) v cc r c 14.89 pf (max) comparator analog input during sampling: on r c ? analog input equivalent circuit
document number: 002-04698 rev. *a page 101 of 110 preliminary mb95610h series a/d conversion error as |v cc ? v ss | decreases, the a/d conversion error increases proportionately. [external impedance = 0 k to 100 k ] external impedance [k ] minimum sampling time [ s] 02468101214161820 100 80 60 40 20 0 [external impedance = 0 k to 20 k ] external impedance [k ] minimum sampling time [ s] 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 20 15 10 5 0 note: external capacitance = 10 pf ? relationship between external impedance and minimum sampling time
document number: 002-04698 rev. *a page 102 of 110 preliminary mb95610h series 18.5.3 definitions of a/d converter terms ? resolution it indicates the level of analog variation that can be distinguished by the a/d converter. when the number of bits is 10, analog voltage can be divided into 2 10 = 1024. ? linearity error (unit: lsb) it indicates how much an actual conversion value deviates from the straight line connecting t he zero transition point (?0000000 000? ? ? ?0000000001?) of a device to the full-scale transition point (?1111111111? ? ? ?1111111110?) of the same device. ? differential linear error (unit: lsb) it indicates how much the input voltage required to chan ge the output code by 1 lsb deviates from an ideal value. ? total error (unit: lsb) it indicates the difference between an actual value and a theoretical value. the error can be caused by a zero transition error , a full-scale transition errors, a linearity error, a quantum error, or noise. (continued) v fst ideal i/o characteristics 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output digital output 2 lsb v 0t 1 lsb 0.5 lsb total error analog input analog input 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff actual conversion characteristic ideal characteristic actual conversion characteristic n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n - 1) to 0xn {1 lsb (n - 1) + 0.5 lsb} v nt total error of digital output n v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] = v cc - v ss 1024 (v) 1 lsb = v ss v cc v ss v cc
document number: 002-04698 rev. *a page 103 of 110 preliminary mb95610h series (continued) zero transition error linearity error full-scale transition error 0x001 0x002 0x003 0x004 0x3fd 0x3fe 0x3ff digital output differential linearity error of digital output n v (n+1)t - v nt 1 lsb - 1 = linearity error of digital output n v nt - {1 lsb n + v 0t } 1 lsb = digital output analog input 0x001 0x002 0x3fc 0x3fd 0x003 0x3fe 0x3ff 0x004 actual conversion characteristic actual conversion characteristic v 0t (measurement value) actual conversion characteristic actual conversion characteristic v fst (measurement value) v ss v cc v ss v cc v ss v cc v ss v cc analog input digital output analog input ideal characteristic {1 lsb n + v 0t } actual conversion characteristic ideal characteristic actual conversion characteristic v 0t (measurement value) v fst (measurement value) v nt differential linearity error 0x(n-2) 0x(n-1) 0xn 0x(n+1) digital output analog input actual conversion characteristic ideal characteristic v nt actual conversion characteristic v (n+1)t n v nt : a/d converter digital output value : voltage at which the digital output transits from 0x(n - 1) to 0xn v 0t (ideal value) = v ss + 0.5 lsb [v] v fst (ideal value) = v cc - 2 lsb [v] ideal characteristic
document number: 002-04698 rev. *a page 104 of 110 preliminary mb95610h series 18.6 flash memory program/erase characteristics *1: v cc = 5.5 v, t a = ? 25 c, 0 cycle *2: v cc = 2.4 v, t a = ? 85 c, 100000 cycles *3: these values were converted from the result of a technol ogy reliability assessment. (these values were converted from the re sult of a high temperature accelerated test using the a rrhenius equation with the average temperature being ? 85 c.) parameter value unit remarks min typ max sector erase time (2 kbyte sector) ?0.3* 1 1.6* 2 s the time of writing ?0x00? prior to erasure is excluded. sector erase time (32 kbyte sector) ?0.6* 1 3.1* 2 s the time of writing ?0x00? prior to erasure is excluded. byte writing time ? 17 272 s syst em-level overhead is excluded. program/erase cycle 100000 ? ? cycle power supply voltage at program/erase 2.4 ? 5.5 v flash memory data retention time 20* 3 ?? year average t a = ? 85 c number of program/erase cycles: 1000 or below 10* 3 ?? average t a = ? 85 c number of program/erase cy cles: 1001 to 10000 inclusive 5* 3 ?? average t a = ? 85 c number of program/erase cycles: 10001 or above
document number: 002-04698 rev. *a page 105 of 110 preliminary mb95610h series 19. mask options no. part number mb95f613h mb95f614h mb95f616h mb95f613k mb95f614k mb95f616k selectable/fixed fixed 1 low-voltage detection reset without low-voltage detection reset with low-voltage detection reset 2 reset with dedicated reset input without dedicated reset input
document number: 002-04698 rev. *a page 106 of 110 preliminary mb95610h series 20. ordering information part number package mb95f613hpmc-g-sne2 mb95f613kpmc-g-sne2 MB95F614HPMC-G-SNE2 mb95f614kpmc-g-sne2 mb95f616hpmc-g-sne2 mb95f616kpmc-g-sne2 80-pin plastic lqfp (fpt-80p-m37)
document number: 002-04698 rev. *a page 107 of 110 preliminary mb95610h series 21. package dimension 80-pin plastic lqfp lead pitch 0.50 mm package width package length 12.00 mm 12.00 mm lead shape gullwing lead bend direction normal bend sealing method plastic mold mounting height 1.70 mm max weight 0.47 g 80-pin plastic lqfp (fpt-80p-m37) (fpt-80p-m37) 2009-2010 fujitsu semiconductor limited f80037s-c-1-2 120 40 21 60 41 80 61 index *12.00 0.10(.472 .004)sq 14.00 0.20(.551 .008)sq 0.50(.020) 0.22 0.05 (.009 .002) m 0.08(.003) 0.145 0.055 (.006 .002) 0.08(.003) "a" (stand off) details of "a" part (.004 .002) 0.10 0.05 (.024 .006) 0.60 0.15 (.020 .008) 0.25(.010) 0.50 0.20 (mounting height) .059 ? .004 +.008 ? 0.10 +0.20 1.50 0~8 c dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002-04698 rev. *a page 108 of 110 preliminary mb95610h series 22. major changes spansion publication number: ds702?00017?0v02-e . note: please see ?document history? about later revised information. page section details 19 pin connection ?dbg pin revised details of ?? dbg pin?. ?rst pin revised details of ?? rst pin?. 20 ? c pin corrected the following statement. the decoupling capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . 75 electrical characteristics recommended operating conditions revised remark *1. the minimum value becomes 2.88 v when the low-voltage detection reset is used or in on-chip debug mode. ? the minimum power supply voltage becomes 2.88 v when a product with the low-voltage detection reset is used or when the on-chip debug mode is used. corrected the following statement in remark *2. the decoupling capacitor for the v cc pin must have a capacitance larger than c s . ? the decoupling capacitor for the v cc pin must have a capacitance equal to or larger than the capacitance of c s . revised the remark in ?? dbg/rst /c pins connection diagram?. 77 dc characteristics revised the remark of the parameter ?input leak current (hi-z output leak current)?. when pull-up resistance is disabled ? when the internal pull-up resistor is disabled rename the parameter ?pull-up re sistance? to ?internal pull-up resistor?. revised the remark of the parameter ?internal pull-up resistor?. when pull-up resistance is enabled ? when the internal pull-up resistor is enabled 82 ac characteristics clock timing corrected the pin names of the parameter ?input clock rising time and falling time?. x0 ? x0, x0a x0, x1 ? x0, x1, x0a, x1a
document number: 002-04698 rev. *a page 109 of 110 preliminary mb95610h series document history document title: mb95f613h/f613k/f614h, mb95f614k/f616h/f616k new 8fx mb95610h series 8-bit microcontrollers document number: 002-04698 revision ecn orig. of change submission date description of change ** ? akih 06/14/2013 migrated to cypress and assigned document number 002-04698. no change to document contents or format. *a 5211405 akih 04/08/2016 updated to cypress template
document number: 002-04698 rev. *a revised april 8, 2016 page 110 of 110 preliminary mb95610h series ? cypress semiconductor corporation, 2012-2016. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc ("cypress"). this document, including any software or firmware included or referenced in this document ("software"), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a writte n agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hardware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information provided in this document, including any sample design informat ion or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly desi gn, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear inst allations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("unintended uses"). a crit ical component is any compo nent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in who le or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cy press harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, psoc, capsense, ez-usb, f-ram, and traveo are trademarks or registered trad emarks of cypress in the united states and other countries. for a more complete list of cypre ss trademarks, visit cypress.com. other names and brands may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community forums | projects | video | blogs | training | components technical support cypress.com/support

▲Up To Search▲

Price & Availability of MB95F614HPMC-G-SNE2

	To Download MB95F614HPMC-G-SNE2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .