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phy1040 - ad - 1.0 advance datasheet page 1 125m bps C 1.25 g bps vcsel/laser driver and postamplifier features ? common anode v csel driver output stage with 32ma max modulation drive and 20ma bias current. ? continuous mode laser driver with up to 80ma modulation and 90 ma bias c urrent ? closed or open loop b ias mode with temperature lookup table ? temperature compensated modulation current ? l imiting amp lifier with p rogrammable low pass filter and output swing ? device settings stored in external 2k eeprom applications ? fast ethernet ? gi gabit ethernet ? oc -3 description the phy1040 - 01 is a continuous mode vcsel/laser driver and limiting amplifier for use within fiber optic modules for sfp and sff a pplications. used with the phy109 2- 01 or phy1095 - 01 transimpedance amplifier s and a low cost seri al eeprom or microcontroller it forms a complete sfp module solution. the transmit section integrates a modulator output st age optimised as a laser or vcsel driver in common anode configurations. the bias current can be controlled either by a fast set tling apc loop or in open loop mode which uses a temperature lookup table. the receive r includes a limiting amplifier with programmable bandwidth. a signal detect/loss of s ignal function is implemented using the input signal modulation amplitude with user selectable threshold and hysteresis. operating with a 3.3v supply and rated from - 40 to +9 5c ambient, the phy1040 - 01 is housed in a 32pin, 5x5mm, rohs compliant, qfn package. figure 1 C block diagram figure 2 C device pin out phy1040 - 01 a maxim integrated products brand 19 - 5677; rev 1/11 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 2 content s 1. ordering information ................................................................................................................... 3 2. pin description ............................................................................................................................. 3 3. key specification s ....................................................................................................................... 5 3.1. absolute maximum ratings ................................................................................................ . 5 3.2. continuous ratings ............................................................................................................. 5 3.3. transmitter .......................................................................................................................... 5 3.4. receiver .............................................................................................................................. 8 3.5. 2- wire serial interface ....................................................................................................... 12 4. functional description ............................................................................................................... 14 4.1. overview ........................................................................................................................... 14 4.2. transmitter features .......................................................................................................... 14 4.3. receiver features ............................................................................................................. 21 4.4. laser/vcsel safety features .......................................................................................... 23 4.5. temperature measurement ............................................................................................... 26 5. control interface ........................................................................................................................ 27 5.1. boot sequence .................................................................................................................. 28 5.2. main control loop ............................................................................................................. 30 5.3. 2- wire serial interface ....................................................................................................... 31 6. register map ............................................................................................................................. 33 7. simplified interface mod els ....................................................................................................... 45 8. applications information ............................................................................................................ 47 8.1. power supply connections ............................................................................................... 47 8.2. vcsel/laser connection C dc - coupled .......................................................................... 48 8.3. vcsel/laser connection C ac- coupled .......................................................................... 49 8.4. tx_fault circuit C standalon e mode ................................................................................ 50 9. packaging ................................................................................................................................ . 52 10. contact information ................................................................................................................... 53 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 3 1. ordering information part number descrip tion package phy1040-01qs-re vcsel/laser driver and post amp qfn32, 5mmx5mm in tape and reel 2. pin description pin no name direction type description 1 eeprom _sda i/o lvttl eeprom 2 wire serial interface data, internal 8k pull up 2 vdd_rxo power receiver output power supply 3 vss_rxo ground receiver output ground connection 4 rxoutm o/p cml limiting amplifier serial data output 5 rxoutp o/p cml limiting amplifier serial data output 6 sda i/o lvttl 2-wire serial interface data 7 scl i/o lvttl 2- wir e serial interface clock 8 ic internally connected, this pin must be left open circuit 9 tx_fault o/p lvttl (open collector) laser fail alarm (requires external pull up) 10 tx_disable i/p lvttl laser enable / disable 11 txinp i/p high speed input laser driver serial input, see section 7.0 for interfacing details 12 txinm i/p high speed input laser driver serial input, see section 7.0 for interfacing details 13 vss_ ic internal connection, connect to ground 14 nc no connection 15 nc no connection 16 mpd i/p analog monitor photodiode input 17 lv bias o/p analog laser bias current output 18 lvmode analog select vcsel or laser mode 19 vdd_txo power driver output power supply 20 vss_txo g rou nd driver output ground connection 21 lvoutm o/ p high speed output laser /vcsel driver serial output 22 lvoutp o/p high speed output laser /vcsel driver serial output 23 vss_txo g rou nd driver output ground connection 24 vdd_txo power driver output power supply 25 ic internally connected, this pin must be left open circuit 26 sd/ los o/p lvttl (open collector) signal detect or loss of signal output (requires external pull up ) . polarity selected by user 27 vss_rx ground receiver ground connection downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 4 pin no name direction type description 28 rxinm i/p cml limiting amplifier serial data input 29 rxinp i/p cml limiting amplifier serial data input 30 vss _rx ground receiver ground connection 31 vdd_rx power receiver power supply 32 eeprom _scl o/p lvttl eeprom 2 -wire serial interface clock, internal 8k ? pull up ep vss_ep g roun d common ground / thermal pad downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 5 3. key specifications 3.1. absolute maximum ratings parameter conditions min typ max unit supply voltage -0.5v 6.5 v voltage on any signal pin -0.5 vdd + 0.5v v storage temperature 150 c max junction temperature 140 c max soldering temperature ipc/jedec j- std -020c 260 c esd human body model jesd -22-a114-b 2 kv device not guaranteed to meet specifications, permanent damage may be incurred by operating beyond these limits. 3.2. continuous ratings parameter conditions m in typ max unit operating supply voltage continuous operation 2.97 3.3 3.63 v current consumption excluding bias & modulation current at 20ma bias & 20ma modulation 120 145 ma operating temperature ambient still air -40 25 +9 5 c 3.3. transmitter 3.3.1. transmit ter inputs : txinp /m parameter conditions min typ max unit input voltage vilmin 1.14 v vihmax vdd_tx v input swing vpp(diff) 0.2www.jojwww vpp figure 3 C valid combinations of transmitter input voltages downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 6 3.3.2. vcsel driver parameter conditions min t yp max unit vcsel output compliance range allowable voltage for pins lvoutp/m in dynamic operation 900 vdd_txo mv vcsel bias current output compliance minimum allowed voltage for pin lv_bias, referenced to ground. 600 mv 3.3.3. vcsel b ias adc parameter d escription step size and resolution range vcsel ibias vcsel bias current 0.102ma (+/- 0.05ma) 8 bits 1ma to 26ma 3.3.4. vcsel modulation dac C high range setting parameter description step size and resolution range vcsel imod range of modulation current measured at lvout p/m (jitter within spec), subject to vvcsel_modh and vvcsel_modl levels 2ma < ibias < 32ma = 125 a (62.5 a) 8 bit referencing eeprom lookup table 2ma to 32ma 3.3.5. vcsel modulation dac C low range setting parameter description step size and resol ution range vcsel imod range of modulation current measured at lvout p/m (jitter within spec), subject to vvcsel_modh and vvcsel_modl levels 1ma < ibias < 16ma = 62.7a (31.3a) 8 bit referencing eeprom lookup table 1ma to 16ma 3.3.6. laser driver parameter c onditions min typ max unit maximum laser bias current 90 ma bias generator shutdown current tx_disable active 100 a maximum laser modulation current 80 ma modulation generator shutdown current tx_disable active 100 a electrical 20% to 80% rise / fall time measured using 15 ? ? effective termination, imod = 50ma, ac and dc applications 95 ps total jitter contribution measured over modulation current range 150 muip-p laser output compliance range allowed voltage for laser driver output pins in dynamic operation. 900 vdd_txo mv bias current output compliance minimum allowed voltage for pin bias, referenced to ground 600 mv mpd input sink current for correct apc loop operation 2.6 ma mpd capacitance for correct apc loop operation 20 pf downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 7 3.3.7. laser modulation dac parameter description step size and resolution dac range operational range imod _dac modulation current dac (8 bits) 0.375ma (1 87 a) 0 to 96ma 2ma to 80ma 3.3.8. laser bias adc parameter description step size and resolution dac range operational range ibias_ad c bias current adc (8 bits) 0.588 ma ( 0.294 ma) 0 to 150ma 1ma to 90ma 3.3.9. laser bias dac parameter description step size and reso lution dac range operational range ibias_dac bias current dac (8 bits) 0.392ma (0.196ma) 0 to 100ma 1ma to 90ma 3.3.10. mean power dac parameter description step size and resolution operational range imonset mean power dac (8 bits). mon_dac 31 = 1.042 a ( 0.5 a) 32 mon_dac 127 = 4.167 a (2 a) mon_dac 128 = 16.67a (8a) 0 to 2.55ma downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 8 3.4. receiver 3.4.1. receive limiting amplifier parameter conditions min typ max unit input sensitivity 1.25gbps, prbs 2 7 -1, ber=1 x10 - 12 6 8 mvp -p system sensiti vity 1.25gbps, prbs 2 7 -1, ber=1x10 -12 with phy1095 tia pd responsivity = 0.8a/w, pd capacitance = 0.5pf -32 dbm maximum differential input tj within spec 1200 mvp -p input termination impedance differential 80 100 120 ? input common mode voltage vdd_rx - 1.5 v input l ow frequency cutoff high pass 3db point for rx system 15 khz differential output rise and f all times (20% - 80%) fast slew rate setting, 1250mbps filter setting 100 ps differential output s wing cml_level = 0 cml_level = 1 700 370 900 470 mvp -p total jitter input voltage swing 30mvp-p, k28.5 pattern 200 muip-p output resistance rxout p/m single ended to vdd_rxo 40 50 60 ? output return loss differential, f<2ghz, device powered on 10 db rx 3db frequency 125/155 mbps setting 622 mbps setting 1250 mbps setting 120 470 940 mhz downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 9 3.4.2. oma los parameter symbol conditions min typ max unit oma los assert time t loss_on 100 s oma los de -assert time t loss_off 20 s electrical hysteresis 20log 10 (vdeassert / vassert) high setting low setting 4 3 db oma los assert level set by oma_dac, address d9h 10 50 mv squelch assert time t squelch_on 100 s squelch de-assert time t squelch_off 20 s t loss _ on t squelch _ on t loss _ off t squelch _ off los squelch differential rxin signal figure 4 - oma los detection downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 10 3.4.3. los dac parameter description step size and resolution dac range range oma_ dac oma los dac (8 bits) 250 v (125 v) 0 to 64mv 10mv to 50mv 3.4.4. fault timing parameter symbol condition min typ max unit time to initialize t init from power on or application of vdd>2.97v during plug in 300 ms hard tx_disable assert time t off time from rising edge of tx_disable to when the optical output falls below 10% of nominal 5.5 s hard tx_disable negate time t on time from falling edge of tx_disable to when the modulated optical output rises above 90% of nominal 1 ms hard tx_fault assert time t fault time from fault to tx_fault on bias/temperature adc outside safe range see section 8.4 for sfp/msa compliant timing circuit. 10 ms all other fault conditions. see section 8.4 for sfp/msa compliant timing circuit. 100 s tx_disable pulse width t reset time tx_disable must be held high to reset tx_fault 5 s tx_fault deassert time t faultdass time to deassert tx_fault after tx_disable 300 ms tx _ fault vdd >2. 97 tx _ disable bias t init t off t on figure 5 - device turn on downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 11 tx _ fault tx _ disable laser transmitting t fault occurrence of fault t reset t faultdass figure 6 - fa ult detection 3.4.5. eye safety internal fixed limits parameter symbol comment min ty p max unit high supply voltage assert limit v eyeh a applies to vdd_txo or vdd_tx 4.0 4.15 4.3 v high supply voltage de-assert limit v eyeh d 3.7 3.85 4.0 v low supply voltage assert limit v eyel a 2.45 2.6 2.75 v low supply voltage de-assert limit v eyel d 2.7 2.8 2.95 v high supply hysteresis - 0.1 v low supply hysteresis 0.1 v downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 12 3.5. 2- wire serial interface 3.5.1. ac electrical characteristics parameter symbol comment min typ max unit scl clock frequency f scl 0 100 khz low period of the scl clock t low 4.7 s high period of the scl clock t high 4.0 s set-up time for a repeated start condition t su:sta 4.7 s hold time (repeated) start condition t hd:sta 4.0 s data hold time t hd:dat 0 3.45 s data set-up time t su:dat 250 ns rise time of both sda and scl signals t r 1000 ns fall time of both sda and scl signals t f 300 ns set-up time for stop condition t su:sto 4.0 s bus free time between a stop and start condition t buf 4.7 s output fall time from v ihmin to v ilmax t of 10pf < c b (1 ) < 400pf 0 250 ns capacitance for each i/o pin c i 10 pf 1: c b = capacitance of a single bus line in pf. t hd : sta t su : sta t high t low t su : dat t hd : dat t r t f t su : sto t buf sda scl figure 7 - sda and scl bus timing downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 13 3.5.2. dc electrical characteristics parameter symbol comment min typ max unit low level input voltage v il -0.5 0.3vdd v high level input voltage v ih 0.7vdd vdd+0.5 v low level o/p voltage v ol 3 ma sink current 0 0.4 v i/p current each i/o pin i i 0.1v dd < v i < 0.9v dd -10 10 ma 3.5.3. lvttl i/o p ins 1 parameter comment min typ max unit lvttl voltage out high external 4.7k to 10k pullup 2.4 v lvttl voltage out low external 4.7k to 10k pullup 0.4 v lvttl voltage i n high internal pullup 2.0 vdd C 0.2 v lvttl voltage in low internal pullup 0 0.8 v internal pull-up resistance tx_disable, eeprom_sda, eeprom_scl 6 10 k ? 1 applies to lvttl pins specified on pages 3-4 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 14 4. functional description 4.1. overview figure 8 - phy1040 - 01 functional overview 4.2. transmitter features the transmitter input buffer provides the necessary drive to the vcsel/laser driver output stage. it includes an internal high impedance bias network and is designed to be dc or ac - coupled. for high frequency applications an external termination network must be implemente d. the vcsel/laser driver output is designed to drive vcsel/laser s in the common anode configuration using either ac - or dc - coupling. the laser driver circuit delivers a maximum peak to peak modulation current of 80ma measur ed at the device output pin l voutp . the vcsel driver output stage provides 30ma max modulation drive and 20ma bias current. by default the transmitter is non - inverting; however, to simplify the pcb layout of differential signals the polarity of the data can be inverted by setting tx_polarity (cah, t x_ dbuff , bit 0) to 1. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 15 4.2.1. lvmode vcsel or laser mode for phy1040 is selectable by connecting the lvmode pin high (laser) or low (vcsel). lvmode (ech, lvmode, bit 5) can be used to identify the logi cal level at this pin . 4.2.2. modulation current control figure 9 - modula tion current generation the modulation current can be either set by a constant register value or controlled by a temperature indexed look - up table (lut). if mod_temp_disable is set to 1 (d0h, tx_biasloop_control, bit 7) then the modulation dac is set directly from a register (d4h, mod_dac). if mod_temp_disable is set to 0 then a 64 byte lut is used to set the modulation dac. the lut is indexed by the temperature adc (e1h, temp_adc_value), where the index is given by: index = (temperature adc x 64)/255 . the values of the lut reside in the eeprom, between addresses 80h (lowest temperature entry) and bfh (highest temperature entry), and are transferred at start up to on - chip registers. the active setting for the modulation dac can be observed by reading mod_dac_observe (f0h). downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 16 4.2.3. bias current control mpd bias ibias dac digital contr ol m ean power dac bias lookup table 01 mon _ dac d5h bias _ dac d8h bias _ temp _ disable bit 6 tx _ biasloop _ control d0h 10 openloop bit 4 tx _ biasloop cch e2h bias _ adc _ value bias driver ibias adc efh bias _ dac _ observe comp kfactor imonset vdd figure 1 0 - bias current generation the phy1040 - 01 can operate with open or closed loop bias control. in either mode the current setti ng for the bias dac can be observed by reading bias_dac_observe (ef h). the actual bias current is measured using an on - chip adc and can be observed by reading bias_adc_value (e2h). in vcsel mode a high (32ma) or low (16ma) bias dac range can be selected using vmodresolution (cah, vmodresolution, bit 1). 4.2.4. open loop if op enloop is set to 1 (cch, tx_biasloop, bit 4) the bias generator operat es in open loop mode. the bias current can be either set by a constant register value or controlled by a temperature indexed lookup table (lut). if bias_temp_disable is set to 1 (d0 h, tx_biasloop_control, bit 6) then the bias dac is set directly from a register (d8h, bias_dac). if bias_temp_disable is set to 0 then a 128 byte lut is used to set the bias dac. the lut is indexed by the temperature adc (e1h), where the index is given by: index = (temperature adc x 128)/255. the values for the lut reside in the eeprom, between addresses 00h (lowest t emperature entry) and 7fh (highest temperature entry), and are loaded into on - chip registers at start up. in open loop mode the mpd device pin is not used and can be left unconnected. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 17 mpd bias ibias dac bias lookup table 01 bias _ dac d8h bias _ temp _ disable bit 6 tx _ biasloop _ control d0h 10 openloop bit 4 tx _ biasloop cch bias driver kfactor vdd figure 1 1 - bias current generation, open loop 4.2.5. closed loop if openloop is set to 0 the bias generator operates in closed loop mod e. the average output power of the vcsel/laser is controlled by a digital mean power control loop. the feedback to the contr ol loop is provided by a monitor photodiode connected to mpd. the current from the monitor photodiode is compared with a reference current (imonset). this is output by the mean power dac and controlled by m on_dac (d5h). in order to provide the required resolution and range the mean power dac has three step si zes as shown in section 3.3.10 . the 3db frequency of the digital mean power control loop is controlled by the size of a prescaling counter and can be determined (in hertz) by: f 3db = (kfactor x 692) / (m x imonset) where kfactor = vcsel/laser current to monitor photodiode current coupling coefficient imonset = desired monitor photodiode current (a) m = 2 ( 2 x prescale_ size) prescale_size is set by (d 0h, tx_biasloop_control, bits 2:0). downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 18 mpd bias ibias dac digital contr ol m ean power dac mon _ dac d5h 10 e2h bias _ adc _ value bias driver ibias adc efh bias _ dac _ observe comp kfactor imonset tx _ biasloop cch openloop bit 4 vdd figure 1 2 - bias current generation, closed loop 4.2.6. laser/vcsel eye diagrams figure 1 3 C vcsel output 1.25 gbps, prbs7, - 3 dbm average power, 25 c downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 19 figure 14 C laser output 1.25 gbps, prbs7, - 4 dbm output power , 25 c 4.2.7. initial start - up at power up or after tx_disable is de - asserted the phy1040 - 01 can initializ e within the time defined in the small form - factor pluggable (sfp) multis ource agreement (msa). see section 3.4.4 for initialization time. 4.2.8. vcsel/laser driver setup there is a trimming network on the output driver which adjusts the time const ant of the output damping on lvoutm/p . it is controlled by the value in tx_driver_cap (c9h). table 1 contains the valid register settings and the damping time constant they set, where rc = 16.8ps. tx_drive_cap value time constant 00h 0 01h rc 02h 3rc 04h 5rc 08h 6rc 10h 7rc 20h 8rc table 1 - time constant selection for the transmit output damping network downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 20 4.2.9. p erformance monitoring as part of its main control loop the phy1040 - 01 monitors temperature and transmit bias current via an on - chip adc. the adc values are reported via registers temp_adc_value (e1h) and bias_adc_value (e2h). the user has the option of using the measured values of temperature and bias current to set alarm bits. these are generated if the values measured are above or below programmable limits. the conditions are shown in table 2 and 3 below. temp_max_alarm_en (dah alarm_en bit 3) temp_min_ alarm_en (dah alarm_en bit 2) condition temp_max_error (eah bit7) temp_min_error (eah bit 6) 1 x temp_adc_value > temp_max (dbh) 1 0 x x temp_min (dch)< temp_adc_value < temp_max (dbh) 0 0 x 1 temp_adc_value < temp_min (dch) 0 1 0 0 x 0 0 table 2 - o ver and under temperature alarm generation bias_max_alarm_en (dah alarm_en bit 1) bias_min_alarm_en (dah alarm_en bit 0) condition bias_max_error (eah bit 5) bias_min_error (eah bit 4) 1 x bias_adc_value > bias_max (ddh) 1 0 x x bias_min (deh) < bias_ad c_value < bias_max (ddh) 0 0 x 1 bias_adc_value < bias_min (deh) 0 1 0 0 x 0 0 table 3 - bias current alarm generation an out of range monitored temperature (temp_max_error is set to 1 or tem p_min_error is set to 1) will cause a tx_fault condition to be raised. an out of range monitored bias current (bias_max_error is set to 1 or bias_min_error is set to 1) will cause a tx_fault condition to be raised. the response of the phy1040 - 01 to an alarm condition is described in section 4.4. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 21 4.3. receiver f eatures the phy1040 - 01 receiver section consists of an automatic gain control (agc) input amplifi er, which is followed by a programmable low pass filter. the filtered signal is passed to a limiting s tage and the receiver output is a cml driver. offset cancellation is provided by dc - feedback. a signal detect (sd)/ l oss o f s ignal (los) alarm is provided to detect if the amplitude of the ac - signal at the receiver input is below a programmable threshold. for a transimpedance amplifier with a constant gain, the los threshold corresponds to a particular o ptical m odulation a mplitude (oma) . 4.3.1. receiver input stage the receiver input stage includes internal 50 ? single - ended termination resistor s and is designed to be ac - coupled to the transimpedance amplifier. by defa ult the receiver is non - inverting ; however , to simplify the pcb layout of differential signals the polarity of the data can be inverted by setting rx_polarity (c3h, rx_limiter , bit 1) to 1. 4.3.2. receiver filter the programmable low pass filter provides band limiting in the receive signal path and can be used to improve the system sensitivity when a higher bandwidth tia is used. the bandwi dth of the filter is set to 0.7 x signal data rate selected and is controlled by a 3 - bit control word as follows: b it 1 0 data rate 0 0 125/155mbps 0 1 622mbps 1 0 1063mbps 1 1 1.25gbps table 4 - receive filter data rates the 2 - bit control word is set in the rate_select register (c4 h, rx_filter , bits 1 :0). 4.3.3. receiver cml output stage the cml output stage has two slew rate settings, selected by cml_slew (c5h , rx_driver , bit 1). the switching speed can be reduced in order to minimise electromagnetic radiation by setting cml_slew to a 1 . s et ting cml_slew to 0 maximises the slew rate of the output . th e signal swing can also be adjusted . setting cml_level to 0 (c5h , rx_driver , bit 0) results in a higher receiver differential output swing. set ting cml_level to 1 results in a reduce d output swing . rxoutp/m can also be disabled by setting rx_squelch to a 1 (c2h, rx_agc, bit 2). the phy1040 - 01 can automatically disable rxout p/m if a los condition is detected. to enable this function los_to_squelc h should be set to 1 (c2h , rx_agc , bit 3). in both cases the output termination remains as 50 ? but a logical 0 is output on rxoutp/m . downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 22 4.3.4. loss of signal figure 15 - los detection signal detect (sd) or loss of s ignal (los) is detected by measuring the optical modulation amplitude (oma). the signal amplitude measured at rxin p/m is compared to an analog threshold level set by the oma_dac register (d9h , oma_dac). if the received signal amplitude does not exceed the threshold then the los pin is asserted and the los indicator bit is set (ech , hware_sense_status , bit 3). the polarity of the los pin and register indicator bit are controlled by mux_polarity (c6h , rx_muxpol , bit 0). if mux_polarity is set to 0 then the los pin is set high during a loss of signal condition. conversely, if mux_polarity is set to 1 then the los pin is set high when a sig nal is detected. los detection has hysteresis, the level of which can be selected by omahystsel (c6h , rx_muxpol , bit 1). if omahystsel is set to 0 then 3db of hysteresis is used. if omahystsel is set to 1 then 4db of hysteresis is used. 4.3.5. voltage refere nce the phy1040 - 01 includes a temperature stable 1v reference source which provides the bias for the internal analog circuitry. the reference voltage is set using an internal resistor and rinternal (ceh, dac _ pwrd, bit 5) set to 1 . t he accuracy of the refer ence voltage using the internal resistor is +/ - 10 %. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 23 4.4. laser /vcsel safety features figure 1 6 - transmit fault generation the vcsel/laser safety circuit monitors the device for potential faults. if a fault is detected the pin tx_fault is asserted. the re gister bit tx_fault (eah , status , bit 3) reflects the status of the pin tx_fault. using bias alarm requires fault_latch_enable to be set to 0 . a transmit fault can be raised by the following: 1. the temperature monitor detects that the measured temperature has gone out of range. 2. the bias current monitor detects that the measured transmit bias current has gone out of range . 3. the internal controller logic detects that a dma from eeprom has fai led (see section 5 .1 ) 4. the soft_tx_fault bit (e8h , tx_disables , bit 2) is set to 1 5. the voltage reference monitoring circuit detects that the reference voltage is incorrect 6. the supply monitoring circuit detects that the power supply voltage is inc orrect if fault_latch_en = 0 (dah , alarm_enable, bit 4) then a transmit fault condition will cause the tx_fault pin to stay asserted even if the fault condition goes away. the pin will stay assert ed until either the chip is power cycled or the pin tx_disable is set to 1 or t he register soft_tx_disable is set to 1 (e8 h, tx_disables , bit 1) or fault_latch_en is set to 1. if fault_latch_en = 1 then the tx_fault pin is deasserted when the fault con dition goes away. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 24 supply_ok bit 1 hware_sense_status ech tx_disable supply monitor vref monitor vref_ok bit 0 soft_tx_disable bit 1 tx_disables e8h eye_safety_disable bit 0 tx_biasloop cch from tx_fault circuit figure 16 b fault_powerdown_en bit 5 alarm_enable dah tx_shutdown bit 2 status eah a to tx_fault circuitfigure 16 to bias andmodulation driver disable tx_disable bit 4 hware_sense_status ech controller logic tx_disable_polarity bit 7 tx_biasloop cch figure 17 - transmit shutdown generation the phy1040 - 01 contains circuitry to shutdown the transmitter bias and modulation current i f a problem is detected. the circuit in section 8.4 is required to meet sfp msa shutdown timing requirements . the conditions to cause a shutdown are: 1. the voltage reference monitoring circuit detects that the reference voltage is incorrect 2. the supply monitoring circuit detects that the power supply voltage is inc orrect 3 . the soft_tx_disable bit (e8h, tx_disables, bit 1) is set to 1 4 . the internal controller logic has not successfully completed its init ialisation (see section 5 .1 ) 5. the pin tx_disable is asserted 6. tx_fault is active and fault_powerdown_en = 1 (dah alarm_en bit 5) if a shutdown condition occurs the modulation and bias currents are disabled. conditions 1 -4 can be disab led from contributing to shutdown by setting eye_safety_disable = 1 (cch, tx_biasloop, bit 0). this feature should be used with great caution. the polarity of the tx_disable pin can be inverted by setting tx_disable_polarity (cch, tx_biasloop, bit 7). t he register bit tx_shutdown (eah, status, bit 2) reflects the status of the shutdown circuit. the register bit tx_disable (ech, hware_sense_status, bit 4) reflects the status of the pin tx_disable (after optional inversion using tx_disable_polarity ). downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 25 figure 1 8 - circuit response to single point fail conditions does not affect laser power does not affect laser power eeprom_scl 32 does not affect laser power does not affect laser power rxinp 29 does not affect laser power does not affect laser power rxinm 28 does not affect laser power does not affect laser power sd/los 26 does not affect vcsel/laser power (dc coupled system) does not affect vcsel/laser power (dc coupled system) lvoutp 22 fault state occurs (dc coupled system) bias current increases until a fault is detected; then a fault state occurs (dc coupled system) lvoutm 21 fault state occurs the laser forward voltage is 0v and no light is emitted bias 17 the apc circuit responds by increasing the bias current until a fault is detected; then a fault states occurs. the apc circuit responds by increasing the bias current until a fault is detected; then a fault states occurs. mpd 16 does not affect vcsel/laser power does not affect vcsel/laser power txinm 12 does not affect vcsel/laser power does not affect vcsel/laser power txinp 11 normal condition for circuit operation modulation and bias currents are disabled tx_disable 10 does not affect vcsel/laser power does not affect vcsel/laser power tx_fault 9 does not affect vcsel/laser power does not affect vcsel/laser power scl 7 does not affect vcsel/laser power does not affect vcsel/laser power sda 6 does not affect vcsel/laser power does not affect vcsel/laser power rxoutp 5 does not affect vcsel/laser power does not affect vcsel/laser power rxoutm 4 does not affect vcsel/laser power does not affect vcsel/laser power eeprom_sda 1 circuit response to under voltage or short to ground circuit response to over voltage or short to vcc name pin no does not affect laser power does not affect laser power eeprom_scl 32 does not affect laser power does not affect laser power rxinp 29 does not affect laser power does not affect laser power rxinm 28 does not affect laser power does not affect laser power sd/los 26 does not affect vcsel/laser power (dc coupled system) does not affect vcsel/laser power (dc coupled system) lvoutp 22 fault state occurs (dc coupled system) bias current increases until a fault is detected; then a fault state occurs (dc coupled system) lvoutm 21 fault state occurs the laser forward voltage is 0v and no light is emitted bias 17 the apc circuit responds by increasing the bias current until a fault is detected; then a fault states occurs. the apc circuit responds by increasing the bias current until a fault is detected; then a fault states occurs. mpd 16 does not affect vcsel/laser power does not affect vcsel/laser power txinm 12 does not affect vcsel/laser power does not affect vcsel/laser power txinp 11 normal condition for circuit operation modulation and bias currents are disabled tx_disable 10 does not affect vcsel/laser power does not affect vcsel/laser power tx_fault 9 does not affect vcsel/laser power does not affect vcsel/laser power scl 7 does not affect vcsel/laser power does not affect vcsel/laser power sda 6 does not affect vcsel/laser power does not affect vcsel/laser power rxoutp 5 does not affect vcsel/laser power does not affect vcsel/laser power rxoutm 4 does not affect vcsel/laser power does not affect vcsel/laser power eeprom_sda 1 circuit response to under voltage or short to ground circuit response to over voltage or short to vcc name pin no downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 26 4.5. temperature measurement the phy1040 - 01 uses an on - chip 8 bit adc to perform a temperature measurement once per iteration of its main control loop (approximately every 10ms). the measured adc value can be read from register temp_adc_value (e1h). this measurement can be used to control the modulat ion and bias currents. the temperature is determined by forcing two different currents through a diode connected transistor (base and collector shorted together) measuring the resulting voltage difference, ? v be . this voltage is directly proportional to the temperature. select_3i (cbh, tx_tempsense, bit 0) and vtoislopesel (cbh, tx_tempsense, bi ts 2 - 3) can be adjusted to ensure that the phy1 040 - 01 is capable of measuring the required range of temperatures. the temperature sensor operating range is shown in table 5. figure 1 9 C temperature sensor functional block diagram parameter comment symbol min typical max units temperature t -45 90 c adc slope vtoislopesel = 00 0.79 c/bit vtoislopesel = 0 1 0.5 c/bit vtoislopesel = 10 0.417 c/bit vtoislopesel = 11 0.294 c/bit table 5 - temperature measurement downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 27 5. control interface twi master twi slave internal registers arbiter 4 3 controller 1 2 host scl sda eeprom eeprom _ scl eeprom _ sda figure 20 - serial interfaces to internal re gisters the host communicates with the phy1040 - 01 and the eeprom via the slave two w ire i nterface (twi) pins of the phy1040 - 01 . s lave addresses a0h and a2h are supported . if a tra nsaction arriving at the slave interface is addressed to a2h, then the phy10 40 - 01 examines the register address in order to decide how the transaction should be processed (see address map in figure 21). ? if the register is implemented in eeprom only (addresses 00h to bfh) then the transaction is forwarded to the eeprom via path 4 in figure 20 . there is a direct combinational logic path between the slave and maste r interfaces which makes the phy1040 - 01 transparent when transactions from the host are forwarded to the eeprom. ? if the reg ister is only implemented internally to the phy104 0- 01 (addresses e0h to ffh) then the data is written to or read from the registers inside the phy1040 - 01 (path 3 ). ? if the register is implemented both internally and eeprom (addresses c0h to dfh) then the phy1040 - 01 checks the internal_access register bit (e7h internal bit 1) to determine whether the host wishes to access the eeprom or internal registers . set internal_access is set to 1 to access the internal registers and 0 to access the eeprom. when the phy1040 - 01 comes out of reset, the state machine us es the master two wire interface to read configuration bytes out of eeprom. this data is used to configure the internal regist ers of the device (path 1). subsequently, during normal operation t he state machine will use the master interface to periodical ly access look - up table and alarm threshold information stored in the eeprom (path 2). in order to prevent collisions between state machine and host accesses to eeprom , the host must always stop the state machine before attempting to access the eeprom by setting an internal register bit, sm_stop, to 1 (e7h, internal, bit 0). when the host has completed its transactions with the eepro m it must set sm_stop to 0 to allow normal operation of the state machine to resume . if the host attempts to access the ee prom when sm_stop is set to 0 then writes are ignored and reads return a zero. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 28 reads / wr ites to inter nal r egister s internal _ access = 1 inter nal _ access = 0 sm _ stop = 0 sm _ stop = 1 r eads / writes to inter nal r egisters r eads r eturn zero wr ites ignored r eads / writes to eeprom sm _ stop = 0 sm _ stop = 1 r eads r etur n zero writes ignored reads / writes to eeprom a d dr es s t ar get not accessible not accessible not accessible i nt er nal e epr o m 0 -7f 80 - bf c 0 - df e 0 - ff boot configur ation register s control and status register s bias / tem per atur e lookup table m odulation / tem per atur e lookup table boot configuration register s 0 - bf c 0 - df e 0 - ff a ddr es s figure 21 - phy1040 - 01 twi slave accesses 5.1. boot sequence power up tr ansfer data from eeprom to internal register s dma fail integr ity fail set boot complete m ain loop set boot _ fail _e set integrity _ fail _e set tx _ fault error flag (s) clear ed yes no yes yes no clear tx _ fault figure 22 - phy1040 - 01 boot sequence at power up the phy1040 - 01 attempts to read a number of bytes of configuration information from an external eeprom into its internal registers. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 29 if the read fails due to a problem on the twi, such as a read not being correctly acknowledg ed, the state machine sets register bit boot_fail_e to 1 (edh , debug_events , bit 2), raises a transmit fault condition and remains in an error state. the first two bytes read from eeprom, c0h and c1h, are compared against a data integrity number (c35ah). if the compare fails , the state machine sets register bit integrity_fail_e to 1 (edh , debug_events , bit 4), raises a transmit fault condition and remain s in an error state. in the error state the host is able to configure the internal registers of the phy1040 - 01 using the slave twi. when it has completed configuration the host must clear the active error(s) by writing a 1 t o the corresponding bit(s). when the state machine sees that the error bit(s) are cleared it clears the transmit fault condition. the state machine sets the register boot_complete_e (edh , debug_events , bit 1) to indicate that t he boot process is complete and then enters the main control loop. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 30 5.2. main control loop read adcs m od lut enabled boot seq yes no read m in / m ax thr esholds . set / clear errors accordingly set m od dac to m od / temp lut entry set m od dac to register value open loop yes no bias lut enabled yes no set bias dac to r egister value set bias dac to bias / tem p lut entr y first time yes no clear transmit disable tim er expir ed restar t tim er yes no figure 23 - phy1040 - 01 main loop function a loop timer is implemented in the state machine to ensure that the start of each iteration of the loop is separated by 10ms. when the timer has expired the state machine reads the on - chip adc to obtain temperature and bias current levels, reads alarm levels out of eeprom and sets/clears perfor mance alarms accordingly. the state machine th en sets the modulation current and bias c urrent. at the end of the first iteration of the loop after boot - up the state machine clears transmit disable to enable the transmit data path . downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 31 5.3. 2-wire serial interface the phy1040 - 01 has a pair of 2 - wire serial interfaces : a slave for interfacing to a hos t for module setup and programming , and a master for interfacing to an external eeprom and for device configuration after reset. both interfaces communicate using the protocol described in this section. 5.3.1. framing and data transfer the two - wire interface comp rises a clock line (scl) and a data line (sda). when the bus is i dle both are pulled high within the phy1040 - 01 by 8k ? pull - ups. an individual transaction is framed by a start condition and a stop condition. a start condition occurs when a bus master pulls sda low while the clock is high. a stop condition occu rs when the bus master allows sda to transition low - to - high when the clock is high. within the frame, the master has exclusive control of the bus. the phy1040 - 01 supports repeat start conditions whereby the master may simultaneously end one frame and start another without releasing the bus by replacing the stop condi tion with a start condition. within a frame, the state of sda may only change when scl is low. a data bit is transferred on a low - to - high transition of scl. data is arranged in packets of 9 bits. the first 8 bits represent data t o be transferred (most significant bit first). the last bit is an acknowledge bit. t he recipient of the data holds sda low during the ninth clock cycle of a data packet to ack nowledge (ack) the byte. leaving sda to float high on the ninth bit signals a not - acknowledged (nack) condition. the interpretation of the acknowledge bit by the sender will depend on the type of transaction and the nature of the byte being received. 5.3.2. device a ddressing the first byte to be sent after a start condition is an address byte. the first seven bits of the by te contain the target slave address (msb first). the eighth bit indicates the tr ansaction type C 0 = write, 1 = read. each slave interface on the bus is assigned a 7 - bit slave address. if no slave matches the address broadcast by the master then sda will be left to float high during the acknowledge bit and the master receives a nack. the master must then assert a stop condition. if a slave identifies the address then it acknowledges the master and proceeds with the transaction identified by the ty pe bit. msb 7 6 4 5 3 2 1 0 start nack stop r/w address sda scl figure 24 - address decoding example C slave not available 5.3.3. write transaction figure 25 shows an example of a write transaction. the address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. after the acknowledge the mas ter sends a single data byte. all signalling is controlled by the master except for the sda line dur ing th e acknowledge bits. during the acknowledge the direction of the sda line is reversed and the slav e pulls sda low to return a 0 (ack) to the master. figure 25 - write transaction 7 1 start ack stop sda scl 4 3 2 1 0 w 7 6 5 msb ack sda direction to slave from slave downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 32 if the slave is unable to receive data then it should return a nack after the dat a byte. this will cause the master to issue a stop and thus terminate the transaction. the phy1040 - 01 interprets the first data byte as a register address. this will be used to set an internal memory pointer. subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer. the pointer is auto - incremented after each byte. there is no limit to the number of bytes which may be written to the internal ram of the phy1040 - 01 . if, however, the write access is destined for the eeprom the requirements of page writes speci fied for the eeprom apply. if the slave is not ready to receive a byte then it may hold scl low immediatel y after the acknowledge bit. when scl is released the master starts to send the next byte. this is known as clock stretching. the phy1040 - 01 slave interface will not clock stretch at up to 100 khz scl frequency. 5.3.4. read transaction 7 1 start ack stop sda scl r nack sda direction to slave from slave 7 0 7 0 ack figure 2 6 - read transaction figure 26 shows an example of a 2 byte read transaction. the address byt e is successfully acknowledged by the slave, and the type bit is set high to signify a read. af ter the ack the slave returns a byte from the location identified by the internal memory pointer. this pointer is then auto - incremented. the slave then releases sda so that the master can ack the byte. if the s lave receives an ack then it will send another byte. the master identifies the last byte by sending a nack to the slave. the m aster then issues a stop to terminate the transaction. thus, to implement a random access read transaction, a write must first be issued by the m aster containing a slave address byte and a single data byte (the register address) as s hown in figure 25 . this sets up the memory pointer. a read is then sent to retrieve data from this add ress (see figure 26 ). downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 33 6. register map where a single power - on reset (por) value is shown for a range of addresses, that value applies to al l bytes in the range. note that the power on reset values may be overwritten during i nitialisation from the eeprom. for registers containing a single 8 - bit field, the most significant bit of the field is stored in bit 7 of the register byte. note that reserved or internal use only register bits are specified as read only. these registers should not changed from their por default settings. r bit is read only. a write to this bit via the twi will have no effect . the value may be changed by the device itself as part of its normal operation r/w bit is readable and writable via the twi. the value will not be changed by the devi ce itself except under a device reset. e bit is readable via the twi. the bit may be set by the device itself as part of its normal operation. once set the bit may be cleared by writing a 1 via the twi. writing a 0 via the twi has no effect. c0h data_integrity_lower integrity check for eeprom contents. must be set to c3 h for a boot load from eeprom to be successful. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00h c1h data_integrity_upper integrity check for eeprom contents. must be set to 5a h for a boot load from eeprom to be successful. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00h c2h rx_agc this register controls functions in the agc in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 los_to_ squelch r/w 0 setting this bit to a 1 connects the los function to the receiver squelch such that a los will automa tically disable the receiver output 2 rx_squelch r/w 0 setting this bit to a 1 causes the receiver output to be disabled 1 - r/w 0 internal use only. must be set to 0 0 - r/w 0 internal use only. must be set to 0 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 34 c3h rx_limiter this register controls functions in the limiter in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r/w 0 internal use only. must be set to 0 1 rx_polarity r/w 0 s etting this bit to a 1 causes the receive output polarity to be inverted 0 - r/w 0 internal use only. must be set to 0 c4h rx_filter this register controls functions in the filter in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r/w 0 internal use only. must be set to 0 2 - r/w 0 reserved 1 rate_select(1) r/w 0 selects the filter rate in the receiver 00 = 155 mbps 01 = 622 mbps 10 = 1063mbps 11 = 1250 mbps 0 rate_select(0) r/w 0 c5h rx_driver this register controls functions in the output driver in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r 0 reserved 1 cml_slew r/w 0 sets the receiver output slew rate 1 = slow 0 = fast 0 cml_level r/w 0 sets the receiver output swing level 1 = low swing 0 = high swing downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 35 c6h rx_muxpol this register controls the loss of signal detection cir cuit in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r 0 reserved 1 omahystsel r/w 0 sets the amount of hysteresis in the los detection circuit 1 = 4 db of hysteresis 0 = 3 db of hysteresis 0 mux_polarity r/w 0 sets the polarity of los output pin 1 = pin is high when signal detect 0 = pin is high when loss of signal c7h test0 internal use only, must be set to 00h type r/w por 00h c8h test1 internal use only, must be set to 00h type r/w por 00h c9h tx_driver_cap this register allows selective snubbing capacitors to be applied to the transmit output stage. setting the register to 0h applies no damping. type r/w por 00 h cah tx_d buff this register controls functions in the data buffer in the transmit path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r/w 0 internal use only, must be set to 00h 3 - r/w 0 2 - 1 vmodresoluti on r/w 0 control over vcsel mode modulation current and resolution, 16ma/32ma select 0 tx_polarity r/w 0 setting this bit to a 1 causes the transmit output polarity to be inverted downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 36 cbh tx_tempsense this register controls functions associated with the device temperature measurement bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 vtoislopesel(1) r/w 0 this field modifies the expected slope from the temperature sensor into the adc and should be set depending on the type of external temperature sensor 2 vtoislopesel(0) r/w 0 1 reserved r/w 0 internal use only. must be set to 1 0 select_3i r/w 0 setting this bit to 1 causes the temperature sensor to operate at 3 times the default measurement cu rr ent. cch tx_biasloop this register controls functions in the bias current generator in the transmit path of the device bit field name type por 7 tx_disable_ polarity r/w 0 setting this bit to a 1 inverts the polarity of the tx_disable input pin 6 - r/w 0 internal use only. must be set to 0 5 - r/w 0 internal use only. must be set to 0 4 openloop r/w 0 sets the configuration of the transmit bias circuit 1 = open loop 0 = closed loop 3 - r/w 0 internal use only. must be set to 0 2 - r/w 0 internal use only. must be set to 0 1 - r/w 0 internal use only. must be set to 0 0 reserved r/w 0 set to 0 during operation of the device cdh test2 internal use only, must be set to 00h type r/w por 00h downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 37 ceh dac_pwrd bit field nam e type por 7 - r 0 reserved 6 - r 0 reserved 5 rinternal r/w 0 s et to 1 , an internal 10k ? resistor is used for generating the reference voltage. 4 - r/w 0 internal use only, must be set to 0 3 - r/w 0 internal use only, must be set to 0 2 - r/w 0 internal use only, must be set to 0 1 - r/w 0 internal use only, must be set to 0 0 - r/w 0 internal use only, must be set to 0 cfh test3 internal use only, must be set to 00h type r/w por 00h d0h tx_biasloop_control this register controls generation of the transmit bias current bit field name type por 7 mod_temp_ disable r/w 0 setting this bit to 1 disables the modulation current / temperature lookup table 6 bias_temp_ disable r/w 0 in open loop mode setting this bit to 1 disables the bia s current / temperature lookup table. in closed loop mode it has no effect 5 reserved r/w 0 internal use only, must be set to 0 4 reserved r/w 0 internal use only, must be set to 0 3 reserved r/w 0 internal use only, must be set to 1 2 prescale_ size(2 ) r/w 0 these bits configure the loop bandwidth of the closed loop bias current. see section 4.2.5 for further details 1 prescale_ size(1) r/w 0 0 prescale_ size(0) r/w 0 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 38 d1h test4 internal use only, must be set to 00h type r/w por 00h d2h test5 internal use only, must be set to 00h type r/w por 00h d3h vref_dac reference voltage trim dac set to 71h type r/w por 00 h d4h mod_dac sets the modulation current (via a dac) when the modulation / temperature lut is disabled (mod_temp_disable is set to 1) type r/w por 00 h d5h mon_dac sets the target bias current level (via a dac) when the device is in closed loop configuration (openloop is set to 0) type r/w por 00 h d8h bias_dac sets the bias current (via a dac) when the device i s in open loop configuration (openloop is set to 1) and the bias / temperature lut is disabled (bias_temp_disable is set to 1) type r/w por 00 h d9h oma_dac sets the threshold level for optical measurement amplitude based los detection type r/w por 00 h downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 39 dah alarm_enable controls the behavio ur of the tx_fault pin and the generation of alarms based on temperature and bias current levels bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 fault_powerd own_en r /w 0 if this bit is set to 1 a tx_fault condition will cause the transmitter modulation and bias currents to be shutdown 4 fault_latch_ en r/w 0 if this bit is set to a 0 the output pin tx_fault will remain asserted once a fault condition has been detected even if the fault condition goes away. the pin will remain asserted until either the device is reset or this bit is set to a 1. if this bit is set to a 1 then the output pin tx_fault will be asserted if a fault condition is detected and will be deasserted once the condition is cleared. 3 temp_max_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured temperature exceeds temp_max 2 temp_min_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured temperature falls be low temp_min 1 bias_max alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured bias current exceeds bias_max 0 bias_min_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured bias current falls below bia s_min dbh temp_max if temp_max_alarm_en is set then this register sets the threshold above which a maximum temperature error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h dch temp_min if temp_min_alarm_en is set then this register sets the threshold below which a minimum temperature er ror is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h ddh bias_max if bias_max_alarm_en is set then this register sets the threshold above which a maximum bias current error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 40 deh bias_min if bias_min_alarm_en is set then this register sets the threshold below which a minimum bias current error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zer o. type r/w por 00 h the following registers exist only in the internal registers of the device. the corresponding addresses in eeprom are unreachable. therefore a twi transaction to these addresses will target the internal device registers regardless of the setting of internal_access. e0h test 6 internal use only, must be set to 00h type r/w por 00h e1h temp_adc_value indicates the current temperature value measured by the internal adc. type r por 00 h e2h bias_adc_value indicates the curre nt bias current value measured by the internal adc. type r por 00 h e3h test 7 internal use only, must be set to 00h type r/w por 00 h e4h test 8 internal use only, must be set to 00h type r/w por 00h e5h test 9 internal use only, must be set to 00h type r/w por 00h e6h test 10 internal use only, must be set to 00h type r/w por 00 h downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 41 e7h internal this register controls the internal state machines used to generate transmit modulation and bias currents bit field name type por 7 - r 0 res erved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 bias_sm_reset r/w 0 set this bit to a 1 to put the bias current control logic into reset. set to 0 for normal device operation 2 mod_sm_reset r/w 0 set this bit to a 1 to put the modulation current control logic into reset. set to 0 for normal device operation 1 internal _ access r/w 0 set this bit to a 1 to direct twi accesses to addresses c0h C dfh to the internal registers of the device. if set to 0 such addresses map to the exte rnal eeprom. 0 sm_stop r/w 0 set this bit to a 1 to suspend the internal control logic and allow twi accesses to the external eeprom. if this bit is set to 0 and a twi access is targeted at the eeprom then a write will be ignored and a read will retur n zero. e8h tx_disables this register controls the transmit safety shutdown circuit. see section 4.4 for further details bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 soft_tx_faul t r/w 0 this bit allows a tx_fault to be declared under control of the twi. setting this bit to a 1 causes a tx_fault condition to be declared 1 soft_tx_ disable r/w 0 this bit allows a tx_disable to be declared under control of the twi. setting this bit to a 1 causes a tx_disable condition to be declared 0 - r/w 0 internal use only. must be set to 0 downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 42 e9h events this register contains latched versions of the bits in the status register. if a condition becomes active the bit will report a 1. if the condition goes inactive the bit will stay at 1 until a 1 is written to the bit via the twi bit field name type por 7 temp_max_ error_e e 0 has value 1 if a maximum temperature error condition has occurred 6 temp_min_ error_e e 0 has value 1 if a minimum temperature error condition has occurred 5 bias_max_ error_e e 0 has value 1 if a maximum bias current error condition has occurred 4 bias_min_ error_e e 0 has value 1 if a minimum bias current error condition has occurred 3 tx_fault_e e 0 has value 1 if the output pin tx_fault has been asserted 2 tx_shutdown_ e e 0 has value 1 if a shutdown condition has been detected 1 sm_tx_fault_e e 0 has value 1 if the internal control logic has reported a fault condition 0 sm_tx_disable_ e e 0 has value 1 if the internal control has disabled the transmit circuitry eah status this register reports the status of a number of internally monitored conditions within the device. a bit will report a 1 if the condition is active and a 0 if the condition is inactive bit field name type por 7 temp_max_ error r 0 has value 1 if a maximum temperature error condition is currently being detected 6 temp_min_ error r 0 has value 1 if a minimum temperature error condition is currently being d etected 5 bias_max_ error r 0 has value 1 if a maximum bias current error condition is currently being detected 4 bias_min_ error r 0 has value 1 if a minimum bias current error condition is currently being detected 3 tx_fault r 0 has value 1 if t he output pin tx_fault is currently being asserted 2 tx_shutdown r 0 has value 1 if a shutdown condition is currently being asserted 1 sm_tx_fault r 0 has value 1 if the internal control logic is currently reporting a fault condition 0 sm_tx_disable r 0 has value 1 if the internal control logic is currently disabling the transmit circuitry downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 43 ebh hware_sense_events this register contains latched versions of the bits in the hware_sense_status register. if a condition becomes active the bit will report a 1. if the condition goes inactive the bit will stay at 1 until a 1 is written to the bit via the twi bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 tx_disable_e e 0 has value 1 if the input pin tx_disable changes from 0 to 1 3 los_e e 0 has value 1 if the los detect circuit has detected a los condition 2 - r 0 reserved 1 supply _ok_e e 0 has value 1 if the power supply monitoring circuit detects the supply voltage has gone from correct to incorrec t 0 vref _ok_e e 0 has value 1 if the voltage reference monitoring circuit detects the reference voltage has gone from correct to incorrect ech hware_sense_status this register reports the status of various device input pins and detection circuits b it field name type por 7 - r 0 reserved 6 - r 0 reserved 5 lvmode r 0 status of input pin lvmode 0 = vcsel mode 1 = laser mode 4 tx_disable e 0 indicates the logical status of the input pin tx_disable (after potential inversion according to tx_disable_polarity) 3 los e 0 indicates the status of the los detect circuit. the polarity depends on mux_polarity 2 - r 0 reserved 1 supply _ok e 0 indicates the status of the power supply monitoring circuit. if set to 1 then the supply voltage is correct 0 vref_ok e 0 indicates the status of the voltage reference monitoring circuit. if set to 1 then the reference voltage is correct downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 44 edh debug_events this register indicates whether certain events have occurred within the control logic of the device. if a condition occurs bit will report a 1 and will stay at 1 until a 1 is written to the bit via the twi bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 integrity_fail_ e e 0 this bit is set to 1 by the device if the boot dma from eeprom fails its integrity check 3 dma_fail_e e 0 this bit is set to 1 by the device if a dma from eeprom does not complete successfully 2 boot_fail_e e 0 this bit is set to 1 by the device if the boot dma from eeprom does not complete successfully 1 boot_ complete_e e 0 this bit is set to 1 by the device if the boot dma from eeprom completes successfully 0 iteration_e e 0 this bit is set to 1 by the device once per iteration of the modulation state machine logic (approx every 10ms ) efh bias_dac_observe this register indicates the current value of the transmit bias current setting dac type r por 00 h f0h mod_dac_observe this register indicates the current value of the transmit modulation current setting dac type r/w por 00 h ffh test11 internal use only type r por - downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 45 7. simplified interface models figure 2 7 - transmit input structure figure 2 8 - transmit output structure figure 2 9- receive input structure figure 30 - receive output structure downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 46 imon vcc ibias vcc figure 31 - mpd input structure figure 32 - vcsel/laser bias output structure los, txfault vcc fi gure 3 3 - los/tx_fault output downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 47 8. applications information 8.1. power supply connections the phy1040 - 01 has been designed as a low power device. in order to achieve low operating power consumption the transmitter and receiver circuitry in the phy1040 - 01 share some common internal bias circuitry. this requires that the phy1040 - 01 transmitter and receiver be powered up together for correct operation. 8.1.1. power supply filtering although the tx vdds and rx vdds should be powered together and therefore, ultim ately be connected at a common node, it is beneficial to separately filter the power supplies for the tx vdd and rx vdd supplies. separately filtering the transmitter and receiver supplies off c hip will reduce power supply noise and cross talk between the transmitter and receiver C it is generally good practice to separately filter and decouple the individual supplies on any multifunction ic. in a ddition to supplying separately filtered supplies to the tx vdds and rx vd ds of the phy1040 - 01 , it is recommended that any other ics and digital circuitry connected to the phy1040 - 01 in an application environment (e.g. sf f module) be suitably filtered and decoupled. an example of this would be to supply a filtered digital supply for an external mcu. figure 34 C recommended power supply connections and filtering. downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 48 8.2. vcsel/ laser connection C dc- coupled figure 3 5 - dc - coupled application diagram figure 3 5 shows a typical dc - coupled application. dc current is provided to the output stage via a resistive network. the ac impedance to ground of the lvout p pin should be approximately 50 ? to properly terminate that output. rseries is used to match the vcsel/l aser impedance. it may also be necessary to use a rc snubbing circuit connected in parallel with the vcsel/laser to reduce any ringing caused by series inductance in the packaging. a 10 ? resistor, rblock, is used to isolate the output stage from the capacitive loading of the bias pin. in laser mode, the bias pin can sink up to 80ma of current. downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 49 8.3. vcsel/laser connection C ac- coupled figure 3 6 C ac - coupled application diagram downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 50 8.4. tx_fault circuit C standalone mode r24 10k r15 300r vdd_tx r20 9k1 (do not fit) 6 1 2 3 4 5 ic2 fdg6332c 4 3 1 5 2 ic6 lmv7235m7 c13 1uf r22 10k (do not fit) vdd_tx c22 100nf 6 1 2 3 4 5 ic1 fdg6316p c5 100 nf r1 270k c10 1uf l2 blm15bd102 l1 blm15bd102 vdd_tx vdd_rx c12 1uf vdd_tx r16 10k vdd_in l3 blm15bd102 vdd_rosa vdd_tx tx_fault output for ic vdd_shd tx_fault fault_sense figure 3 7 C tx_fault circuit a vcsel/laser safety timing circuit is provided for phy1040 - 01 used in standalone mode. th e circuit will detect and shutdown the vcsel/laser within sfp msa specified timing in case of hardware faults such as short circuits to the vcsel/laser or tx_fault software faults from phy1040 - 01 . when used with an external microcontroller the circuit can be modified to use the internal com parator of the microcontroller. the safety logic detects voltage variation at fault_sense and compares it with a preset threshold of 0.94vcc. during normal operation, voltage at fault_sense is higher than 0.94vcc an d the comparator output is low. when dc current flow through fault_sense is higher than 90ma, the voltage at fault_sense will drop to less than 0.94vdd and the comparator output will be asserted to high to shut down ic1 and turn off the vcsel/laser supply voltage. the current threshold can be adjusted by varying r15 and r24 . the comparator output will remain high and will not be cleared by toggl ing the t x_disable input. when the fault is generated by phy1040 - 01 , the tx_fault output will be asserted to high which will turn on ic2 and assert comparator output to high to switch off ld using ic1. if the fault is transient, the transmission can be restarted by toggling the tx_disable input. downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 51 figure 3 8 - tx_fault timing result the fault shown in figure 3 8 is generated by connecting the vcsel/laser cathode to ground. the y ellow trace is the voltage at the vcsel/laser cathode. downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 52 9. packaging figure 39 C 32pin qfn package dimensions symbol typical unit thermal resistance C junction to ambient ja 39 c/w thermal resistance C junction to case jc 31 c/w note: refer to eia/ jedec standard jesd51 for test method and conditions table 6 - 32pin qfn package thermal data downloaded from: http:///
phy1040 - ad - 1.0 advance d atasheet page 53 10. contact information for technical support, contact maxim at www.maxim - ic.com/support . disclaimer this datasheet contains pr eliminary information and is subject to change. the phy1040 - 01 contains circuitry to aid the implementation of eye safety functions in equi pment using vcsel/laser devices. phyworks ltd accepts no liability for failure of this function in this product nor f or injury to persons as a result of use of this product. testing of the functionality of eye safety c ircuits in equipment using this product is the responsibility of the manufacturer of the equi pment. this document does not transfer or license any intellectual property ri ghts to the user. phyworks ltd assumes no liability or warranty for infringement of patent, copyright or other intellect ual property rights through the use of this product . phyworks ltd assumes no liability for fitness for particular use or claims arising from sale or use of its products. phyworks ltd products are not intended for use in life critical or sustai ning applications. downloaded from: http:///
phy1040 - ad - 1.0 advance datasheet page 54 maxim cannot assume responsibility for use of any circuitry other than circuitry enti rely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, inc. 160 rio robles , san jose , ca 9 5134 usa 1 - 408 - 601 - 1000 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. downloaded from: http:///

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