short form data sheet 82v3399 revision 9 01/05/16 9 ?2016 integrated device technology, inc. synchronization management wan pll and clock generatiion for ieee-1588 82v3399 this short form datasheet is inte nded to provide an overview only. additional de tails are available from idt. contact informati on may be found on the last page. features highlights ? single chip pll: ? features 0.5 mhz to 560 hz bandwidth ? provides node clock for itu-t g.8261/g.8262 synchronous ethernet (synce) ? exceeds gr-253-core (oc-192) and itu-t g.813 (stm-64) jitter generation requirements ? provides node clocks for cellul ar and wll base-station (gsm and 3g networks) ? provides clocks for dsl access concentrators (dslam), espe- cially for japan tcm-isdn netwo rk timing based adsl equip- ments ? provides clocks for 1 gigabi t and 10 gigabit ethernet applica- tions ? it supports clock generati on for ieee-1588 application main features ? provides an integrated single-chip solution for synchronous equip- ment timing source, including stratum 3, 4e, 4, smc, eec-option 1 and eec-option 2 clocks ? provides sonet clocks with less than 1 ps of rms phase jitter (12 khz - 20 mhz) ? supports 1pps input and output ? employs pll architecture to feature excellent jitter performance and minimize the number of the external components ? integrates t0 dpll and t4 dpll; t4 dpll locks independently or locks to t0 dpll ? supports programmable dpll bandwidth (0.5 mhz to 560 hz in 19 steps) and damping factor (1.2 to 20 in 5 steps) ? supports 1.1x10 -5 ppm absolute holdover accuracy and 4.4x10 -8 ppm instantaneous holdover accuracy ? supports hitless reference switch ing to minimize phase transients on t0 dpll output to be no more than 0.61 ns ? supports programmable input-to- output phase offset adjustment ? limits the phase and frequency offset of the outputs ? provides out1~out6 output cloc ks whose frequencies cover from 1 hz (1pps) to 644.53125 mhz ? includes 25 mhz, 125 mhz and 156.25 mhz for cmos outputs ? includes 25.78125 mhz, 128.90625 mhz, 161.1328125 mhz, for cmos outputs ? includes 25 mhz,125 mhz, 156.25 mhz, 312.5 mhz and 625 mhz for differential outputs ? includes 25.78125 mhz, 128.90625 mhz, 161.1328125 mhz, 322.265625 mhz and 644.53125 mhz for differential outputs ? provides in1~in6 input clocks whose frequencies cover from 1 hz (1pps) to 625 mhz ? includes 25 mhz, 125 mhz and 156.25 mhz for cmos inputs ? includes 25 mhz, 156.25 mhz, 312.5 mhz and 625 mhz for dif- ferential inputs ? internal dco can be controlled by an external processor to be used for ieee-1588 clock generation ? supports forced or automatic oper ating mode switch controlled by an internal state machine. it s upports free- run, locked and hold- over modes ? supports manual and automatic selected input clock switch ? supports automatic hitless selected input clock switch on clock fail- ure ? supports three types of input clo ck sources: recovered clock from stm-n or oc-n, pdh network sy nchronization timing and external synchronization reference timing ? provides a 2 khz, 4 khz, or 8 khz frame sync input signal, and a 2 khz or 8 khz frame sync output signal ? provides a 1pps sync input signal and a 1pps sync output signal ? provides output clocks for bits, gps, 3g, gsm, etc. ? supports pecl/lvds and cmos input/output technologies ? supports master clock calibration ? supports master/slave applicati on (two chips used together) to enable system protection against single chip failure ? supports telcordia gr-1244-co re, telcordia gr-253-core, itu-t g.812, itu-t g.8262. itu-t g.813 and itu-t g.783 recom- mendations other features ? i2c and serial microprocessor interface modes ? ieee 1149.1 jtag boundary scan ? single 3.3 v operation with 5 v tolerant cmos i/os ? 72-pin qfn package, green package options available applications ? 1 gigabit ethernet and 10 gigabit ethernet ? bits / ssu ? smc / sec (sonet / sdh) ? dwdm cross-connect and transmission equipment ? synchronous ethernet equipment ? central office timing source and distribution ? core and access ip switches / routers ? gigabit and terabit ip switches / routers ? ip and atm core switches and access equipment ? cellular and wll base-station node clocks ? broadband and multi-service access equipment
82v3399 short form data sheet synchronization management wan pll and clock generatiion for ieee-1588 10 revision 9 01/05/16 description the 82v3399 is an integrated, single-chip solution for the synchro- nous equipment timing source for stratum 3, 4e, 4, smc, eec- option1, eec-option2 clocks in so net / sdh / synchronous ethernet equipment, dwdm and wireless base station. the device supports several types of input clock sources: recovered clock from synchronous ethernet, st m-n or oc-n, pdh network syn- chronization timing and external synchronization reference timing. the device consists of t0 and t4 paths. the t0 path is a high quality and highly configurable path to prov ide system clock for node timing synchronization within a sonet / sdh / synchronous ethernet network. the t4 path is simpler and less c onfigurable for equipment synchroniza- tion. the t4 path locks independently from the t0 path or locks to the t0 path. an input clock is automatically or manually selected for t0 and t4 path. both the t0 and t4 paths s upport three primary operating modes: free-run, locked and holdover. in free-run mode, the dpll refers to the master clock. in locked mode, the dpll locks to the selected input clock. in holdover mode, the dpll resorts to the frequency data acquired in locked mode. whatever the operating mode is, the dpll gives a stable performance without being affected by operating condi- tions or silicon pr ocess variations. there are 2 high performance aplls that can be used for low jitter sonet and ethernet clocks the device provides programma ble dpll bandwidths: 0.5 mhz to 560 hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. different settings cover all sonet / sdh cl ock synchronization requirements. a highly stable input is required for the master clock in different appli- cations. the master clock is used as a reference clock for all the internal circuits in the device. it can be calibrated within 741 ppm. all the read/write registers are accessed through a microprocessor interface. the device supports i2c and serial microprocessor interface modes. in general, the device can be used in master/slave application. in this application, two devices s hould be used together to enable system protection against singl e chip failure.
82v3399 short form data sheet revision 9 01/05/16 11 synchroniz ation management wan pll and clock generatiion for ieee-1588 functional block diagram figure 1. functional block diagram ex_sync1 monitors t4 dpll apll microprocessor interface jtag divider out3 out3 mux divider out4 out4 mux out5 mux out6 mux divider out2 out2 mux divider out1 out1 mux t4 apll mux t0 apll mux t4 input selector t0 input selector osci auto divider selection input in1 in2 in3 in4 in5 in6 frsync_8k_1pps output input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority input pre-divider priority divider divider t0 apll t4 apll t0 dpll out5_pos out5_neg out6_pos out6_neg ex_sync2 auto divider mfrsync_2k_1pps
82v3399 short form data sheet synchronization management wan pll and clock generatiion for ieee-1588 12 revision 9 01/05/16 ordering information xxxxxxx xx x device type blank process / temperature range 82v3399b industrial (- 40 c to + 85 c) wan pll nlg green quad flatpack, no lead (vfqfp-n, nlg72)
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