View ADRF5020BCCZN_8740262.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

100 mhz to 30 ghz, silicon spdt switch data sheet adrf5020 rev. a document feedback information furnished by analog devices is bel ieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 C 2017 analog devices, inc. all rights reserved. technical support www.analog.com features ultra w ideband frequency ran ge: 100 m hz to 3 0 ghz nonreflective 50 design low insertion loss: 2 .0 db to 30 ghz high i solation: 60 db to 30 ghz high input linearity 1 db power compression (p 1db): 2 8 dbm typical third - order intercept (ip3): 5 2 dbm typical high power handling 24 dbm through path 24 dbm terminated path esd se n sitivity : class 1 , 1 kv human body model (hbm ) 2 0 - terminal , 3 mm 3 mm , land grid array package no low frequency spurious radio frequency (rf) settling time (to 0.1 db of final rf output): 15 ns applications test instrumentation microwave radios and very small aperture terminals (vsats) military radios, radars, electronic counter measures (ecms) b roadband telecommunications systems functional block dia gram rf2 rf1 rfc en vss ctrl vdd 50? 50? driver 14581-001 adrf5020 figure 1. general description the adrf5020 is a general - purpose , single - pole, double - throw (spdt) switch manufactured using a silicon process. it comes in a 3 mm 3 mm, 20- terminal land grid array (lga) package and pr ovide s high isolat io n and low insertion loss from 100 m hz to 3 0 ghz . this broadband switch requires dual supply voltages, + 3.3 v and ?2.5 v, and provides cmos/lvttl logic - compatible control.
adrf5020 data sheet rev. a | page 2 of 12 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ........................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 power derating curves ................................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 interface sche matics .....................................................................6 typical performance characterics ..................................................7 insertion loss, return loss, and isolation ................................7 input power compression and third - order intercept (ip3) ........ 8 theory of operation .........................................................................9 applications informatio n .............................................................. 10 evaluation board ........................................................................ 10 probe matrix board ................................................................... 11 outline dimension s ....................................................................... 12 ordering guide .......................................................................... 12 revision history 2/2017 rev . 0 to rev. a changed v en = 3.3 v to 5 v to v en = 0 v or 3.3 v to 5 v .......... 3 7 /2016 revision 0 : initial version
data sheet adrf5020 rev. a | page 3 of 12 specifications v dd = 3.3 v to 5 v, v ss = ?2.5 v, v ctrl = 0 v or 3.3 v to 5 v, v en = 0 v or 3.3 v to 5 v, t case = 25c, 50 ? system, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit frequency range 100 30, 000 m hz inserti on loss between rfc and rf1/rf2 100 mhz to 10 ghz 1.2 db 10 ghz to 20 ghz 1.5 db 20 ghz to 30 ghz 2.0 db isolation between rfc and rf1/rf2 100 mhz to 10 ghz 65 db 10 ghz to 20 ghz 60 db 20 ghz to 30 ghz 60 db betw een rf1 and rf2 100 mhz to 10 ghz 70 db 10 ghz to 20 ghz 65 db 20 ghz to 30 ghz 65 db return loss rfc and rf1/rf2 (o n ) 100 mhz to 10 ghz 22 db 10 ghz to 20 ghz 16 db 20 ghz to 30 ghz 13 db rf1/rf2 ( o ff ) 1 00 mhz to 10 ghz 28 db 10 ghz to 20 ghz 20 db 20 ghz to 30 ghz 10 db switching rise and fall time t rise , t fal l 10% to 90% of rf output 2 ns on and off time t on , t off 50% v ctl to 90% of rf output 10 ns rf settling time 0.1 db 50% v ctl to 0.1 db of final rf output 15 ns 0. 05 db 50% v ctl to 0.05 db of final rf output 20 ns input linearity 1 600 mhz to 30 ghz power compression 0.1 db p 0.1 db 2 6 dbm 1 db p 1db 2 8 dbm third - order intercept ip3 two - tone input power = 14 dbm each tone, f = 1 mhz 52 dbm supply current vdd, vss pins positive i dd v dd = 3.3 v 80 300 a v dd = 5 v 100 600 a negative i ss v ss = ?2.5 v <1 10 a digital control inputs ctrl, en pins voltage low v inl v dd = 3.3 v 0 0.8 v v dd = 5 v 0.9 v high v inh v dd = 3.3 v 1.2 3.3 v v dd = 5 v 1.7 5.0 v current low and high i inl , i inh <1 a
adrf5020 data sheet rev. a | page 4 of 12 parameter symbol test conditions/comments min typ max unit recommended operating conditons supply voltage positive v dd 3.0 5.4 v negative v ss ?2.75 ?2.25 v digital control voltage v ctl 0 v dd v rf input power 2 p in f = 600 mhz to 30 ghz, t case = 85c through path rf signal is applied to rfc or through connected rf1/rf2 24 dbm terminated path rf signal is applied to terminated rf1/rf2 24 dbm h ot switching rf signal is present at rfc while switching between rf1 and rf2 18 dbm case temperature t case ?40 +85 c 1 f or input linearity performance at frequencies less than 600 mhz , see figure 15 to figure 17. 2 f or p ower derating at frequencies less than 600 mhz , see figure 2 t o figure 4 .
data sheet adrf5020 rev. a | page 5 of 12 absolute maximum rat ings for recommended operating conditions, see table 1 . table 2 . parameter rating supply voltage positive ? 0.3 v to +5. 5 v negative ? 2.75 v to +0.3 v digital cont rol input voltage ? 0.3 v to v dd + 0.3 v rf input power 1 ( f = 600 mhz to 30 ghz, t case ) = 85c) through path 27 dbm terminated path 25 dbm hot switching 21 dbm temperature junction ( t j ) 135c storage ? 65c to +150c reflow (msl3 rating) 2 260c junction to case thermal resistance ( jc ) through path 420c/w terminated path 160c/w esd sensitivity hbm 1 kv (class 1) 1 for p ow er derating at frequenc ies less than 6 00 mhz , see figure 2 to figure 4 . 2 see the ordering guide section. stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; fun ctional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. only one absolute maximum rating can be applied at any one time. power derating curve s 4 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 power derating (db) frequency (hz) 10k 1m 100m 10g 100k 10m 1g 14581-002 figure 2 . power derating for through path vs. frequency, t case = 85c 4 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 power derating (db) frequency (hz) 10k 1m 100m 10g 100k 10m 1g 14581-003 figure 3 . power derating for terminated path vs. frequency, t case = 85c 4 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 power derating (db) 14581-004 frequency (hz) 10k 1m 100m 10g 100k 10m 1g figure 4 . power derating for hot swit ching vs. frequency, t case = 85c esd caution
adrf5020 data sheet rev. a | page 6 of 12 pin configuration and fu nction descriptions g n d r f 2 g n d g n d g n d g n d g n d r f 1 g n d g n d gnd gnd rfc gnd gnd gnd en vss ctrl vdd 1 2 3 4 5 678910 11 12 13 14 15 1617181920 adrf5020 top view (not to scale) notes 1. the exposed pad must be connected to the rf/dc ground of the printed circuit board (pcb). 14581-005 figure 5. pin configuration (top view) table 3. pin function descriptions pin no. mnemonic description 1, 2, 4 to 7, 9, 10, 13, 16, 17, 19, 20 gnd ground. these pins must be connected to the rf/dc ground of the printed circuit board (pcb). 3 rfc rf common port. this pin is dc-coupled to 0 v and ac matched to 50 . no dc blocking capacitor is necessary when the rf line potential is equal to 0 v dc. see figure 6 for the interface schematic. 8 rf1 rf1 port. this pin is dc-coupled to 0 v and ac matc hed to 50 . no dc blocking capacitor is necessary when the rf line potential is equal to 0 v dc. see figure 6 for the interface schematic. 11 vdd positive supply voltage. 12 ctrl control input. see figure 7 for the interface schematic. 14 en enable input. see figure 7 for the interface schematic. 15 vss negative supply voltage. 18 rf2 rf2 port. this pin is dc-coupled to 0 v and ac matc hed to 50 . no dc blocking capacitor is necessary when the rf line potential is equal to 0 v dc. see figure 6 for the interface schematic. epad exposed pad. the exposed pad must be connected to the rf/dc ground of the pcb. interface schematics rfc, rf1, rf2 14581-006 figure 6. rfc, rf1, and rf2 pins interface schematic ctrl, en v dd vdd 14581-007 figure 7. digital pins (ctr l and en) interface schematic
data sheet adrf5020 rev. a | page 7 of 12 typical performance characterics i nsertion l oss , r eturn l oss , a nd i solation insertion loss and return loss measured on the probe matrix board using the ground, signal, ground ( gsg ) probes close to the rf pins; isolation measured on an evaluation board because signal coupling between the probes limits the isolati on performance of the adrf5020 on the probe matrix board (see the applications information section for details of evaluation and probe matrix boards) . 0 ?5.0 ?4.5 ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 insertion loss (db) frequency (ghz) 0 40 35 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-008 figure 8. insertion loss between rfc and rf 1/ rf 2 vs. frequency over temperatur e 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 isolation (db) frequency (ghz) 0 40 35 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-009 figure 9. i solation between rfc and rf 1/rf2 vs. frequency over temperature 0 ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 return loss (db) frequency (ghz) 0 40 35 30 25 20 15 10 5 rf2 off rf1 on rfc 14581-010 figure 10 . return loss vs . frequenc y for rfc, rf1 on, and rf2 off 0 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 isolation (db) frequency (ghz) 0 40 35 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-0 1 1 figure 11 . isolation between rf1 and rf2 vs. frequency over temperature
adrf5020 data sheet rev. a | page 8 of 12 i nput p ower c ompression and t hird - order i ntercept (ip3) all large signal performance parameters were measure d on the evaluation board. 32 10 12 14 16 18 20 22 24 26 30 28 input p0.1db (dbm) frequency (ghz) 0 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-012 figure 12 . input 0.1 db power compression (p0.1db) vs . frequency over temperature 32 10 12 14 16 18 20 22 24 26 30 28 input p1db (dbm) frequency (ghz) 0 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-013 figure 13 . input 1 db power compression (p1db) vs. frequency over temperature 60 20 25 30 35 40 45 50 55 input ip3 (dbm) frequency (ghz) 0 30 25 20 15 10 5 t case = ?40c t case = +25c t case = +85c 14581-014 figure 14 . input ip3 vs. frequency over temperature 32 10 12 14 16 18 20 22 24 26 28 30 input p0.1db (dbm) frequency (hz) t case = ?40c t case = +25c t case = +85c 14581-015 10k 1m 100m 100k 10m 1g figure 15 . input 0.1 db power compression (p0.1db) vs. frequency over temperature (low frequency detail) 32 10 12 14 16 18 20 22 24 26 28 30 input p1db (dbm) frequency (hz) 10k 1m 100m 100k 10m 1g t case = ?40c t case = +25c t case = +85c 14581-016 figure 16 . input 1 d b power compression (p1db) vs. frequency over temperature (low frequency detail) 60 20 25 30 35 40 45 50 55 input ip3 (dbm) frequency (hz) 10k 1m 100m 100k 10m 1g t case = ?40c t case = +25c t case = +85c 14581-017 figure 17 . input ip3 vs. frequency over temperature (low frequency detail)
data sheet adrf5020 rev. a | page 9 of 12 theory of operation the adrf5020 require s a positive supply voltage applied to the vdd pin and a negative supply voltage applied to the vss pin. bypassing capacitors are recommended on the supply lines to minimize rf coupling. the adrf5020 is internally matched to 50 at the rf common port (rfc) and the rf throw ports (rf1 and rf2); therefore, no external matching components are required. all of the rf p orts are dc - coupled to 0 v , and no dc blocking is required at the rf ports when the rf lin e potential is equal to 0 v. the design is bidirectional; the rf input signal can be applied to the rfc port while the rf throw port (rf1 or rf2) is output or vice versa. the adrf5020 incorpo rate s a driver to perform logic function s internally and to provide the user with the advantage of a simplifie d control interface. the driver features two digital c ontrol input pins, ctrl and en. when the en pin is logic low, the rf1 to rfc path is in an insertion loss state , and the rf2 to rfc path is in an isolation state , or vi ce versa , depending on the logic level applied to the ctrl pin. the insertion loss path ( for example, rf1 to rfc) conducts the rf signal equally well in both directions between it s throw port ( for example, rf1) and common port (rfc). the isolation path ( for example, rf2 to rfc) provides high loss between the insertion loss path and its throw port ( for example, rf2) terminated to an internal 50 ? resistor. when the en pin is logic high, both the rf1 to rfc path and the rf2 to rfc path are in an isolation state regardless of the logic state of ctrl. rf1 and rf2 ports are terminated to internal 50 ? resistors , a nd rfc becomes open reflective. the i deal power - up sequence is as follows: 1. power up gnd. 2. power up vdd and vss. the relative order is not important. 3. power up the digital control inputs. the relative order of the logic control inputs is not important. however, p owering the digital control inpu ts before the vdd supply can inadvertently forward bias and damage the internal esd protection structures. 4. apply an rf input signal. table 4 . control voltage truth table digital control input rf paths en ctrl rf1 to rfc rf2 to rf c low low isolation ( off ) insertion loss (on) low high insertion l oss ( on ) isolation (off ) high low isolation ( off ) isolation (off ) high high isolation ( off ) isolation (off )
adrf5020 data sheet rev. a | page 10 of 12 applications informa tion evaluation board figur e 18 and figure 19 show the top and cross sectional views of the evaluation board, which uses 4 - layer construction with a copper thickness of 0.5 oz (0.7 mil) and dielectric materials between each copper layer. 14581-018 1500mil 940mil 828mil 40mil 40mil edge plating 5 520mil 570mil r 32mil figure 18 . evaluation board layout (top view) 14581-019 0.5oz cu (0.7mil) 0.5oz cu (0.7mil) 0.5oz cu (0.7mil) 0.5oz cu (0.7mil) 0.5oz cu (0.7mil) ro4003 fr4 fr4 0.5oz cu (0.7mil) total thickness ~62mil w = 14mil g = 5mil t = 0.7mil h = 8mil figure 19 . evaluation board (cross sectional view) all rf and dc traces are routed on the top copper layer whereas the inner and bottom layers are grounded planes that prov ide a solid ground for the rf transmission lines . top dielectric material is 8 mil rogers ro4003, offering good high frequency performance. the middle and bottom dielectric materials are fr - 4 type materials to achieve an overall board thickness of 62 mil. the rf transmission lines wer e designed using a coplanar waveguide (cpwg) model with a width of 14 mil and ground spacing of 5 mil to have a characteristic impedance of 50 ?. for good rf and thermal grounding, as many plated through vias as possible are a rranged around transmission lines and under the exposed pad of the package. figure 20 shows the actual adrf5020 evaluation board with component placement. two power supply ports are connected to the vdd and vss test points, tp5 and tp2, and the ground reference is connected to the gnd test point, tp1. on each supply trace, a 100 pf bypass capacitor is used, and unpopulated components positions are available for applyi ng extra bypass capacitors. 14581-020 figure 20 . populated evaluation board two control ports are connected to the en and ctrl test points, tp3 and tp4. on each control trace, a resistor position is available to improve the isolation bet ween the rf and control signals. the rf ports are connected to the rfc, rf1, and rf2 connectors (j1, j2, and j3) that are end launch 2.4 mm rf connectors. a through transmission line that connects unpopulated rf connectors (j7 and j8) is also available to measure the loss of the pcb. figure 21 and table 5 are the evaluation board schematic and bill of materials, respectively. the evaluation board shown in figure 20 is available f rom analog devices, inc., upon request.
data sheet adrf5020 rev. a | page 11 of 12 14581-021 gnd rf2 gnd gnd gnd gnd gnd rf1 gnd gnd gnd gnd rfc gnd gnd gnd en vss vss ctrl vdd en ctrl vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 u1 j1 j3 j2 j7 depop j8 depop thr_cal rf2 rfc rf1 r2 0? r1 0? tp5 tp4 tp3 tp2 tp1 c5 100pf c2 100pf depop c1 10f depop c4 100pf c3 100nf depop c6 10f depop figure 21 . evaluation board schematic table 5 . bill of materials, evaluation board components component description j1, j2, j3 end launch connector s , 2.4 mm j7, j8 unpopulated end launch connector s , 2.4 mm tp1 to tp5 through hole mount test point s c4, c5 100 pf capacitor s , 0402 package c2, c3 unpopulated capacitor s , 0402 package c1, c6 unpopulated capacitor s , 0603 package r1, r2 0 resistor s , 0402 pac kage u1 adrf5020 spdt switch pcb 600- 01583 -00 - 1 evaluation pcb p robe m atrix board figure 22 and figure 23 show t he top and cros s sectional views of the probe matrix board that measure s the s- parameters of the adrf5020 at close proximity to the rf pins using the gsg probes. the actual board duplicates the same layout in matrix form to assemble multiple device s and u s es rf traces for t hr ough , r eflect , and l ine (trl) calibration. 14581-022 220mil 340mil figure 22 . probe board layout (top view) 14581-023 0.5oz cu 0.5oz cu 0.5oz cu ro4003 0.5oz cu w = 14mil g = 5mil t = 0.7mil h = 8mil figure 23 . probe matrix board ( cross sectional view )
adrf5020 data sheet rev. a | page 12 of 12 outline dimensions 05-25-2016- b pkg-004908 3.10 3.00 2.90 0.776 0.726 0.676 top view side view bottom view 1 5 6 10 11 15 16 20 1.70 1.60 sq 1.50 0.40 bsc 0.13 ref 0.70 ref 1.60 ref sq 0.25 0.20 0.15 0.30 0.25 0.20 0.236 0.196 0.156 for proper connection of the exposed pads, refer to the pin configuration and function descriptions section of this data sheet. exposed pad 0.530 ref chamfered pin 1 (0.3 45 ) pin 1 corner area figure 24. 20-terminal land grid array [lga] 3 mm 3 mm body and 0.72 mm package height (cc-20-3) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 ADRF5020BCCZN ?40c to +85c msl3 20-ter minal land grid array [lga] cc-20-3 xxx x 020 ADRF5020BCCZN-r7 ?40c to +85c msl3 20-te rminal land grid array [lga] cc-20-3 xxx x 020 adrf5020-evalz evaluation board 1 z = rohs-compliant part. 2 see the absolute maximum ratings section. 3 xxxx is the 4-digit lot number. ?2016C2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d14581-0-2/17(a)

▲Up To Search▲

Price & Availability of ADRF5020BCCZN

	To Download ADRF5020BCCZN Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .