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f 1956 datasheet 7 - bit 0.25 db wideband digital step attenuator 1 to 6000 mhz F1956, rev 2 0 4 / 0 8 /2016 1 ? 201 6 integrated device technology, inc. g eneral d escription this document describes the specification for the F1956 digital step attenuator. the F1956 is part of idts glitch - free tm family of dsas optimized for the demanding requirements of base station (bts) radio cards and numerous other non - bts applications. this device is offered in compact 5 mm x 5 mm 32 - pin package with 50 ? input and output impedance for ease of integration into the radio or rf system. c ompetitive a dvantage the F1956 offers very high reliability due to its construction f rom a monolithic silicon die in a qfn package. t he insertion loss is very low with minimal distortion. additiona lly the device is designed to have extremely accurate attenuations levels. these accurate attenuation level improves system snr and/or aclr b y ensuring system gain is as close to targeted level as possible. also, the very fast settling time in parallel mode is ideal for fast switching systems. finally, the device is glitch - free tm with less than 2 db of ringing across the attenuation range in stark contrast to competing dsas that glitch as much as 10 db during msb state changes. ? lowest insertion loss for best snr ? glitch - free tm technology to protect pa or adc during transition s between attenuation states. ? extremely accurate attenuation levels ? ul tra low distortion ? msl1 and 2000 v hbm esd o rdering i nformation f eatures ? serial & 7 - bit parallel interface ? 31.75 db range ? 0.25 db steps ? glitch - free tm : low transient overshoot ? 500 ns settling time ? ultra linear > 64 dbm iip3 ? low insertion loss < 1.7 db @ 4 ghz ? attenuation error < 0.2 db @ 4 ghz ? bi - direction al rf use ? 3.3 v or 5 v supply ? 1.8 v or 3.3 v control logic ? low current consumption: 350 a typica l ? - 40 c to +105 c operating temperature ? 5 mm x 5 mm thin qfn 32 pin package f unctional b lock d iagram part# details part# freq range (mhz) resolution / range (db) control il (db) pinout f1950 150 - 4000 0.25 / 31.75 parallel & serial 1.3 pe43702 pe43701 f1951 100 - 4000 0.50 / 31.5 serial only 1.2 hmc305 f1952 100 C 4000 0 .50 / 15.5 serial only 0.9 hmc305 f1953 400 C 4000 0.50 / 31.5 parallel & serial 1.3 pe4302 dat - 31r5 F1956 1 - 4000 0.25 / 31.75 parallel & serial 1.4 pe43705, pe43712, rfsa3715 f1912 1 C 4000 0.50 / 31.5 parallel & serial 1.6 pe4312 pe4302 F1956nbg i8 green tape & reel d e c o d e r r f 1 r f 2 d [ 6 : 0 ] s p i b i a s a [ 2 : 0 ] c l k d a t a l e v m o d e glitch - free tm glitch - free tm
F1956 7 - bit 0.25 db wideband digital step attenuator 2 rev 2 0 4 / 0 8 /2016 a bsolute m aximum r atings parameter symbol min max units vdd to gnd v dd - 0.3 +5.5 v d[6:0], data, clk, le, a0, a1, a2, v mode vcntl - 0.3 min (v dd + 0.3, 3.9 ) v rf1, rf2 v rf - 0.3 +0.3 v maximum input power applied to rf1 or rf2 (>100 mhz) p rf +34 dbm operatin g case temperature 105 c continuous power dissipation 1.5 w maximum junction temperature tj max +150 c storage temperature range t st - 65 +150 c lead temperature (soldering, 10s) t lead +260 c electrostatic discharge C esdhbm 1500 (class 1c) v esd voltage C esdcdm 500 (class c2) v stresses above those listed above may cause permanent damage to the device. functional operation of the device at these or any other conditions above those ind icated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd c aution this product features proprietary protection circuitry. however, it may b e damaged if subjected to high energy esd. please use proper esd precautions when handling to avoid damage or loss of performance . p ackage t hermal and m oisture c haracteristics ja (junction C ambient) 40 c/w jc (junction C case) [the case is defined as the exposed paddle] 4 c/w moisture sensitivity rating (per j - std - 020) msl1
F1956 rev 2 0 4 / 0 8 /2016 3 7 - bit 0.25 db wideband digital step attenuator f 1956 r ecommended o perating c onditions parameter symbol conditions min typ max units supply voltage(s) v dd 3.00 5.25 v operating temperature range t case case temperat ure - 40 +105 c frequency range f rf 1 6 000 mhz rf cw input power p cw rf1 or rf2 see figure 1 dbm rf peak input power p peak rf1 port, v dd = 3.3v, t case = 85 c, f rf > 500 mhz, wcdma, 3gpp, downlink, 64 dpch, chip rate =3.84 msps, avg. pin = +22 dbm 1 % 28.9 dbm 0.1 % 30.7 0.01 % 3 2 .3 0.001 % 33.2 rf source impedance z rfi single ended 50 rfo single ended 50 figure 1 - maximum operating rf input power vs input frequenc y 0 4 8 12 16 20 24 28 32 0.01 0.10 1.00 10.00 100.00 1000.00 max cw p in (dbm) frequency (mhz)
F1956 7 - bit 0.25 db wideband digital step attenuator 4 rev 2 0 4 / 0 8 /2016 F1956 s pecification specifications apply at v dd = +3.3 v, t case = +25 c, f rf = 2 ghz, 0.25 db steps unless otherwise noted. minimum attenuation d[6:0] = [0000000], maximum attenuation d[6:0] = [1111111], evkit losses are de - embedded unless otherwise noted. parameter symbol conditions min typ max units logic input high v ih clk, le, data, d[6:0], a0, a1, a2, v mode 3.0 v v dd 3.6 2 v dd v 3.6 v < v dd 1.17 1 3.6 logic input low v il clk, le, data, d[6:0], a0, a1, a2, v mode 0.63 v logic current i ih, i il individual pins - 40 +20 a dd 350 800 a rng no missing codes 31.75 db minimum gain step lsb f rf ? rf ? rf ? ? set max to min attenuation to settle to within 0.5 db of final value 0.9 ? 1.8 video feedthrough rf1, rf2 ports vid ft measured at rf ports with 2.5 ns risetime, 0 to 3.3 v control pulse 10 mv pp maximum spurious level on any rf port 4 spur max spur freq ~ 2.2 mhz - 140 dbm serial clock speed f clk spi 3 w ire bus 25 mhz parallel to serial setup a spi 3 wire bus 100 ns serial data hold time b spi 3 wire bus 10 ns le delay c spi 3 wire bus time from final serial clock rising edge 10 ns maximum switching rate sw rate 25 khz specification notes : note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/italics are guaranteed by design characterization. note 3. the input 0.1 db compression point is used as a linearity figure of mer it. the recommended maximum input power is specified as the lesser of the two values from rf cw power (figure 1) and the rf average power (recommended operating conditions table).. note 4: spurious due to on - chip negative voltage generator. typical genera tor fundamental frequency is 2.2 mhz.
F1956 rev 2 0 4 / 0 8 /2016 5 7 - bit 0.25 db wideband digital step attenuator F1956 s pecification ( continued ) specifications apply at v dd = +3.3 v, t case = +25c, f rf = 2 ghz, 0.25 db steps unless otherwise noted. minimum attenuation d[6:0] = [0000000], maximum attenuation d[6:0] = [1111111] , evkit losses are de - embedded unless otherwise noted. parameter symbol conditions min typ max units insertion loss il 1 mhz < f rf 2 ghz 1.8 db 2 ghz < f rf 3 ghz rf 4 ghz rf 5 ghz rf 6 ghz ? rf = 1 ghz 12 deg f rf = 2 ghz 25 f rf = 4 ghz 55 f rf = 6 ghz 90 step error (differential non - linearity) dnl max error between adjacent steps 0.10 0.19 db absolute attenuation error (integral non - linearity) inl max error for state 19.75 db, frf = 2 ghz - 0.4 0.1 +0.5 db max error, over all states f rf = 2 ghz - 0.8 +0.5 input return loss s 11 1 mhz < f rf 2 ghz rf 4 ghz rf 6 ghz 22 1 mhz < f rf 2 ghz rf 4 ghz rf 6 ghz in = +10 dbm per tone 50 mhz tone separation attn = 0.00 db 64 dbm attn = 15.75 db 64 attn = 31.75 db 64 attn = 0.00 db p in = +22 dbm per tone 1 mhz tone separation f rf = 0.7 ghz 60 63.4 dbm f rf = 1.8 ghz 60 63.4 f rf = 2.2 ghz 60 64.1 f rf = 2.6 ghz 6 0 63.3 input 0.1db compression 3 p 0.1db f rf = 2 ghz, attn = 10 db 34.5 dbm specification notes: note 1: items in min/max columns in bold italics are guaranteed by test. note 2: items in min/max columns that are not bold/italics are guaranteed by desi gn characterization. note 3. the input 0.1 db compression point is used as a linearity figure of merit. the recommended maximum input power is specified as the lesser of the two values from rf cw power (figure 1) and the rf average power (recommended oper ating conditions table).. note 4: spurious due to on - chip negative voltage generator. typical generator fundamental frequency is 2.2 mhz.
F1956 7 - bit 0.25 db wideband digital step attenuator 6 rev 2 0 4 / 0 8 /2016 p rogramming o ptions F1956 can be programmed using either the parallel or serial interface; selectable via v mode ( pin 3 ) . serial mode is selected by floating v mode or pulling v mode to a logic high and parall el mode is selected by setting v mode to logic low . s erial c ontrol m ode F1956 serial mode is selected by floating v mode (pin 3) or pulling it to logic high. the seri al interface is a 16 - bit shift register made up of two words. the first 8 - bit word is the attenuation word, which controls the dsa state. the second word is the address word, which uses only 3 of 8 - bits that must match the hard wired a0 - a2 programming in order to change the dsa state. if no external connections are made to a0 C a2 then internally they will default to 000 due to internal pull down resistors. if these 3 external preset address bits are not matched with the spi loaded address bits then the current attenuator state will remain unchanged. this allows up to 8 serial - controlled devices to be used on a single board, which share a common data, clk and le . when serial programming is used, all the parallel control input pins 26 C 32 can be left op en or gro unded. if a pin is grounded the n an additional 25 a will be drawn from the voltage supply per pin. set to either logic high or low set to logic low msb (last in) lsb (first in) q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 8 - bit address word 8 - bit attenuation word figure 2 - two 8 - bit words are comprised of 16bit serial in, parallel out shift register table 1 - truth table for the serial address word a7 (msb) a6 a5 a4 a3 a2 a1 a0 address setting x x x x x 0 0 0 000 x x x x x 0 0 1 001 x x x x x 0 1 0 010 x x x x x 0 1 1 011 x x x x x 1 0 0 100 x x x x x 1 0 1 101 x x x x x 1 1 0 110 x x x x x 1 1 1 111
F1956 rev 2 0 4 / 0 8 /2016 7 7 - bit 0.25 db wideband digital step attenuator table 2 - truth table for the serial control word d7 d6 d5 d4 d3 d2 d1 d0 (lsb) attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 0 1 0 0.5 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 2 0 0 0 1 0 0 0 0 4 0 0 1 0 0 0 0 0 8 0 1 0 0 0 0 0 0 16 0 1 1 1 1 1 1 1 31.75 s erial m ode d efault c ondition when the device is first powered up it will default to the maximum attenuation setting as described below: note that for the F1956 in all cases logic high (1) has the a ttenu ation s tepped in, while l ogic low (0) has the attenuation s tepped out. msb (last in) lsb (first in) q15 q14 q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 x x x x x 0 0 0 0 1 1 1 1 1 1 1 8 - bit address word 8 - bit attenuation word figure 3 - default register settings set for max attenuation and 000 address word r egister t iming d iagram : (n ote the t iming s pec i ntervals in b lue ) with serial control, t he F1956 can be programmed via the serial port on the rising edge of latch enable (le) which loads the last 8 data line bits [formatted lsb (d0) first] resident in the shift register followed by the address word into the active register.
F1956 7 - bit 0.25 db wideband digital step attenuator 8 rev 2 0 4 / 0 8 /2016 reinsert figure 4 - serial timing diagram note - when latch enable is high, the shift register is disabled and data is not continuously clocked into the shift register which minimizes noise. it is recommended that latch enable be left high when the device is not being programmed. table 3 - serial mode timing table interval symbol description min spec max spec units t ps parallel to serial setup time - from rising edge of vmode to rising edge of clk for d5 100 ns t p cloc k high pulse width 10 ns t cls le setup time - from the rising edge of clk pulse for d0 to le rising edge minus half the clock period. 10 ns t lew le pulse width 30 ns t dst data setup time - from the starting edge of data bit to rising edge of clk 10 ns t dht data hold time - from rising edge of clk to falling edge of the data bit. 10 ns p arallel c ontrol m ode for the F1956 the user has the option of running in one of two parallel modes. direct parallel mode or latched parallel mode. direct paralle l mode: direct parallel mode is selected when v mode is a logic low and le is a logic high. in this mode the device will immediately react to any voltage changes to the parallel control pins [pins 26 C 32]. use direct parallel mode for the fastest settlin g time.
F1956 rev 2 0 4 / 0 8 /2016 9 7 - bit 0.25 db wideband digital step attenuator latched parallel mode: latched parallel mode is selected when v mode is logic low and le is toggled from logic low to high. to utilize latched parallel mode: ? set v mode is logic low. ? set le to logic low. ? adjust pins [26, 27, 28, 29, 30, 31, 32] to the desired attenuation setting. (note the device will not react to these pins while le is a logic low). ? pull le to a logic high. the device will then transition to the attenuation settings reflected by pins d6 - d0. ? if le is pulled to a logic low then t he attenuator will not change state. latched parallel mode implies a default state for when the device is first powered up with v mode set for logic low and le logic low. in this case the default setting is maximum attenuation. table 4 - truth table for the parallel control word d6 d5 d4 d3 d2 d1 d0 attenuation (db) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0.25 0 0 0 0 0 1 0 0.5 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 4 0 1 0 0 0 0 0 8 1 0 0 0 0 0 0 16 1 1 1 1 1 1 1 31.75 f igure 5 - latched parallel mode timing diagram
F1956 7 - bit 0.25 db wideband digital step attenuator 10 rev 2 0 4 / 0 8 /2016 table 5 - latched parallel mode timing interval symbol description min spec max spec units t sps serial to parallel mode setup time 100 ns t pdh parallel d ata hold time 10 ns t le le minimum pulse width 10 ns t pds parallel data setup time 10 ns t ypical o perating c onditions (toc) unless otherwise noted for the toc graphs on the following pages, the following conditions apply. 1. v dd = +3.30 v 2. t case = +2 5 c 3. 50 mhz tone space 4. serial control 5. p in = 0 dbm 6. rf1 is the input port 7. attenuation setting = 0 db 8. evkit losses (traces and connectors) are fully de - embedded
F1956 rev 2 0 4 / 0 8 /2016 11 7 - bit 0.25 db wideband digital step attenuator t ypical o perating c onditions ( - 1 - ) insertion loss vs frequency input return loss vs freque ncy [all states] output return loss vs frequency [all states] insertion loss vs attenuation input return loss vs attenuation output return loss vs attenuation - 5 - 4 - 3 - 2 - 1 0 0 1 2 3 4 5 6 7 8 insertion loss (db) frequency (ghz) - 40 c +25 c +105 c - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 1 2 3 4 5 6 7 8 match (db) frequency (ghz) - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 1 2 3 4 5 6 7 8 match (db) frequency (ghz) - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 insertion loss (db) attenuation (db) 3.0 ghz, - 40 c 3.0 ghz, +25 c 3.0 ghz, +105 c - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match(db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz - 40 - 35 - 30 - 25 - 20 - 15 - 10 - 5 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 match (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz
F1956 7 - bit 0.25 db wideband digital step attenuator 12 rev 2 0 4 / 0 8 /2016 t ypical o perating c onditions ( - 2 - ) worst case absolute accuracy (lsb=0.25 db) worst case absolute accuracy (lsb=0.5 0 db) worst case absolute accuracy (lsb=1 .00 db) absolute accuracy (lsb=0.25 db) absolute accuracy (lsb=0.50 db) absolute accuracy (lsb=1.00 db) - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 2.0 - 1.5 - 1.0 - 0.5 0.0 0.5 1.0 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 1.8 - 1.6 - 1.4 - 1.2 - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz - 1.8 - 1.6 - 1.4 - 1.2 - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz - 1.8 - 1.6 - 1.4 - 1.2 - 1.0 - 0.8 - 0.6 - 0.4 - 0.2 0.0 0.2 0.4 0.6 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz
F1956 rev 2 0 4 / 0 8 /2016 13 7 - bit 0.25 db wideband digital step attenuator t ypical o perating c onditions ( - 3 - ) worst case step accura cy (lsb=0.25 db) worst case step accuracy (lsb=0.50 db) worst case step accuracy (lsb=1.00 db) step accuracy (lsb=0.25 db) step accuracy (lsb=0.50 db) step accuracy (lsb=1.00 db) - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0 1 2 3 4 5 6 7 8 error (db) frequency (ghz) - 40 c min - 40 c max +25 c min +25 c max +105 c min +105 c max - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.50 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 error (db) attenuation (db) 0.02 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz
F1956 7 - bit 0.25 db wideband digital step attenuator 14 rev 2 0 4 / 0 8 /2016 t ypical o perating c onditions ( - 4 - ) relative insertion pha se vs frequency [all states] input compression (at 2 ghz, attn=0 db) input compression (at 2 ghz, attn=4 db) relative insertion phase vs attenuation input compression (at 2 ghz, attn=16 db) input compression (at 2 ghz, attn=31.75 db) - 10 0 10 20 30 40 50 60 70 80 90 100 110 0 1 2 3 4 5 6 7 8 phase (degrees) frequency (ghz) - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c - 10 0 10 20 30 40 50 60 70 80 90 100 110 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 phase (degrees) attenuation (db) 0.50 ghz 1.00 ghz 1.50 ghz 2.00 ghz 2.50 ghz 3.00 ghz 3.50 ghz 4.00 ghz 4.50 ghz 5.00 ghz 5.50 ghz 6.00 ghz - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 18 20 22 24 26 28 30 32 34 compression (db) input power (dbm) - 40 c +25 c +105 c
F1956 rev 2 0 4 / 0 8 /2016 15 7 - bit 0.25 db wideband digital step attenuator t ypical o perating c onditions ( - 5 - ) input compression (+25 c, 4 ghz ) input ip3 vs attenuation [2 ghz] input ip3 vs frequency [attn=0 db, pin=+22 dbm] input compression (+25 c, 6 ghz) input ip3 vs attenuation [ 3.92 ghz] - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 24 25 26 27 28 29 30 31 32 33 34 compression (db) input power (dbm) 4 ghz 0 db 4 ghz 4 db 4 ghz 8 db 4 ghz 16 db 40 45 50 55 60 65 70 75 80 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input ip3 (dbm) attenuation (db) - 40 c / pin = 10 dbm/tone - 40 c / pin = 15 dbm/tone +25 c / pin = 10 dbm/tone +25 c / pin = 15 dbm/tone +105 c / pin = 10 dbm/tone +105 c / pin = 15 dbm/tone 40 45 50 55 60 65 70 75 80 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 input ip3 (dbm) frequency (ghz) iip3 - hs iip3 - ls - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0.0 0.1 0.2 0.3 0.4 0.5 24 25 26 27 28 29 30 31 32 33 34 compression (db) input power (dbm) 6 ghz 0 db 6 ghz 4 db 6 ghz 8 db 6 ghz 16 db 40 45 50 55 60 65 70 75 80 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input ip3 (dbm) attenuation (db)
F1956 7 - bit 0.25 db wideband digital step attenuator 16 rev 2 0 4 / 0 8 /2016 p ackage d rawing 5mm x 5mm 32 - pin tqfn), use exposed pad (epad) option p1
F1956 rev 2 0 4 / 0 8 /2016 17 7 - bit 0.25 db wideband digital step attenuator l and p attern d imension p in d iagram f 1 9 5 6 e x p o s e d p a d ( g n d ) 1 2 3 4 5 6 7 8 n c v d d v _ m o d e a 0 g n d g n d r f 1 g n d c l k l e a 1 a 2 n c g n d r f 2 g n d g n d g n d g n d g n d g n d g n d g n d g n d d 0 d 1 d 2 d 3 d 4 d 5 d 6 d a t a 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 t o p v i e w ( l o o k i n g t h r o u g h t h e t o p o f t h e p a c k a g e )
F1956 7 - bit 0.25 db wideband digital step attenuator 18 rev 2 0 4 / 0 8 /2016 p in d escription pin name function 1 dnc this pin must be left open. 2 vdd main supply. use 3.3 v or 5 v. bypass capacitor as clo se to pin as possible. 3 v mode 1 logic low for parallel mode. logic high or nc for serial mode. 4 a0 2 address bit a0 connection. 5 gnd connect directly to paddle ground or as close as possible to pin with thru via. this pin is not internally connec ted 6 gnd connect directly to paddle ground or as close as possible to pin with thru via. 7 rf1 3 device rf input or output (bi - directional). ac couple to this pin unless 0v dc. 8 C 17 gnd connect each pin directly to paddle ground or as close as possib le to pin with thru vias. 18 rf2 3 device rf input or output (bi - directional). ac couple to this pin unless 0v dc. 19 gnd connect directly to paddle ground or as close as possible to pin with thru via. 20 nc no internal connection. these pins can be le ft unconnected, voltage applied, or connected to ground (recommended). 21 a2 2 address bit a2 connection 22 a1 2 address bit a1 connection. 23 le 1 serial interface latch enable input. 24 clk 1 serial interface clock input. 25 data 1 serial interface dat a input. 26 d6 1 parallel control bit, 16 db. ground pin if not used. 27 d5 1 parallel control bit, 8 db. ground pin if not used. 28 d4 1 parallel control bit, 4 db. ground pin if not used. 29 d3 1 parallel control bit, 2 db. ground pin if not used. 30 d2 1 parallel control bit, 1 db. ground pin if not used. 31 d1 1 parallel control bit, 0.5 db. ground pin if not used. 32 d0 1 parallel control bit, 0.25 db. ground pin if not used. ep exposed paddle connect to ground with multiple vias for good thermal and rf performance.
F1956 rev 2 0 4 / 0 8 /2016 19 7 - bit 0.25 db wideband digital step attenuator e v k it p icture
F1956 7 - bit 0.25 db wideband digital step attenuator 20 rev 2 0 4 / 0 8 /2016 evk it / a pplications c ircuit c15 c14 r15 r16 vdd j6 1 3 4 5 2 c17 c18 j10 header 1x2 1 2 j7 header 1x2 1 2 vdd vdd j8 1 3 4 5 2 tp1 1 j1 header 12 1 2 3 4 5 6 7 8 9 10 11 12 c19 c20 u1 F1956 nc 1 vdd 2 v_mode 3 a0 4 gnd 5 gnd 6 rf1 7 gnd 8 gnd 9 gnd 10 gnd 11 gnd 12 gnd 13 gnd 14 gnd 15 gnd 16 clk 24 le 23 a1 22 a2 21 nc 20 gnd 19 rf2 18 gnd 17 d0 32 d1 31 d2 30 d3 29 d4 28 d5 27 d6 26 data 25 pad 33 j2 1 3 4 5 2 r1 c1 r2 c2 r17 r3 c3 r4 c4 r5 c5 r6 c6 r7 c7 r8 c8 r9 c9 r10 c10 r15 - 6 kohms 1% r16 - 10 kohms 1% r11 c11 j11 header 1x2 1 2 sw1 10 pin dip swtich 10 9 8 7 6 5 4 3 2 1 12 11 j3 header 1x2 1 2 j4 1 3 4 5 2 c21 c22 j5 header 4 1 2 3 4 j12 1 3 4 5 2 j9 header 1x2 1 2 j13 1 3 4 5 2 thru cal r12 r13 r14 c16
F1956 rev 2 0 4 / 0 8 /2016 21 7 - bit 0.25 db wideband digital step attenuator evk it bom (r ev 2) item # part reference qty description mfr. part # mfr. 1 c1 - c11, c14, c15, c16 14 100 pf 5%, 50 v, c0g ceramic capacitor (0402) grm1555c1h101j murata 2 c18, c20, c2 2 3 1000 pf 5%, 50 v, c0g ceramic capacitor (0402) grm1555c1h102j murata 3 c17, c19, c21 3 10 nf 5%, 50 v, x7r ceramic capacitor (0603) grm188r71h103j murata 4 r17 1 0 resistors (0402) erj - 2ge0r00x panasonic 5 r1 - r14 14 100 1%, 1/10 w, resistor (0402) erj - 2rkf1000x panasonic 6 r15 1 6.98 k 5%, 1/10 w, resistor (0402) erj - 2rkf6981x panasonic 7 r16 1 10 k 1%, 1/10 w, resistor (0402) erj - 2rkf1002x panasonic 8 j3, j7, j9, j10, j11 5 conn header vert sgl 2 x 1 pos gold 961102 - 6404 - ar 3m 9 j5 1 conn header vert sgl 4 x 1 pos gold 961104 - 6404 - ar 3m 10 j1 1 conn header vert sgl 12 x 1 pos gold 961112 - 6404 - ar 3m 11 j2, j4, j6, j8, j12, j13 6 edge launch sma (0.37 5 inch pitch ground, tab) 142 - 0701 - 851 emerson johnson 12 sw1 1 switch 10 position dip switch kat1110e e - switch 13 u1 1 dsa F1956 idt 14 1 printed circuit board f1955 evkit rev 02 idt t op m arkings i d t f 1 9 5 6 n b g i z a 1 5 1 5 g p a r t n u m b e r d a t e c o d e [ y y w w ] ( w e e k 1 5 o f 2 0 1 5 ) a s m t e s t s t e p a s s e m b l e r c o d e q 2 0 a 0 0 6 m y l o t c o d e
F1956 7 - bit 0.25 db wideband digital step attenuator 22 rev 2 0 4 / 0 8 /2016 a pplications i nformat ion power supplies a common v dd power supply should be used for all pins requiring dc power. all supply pins should be bypassed with external capacitors to minimize noise and fast transients. supply noise can degrade noise figure and fast transients can t rigger esd clamps and cause them to fail. supply voltage change or transients should have a slew rate smaller than 1v/20us. in addition, all control pins should remain at 0v (+/ - 0.3v) while the supply voltage ramps or while it returns to zero. digital pi n voltage & resistance values the following table provides open - circuit dc voltage referenced to ground and resistance values for each of the control pins listed. pin name open circuit dc voltage internal connection 3 v mode 2.5 v 100 k? pullup resistor t 100 k? resistor to gnd 100 k? pullup resistor to C C 100 k? pullup resistor to
F1956 corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1 - 800 - 345 - 7015 or 408 - 284 - 8200 fax: 408 - 28 4 - 2775 www.idt.com tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idts sole discretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. the information contained herein is provided without representati on or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idts products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idts products are not intended for use in applications involving extreme environmental conditions or in life suppo rt systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner d oes so at their own risk, absent an express, w ritten agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respec tive third party owners. copyright ? 2016 . integrated device technology, inc. all rights reserved. 7 - bit 0.25 db wideband digital step attenuator 23 rev 2 0 4 / 0 8 / 2016 r evision h is tory s heet rev date page description of change o 2015 - may - 22 initial release 1 2015 - sep - 29 2 datasheet format update added maximum average power rating 2 2016 - apr - 01 maximum operating frequency changed to 6 ghz . added curves showing performance at hi gher frequencies.

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