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ds26303d k 3.3v, e1/t1/j1, short-haul, octal liu design kit general description www.maxim-ic.com the DS26303DK is a fully integrated design kit for the ds26303 3.3v, 8-port, e1/t1/j1 line interface unit (liu). this design kit contains all the necessary circuitry to evaluate the ds26303 in all modes of operation. the design kit also includes an on-board microprocessor to run real-time code for further part evaluation. design kit contents DS26303DK board 5v ac/dc adapter 3ft usb cable download: chipview software DS26303DK.def definition files DS26303DK data sheet ordering information part description DS26303DK ds26303 design kit board features expedites new designs by eliminating first- pass prototyping demonstrates key functions of the ds26303 includes ds26303 x 8-port liu, transformers, 75 ? bnc connectors, rj-48 connectors, and termination passives communicates directly with any pc with a usb or rs-232 serial interface high-level windows?-based software provides visual access to all registers software-controlled (register) mapped configuration switches facilitate real-time clock and signal routing precision test points for all clocks and signals on-board t1 and e1 crystal oscillators for stable clock generation on-board bert for testing and pattern generation windows is a registered trademark of microsoft corp. 1 of 43 rev: 101105 downloaded from: http:///
ds26303 design kit table of contents componen t list ................................................................................................................. ....3 board floor plan................................................................................................................ .6 basic op eration................................................................................................................ ....7 hardware conf iguration ................................................................................................7 q uick s tart (h ardware s ettings s ingle p ower s upply )............................................................... 7 jtag c onfiguration ............................................................................................................................. 7 table 1. jtag conn ector (j6) pinout............................................................................................ ................... 7 figure 1. ds26303d k jtag chain ................................................................................................. ................. 8 a ddress /d ata b us c onnector ............................................................................................................. 8 table 2. address/da ta connec tor pinout ......................................................................................... ................ 8 t elecom c lock and d ata t est p oints ................................................................................................. 9 table 3. telecom connecto r pinout .............................................................................................. ................... 9 o n -b oard b it e rror -r ate t ester (bert) .......................................................................................... 9 table 4. bert c onnector pinout ................................................................................................. .................... 9 prom spi c onfiguration ................................................................................................................... 10 figure 2. spi timing di agram ................................................................................................... ..................... 10 figure 3. spi config uration with prom .......................................................................................... ............... 11 table 5. confi guration memory .................................................................................................. .................... 11 software conf iguration ...............................................................................................12 q uick s tart (s oftware c hip v iew ) .................................................................................................. 12 memory map..................................................................................................................... .....12 table 6. DS26303DK re lative addr ess map........................................................................................ .......... 12 table 7. general-purpos e fpga memo ry map....................................................................................... ....... 12 id regis ters................................................................................................................... .......13 control re gisters ............................................................................................................13 ds26303 info rmation..........................................................................................................21 DS26303DK info rmation .....................................................................................................21 technical su pport ............................................................................................................21 schema tics ..................................................................................................................... ......21 2 of 43 downloaded from: http:///
ds26303 design kit component list designation qty description supplier/ part number c1, c4, c6, c7, c18, c24, c26, c34, c36, c37, c38, c41, c43C c47, c49, c50, c51, c53Cc59, c61Cc83, c85, c86, c90 53 0.1 f 20%, 16v x7r ceramic capacitors (0603) avx 0603yc104mat c2, c3, c22, c30, c35, c40, c42, c48, c52, c60, c84, c88, c89 13 1 f 10%, 16v ceramic capacitors (1206) panasonic ecj-3yb1c105k c5, c9, c19, c21, c27, c28, c87 7 10 f 20%, 10v ceramic capacitors (1206) panasonic ecj-3yb1a106m c8 1 6.8 f 10%, 6.3v x5r ceramic capacitor (1206) panasonic ecj-3yb0j685k c10Cc17 8 470pf 10%, 100v ceramic capacitors (0603) panasonic ecj-1vb2a471k c20, c23, c25, c91, c92 5 68 f 20%, 16v tantalum capacitors (d case) panasonic ecs-t1cd686r c29, c31, c39 3 22pf 5%, 25v ceramic capacitors (0603) avx 06033a220jat c32, c33 2 10pf 5%, 50v ceramic capacitors (1206) (tall case) phycomp 1206cg100j9b200 d1, d12 2 green leds (smd) panasonic ln1351c d2Cd11 10 red leds (smd) panasonic ln1251c d13, d14, d15 3 1a, 40v schottky diodes international rectifier 10bq040 h1Ch4 4 kit, 4-40 hardware 0.75 nylon standoff and 0.25 nylon screw not applicable 4-40kit2 j1 1 40-pin terminal strip (dual row, vertical) samtec tsw-120-07-t-d j2 1 2.1mm/5.5mm connector power jack, right-angle pc board mount; closed frame, high current, 24v dc at 5a cui, inc. pj-002ah j3 1 black, single right angle (type b) molex not applicable j4 1 db9 right-angle connector (short case) amp 788750-2 j5, j7, j8, j21Cj36 19 5-pin smb connectors 50 ? , vertical, gold amp 413990-1 j6, j9Cj17 10 14-pin headers (dual row, vertical) samtec tsw-107-14-t-d j18, j19, j20 3 100-mil 3-position jumpers samtec not applicable j37Cj44 8 2-pin headers, 0.100in centers (vertical) samtec tsw-102-07-t-s j45, j46 2 8-pin 4-port rj45 jacks (right angle) molex 43223-8140 l1 1 1.0 h 20%, 2-pin smt inductor coiltronics up1b-1r0 3 of 43 downloaded from: http:///
ds26303 design kit 4 of 43 designation qty description supplier/ part number r1, r58, r87 3 resistors (0603) do not populate r2, r14Cr26, r28, r32Cr43, r46C r50, r52, r54C r57, r63Cr66, r68, r69, r71, r72, r73, r76, r77, r82, r85, r86, r88, r91, r93, r96, r97, r130 57 10k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj103v r3Cr9, r11, r12, r13, r29, r31, r44, r45, r60, r61, r62, r78, r79, r94, r95, r98Cr102, r104, r117, r120, r121, r124Cr129 36 33 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj330v r10 1 22k ? 5%, 1/16w resistor (0603) panasonic erj-3geyj223v r27, r67, r70, r74, r75, r80, r81, r83, r84, r89, r90, r123 12 330 ? 5%, 1/16w resistors (0603) panasonic erj-3geyj331v r30, r59 2 15k ? 5%, 1/16w resistors (0603) panasonic erj-3geyj153v r51 1 resistor (1206) do not populate r53 1 470 ? 5%, 1/16w resistor (0603) panasonic erj-3geyj471v r92 1 51 ? 5%, 1/16w resistor (0603) panasonic erj-3geyj510v r103, r105Cr116, r118, r119, r122 16 60.4 ? 1%, 1/16w resistors (0603) panasonic erj-3ekf60r4v sw2, sw6 2 4-pin single-pole switch panasonic evqpae04m sw3, sw4, sw5, sw7 4 6-pin slide switches (dpdt, through hole) tyco electronics ssa22 t1, t2 2 transformers (1:2 count transmitter/1:1 count receiver) (40-pin wide so, -40 c to +85 c) pulse engineering t1114 u1 1 8-bit fifo usb uart (32-pin lqfp) ftdi ft245bm u2 1 mcore microcontroller (144-pin lqfp) motorola mmc2107pv u3, u11 2 128k x 8 sram (32-pin so) cypress cy62128vl-70sc u4 1 ds2174 ebert (44-pin plcc, 0 c to +70 c) dallas semiconductor ds2174q u5 1 spartan-ii 2.5v fpga, 200k gate (256-pin bga) xilinx xc2s200-5fg256c u6 1 3.3v, e1/t1/j1 long-haul octal liu (144-pin elqfp, 0 c to +70 c) dallas semiconductor ds26303l downloaded from: http:///
ds26303 design kit 5 of 43 designation qty description supplier/ part number u7 1 prom for fpga (44-pin tqfp) xilinx xc18v02vq44c u8 1 dual rs-232 transmitter/receiver (150-mil, 16-pin so) dallas semiconductor ds232ar u9, u12 2 high-speed buffers fairchild semiconductor nc7sz86 u10, u18 2 1.5w, 3.3v or adj, 1a linear regulators (16-pin tssop-ep) maxim max1793eue-33 u13, u15 2 hex inverters (14-pin so) toshiba tc74hc04afn u14 1 quad 2-input nand gate (14-pin so) toshiba tc74hc00afn u16 1 switch debouncer (4-pin sot143) maxim max6816eus-t u17 1 2.5v or adj linear regulator (8-pin max/so) maxim max1792eua25 u19 1 platform flash in-system programmable configuration prom (2mb, 20-pin tssop) xilinx xcf02svo20c x1 1 6.00mhz low-profile crystal pletronics lp49-26-6.00m x2 1 8.000mhz low-profile crystal ecliptek corp. ec1-8.000m y1 1 oscillator, crystal clock 5v, 2.048mhz saronix nth039a-2.0480 y2 1 oscillator, crystal clock 5v, 1.544mhz saronix nth039a-1.5440 downloaded from: http:///
ds26303 design kit 6 of 43 board floorplan serial con liu pwr jumper user switches rj48 ports 5C8 rj48 ports 1C4 xfmr xfmr ports 1C4 ports 5C8 tclk, rclk, rlos tpos, rpos, tneg, rneg tclk, rclk, rlos tpos, rpos, tneg, rneg bert con ds2174 bert los led flash prom los led jtag con usb tx/rx clk a teclk user bnc usb con address/data sram sram ds26303 fpga tx/rx clock, data switch/mux rst board on-board c osc t1 osc e1 5v pwr downloaded from: http:///
ds26303 design kit 7 of 43 basic operation this design kit relies upon several supporting files, which are available for downloading on our website at www.maxim-ic.com/DS26303DK . the support files are used with an evaluation program called chipview, which is available for download at www.maxim-ic.com/telecom . hardware configuration quick start (hardware settingssingle power supply) ? for single power-supply operation, short jumpers j18, j19, and j20 between the 3.3v pin and the vliu pin. this connects vdd of the ds26303 to the 3.3v supply on the design kit. ? ensure that the flash switch (sw3) is in the run position. ? ensure that the fpga switch (sw5) is in the on position. ? ensure that the spi/prom switch (sw7) is in the off position. ? if using the serial port, connect a rs-232 se rial cable from DS26303DK (j4) to the pc. ? if using the usb port, connect a usb cable from DS26303DK (j3) to the pc. ? connect ac/dc adapter with an ac power source and the DS26303DK (j2). pwr led should be on. jtag configuration the jtag chain is controlled by the connector jtag con (j6) and two on-board switches: flash (sw3) and once/jtag (sw4). depending on the f unction, such as programming the internal microcontroller flash or performing boundary scan operations, the jtag con conn ector can be used and the switches can be configured to accomplish the desired task. for information on programm ing the internal flash of the on-board microcontroller, refer to the mmc2107 microcontroller user manual and board schematic. for most purposes, having the complete jtag chain is sufficient. figure 1 shows the complete chain as well as what order the devices appear during boundary scan. table 1 shows the pinout of the jtag connector. connect any jtag cable to the connector to perform all operations. note the jtag chain changes depending on the switch sw4. the once location of sw4 is used for programming the on-board microcontroller only. table 1. jtag conn ector (j6) pinout pin name 1 jtdi 2, 4, 6, 7 gnd 3 jtdo 5 jtclk 8 align key 9 brd rst 10 jtms 11 brd v3.3 12 jde 13 n.c. 14 jtrst downloaded from: http:///
ds26303 design kit 8 of 43 figure 1. ds26303d k jtag chain address/data bus connector the DS26303DK has a connector (j1) to monitor all local bus activity for the design kit. all the signals can be captured with a high-impedance probe and displayed on an oscilloscope or logic analyzer. note: if the fpga switch (sw5) is in the off position, the on-board microcontroller will no l onger drive any data onto the local bus. therefore, the user can now connect the local bus of the ds26303 into another system without making any modifications to the hardware. see table 2 for specific pin information for connector j1. table 2. address/data connector pinout pin name function pin name function 1 a8 local address bit 8 2 d0 local data bit 0 3 a7 local address bit 7 4 d1 local data bit 1 5 a6 local address bit 6 6 d2 local data bit 2 7 a5 local address bit 5 8 d3 local data bit 3 9 a4 local address bit 4 10 d4 local data bit 4 11 a3 local address bit 3 12 d5 local data bit 5 13 a2 local address bit 2 14 d6 local data bit 6 15 a1 local address bit 1 16 d7 local data bit 7 17 a0 local address bit 0 18 clke spi clock edge select 19 mux mux 20 rdy ready handshake from liu 21 csfpga chip select fpga 22 oe output enable liu 23 csbert chip select ds2174 24 motel motorola/intel select 25 csliu chip select ds26303 26 int interrupt for ds26303 27 aleliu address latch enable 28 fpgaen fpga enable pin 29 rd read signal 30 uin1 user input 1 31 wr write signal 32 uin2 user input 2 33 modesel mode select 34, 36 3.3v board 3.3v 35 not used 37C40 gnd ground on-board c flash mem for fpga gen fpga flash mem for spi ds26303 (u2) (u19) (u5) jtdo jtdi jtclk jtms (u6) (u7) sw4 jtag on-board c (u2) jtdo jtdi jtclk jtms once sw4 downloaded from: http:///
ds26303 design kit 9 of 43 telecom clock and data test points the DS26303DK has high-impedance test points for all the telecom signals that are related to the liu. these signals are split up by port number and marked with easy to read silkscreen labels. table 3 shows the telecom connector for port 1. the pinout for this connector is repeated for all 8 ports. table 3. telecom connector pinout pin name function 1 tclk transmit clock input 2, 4, 6, 8, 10, 12, 14 gnd ground 3 rclk receive clock output 5 tpos transmit positive data input 7 rpos receive positive data output 9 tneg transmit negative data input 11 rneg receive positive data output 13 rlos receive loss-of-signal output note that the input signals in the telecom connector go from the connector to the on-board fpga, then to the ds26303. the fpga was designed to perform specific sign al routing functions such as looping back rpos to tpos on a particular port or transferring data from t he on-board bert. if you are using user-defined data and drive the signal on the connector, be sure to tri-state the input signal in the fpga. failure to do so could cause damage to the fpga ! on-board bit error-rate tester (bert) the DS26303DK has an on-board bit error-rate tester (bert) to generate and detect errors in either pseudorandom or user-defined patterns. the bert on t he DS26303DK is the ds2174. a header for the relevant signals related to the bert is located on the board (j17). see table 4 for the pinout of the bert connector. the bert signals are routed into the fpga and can be muxed into any of the 8 ds26303 liu ports under software control. for all questions concerning t he operation of the on-board bert, refe r to the device data sheet available online at www.maxim-ic.com/telecom . if you are using user-defined data and driver the signal on the connector, be sure to tri-state the input signal in the fpga. failure to do so could cause damage to the fpga! table 4. bert connector pinout pin name function 1 tclk_en bert tclk enable 2, 4, 6, 8, 10, 12, 14 gnd ground 3 tclkin bert tclk input 5 tclko bert tclk output 7 rclkin bert rclk input 9 rclken bert rclk enable 11 tdat bert tdat output 13 rdat bert rdat input downloaded from: http:///
ds26303 design kit 10 of 43 prom spi configuration in software mode, it is possible to configure the ds26303 using a parallel interface or a serial peripheral interface (spi). most advanced microcontrollers have both a paralle l interface and spi interface such as the microcontroller on the DS26303DK. the command you send to the microc ontroller through either the usb or serial port determines if that data is placed on the paral lel or spi bus. refer to the data sheet for chipview on the particular commands required to switch data ports. a unique feature with the spi port is that a prom can be used to provide the liu with the specific data needed for configuration. if the data in the prom is formatted a ce rtain way, it can seem as the prom is acting like a controller with a spi interface in master mode. the most common proms to use for this type of applicatio n are those with an internal address accumulator. this feature for the prom is important bec ause the device must automatically jump to the next available address in the configuration memory. the xilinx xc18v00 device family is a byte-wide nonvolatile memory with an autoincrement address function. the family of devices is available in 1mb, 2mb, and 4mb densities. the prom is also useful because the device can perform in-circu it programming with the jtag port. refer the data sheet for the xc18v00 for the jtag codes for programming the configuration memory. figure 2 shows a general relationship of the timing for a spi bus. for this case, all data is clocked into the slave device on the rising edge of sclk. this f eature can be configurable on the ds26303. figure 2. spi timing diagram 1234567891 0 1 11 21 31 41 51 6 sclk csb 0 a 1 a 2 a 3 a 4 a 5 a 6 x (adrs msb) sdi sdo d1 d2 d3 d4 d5 d7 (lsb) (msb) do d6 (lsb) write access enabled figure 3 shows a simplified diagram of the xc18v00 device a nd the ds26303 in spi (serial) mode. notice a few key points about this diagram. first, the clk for the xc18v00 is the mclk for the liu, but this is not the sclk for the spi interface. the sclk ca n be programmed as needed. see table 5 for an example of the memory map. second, the programming for this device begins when oe on the xc18v00 goes high. therefore, consideration must be taken if some delay is necessary. generally, it is sufficient for the oe pin to be connected to some power- up delay device. the oe delay is not necessary on this dk. downloaded from: http:///
ds26303 design kit 11 of 43 figure 3. spi configuration with prom (u6) ds26303 sdi sclk cs d5 d6 d7 c e clk mclk ( liu ) 3.3v delay oe jtdo jtdi jtms jtclk (u12) xc18v00 cfg prom table 5. configuration memory d7 d6 d5 d4 d3 d2 d1 d0 address csb sclk sdi x x x x x 0x00 1 0 0 start of write cycle 0x01 0 0 0 0x02 0 1 0 bit a0 (always a 0 for a write) 0x03 0 0 1 0x04 0 1 1 bit a1 0x05 0 0 0 0x06 0 1 0 bit a2 0x07 0 0 0 0x08 0 1 0 bit a3 0x09 0 0 0 0x0a 0 1 0 bit a4 0x0b 0 0 0 0x0c 0 1 0 bit a5 0x0d 0 0 0 0x0e 0 1 0 bit a6 0x0f 0 0 0 0x10 0 1 0 bit a7 0x11 0 0 0 0x12 0 1 0 bit d0 (lsb) 0x13 0 0 1 0x14 0 1 1 bit d1 0x15 0 0 1 0x16 0 1 1 bit d2 0x17 0 0 0 0x18 0 1 0 bit d3 0x19 0 0 0 0x1a 0 1 0 bit d4 0x1b 0 0 1 0x1c 0 1 1 bit d5 0x1d 0 0 1 0x1e 0 1 1 bit d6 0x1f 0 0 0 0x20 0 1 0 bit d7 0x21 1 0 x 0x22 1 x x end of write cycle downloaded from: http:///
ds26303 design kit 12 of 43 software configuration quick start (softwarechipview) ? perform steps in the quick st art (hardware configuration). ? load chipview software. ? select com port. ? select register view. ? from the programs menu, launch the host application named chipview.exe. if the default installation options were used, click the start button on the windows toolbar and select programs -> chipview -> chipview. ? load the DS26303DK.def file. ? make sure that all the register settings are correc t for the proper function desired for the DS26303DK. ? refer to the ds26303 data sheet for all questions pertaining to device functionality. memory map the on-board microcontroller is configured to start the user address space at 0x81000000. all offsets given below are relative to the beginning of the user address space. table 6. DS26303DK relative address map ref des device offset u5 general-purpose fpga tx/rx clock, data switch/mux 0x0000 u4 ds2174 bert 0x1000 u6 ds26303 8-port t1/e1/j1 liu 0x2000 all device registers can be easily m odified using the chipview.exe hos t-based user-interface software. table 7. general-purpose fpga memory map offset register name type description 0x00 brdid read-only board id 0x02 dsidh read-only dallas extended id upper nibble 0x03 dsidm read-only dallas extended id middle nibble 0x04 dsidl read-only dallas extended id lower nibble 0x05 brdrev read-only board rev 0x06 asmrev read-only assembly rev 0x07 fpgarev read-only fpga firmware rev 0x08 ctrl1 control control register 1 0x0a absp control address bank select pointer 0x0b btclk control bert tclk input 0x0c brclk control bert rclk input 0x0d brdat control bert rdat input 0x10 tclk control indirect regi ster for tclk source control 0x11 tpos control indirect regi ster for tpos source control 0x12 tneg control indirect regi ster for tpos source control downloaded from: http:///
ds26303 design kit 13 of 43 id registers bid: board id (offset = 0x0000) bid is read-only with a value of 0xd. xbidh: high nibble extended board id (offset = 0x0002) xbidh is read-only with a value of 0x0. xbidm: middle nibble extended board id (offset = 0x0003) xbidm is read-only with a value of 0x1. xbidl: low nibble extended board id (offset = 0x0004) xbidl is read-only with a value of 0x6. brev: board fab revision (offset = 0x0005) brev is read-only and displays the current fab revision. arev: board assembly revi sion (offset = 0x0006) arev is read-only and displays the current assembly revision. prev: fpga revision (offset = 0x0007) prev is read-only and displays the current pld firmware revision. control registers register name: ctrl_1 register description: DS26303DK fpga control register 1 register offset: 0x08 bit # 7 6 5 4 3 2 1 0 name int303 enrlos1 clke spi_swap spi oe mclk1 mclk0 bit 7: int303. this bit indicates the status of the int303 line. if int303 = low, there is no har dware interrupt on the ds26303. if int303 = high, there is a hardware interrupt on the ds26303. bit 6: enrlos1. this bit enables the rlos1 led. this should not be enabled when driving teclk from the ds26303. if enrlos1 = low, the rlos1 led is not enabled. if enrlos1 = high, the rlos1 led is enabled and lights when rlos1 is high. bit 5: clke. this bit sets the clke pin on the ds26303. this is only active when spi (bit 0) is high. if spi (bit 0) is low, clke is always low. if clke = low, sdo is clocked out on the rising edge of sclk. if clke = high, sdo is clocked out on the falling edge of sclk. bit 4: spi_swap. this bit sets the bswp/a5 pin on the ds26303. th is is only active when spi (bit 0) is high. if spi_swap = low, the spi bus is lsb first. if spi_swap = high, the spi bus is msb first. bit 3: spi. this bit sets up the fpga to use serial mode. this bit also changes the mode pin on the ds26303. if spi = low, the parallel bus is used for all read/ write access. this also sets the mode pin on the ds26303 to logic 1. if spi = high, the spi bus is used for all read/write access. this also sets the mode pin on the ds26303 to logic 0. bit 2: oe. this bit controls the oe pin to the ds26303. bits 1 and 0: mclk1 and mclk0. these bits control the mclk pin to the ds26303. mclk1 mclk0 description of mclk 0 0 mclk = high-impedance mode 0 1 mclk = on-board t1 oscillator 1 0 mclk = on-board e1 oscillator 1 1 mclk = user clock input downloaded from: http:///
ds26303 design kit 14 of 43 register name: absp register description: address bank swap pointer register offset: 0x0a bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 bits 7 to 0: d7 to d0. these bits control the address bank for address 0x10 (tclk n), 0x11 (tpos), and 0x12 (tneg). absp description 0x00 bank address value for port 1 0x01 bank address value for port 2 0x02 bank address value for port 3 0x03 bank address value for port 4 0x04 bank address value for port 5 0x05 bank address value for port 6 0x06 bank address value for port 7 0x07 bank address value for port 8 downloaded from: http:///
ds26303 design kit 15 of 43 register name: btclk register description: bert tclk source register offset: 0x0b bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 bits 7 to 0: d7 to d0. these bits control the source of the tclk for the bert. btclk description 0x00 rclk port 1 0x01 rclk port 2 0x02 rclk port 3 0x03 rclk port 4 0x04 rclk port 5 0x05 rclk port 6 0x06 rclk port 7 0x07 rclk port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 tclkbert out 0x16C0xff hi-z downloaded from: http:///
ds26303 design kit 16 of 43 register name: brclk register description: bert rclk source register offset: 0x0c bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 bits 7 to 0: d7 to d0. these bits control the source of the rclk for the bert. btclk description 0x00 rclk port 1 0x01 rclk port 2 0x02 rclk port 3 0x03 rclk port 4 0x04 rclk port 5 0x05 rclk port 6 0x06 rclk port 7 0x07 rclk port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 tclkbert out 0x16C0xff hi-z downloaded from: http:///
ds26303 design kit 17 of 43 register name: brdat register description: bert rdat source register offset: 0x0d bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 bits 7 to 0: d7 to d0. these bits control the source of the rdat fo r the bert. note that the ds26303 must be in single-rail mode for bert to function properly. brdat description 0x00 rpos port 1 0x01 rpos port 2 0x02 rpos port 3 0x03 rpos port 4 0x04 rpos port 5 0x05 rpos port 6 0x06 rpos port 7 0x07 rpos port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 tclkbert out 0x16C0xff hi-z downloaded from: http:///
ds26303 design kit 18 of 43 register name: tclk register description: port tclk source register offset: 0x10 bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 note: this is an indirect register that is re lated to absp (0x0a). see register description. bits 7 to 0: d7 to d0. these bits control the source of the port tclk for the ds26303. tclk description 0x00 rclk port 1 0x01 rclk port 2 0x02 rclk port 3 0x03 rclk port 4 0x04 rclk port 5 0x05 rclk port 6 0x06 rclk port 7 0x07 rclk port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 tclkbert out 0x16C0xff hi-z downloaded from: http:///
ds26303 design kit 19 of 43 register name: tpos register description: port tpos source register offset: 0x11 bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 note: this is an indirect register that is re lated to absp (0x0a). see register description. bits 7 to 0: d7 to d0. these bits control the source of the port tpos for the ds26303. tpos description 0x00 rpos port 1 0x01 rpos port 2 0x02 rpos port 3 0x03 rpos port 4 0x04 rpos port 5 0x05 rpos port 6 0x06 rpos port 7 0x07 rpos port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 tdatbert out 0x16C0xff hi-z downloaded from: http:///
ds26303 design kit register name: tneg register description: port tneg source register offset: 0x12 bit # 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 note: this is an indirect register that is re lated to absp (0x0a). see register description. bits 7 to 0: d7 to d0. these bits control the source of the port tneg for the ds26303. tneg description 0x00 rneg port 1 0x01 rneg port 2 0x02 rneg port 3 0x03 rneg port 4 0x04 rneg port 5 0x05 rneg port 6 0x06 rneg port 7 0x07 rneg port 8 0x08 hi-z 0x09 hi-z 0x0a hi-z 0x0b hi-z 0x0c hi-z 0x0d hi-z 0x0e hi-z 0x0f hi-z 0x10 1.544mhz on-board oscillator 0x11 2.048mhz on-board oscillator 0x12 user clock 0x13 clka ds26303 0x14 teclk ds26303 0x15 drive logic 0 0x16C0xff hi-z 20 of 43 downloaded from: http:///
ds26303 design kit 21 of 43 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxi m/dallas semiconductor reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2005 maxim integrated products ? printed usa the maxim logo is a registered trademark of maxim integrated products, inc. the dallas logo is a registered trademark of dallas semiconductor corporation. ds26303 information for more information about the ds26303, refer to the ds26303 data sheet available on our website at www.maxim-ic.com/ds26303 . DS26303DK information for more information about the DS26303DK including software downloads, go to www.maxim-ic.com/DS26303DK . technical support for additional technical support, e-mail your questions to telecom.support@dalsemi.com . schematics the DS26303DK schematics are featured in the following 22 pages. downloaded from: http:///
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