short form data sheet idt8v19n486-02nli june 21, 2013 1 ?2013 integrated device technology, inc. femtoclock ? ng jitter attenuator and ? clock synthesizer IDT8V19N486-02I the short form datasheet is intended to pr ovide an overview only. additional details are available from idt. contact informatio n may be found on the last page. general description IDT8V19N486-02I is a femtoclock ? ng jitter attenuator and clock synthesizer. together with t he idt8v19n476-01i external synthesizer, the device form a high -performance clock solution for conditioning and frequency/phase management of wireless base station radio equipment boards. the two-chip solution is optimized to deliver excellent phase noise performance. the device supports jesd204b subclass 0 and 1 clock implementations. the device is very flexible in programming of the output frequency and phase. a dual-stage pll architecture (the second stage is implemented in the idt8v19n476-01i) supports both jitter attenuation and frequency multiplication. the first stage pll uses an external vcxo for best possible noise characteristics. the device supports the clock generation of high-frequency clocks and low-frequency system reference signals (sysref). th e system reference signals are internally synchronized to the cloc k signals. delay functions exist for achieving alignment and contro lled phase delay between system reference and clock signals and to align/delay individual output signals. four clock inputs are available for redundancy purpose. all inputs are monitored for activity. priority-controlled auto-switching, manual switchover and hold-over is provided to handle clock input failure scenarios. auto-lock, individually programmable output frequency dividers and phase adjustment capabilities are added for flexibility. the device is configured through a 3-wire sp serial interface and reports lock and signal loss status in internal registers and optionally via an lock detect (nint) output. the device is packaged in a lead-free (rohs 6) 72-lead vfqfn package (IDT8V19N486-02I). the extend ed temperature range supports wireless infrastructure, telecommunication and networking end equipment requirements. the device is a member of the high-performance clock family from idt. features ? core timing unit for jesb204b wireless infrastructure clocks ? fourth generation femtoclock ? ng technology ? jitter attenuation and frequency multiplication ? use with the idt8v19n476-01i synthesizer ? nine differential configurable lvpecl/lvds clock outputs with a variable output amplitude ? seven differential lvds system reference (sysref) signal outputs ? synchronization between clock and system reference signals ? phase delay capabilities for alignm ent/delay of individual system reference signals ? individual output phase adjust ment resolution: 101.7ps ? individual output phase adjustment range in 128 steps (delay range encompasses one period of a 153.6mhz signal) ? supports input clocks of 153.6, 76.8, 307.2, 38.4 and 61.44mhz ? supports a 153.6mhz and 38.4mhz vcxo frequency ? output clocks frequencies: 1228. 8, 614.4, 307. 2 and 153.6mhz ? output clock frequency divider: 2, 4, 8 and 16 ? four redundant clock input compatible with lvpecl, lvds, lvcmos signals ? dedicated power-down features for reducing power consumption ? input clock monitoring, manual and auto-switch over ? holdover for temporary loss of input signal scenarios ? spi controlled system referenc e signal (sysref) generation ? first stage pll uses an external vcxo (153.6mhz) ? support of output power-down and output disable ? second stage pll uses an internal oscillator (2457.6mhz), implemented in the idt8v19n476-01i synthesizer ? clock output phase noise at 307.2mhz: ? 10hz offset: -57 dbc/hz ? 100hz offset: -89 dbc/hz ? 500hz offset: -114 dbc/hz ? 1khz offset: -116 dbc/hz ? 10khz offset: -121 dbc/hz ? 60khz offset: -121 dbc/hz ? 100khz offset: -126 dbc/hz ? 200khz offset: -131 dbc/hz ? 800khz offset: -148 dbc/hz ? 5mhz offset: - 153 dbc/hz ? 10mhz offset: - 153 dbc/hz ? status conditions with programmable functionality for loss-of-lock and loss of reference indication ? lock detect (nint) output for status change indication ? lvcmos/lvttl compatible spi serial interface ? 3.3v core and output supply mode ? supports 1.8v i/o logic levels for all control pins ? -40c to +85c ambient operating temperature ? lead-free (rohs 6) 72-lead vfqfn packaging, (10x10x0.85mm, 0.5mm pitch) the information presented herein represents a product that is deve lopmental or prototype. the noted characteristics are design targets. integrated device technologies, inc. (idt) reserves the right to change any circ uitry or specifications without notice.
idt8v19n486-02nli june 21, 2013 2 ?2013 integrated device technology, inc. IDT8V19N486-02I short form data sheet femtoclock ? ng jitter attenuator and clock synthesizer block diagram clk0 nclk0 clk1 nclk1 clk2 nclk2 clk3 nclk3 data spiclk nle nint qclk0 nqclk0 qref0 nqref0 qclk6 nqclk6 qref6 nqref6 qclk7 nqclk7 qclk8 nqclk8 spi slave controller register file n 0 ) 0 sysref 0 delay p v pfd v m v 153.6mhz or 38.4mhz nvcxo vcxo p f pfd f m f femtoclock ng 2457.6 mhz lfv filter clk 0 divider clock monitor and clock selector ? ? ? selection control holdover control ? ? ? 256, sysref control 1 0 bypass qlc nqlc inlc ninlc q nq idt8v19n476-01i IDT8V19N486-02I in nin qref 0 mux 512, 1024, 2048 n 6 ) 6 sysref 6 delay clk 6 divider qref 6 mux ? ? ? n 7 clk 7 divider n 8 clk 8 divider 1? 5 1? 5 n s
IDT8V19N486-02I short form data sheet femtoclock ? ng jitter attenuator and clock synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products ar e determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a gui de and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2013. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales netcom@idt.com +480-763-2056 we?ve got your timing solution
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