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1 ?2016 integrated device technology, inc revision a march 30, 2016 1 2 3 4 8 7 6 5 oe v dd gnd q4 clk_in q2 q3 q1 general description the 830154i-08 is an lvcmos, over-voltage tolerant clock fanout buffer targeted for clock generation in high-performance telecommunication, networking and computing applications. the device is optimized for low-skew clock distribution in low-voltage applications. the input over-voltage tolerance enables using this device in mixed-mode voltage applications. an output enable pin controls whether the outputs are in the active or high impedance state. guaranteed output skew characteristics make the 830154i-08 ideal for those applications demanding well defined performance and repeatability. the 830154i-08 is packaged in a small 8-tssop and in an 8-soic package. block diagram features ? low-skew 1:4 fanout buffer ? supports 3.3v, 2.5v, 1.8v and 1.5v power supplies ? lvcmos input and output levels ? 3.6v over-voltage tolerance at the clock and control inputs ? supports clock frequencies up to 160mhz ? lvcmos compatible control input for output disable ? output disabled to a high-impedance state ? -40c to 85c ambient operating temperature ? available in lead-free rohs 6 packages (8-tssop, 8-soic) clk_in oe q1 q2 q3 q4 pulldown pullup 830154agi-08 8-tssop 4.4mm x 3.0mm x 0.925mm package body g-package top view 830154ami-08 8-soic, 150 mil 3.9mm x 4.9mm x 1.375mm package body m-package top view pin assignments 830154i-08 data sheet over-voltage tolerant 1.5v, 1:4 fanout buffer
2 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function table table 3. oe configuration table note: oe is an asynchronous control. number name type description 1 clk_in input pulldown single-ended clock input. lvcmos interface levels. 2 q1 output single-ended clock output. lvcmos interface levels. 3 q2 output single-ended clock output. lvcmos interface levels. 4 q3 output single-ended clock output. lvcmos interface levels. 5 q4 output single-ended clock output. lvcmos interface levels. 6 gnd power power supply ground. 7v dd power power supply pin. 8 oe input pullup output enable pin. see table 3. lvcmos interface levels. symbol parameter test conditio ns minimum typi cal maximum units c in input capacitance 4pf c pd power dissipation capacitance v dd = 3.465v 14 pf v dd = 2.375v 13 pf v dd = 1.95v 13 pf v dd = 1.6v 12 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance v dd = 3.3v 5% 9 ? v dd = 2.5v 5% 10 ? v dd = 1.8v 0.15v 12 ? v dd = 1.5 0.1v 15 ? input operation oe 0 q[4:1] disabled (high-impedance) 1 (default) q[4:1] enabled
3 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operatio n of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4c. power supply dc characteristics, v dd = 1.8v 0.15v, t a = -40c to 85c table 4d. power supply dc characteristics, v dd = 1.5v 0.1v, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i 3.6v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ? ja 8 lead tssop 8 lead soic 121.5c/w (0 mps) 103c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v i ddq quiescent power supply current inputs open, outputs unloaded 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v i ddq quiescent power supply current inputs open, outputs unloaded 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.65 1.8 1.95 v i ddq quiescent power supply current inputs open, outputs unloaded 1 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.4 1.5 1.6 v i ddq quiescent power supply current inputs open, outputs unloaded 1 ma
4 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet table 4e. lvcmos dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4f. lvcmos dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4g. lvcmos dc characteristics, v dd = 1.8v 0.15v, t a = -40c to 85c symbol parameter test conditio ns minimum typic al maximum units v ih input high voltage 0.65 * v dd 3.6 v v il input low voltage -0.3 0.35 * v dd v i ih input high current clk_in v dd = v in = 3.465v 150 a oe v dd = v in = 3.465v 5 a i il input low current clk_in v dd = 3.465v, v in = 0v -5 a oe v dd = 3.465v, v in = 0v -150 a v oh output high voltage q[4:1] i oh = -12ma 2.6 v v ol output low voltage q[4:1] i ol = 12ma 0.5 v symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 0.65 * v dd 3.6 v v il input low voltage -0.3 0.35 * v dd v i ih input high current clk_in v dd = v in = 2.625v 150 a oe v dd = v in = 2.625v 5 a i il input low current clk_in v dd = 2.625v, v in = 0v -5 a oe v dd = 2.625v, v in = 0v -150 a v oh output high voltage q[4:1]] i oh = -12ma 1.8 v v ol output low voltage q[4:1] i ol = 12ma 0.5 v symbol parameter test conditio ns minimum typic al maximum units v ih input high voltage 0.65 * v dd 3.6 v v il input low voltage -0.3 0.35 * v dd v i ih input high current clk_in v dd = v in = 1.95v 150 a oe 5a i il input low current clk_in v dd = 1.95v, v in = 0v -5 a oe v dd = 1.95v, v in = 0v -150 a v oh output high voltage q[4:1] i oh = -6ma v dd ? 0.45 v v ol output low voltage q[4:1] i ol = 6ma 0.45 v
5 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet table 4h. lvcmos dc characteristics, v dd = 1.5v 0.1v, t a = -40c to 85c ac electrical characteristics table 5a. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when de vice is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note: characterized up to f out ? 150mhz. note 1: measured from the v dd /2 of the input to v dd /2 of the output. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v dd /2. note 4: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of in puts on each device, the outputs are measured at v dd /2. symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 0.65 * v dd 3.6 v v il input low voltage -0.3 0.35 * v dd v i ih input high current clk_in v dd = v in = 1.6v 150 a oe v dd = v in = 1.6v 5 a i il input low current clk_in v dd = 1.6v, v in = 0v -5 a oe v dd = 1.6v, v in = 0v -150 a v oh output high voltage q[4:1] i oh = -4ma 0.75 * v dd v v ol output low voltage q[4:1] i ol = 4ma 0.25 * v dd v symbol parameter test condition s minimum typical maximum units f out output frequency 160 mhz tp lh propagation delay (low to high transition); note 1 0.7 1.45 ns tp hl propagation delay (high to low transition); note 1 0.7 1.45 ns t plz, t phz disable time (active to high-impedance) 10 ns t pzl, t pzh enable time (high-impedance to disable) 10 ns tsk(o) output skew; note 2, 3 250 ps tsk(pp) part-to-part skew; note 2, 4 800 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 25mhz, integration range: 12khz - 5mhz 0.094 ps t r / t f output rise/fall time 10% to 90% 0.35 1.2 ns odc output duty cycle 48 52 %
6 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet table 5b. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when de vice is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note: characterized up to f out ? 150mhz. note 1: measured from the v dd /2 of the input to v dd /2 of the output. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v dd /2. note 4: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of in puts on each device, the outputs are measured at v dd /2. table 5c. ac characteristics, v dd = 1.8v 0.15v, t a = -40c to 85c for notes, see table 5b above. symbol parameter test condition s minimum typical maximum units f out output frequency 160 mhz tp lh propagation delay (low to high transition); note 1 0.8 1.7 ns tp hl propagation delay (high to low transition); note 1 0.8 1.7 ns t plz, t phz disable time (active to high-impedance) 10 ns t pzl, t pzh enable time (high-impedance to disable) 10 ns tsk(o) output skew; note 2, 3 250 ps tsk(pp) part-to-part skew; note 2, 4 800 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 25mhz, integration range: 12khz - 5mhz 0.076 ps t r / t f output rise/fall time 10% to 90% 0.35 1.2 ns odc output duty cycle 48 52 % symbol parameter test condition s minimum typical maximum units f out output frequency 160 mhz tp lh propagation delay (low to high transition); note 1 1.1 2.1 ns tp hl propagation delay (high to low transition); note 1 1.1 2.1 ns t plz, t phz disable time (active to high-impedance) 10 ns t pzl, t pzh enable time (high-impedance to disable) 10 ns tsk(o) output skew; note 2, 3 250 ps tsk(pp) part-to-part skew; note 2, 4 800 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 25mhz, integration range: 12khz - 5mhz 0.193 ps t r / t f output rise/fall time 0.63v to 1.17v 0.12 0.6 ns odc output duty cycle 47 53 %
7 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet table 5d. ac characteristics, v dd = 1.5v 0.1v, t a = -40c to 85c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when de vice is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. device will meet specifications after therma l equilibrium has been reached under these conditions. note: characterized up to f out ? 150mhz. note 1: measured from the v dd /2 of the input to v dd /2 of the output. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v dd /2. note 4: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequ ency and with equal load conditions. using the same type of in puts on each device, the outputs are measured at v dd /2. symbol parameter test condition s minimum typical maximum units f out output frequency 160 mhz tp lh propagation delay (low to high transition); note 1 1.5 2.7 ns tp hl propagation delay (high to low transition); note 1 1.5 2.7 ns t plz, t phz disable time (active to high-impedance) 10 ns t pzl, t pzh enable time (high-impedance to disable) 10 ns tsk(o) output skew; note 2, 3 250 ps tsk(pp) part-to-part skew; note 2, 4 800 ps t jit buffer additive phase jitter, rms; refer to additive phase jitter section 25mhz, integration range: 12khz - 5mhz 0.266 ps t r / t f output rise/fall time 0.525v to 0.975v 0.12 0.6 ns odc output duty cycle 47 53 %
8 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet additive phase jitter (1.5v output) the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator "ifr2042 10khz ? 56.4ghz low noise signal generator as external input to an agilent 8133a 3ghz pulse generator". additive phase jitter @ 25mhz 12khz to 5mhz = 0.266ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
9 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet parameter measureme nt information 3.3v output load ac test circuit 1.8v output load ac test circuit output skew 2.5v output load ac test circuit 1.5v output load ac test circuit part-to-part skew scope qx gnd v dd 1.65v5% -1.65v5% scope qx gnd v dd 0.9v0.075v -0.9v0.075v t sk(o) v dd 2 v dd 2 qx qy scope qx gnd v dd 1.25v5% -1.25v5% scope qx gnd v dd 0.75v0.05v -0.75v0.05v qx t sk(pp) v dd 2 v dd 2 part 1 part 2 qy
parameter measurement in formation, continued output enable/disable time 1.5v output rise/fall time 2.5v and 3.3v output rise/fall time output duty cycle/pulse width/period 1.8v output rise/fall time propagation delay v dd /2 v dd /2 v dd /2 v dd /2 v oh 0v v dd t dis t en output qx (see note) oe (high-level enabling) 0.525v 0.975v 0.975v 0.525v t r t f q1:q4 10% 90% 90% 10% t r t f q1:q4 q1:q4 0.63v 1.17v 1.17v 0.63v t r t f q1:q4 tp lh tp hl v dd 2 v dd 2 v dd 2 v dd 2 q1:q4 clk_in
11 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet applications information recommendations for u nused output pins outputs: lvcmos outputs all unused lvcmos outputs can be left floating. there should be no trace attached.
12 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet power considerations this section provides information on power dissipa tion and junction temperature for the 830154i-08. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the830154i-08 is the sum of the core power plus the power dissipation in the load(s). the follo wing is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.465v *1ma = 3.465mw total static power: = power (core) max = 3.465mw dynamic power dissipation at f out_max (160mhz) total power (160mhz) = [(c pd * n) * frequency * (v ddo ) 2 ] = [(14pf *4) * 160mhz * (3.465v) 2 ] = 107.6mw n = number of outputs total power = static power + dynamic power dissipation = 3.465mw + 107.6mw = 111.065mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and b ond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temp erature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 121. 5c/w per table 6a below. therefore, tj for an ambi ent temperature of 85c with all outputs switching is: 85c + 0.111w *121.5c/w = 98.5c. th is is below the limit of 125c. this calculation is only an example. tj will obviously vary depen ding on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6a. thermal resistance ? ja for 8 lead tssop, forced convection table 6b. thermal resistance ? ja for 8 lead soic, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 121.5c/w 1 17.3c/w 115.3c/w ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 103c/w 94c/w 89c/w
13 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet reliability information table 7a. ? ja vs. air flow table for a 8 lead tssop table 7b. ? ja vs. air flow table for a 8 lead soic transistor count the transistor count for 830154i-08 is: 191 ? ja vs. air flow meter per second 012.5 multi-layer pcb, jedec standard test boards 121.5c/w 117.3c/w 115.3c/w ? ja vs. air flow meter per second 012.5 multi-layer pcb, jedec standard test boards 103c/w 94c/w 89c/w
14 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet package outline and package dimensions package outline - g suffix for 8 lead tssop table 8a. package dimensions for 8lead tssop reference document: jede c publication 95, mo-153 package outline - m suffix for 8 lead soic table 8b. package dimensions reference document: jede c publication 95, ms-012 all dimensions in millimeters symbol minimum maximum n 8 a 1.20 a1 0.5 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10 all dimensions in millimeters symbol minimum maximum n 8 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 8
15 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet ordering information table 9. ordering information part/order number marking packag e shipping packaging temperature 830154agi-08lf ai08l lead-f ree, 8 lead tssop tube -40 ? c to 85 ? c 830154agi-08lft ai08l lead-free, 8 lead tssop tape & reel -40 ? c to 85 ? c 830154ami-08lf 154ai08l lead-free, 8 lead soic tube -40 ? c to 85 ? c 830154AMI-08LFT 154ai08l lead-free, 8 lead soic tape & reel -40 ? c to 85 ? c
16 ?2016 integrated device technology, inc revision a march 30, 2016 830154i-08 data sheet revision history ] revision date description of change march 30, 2016 removed ics chip from general description. removed ics from part number where needed. ordering information - removed quantity from tape and reel and deleted the lf note below the table. updated data sheet header and footer.
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 830154i-08 data sheet

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