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1 high speed, dual channel, 6a, power mosfet driver with programmable delays ISL89166, isl89167, isl89168 the ISL89166, isl89167, and isl89168 are high-speed, 6a, dual channel mosfet drivers. these parts are similar to the isl89160, isl89161, isl89162 drivers but use the nc pins for programming the rising edge time delays of the outputs used for dead time control. as an alternative to using external rc circuits for time delays, the programmable delays on the rdta and rdtb pins allows the user to delay the rising edge of the respective outputs just by connecting an appropriate resistor value between these pins and ground. the accuracy and temper ature characteristics of the time delays are specified freeing the user of the need to select appropriate external resistors an d capacitors that traditionally are applied to the logic inputs to delay the output edges. at high switching frequencies, these mosfet drivers use very little internal bias currents. separate, non-overlapping drive circuits are used to drive each cmos output fet to prevent shoot-thru currents in the output stage. the start-up sequence is design to prevent unexpected glitches when v dd is being turned on or turned off. when v dd < ~1v, an internal 10k resistor between the outp ut and ground helps to keep the output voltage low. when ~1v uvlo, and after a short delay, the outputs now respond to the logic inputs. features ?typical on-resistance <1 ? specified miller plateau drive currents ? very low thermal impedance ( jc = 3c/w) ? hysteretic input logic levels for 3.3v cmos, 5v cmos, and ttl ? precision threshold inputs fo r optional time delays with external rc components ? instead of rc components for time delays, a resistor can be used to program delays ? 20ns rise and fall time driving a 10nf load. ? nc pins may be connected to ground or vdd for flexible pcb layout options applications ? synchronous rectifier (sr) driver ? switch mode power supplies ? motor drives, class d amplifiers, ups, inverters ? pulse transformer driver ? clock/line driver 8 6 7 1 4 3 2 5 epad v dd 4.7f rdtb rdta ina inb gnd outa outb figure 1. typical application 0 50 100 150 200 250 300 350 0 5 10 15 20 delay (ns) rdt (2k to 20k) figure 2. programmable time delays -40c (worst case) +25c (typical) +125c (worst case) caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2011-2013. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. february 26, 2013 fn7720.2
ISL89166, isl89167, isl89168 2 fn7720.2 february 26, 2013 block diagram outx v dd inx gnd for clarity, only one channel is shown epad for proper thermal and electrical performance, the epad must be connected to the pcb ground plane. separate fet drives, with non-overlapping outputs, prevent shoot-thru currents in the output cmos fets resulting with very low operating currents. isl89167, isl89168 ISL89166 10k the uv comparator holds off the outputs until v dd ~> 3.3vdc. rising edge delay rdtx rdtx pin configurations ISL89166fr, ISL89166fb (8 ld tdfn, epsoic) top view isl89167fr, isl89167fb (8 ld tdfn, epsoic) top view isl89168fr, isl89168fb (8 ld tdfn, epsoic) top view ina gnd inb outb outa rdtb rdta vdd 8 6 7 1 4 3 2 5 /ina gnd /inb outb outa rdtb rdta vdd 8 6 7 1 4 3 2 5 /ina gnd inb outb outa rdtb rdta vdd 8 6 7 1 4 3 2 5 pin descriptions pin number symbol description 1 rdta connect a resistor between this pin and ground to program the rising edge delay of outa, 0k to 20k 2 ina or /ina channel a input, 0v to vdd 3 gnd power ground, 0v 4 inb or /inb channel b enable, 0v to vdd 5 outb channel b output 6 vdd power input, 4.5v to 16v 7 outa channel a output, 0v to vdd 8 rdtb connect a resistor between this pin and ground to program the rising edge delay of outb, 0k to 20k epad power ground, 0v
ISL89166, isl89167, isl89168 3 fn7720.2 february 26, 2013 ordering information part number (notes 1, 2, 3) part marking tem p range (c) input configuration package (pb-free) pkg. dwg. # ISL89166frtaz 166a -40 to +125 non-inverting 8 ld 3x3 tdfn l8.3x3i isl89167frtaz 167a -40 to +125 inverting 8 ld 3x3 tdfn l8.3x3i isl89168frtaz 168a -40 to +125 inverting + non-inverting 8 ld 3x3 tdfn l8.3x3i ISL89166fbeaz 89166 fbeaz -40 to +125 non-inverting 8 ld epsoic m8.15d isl89167fbeaz 89167 fbeaz -40 to +125 inverting 8 ld epsoic m8.15d isl89168fbeaz 89168 fbeaz -40 to +125 inverting + non-inverting 8 ld epsoic m8.15d notes: 1. add ?-t*?, suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL89166, isl89167, isl89168 . for more information on msl, please see technical brief tb363 .
ISL89166, isl89167, isl89168 4 fn7720.2 february 26, 2013 absolute maximum rating s thermal information supply voltage, v dd relative to gnd . . . . . . . . . . . . . . . . . . . . -0.3v to 18v logic inputs (ina, inb) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v outputs (outa, outb) . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to v dd + 0.3v average output current (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150ma esd ratings human body model class 2 (tested per jesd22-a114e) . . . . . . . . 2000v machine model class b (tes ted per jesd22-a115-a) . . . . . . . . . . . . 200v charged device model class iv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000v latch-up (tested per jesd-78b; class 2, level a) output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 4, 5). . . . . . . . . 44 3 8 ld epsoic package (notes 4, 5) . . . . . . . 42 3 max power dissipation at +25c in free air . . . . . . . . . . . . . . . . . . . . . 2.27w max power dissipation at +25c with copper plane . . . . . . . . . . . . . 33.3w storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c operating junction temp range . . . . . . . . . . . . . . . . . . . .-40c to +125c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp maximum recommended operating conditions junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c supply voltage, v dd relative to gnd. . . . . . . . . . . . . . . . . . . . . .4.5v to 16v logic inputs (ina, inb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd outputs (outa, outb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0v to v dd caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 for details. 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 6. the average output current, when driving a power mosfet or similar capacitive load, is the average of the rectified output cu rrent. the peak output currents of this driver are self limiting by transconductance or r ds(on) and do not required any external comp onents to minimize the peaks. if the output is driving a non-capacitive load, such as an led, maximum output current must be limited by external means to less than the specified absolute maximum. dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdta = rdtb = 0k unless otherwise specified. boldface limits apply over the operating junc tion temperature range, -40c to +125c. parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) power supply voltage range v dd --- 4.5 16 v v dd quiescent current i dd inx = gnd - 5 - - - ma ina = inb = 1mhz, square wave - 25 - - - ma undervoltage vdd undervoltage lock-out (note 9) (figure 9) v uv ina = inb = true (note 10) -3.3- - - v hysteresis - ~25 - - - mv inputs input range for ina, inb v in --- gnd v dd v logic 0 threshold for ina, inb v il nominally 37% x 3.3v -1.22- 1.12 1.32 v logic 1 threshold for ina, inb v ih nominally 63% x 3.3v -2.08- 1.98 2.18 v input capacitance of ina, inb (note 8) c in -2- - - pf
ISL89166, isl89167, isl89168 5 fn7720.2 february 26, 2013 input bias current for ina, inb i in gnd < v in < v dd --- -10 +10 a outputs high level output voltage v oha v ohb --- v dd - 0.1 v dd v low level output voltage v ola v olb --- gnd gnd + 0.1 v peak output source current i o v o (initial) = 0v, c load = 10nf - -6 - - - a peak output sink current i o v o (initial) = 12v, c load = 10nf - +6 - - - a notes: 7. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 8. this parameter is taken from the simulation models for the inpu t fet. the actual capacitance on this input will be dominated by the pcb parasitic capacitance. 9. a 400s delay further inhibits the release of the output state when the uv positive going thre shold is crossed. see figure 9 10. the true state of a specific part number is defined by the input logic symbol. ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdta = rdtb = 0k unless otherwise specified. boldface limits apply over the operating ju nction temperature rang e, -40c to +125c. parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) output rise time (see figure 4) t r c load = 10nf, 10% to 90% -20- - 40 ns output fall time (see figure 4) t f c load = 10nf, 90% to 10% -20- - 40 ns output rising edge propagation delay (see figure 3) t rdly rdtx = 0k -25- - 50 ns output falling edge propagation delay (see figure 3) (note 12) t fdly rdtx = 0k -25- - 50 ns rising propagation matching (see figure 3) t rm rdtx = 0k - <1ns - - - ns falling propagation matching (see figure 3) t fm rdtx = 0k - <1ns - - - ns rising edge timer delay (note 11) t rtdly20 rtx = 20k , no load - 266 - 237 297 ns t rtdly2 rtx = 2.0k , no load -42- 29 58 ns miller plateau sink current (see test circuit figure 5) -i mp v dd = 10v, v miller = 5v -6- - - a -i mp v dd = 10v, v miller = 3v -4.7- - - a -i mp v dd = 10v, v miller = 2v -3.7- - - a dc electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdta = rdtb = 0k unless otherwise specified. boldface limits apply over the operating junc tion temperature range, -40c to +125c. (continued) parameters symbol test conditions t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7)
ISL89166, isl89167, isl89168 6 fn7720.2 february 26, 2013 miller plateau source current (see test circuit figure 6) i mp v dd = 10v, v miller = 5v -5.2- - - a i mp v dd = 10v, v miller = 3v -5.8- - - a i mp v dd = 10v, v miller = 2v -6.9- - - a note: 11. the rising edge delay timer increases the propagation delay for values of rdtx > 2.0k . time delays for rdtx < 2.0k and rdtx > 20k are not specified and are not recommended. the resistors tole rances (including the boundary values of 2.0k and 20.0k ) are recommended to be 1% or better. 12. the falling edge propagation delays are independent of the rdt value. ac electrical specifications v dd = 12v, gnd = 0v, no load on outa or outb, rdta = rdtb = 0k unless otherwise specified. boldface limits apply over the operating ju nction temperature rang e, -40c to +125c. (continued) parameters symbol test conditions /notes t j = +25c t j = -40c to +125c units min typ max min (note 7) max (note 7) test waveforms and circuits figure 3. prop delays and matching figure 4. rise/fall times figure 5. miller plateau sink current test circuit figure 6. miller plateau source current test circuit ina, inb outa outb 0v 3.3v t rdly t rdly 63% 37% t fdly t fdly t rm t fm /outb /outa outa or outb t r t f 90% 10% v miller 10v +i sense -i sense 10f 0.1f 50m 200ns 10k isl8916x 10nf v miller 10v +i sense -i sense 10f 0.1f 50m 200ns 10k isl8916x 10nf
ISL89166, isl89167, isl89168 7 fn7720.2 february 26, 2013 figure 7. miller plateau sink current figure 8. miller plateau source current figure 9. start-up sequence test waveforms and circuits (continued) 200ns v miller -i mp v out current through 0.1 resistor 10v 0a 0v 200ns v miller i mp v out current through 0.1 resistor 0 3.3v uv threshold ~1v up to 400s outa, outb output state outputs controlled by logical inputs 10k to ground outputs active low <1 to ground rising vdd this duration is dependent on rise time of vdd this duration is independent on rise time of vdd typical performance curves figure 10. i dd vs v dd (static) figure 11. i dd vs v dd (1mhz) 2.0 2.5 3.0 3.5 4 8 12 16 static bias current (ma) v dd +125c +25c -40c 20 25 30 35 15 10 5 4 8 12 16 1mhz bias current (ma) v dd +125c +25c -40c
ISL89166, isl89167, isl89168 8 fn7720.2 february 26, 2013 figure 12. i dd vs frequency (+25c) figure 13. r ds(on) vs temperature figure 14. input thresholds figure 15. output rise/fall time figure 16. propagation delay vs v dd figure 17. propagation delay vs rdt typical performance curves (continued) 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 2.0 frequency (mhz) i dd (ma) no load 5v 10v 16v 12v 1.8 1.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -45 -20 5 30 55 80 105 130 r ds(on) ( ) temperature (c) v out low v out high 0.0 0.5 1.0 1.5 2.0 2.5 3.0 -45 -20 5 30 55 80 105 130 input logic thresholds (3.3v) temperature (c) positive threshold negative threshold 3.5 15 20 25 -45 -20 5 30 55 80 105 130 rise/fall time (ns) temperature (c) fall time, c load = 10nf rise time, c load = 10nf 15 20 25 30 5 7 9 11 13 15 propagation delay (ns) v dd output falling prop delay output rising prop delay 0 50 100 150 200 250 300 350 0 5 10 15 20 delay (ns) rdt (2k to 20k) -40c (worst case) +25c (typical) +125c (worst case)
ISL89166, isl89167, isl89168 9 fn7720.2 february 26, 2013 functional description overview the ISL89166, isl89167, isl89168 drivers incorporate several features including precision inpu t logic thresholds, undervoltage lock-out, fast rising high output drive currents and programmable rising edge output delays. the programmable delays require only a resistor connecter between the rdta or rdtb pins and ground. this is a useful feature to create dead times for bridge applications to prevent shoot-through or for synchronous rectifier applications to adjust the timing. fast rising (or falling) output drive current of the ISL89166, isl89167, isl89168 minimizes the turn-on (off) delay due to the input capacitance of the driven fet. the switching transition period at the miller plateau is also minimized by the high drive currents. (see the specified miller plateau currents in the ac electrical specifications on page 5). the start-up sequence for is designed to prevent unexpected glitches when v dd is being turned on or turned off. when v dd < ~1v, an internal 10k resistor connected between the output and ground, help to keep the gate voltage close to ground. when ~1v uvlo, and after a 400s delay, the outputs now respond to the logic inputs. see figure 9 for complete details. for the negative transition of v dd through the uv lockout voltage, the outputs are active low when v dd < ~3.2v dc regardless of the input logic states. application information programming rising edge delays as compared to setting the output delays of a driver using an resistor, capacitor and diode on the logic inputs, programming the rising edge output delays of the ISL89166, isl89167, isl89168 is almost trivial. all that is necessary is to select the required resistor value from the propagation delay vs rdt graph, figure 17. unlike using an rcd network, the operating tolerances over temperature are specified. if a traditional rcd network (figure 19) is used on the input logic, then it is necessary to account for the tolerance of the logic input threshold, the tolerances of r and c, and their temperature sensitivity. paralleling outputs to double the peak drive currents the typical propagation matching of the ISL89166 and isl89167 is less than 1ns. note that the propagation matching is only valid when rtda and rtdb = 0k . the matching is so precise that carefully matched and calibrated scopes probes and scope channels must be used to make this measurement. because of this excellent performance, these driver outputs can be safely paralleled to double the current drive capacity. it is important that the ina and inb inputs be connected together on the pcb with the shortest possible trace. th is is also required of outa and outb. note that the isl89168 ca nnot be paralleled because of the complementary logic. power dissipation of the driver the power dissipation of the ISL89166, isl89167, isl89168 is dominated by the losses associated with the gate charge of the driven bridge fets and the switching frequency. the internal bias current also contributes to the total dissipation but is usually not significant as compared to the gate charge losses. figure 20 illustrates how the gate charge varies with the gate voltage in a typical power mosfet. in this example, the total gate charge for v gs = 10v is 21.5nc when v ds = 40v. this is the charge that a driver must source to turn-on the mosfet and must sink to turn-off the mosfet. equation 1 shows calculating the power dissipation of the driver: figure 18. setting delays with a resistor inx outx rdtx ISL89166 figure 19. setting delays with a rcd network inx r del c del d outx isl89160 q g, gate charge (nc) 12 10 8 6 4 2 0 024681012141618202224 v gs gate-source voltage (v) figure 20. mosfet gate charge vs gate voltage v ds = 64v v ds = 40v (eq. 1) p d 2q c freq v gs r gate r gate r ds on () + ------------------------------------------ i dd freq () v dd ? + ? ? ? ? =
ISL89166, isl89167, isl89168 10 fn7720.2 february 26, 2013 where: freq = switching frequency, v gs = v dd bias of the ISL89166, isl89167, isl89168 q c = gate charge for v gs i dd (freq) = bias current at the switching frequency (see figure 10 on page 7) r ds(on) = on-resistance of the driver r gate = external gate resistance (if any). note that the gate power dissipation is proportionally shared with the external gate resistor. when si zing an external gate resistor, do not overlook the power dissipated by this resistor. typical application circuit pwm lr ll ll red dashed lines emphasize the resonant switching delay of the low-side bridge fets zvs full bridge t1a t1b t2 u1b u2a u2b q ul q ur q ll q lr ll lr sqr sqr r v gll v gul v glr v gur v glr v gul v gur v gll v bridge isl89162 u1a ? ISL89166 ? ISL89166 ll: lower left lr: lower right ul: upper left ur: upper right gll: gate lower left
ISL89166, isl89167, isl89168 11 fn7720.2 february 26, 2013 the typical application circuit is an example of how the ISL89166, isl89167, isl89168, mosfet drivers can be applied in a zero voltage switching full bridge. two main signals are required: a 50% duty cycle square wave (sqr) and a pwm signal synchronized to the edges of the sqr input. an isl89162 is used to drive t1 with alternating half cycles driving q ul and q ur . an ISL89166 is used to drive q ll and q lr also with alternating half cycles. unlike the two high side bridge fets, the two low-side bridge fets are turned on with a rising edge delay. the delay is setup by resistors connected to rdta and rdtb pins of the ISL89166. the duration of the delay is chosen to turn on the low-side fets when the voltage on their respective drains is at the resonant valley. general pcb layout guidelines the ac performance of the ISL89166, isl89167, isl89168 depends significantly on the design of the pc board. the following layout design guidelines are recommended to achieve optimum performance: ? place the driver as close as possible to the driven power fet. ? understand where the switching power currents flow. the high amplitude di/dt currents of the driven power fet will induce significant voltage transients on the associated traces. ? keep power loops as short as possible by paralleling the source and return traces. ? use planes where practical; they are usually more effective than parallel traces. ? avoid paralleling high amplitud e di/dt traces with low level signal lines. high di/dt will induce currents and consequently, noise voltages in the low level signal lines. ? when practical, minimize impedances in low level signal circuits. the noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. ? be aware of magnetic fields emanating from transformers and inductors. gaps in these structures are especially bad for emitting flux. ? if you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. ? the use of low inductance comp onents such as chip resistors and chip capacitors is highly recommended. ? use decoupling capacitors to reduce the influence of parasitic inductance in the vdd and gnd leads. to be effective, these caps must also have the shortest possible conduction paths. if vias are used, connect several paralleled vias to reduce the inductance of the vias. ? it may be necessary to add resistance to dampen resonating parasitic circuits especially on outa and outb. if an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. ? keep high dv/dt nodes away from low level circuits. guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. this is especially true for control circuits that source the input signals to the ISL89166, isl89167, isl89168. ? avoid having a signal ground plane under a high amplitude dv/dt circuit. this will inject di/dt currents into the signal ground paths. ? do power dissipation and voltage drop calculations of the power traces. many pcb/cad programs have built in tools for calculation of trace resistance. ? large power components (power fets, electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. this must be accounted for in the pcb layout and circuit design. ? if you simulate your circuits, consider including parasitic components especially parasitic inductance. general epad heatsinking considerations the thermal pad is electrically connected to the gnd supply through the ic substrate. the ep ad of the ISL89166, isl89167, isl89168 has two main functions: to provide a quiet gnd for the input threshold comparators and to provide heat sinking for the ic. the epad must be connected to a ground plane and no switching currents from the driven fet should pass through the ground plane under the ic. figure 21 is a pcb layout example of how to use vias to remove heat from the ic through the epad. for maximum heatsinking, it is recommended that a ground plane, connected to the epad, be added to both sides of the pcb. a via array, within the area of the epad, will conduct heat from the epad to the gnd plane on the bottom layer. the number of vias and the size of the gnd planes required for adequate heatsinking is determined by the power dissipated by the ISL89166, isl89167, isl89168, the air flow and the maximum temperature of the air around the ic. epad gnd plane component layer epad gnd plane bottom layer figure 21. typical pcb pattern for thermal vias
ISL89166, isl89167, isl89168 12 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7720.2 february 26, 2013 for additional products, see www.intersil.com/product_tree about intersil intersil corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. the company's products addr ess some of the fastest growing markets wi thin the industrial and infrastructure, personal computing and high-end consumer markets. for more inform ation about intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com . for a complete listing of applications, re lated documentation and related parts, plea se see the respective product information page. also, please check the product information page to ensure that you have the most updated datasheet: ISL89166, isl89167, isl89168 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff reliability reports are available from our website at: http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change december 21, 2012 fn7720.2 removed retired parts isl8916xfrtbz, isl8916xfrtc z, isl8916xfbebz, isl8916xfbecz from ?ordering information? on page 3. (page 4) abs max ratings esd ratings charged device model changed from "1500" to "1000" january 31, 2012 fn7720.1 (page 1) figure 1 illustration improved. (page 1) last paragraph of the product description is changed to better describe the improved turn on characteristics. (page 1) features list is revised to improve read ability and to add new product specific features. (page 3) updated ordering information with new parts. (page 4) abs max ratings esd ratings charged device model changed from "1000" to "1500" (page 4) note and figure references are added to the vdd under-voltage lock-out parameter. (page 5) note 9 is revised to more clearly describe the turn-on characteristics. changed "200s" to "400s" (page 6) wording of note 11 is revised to correctly label the rdt resistors. (page 7) figure 9 added to clearly define the startup characteristics. (page 9) the paragraphs of the functional description ov erview describing the turn-on sequence is replaced by 3 paragraphs to more clearly describe the unde r voltage and turn-on and turn-off characteristics. (page 9) a new section is added to the application in formation describing how the drivers outputs can be paralleled. (pages 1..12) various minor corrections to text for grammar and spelling. m8.15d pod on page 14 - converted to new pod format. removed table of dimensions and moved dimensions onto drawing. added land pattern. january 14, 2011 fn7720.0 initial release
ISL89166, isl89167, isl89168 13 fn7720.2 february 26, 2013 package outline drawing l8.3x3i 8 lead thin dual flat no-lead plastic package rev 1 6/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 0.80 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1
ISL89166, isl89167, isl89168 14 fn7720.2 february 26, 2013 package outline drawing m8.15d 8 lead narrow body small outl ine exposed pad plastic package rev 1, 3/11 detail "a" top view index area 123 -c- seating plane x 45 notes: 1. dimensions are in milli meters. dimensions in ( ) for reference only. 2. dimensioning and toleranc ing per asme-y14.5m-1994. 3. unless otherwise specified, to lerance: decimal 0.05. 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.25mm per side. 5. the pin 1 identifier may be ei ther a mold or a mark feature. 6. the chamfer on the body is optional. if it is not present, a visual index feature must be located wi thin the crosshatched area. side view ?a side view ?b? 1.27 (0.050) 6.20 (0.244) 5.84 (0.230) 3.99 (0.157) 3.81 (0.150) 0.50 (0.02) 0.25 (0.01) 4.98 (0.196) 4.80 (0.189) 1.72 (0.067) 1.52 (0.059) 0.25 (0.010) 0.10 (0.004) 0.46 (0.019) 0.36 (0.014) 8 0 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.41 (0.016) typical recommended land pattern bottom view 8 3.50 (0.137) 3.00 (0.118) 2.50 (0.099) 2.00 (0.078) 123 8 1.27 (0.050) 5.45 (0.214) 5 0.60 (0.023) 2.25 (0.089) 3.25 (0.128) 1.95 (0.077) 7 6 8 1 2 3 4

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