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pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 1 features ? two differential 2.5v/3.3v lvpecl output pairs . ? output frequency: 1 g hz . ? translates any standard single - ended or differential input format to lvpecl output. it can accept the following standard input formats and more: o lvpecl, lvcmos, lvds, hc sl, sstl, lvhstl, cml. ? output skew : 25ps (typ.) . ? part - to- part skew : 140ps (typ.) . ? propa gation delay: 1.5ns (typ.) . ? additive jitter: <100 fs (typ.) . ? operating supply voltage: 2.375v ~ 3.63v . ? op erating temperatur e range from - 4 0 c to 85 c . ? package availabil ity: sop - 8l and tssop - 8l. block diagram description the pl138 - 28 is a high performance low - cost 1: 2 outputs differential pecl fanout buffer. the family of differential lvpecl buffers are designed to operate from a single power supply of 2.5v 5% or 3.3v10%. the differential input pair is designed to accept most standard input signal levels , using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed f or part - to - part or lot - to lot skew. designed to fit in a small form - factor package, pl138 family offer s up to 1ghz of output operation with very low - power consumption, and lowest additive jitter of any comparable device. the output enable feature, when activated, allows the ic to consume less than 10a of current. pl 138 - 28 1 2 3 4 5 6 7 8 q 0 q 1 q 1 b v clk - in 0 b clk - in 0 q 0 b 8 - lead soic or tssop package cc v ee clk - in 0 clk - in 0b q 0 qb 0 q 1 qb 1
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 2 pin descriptions name package pin # type description soic - 8l / tssop - 8l q0 ~ q 1 1, 3 o lvpecl true output qb0 ~ q b 1 2, 4 o lvpecl complementary output v ee 5 p power supply pin connection clk - in0b 6 i complementary part of differential clock input signal clk - in0 7 i true part of differential clock input signal vcc 8 p power su pply pin connection input logic block diagram clk - in 0 clk - in 0 b
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 3 electrical specifica tions absolute maximum ratings parameters symbol min. max. un its supply voltage v dd 4.6 v input voltage, dc v i - 0.5 v dd +0.5 v output voltage, dc v o - 0.5 v dd +0.5 v storage temperature t s - 65 150 c ambient operating te m perature* t a - 40 85 c junction temperature t j 110 c lead temperature (so l dering, 10s) 260 c esd protection, human body model 2 kv exposure of the device under conditions beyond the limits specified by maximum ratings for extended periods may cause permane nt damage to the device and affect product reliability. these conditions represen t a stress rating only, and functional operations of the device at these or any other co n ditions above the operational limits noted in this specification is not implied. * note : operating temperature is guaranteed by design for all parts (comme r cial and in dustrial), but tested for commercial grade only. dc characteristics, vcc = 3.3v; vee = 0v parameter symbol - 40c 25c 80c units min typ max min typ max min typ max output high voltage* v oh 2.21 5 2.320 2. 420 2.27 5 2.350 2. 420 2.27 5 2.3 5 2.420 v out put low voltage* v ol 1.470 1.610 1. 745 1.490 1.585 1.6 80 1.490 1.58 5 1.680 v input high voltage v ih 2.075 2.420 2.13 5 2. 420 2.135 2. 420 v input low voltage v il 1.470 1. 890 1.490 1. 82 5 1.4 90 1. 82 5 v peak - to - peak input voltage v pp 150 800 1200 150 800 1200 150 800 1200 v input high voltage common mode range ? ?? v cmr 1 . 2 3.3 1 . 2 3.3 1 . 2 3.3 v input high current clk - in0, clk - in1 i ih 75 75 75 a input low current i il - 75 - 75 - 75 a input and output paramete rs vary 1:1 with v cc . v ee can vary +0.925v to - 0.5v. * outputs terminated with 50 ? to v cco ? 2v. ** single - ended input operation is limited. v cc 3v in lvpecl mode. ? common mode voltage is defined as v ih . ?? for single - ended applications, the maximum input voltage for clk - inx, clk - inxb is v cc + 0.3v
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 4 dc characteristics, vcc = 2 . 5 v; vee = 0v parameter symbol - 40c 25c 80c units min typ max min typ max min typ max output high voltage* v oh 1.415 1.520 1.620 1.475 1.550 1.620 1.475 1.55 1.620 v output low voltage* v ol 0.670 0.810 0.945 0.690 0.785 0.880 0.690 0.785 0.880 v input high voltage v ih 1.275 1.620 1.335 1.620 1.335 1.620 v input low voltage v il 0.670 1.090 0.690 1.025 0.690 1.025 v peak - to - peak input voltage v pp 150 800 1200 150 800 1200 150 800 1200 v input high voltage common mode range ? v cmr 1 . 2 2.5 1 . 2 2.5 1 . 2 2.5 v input high current clk - in0, clk - in1 i ih 60 6 0 6 0 a input low current i il - 6 0 - 6 0 - 6 0 a input and output parameters vary 1:1 with v cc . v ee can vary +0.925v to - 0.5v. * outputs terminated with 50 ? to v cco ? 2v. ** common mode voltage is defined as v ih . ? for single - ended applications, the maximum input voltage for clk - inx, clk - inxb is v cc + 0.3v ac electrical characteristics v cc = - 3.8v to - 2.375v or, v cc = 2.375v to 3.8v; v ee = 0v, t a = - 40c to 85c par ameter symbol - 40c 25c 80c units min typ max min typ max min typ max output frequency f max 700 700 700 m hz propagation delay* t pd 600 680 750 650 725 790 690 790 890 ps output skew ** ? tsk(o) 25 37 25 37 25 37 ps part - to - part skew *** ? tsk(pp) 85 225 85 225 85 225 ps buffer additive phase jitter, rms; refer to additive phase jitter section t apj 0.10 0.10 0.10 ps output rise/fall time 20% to 80% t r / t f 200 700 2 00 700 200 7 0 0 ps all par ameters are mea sured at f 10 00m hz, unless otherwise noted. * measured from the differential input crossing point to the differential output crossing point. ** defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the out put differential cross points. *** defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross p oints. ? this parameter is defined in accordance with jedec standard 65.
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 5 noise characteristics (commercial and industrial temperature d e vices ) param e ter description test cond i tions min. typ. max. unit t apj additive phase jitter v dd =3.3v, fr e quenc y=622. 08 mhz offset=12khz ~ 20mhz 21 fs -160 -150 -140 -130 -120 -110 -100 -90 -80 -70 -60 100 1000 10000 100000 1000000 10000000 100000000 offset frequency (hz) phase noise (dbc/hz) ref input PL138-28 output when a buffer is used to pass a signal then the buffer will add a little bit of its own noise. the phase noise on the output of the buffer will be a little bit more than the phase noise in the input signal. to quantif y the noise addition in the buffer we compare the phase jitter numbers from the input and the output. the difference is called "additive phase jitter". the formula for the add itive phase jitter is as follows: additive phase jitter = (output phase jitter) - (input phase jitter) 2 2
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 6 parameter measurement information output waveform test circuit: lvpecl v cc v ee -1.80v to -0.375v +2.0v oscilloscope ? 50 ? 50 channel channel ? 50 line ? 50 line differential input level: clk-inx clk-inxb v cc v ee v pp cross points v cmr part - to - part skew: part 1 part 2 qx qbx qy qby tsk(pp) output skew: qx qbx qy qby tsk(o) output rise/fall time: qx qbx t r 20% 80% t f 80% 20% propagation delay: clk-inx clk-inxb qy qby t pd
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 7 application information the following circuits show different configurations for different input logic type signals. for good signal integrity at the pl138 input, the signals need to be properly terminated according to the logic type requirements. the signals need to be presented at the pl138 input according to v cmr , v pp and other input requirements. clk - in inp ut driven by a 3.3v lvpecl driver: lvpecl +3.3v ? 50 line ? 50 line clk-inx pl138 +3.3v 130 130 82 82 +3.3v 3.3v lvpecl driver, alternative termination: lvpecl +3.3v ? 50 line ? 50 line clk-inx pl138 50 50 50 +3.3v clk - in input driven by a cml driver: cml +3.3v ? 50 line ? 50 line clk-inx pl138 +3.3v 50 50 +3.3v clk - in input driven by an sstl driver: sstl +2.5v ? 50 line ? 50 line clk-inx pl138 +2.5v 120 120 120 120 +3.3v clk - in input driven by an lvds driver: lvds +2.5v or +3.3v ? 50 line ? 50 line clk-inx pl138 100 +2.5v or +3.3v lvds driver, alternative ac coupling: lvds +2.5v or +3.3v ? 50 line ? 50 line clk-inx pl138 +2.5v or +3.3v 1k 1k 1k 1k 100 this circ uit is for compatibility only. ac coupling is not really required for lvds. the v cmr range of the pl138 reaches low enough that lvds signals can be connected directly to the pl138 input like in the circuit to the left.
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 8 clk - in input driven by a cmos driv er: cmos clk-inx pl138 +2.5v or +3.3v 1k 1k 0.1f clk - in input driven by single ended lvpecl: lvpecl clk-inx pl138 +3.3v +3.3v 82 130 ? 50 line 1k 0.1f clk - in input driven by an hcsl driver: hcsl +2.5v or +3.3v ? 50 line ? 50 line clk-inx pl138 +2.5v or +3.3v 1k 1k 1k 1k 50 50 hcsl presents its signals very close to the ground rail, below the v cmr range, so the hcsl signals can not be connected to the pl138 input directly. ac coupling is required for hcsl signals on the pl138 input. termination for lvpecl outputs the required termination for lvpecl is 50 ? to a v cc - 2v dc voltage level. below are two schematics to implement this termination. lvpecl termination schematic #1: pl138 vcc ? 50 line ? 50 line lvpecl vcc r1 r1 r2 r2 qx buffer target input lvpecl termination schematic #2: pl138 vcc ? 50 line ? 50 line lvpecl 50 50 qx buffer target input rt vcc=3.3v, ideal values: r1=127 ? , r2=82.5 ? commercial values (e24): r1=130 ? , r2=82 ? vcc=2.5v, id eal values: r1=250 ? , r2=62.5 ? commercial values (e24): r1=240 ? , r2=62 ? schematic #2 is an alternative simplified termination. vcc=3.3v, ideal value: rt=48.7 ? commercial value: rt=50 ? (e24: 51 ? ) vcc=2.5v, ideal value: rt=18.7 ? commercial value: rt=18 ?
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 9 power considerations driving lvpecl outputs requires an amount of power that can warm up the chip significantly. the general requirement for the chip is that the junction temperature should not exceed +110 c. the power consumption can be divided into two p arts: 1) core power dissipation 2) output buffers power dissipation core power dissipation the chip core power is equal to vcciee. with a worst case vcc and iee the power dissipation in the core is 3.63v 45 ma= 163 mw. output buffer power dissipation the output buffers are not exposed to the full vcc - vee voltage. on the differential output , one line is at logic 1 with a small voltage across the buffer and a large output current. the other line is at logic 0 with a larger voltage across the buffer and a smaller ou tput current. the power dissipation per output buffer is 32mw. only buffers that are loaded will hav e power dissipation. with both buffers loaded the worst case output buff er power dissipation will be 64 mw. total chip power dissipation, worst case, is 163 m w + 64 mw = 227 mw. junction temperature how much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to the environment, also known as ?junction to ambient?. the thermal resistance depends upon the type of pa ckage, how the package is assembled to the pcb and if there is additional air flow for improved cooling. for the lqfp package with use of the thermal relief pad, the thermal resistance is as follows: jedec standard multi layer pcb air flow velocity in lin ear feet per minute 0 200 500 soic 8 - pin package ja = 97 c/w ja = 85 c/w ja = 77 c/w tssop 8 - pin package ja = 120c/w ja = 105c/w ja = 95 c/w soic 8 - pin: the temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to ja power. for an ambient temperature of +85 c, all outputs loaded and no air flow, the junction temperature t j = 85c+ 97 0. 227 = 1 07 c. ts so p 8 - pin: for an ambient temperature of +85c, all outputs loaded and 200lfm air flow, the ju nction temperature t j = 85c+ 105 0. 227 = 10 9 c. it is recommended to use at least 200lfm air flow to prevent the junction temperature from increasing above +110c. for use up to +80c or lower no air flow is needed: t j = 80 c+ 120 0. 227 = 107 c.
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 10 package d rawings ( green package compliant) 8 pin (d imensions in mm ) symbol soic tssop min. max. min. max. a 1. 35 1.7 5 - 1.20 a1 0.1 0 0.25 0. 0 5 0.15 a2 1.25 1.50 - 1.05 b 0.33 0.5 3 0.19 0.30 c 0.19 0.27 0. 0 9 0.2 0 d 4.8 0 5.00 2.9 0 3.1 0 e 3.8 0 4.0 0 4. 3 0 4.5 0 h 5.80 6.20 6.2 0 6.60 l 0. 40 0.89 0. 4 5 0. 75 e 1.27 bsc 0.65 bsc c l a 2 e h d a 1 e b a
pl138 - 2 8 2.5v - 3.3v low - skew 1 -2 differential pecl fanout buffer micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1(408) 944 - 0800 ? fax +1(408) 474 - 1000 ? www.micrel.com rev 11/26/13 page 11 ordering information ( green package) for part ordering, please contact our sales department: 2 1 80 fortune drive , san jose, ca 95131 , usa tel: (408) 944 - 0800 fax: (408) 474- 1 00 0 part number the order number for this device is a combination of the following: part number, package type and operating temperature range pl 138 - 28 x x - r part number package type s = sop- 8 o = tssop- 8 temperature range c = commercial ( 0 c to + 70c) i = industrial ( - 40c to + 85c) r = tape and reel part /order number marking package option pl 138 - 28 s c - r p138 - 28 sc lllll 8- pin sop (t ape and reel) pl 138 - 28 o c - r p138 - 28 o c lllll 8- pin tssop (tape and reel) *note: lllll designates lot number micrel inc., reserves the right to make changes in its products or specifications, or both at any time without notice. the in formation furni shed by micrel is believed to be accurate and reliable. however, micrel makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or relianc e upon this product. life support policy : micrel?s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of micrel inc.

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