View SABRE-LL-I_8822401.PDF datasheet online --- IC-ON-LINE

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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2007 rev 1 1/141 1 SABRE-LL-I combo motor driver features configurable device 4 full bridges to generate ? up 2 dc motor drivers and 1 stepper motor driver or ? 4 dc motor drivers bridges (1 & 2) additional configurations are ? super dc ? 2 half bridges ? 1 super half bridge ? 2 switches ?1 super switch bridges (3 & 4) additional configurations are: ? same as bridges 1&2, listed above ? 2 buck regulators (bridge 3) ? 1 super buck regulator ? battery charger (bridge 4) one variable voltage bu ck switching regulator one switching regulator controller one linear regulator bidirectional serial interface programmable watchdog function integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin thermal shutdown protection with thermal warning capability very low power dissipation in shut-down mode (~35 mw) aux features ? operational amplifiers ?comparators ? pass switches ? multi-channels 9 bit adc ?gpios description s.a.b.re? (structured architecture of bridges and regulators) is a new concept of ic in the motion & power supply field. st aim is to follow the s.a.b.re specification and to offer to the customer an ic with a wide number of features, that can be configured and customized: motor drivers, regulators, high precision a/d converter, operational amplifiers and voltage comparators. the start up configuration can be defined by the gpios and then through the serial interface; a customization can be done through a metal layer in order to set more complex functions. tqfp64 exposed pad table 1. device summary part number package packing SABRE-LL-I tqfp64 tray www.st.com
contents SABRE-LL-I 2/141 contents 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 s.a.b.re?s main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 global specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 absolute maximum rating specifications . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 operating ratings specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 internal supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 v supplyint regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 v supplyint specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.4 charge pump regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 v3v3 regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.6 v3v3 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 supervisory system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2 power on reset (por) circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3 nreset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 nreset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 thermal shut down generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.6 tsd specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 watchdog circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 internal clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SABRE-LL-I contents 3/141 8 start-up configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.2 operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3 basic device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 slave device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.5 master device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.6 single device mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.7 sub-configurations for slave, master or single device modes . . . . . . . . . 29 8.7.1 bridge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.7.2 primary regulator mode (kp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.7.3 regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.4 simple regulator mode (kt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.5 bridge+ v ext mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.7.6 secondary regulators mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9 power sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.3 hibernate mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.4 low power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.5 nawake pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 12 main switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.2 pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 13 switching regulator controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 13.2 pulse skipping operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
contents SABRE-LL-I 4/141 13.3 output equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.4 switching regulator controller specifications . . . . . . . . . . . . . . . . . . . . . . 45 13.5 switching regulator controller application considerations . . . . . . . . . . . . . 45 14 power bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 14.2 power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 50 14.3 possible configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 14.3.1 full bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 14.3.2 parallel configuration (super bridge) . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.3.3 half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14.3.4 switch configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.3.5 bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 14.3.6 synchronous buck regulator configuration . . . . . . . . . . . . . . . . . . . . . . . 64 14.3.7 regulation loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15 ad converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 15.2 a2d specification with a2dtype=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 15.3 a2d specification with a2dtype=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 15.4 voltage divider specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 16 current dac circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 17 operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 17.2 operational amplifiers specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 17.3 operational amplifiers used as comparators specifications . . . . . . . . . . . 85 18 low voltage power switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 18.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 19 general purpose pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 19.2 general purpose pwm generators 1 and 2 (auxpwm1 and auxpwm2) . 88
SABRE-LL-I contents 5/141 19.3 programmable pwm generator (gppwm) . . . . . . . . . . . . . . . . . . . . . . . . 88 20 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.2 interrupt controller monitored signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 21 digital comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 21.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 22 gpio pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 22.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 22.2 gpio[0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 22.3 gpio[1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 22.4 gpio[2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 22.5 gpio[3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 22.6 gpio[4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 22.7 gpio[5] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 22.8 gpio[6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 22.9 gpio[7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 22.10 gpio[8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 22.11 gpio[9] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 22.12 gpio[10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 22.13 gpio[11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 22.14 gpio[12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 22.15 gpio[13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 22.16 gpio[14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 23 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23.1 read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 23.2 write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 24 registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 25 schematic samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
contents SABRE-LL-I 6/141 26 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 26.1 pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 27 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 28 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
SABRE-LL-I list of tables 7/141 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. ic operating ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. v supplyint specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. v pump specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. v supplyint specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 7. power on reset specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. stretch time selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. nreset circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. tsd circuit specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. watchdog timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. watchdog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 13. internal clock specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 14. possible start-up pins state symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 15. start-up correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 16. nawake function specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 17. system linear regulator operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 18. switching regulator controller pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. main switching regulator pwm specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 20. main switching regulator current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 21. main switching regulator specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. switching regulator controller pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 23. switching regulator controller pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 24. switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 25. switching regulator controller operating specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 26. switching regulator controller application feedback reference . . . . . . . . . . . . . . . . . . . . . . 46 table 27. pwm selection truth for bridge 1 or 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 28. pwm selection truth for bridge 3 or 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 29. power bridges operating specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 30. bridge selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 31. bridge 3 and 4 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 32. full bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 33. half bridge truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. switch truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. stepper specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 36. sequencer drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 37. stepper mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 38. stepper sequencer direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 39. dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 40. internal sequencer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 41. blanking times specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 42. stepper off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 43. stepper fast decay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 44. switching regulator controller pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 45. pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 46. operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 47. battery charger control loop fbref specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 48. battery charger control loop currref specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
list of tables SABRE-LL-I 8/141 table 49. battery charger regulator controller pwm specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 50. battery charger operating specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 51. adc truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 52. channel addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 53. adc sample times when working as a 8-bit adc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 54. adc sample time when working as a 9-bit adc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 55. adc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 56. adc specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 57. voltage divider specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 58. current dac truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 59. current dac specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 60. configurable 3.3v operational amplifier specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 61. configurable 3.3v operational amplifier used as comparator specification . . . . . . . . . . . . 85 table 62. 3.3v low power switch specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 63. interrupt controller event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 64. interrupt controller specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 65. comparison type truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 66. datax selection truth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 67. gpio functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 68. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 69. gpio[0] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 70. gpio[0] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 71. gpio[1] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 72. gpio[1] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 73. gpio[2] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 74. gpio[2] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 75. gpio[3] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 76. gpio[3] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 77. gpio[4] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 78. gpio[4] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 79. gpio[5] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 80. gpio[5] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 81. gpio[6] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 82. gpio[6] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 83. gpio[7] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 84. gpio[7] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 85. gpio[8] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 86. gpio[8] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 87. gpio[9] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 88. gpio[9] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 89. gpio[10] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 90. gpio[10] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 91. gpio[11] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 92. gpio[11] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 93. gpio[12] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 table 94. gpio[12] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 95. gpio[13] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 table 96. gpio[13] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 97. gpio[14] truth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 table 98. gpio[14] specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 99. spi interface specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 100. register address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
SABRE-LL-I list of tables 9/141 table 101. pins configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 102. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
list of figures SABRE-LL-I 10/141 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. v supplyint pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 3. nreset generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 4. watchdog circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. standby mode function description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 6. nawake function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7. linear main regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. linear main regulator external bipolar example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 9. main switching regulator functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 10. switching regulator controller functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 11. switching regulator controller output driving equivalent circuit . . . . . . . . . . . . . . . . . . . . . . 44 figure 12. h bridge block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 13. bridge 1 and 2 pwm selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 14. super bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 15. half bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 16. bipolar stepper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 17. regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 18. internal comparator functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. battery charger control loop block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 20. li-ion battery charge profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 21. simple buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 22. a2d block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 23. current dac block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 24. configurable 3.3v operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 25. low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 26. low power switch block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 27. digital comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 28. gpio[0] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 29. gpio[1] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. gpio[2] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 31. gpio[3] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 32. gpio[4] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 33. gpio[5] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 34. gpio[6] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 35. gpio[7] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 36. gpio[8] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 37. gpio[9] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 38. gpio[10] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 figure 39. gpio[11] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 40. gpio[12] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 41. gpio[13] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 42. gpio[14] block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 figure 43. spi read transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 44. spi write transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 figure 45. spi input timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 46. spi output timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 figure 47. application with 2 dc motors, 1 stepper motor and 3 power supplies . . . . . . . . . . . . . . . 134 figure 48. application with 2 dc motors, a battery charger and 5 power supplies . . . . . . . . . . . . . . 135
SABRE-LL-I list of figures 11/141 figure 49. tqfp64 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
general description SABRE-LL-I 12/141 1 general description 1.1 overview s.a.b.re represents a new concept of ic in motion & power supply field. the aim that st followed in defining s.a.b.re specification was to offer to the customer an ic with a wide number of features: motor driver s, regulators, high precision a/d converter, operational amplifiers, voltage comparators and many other circuits can easily be configured and customized. the device configuration can be defined by programming the ic via the serial interface while a deeper customization can be done through metal layer in order to set more complex functions. figure 1. block diagram note: see following ?s.a.b.re?s main features? for a detailed description of possible configurations. main switching regulator main linear regulator internal regulators gpios batt. charg. circuitry charge pump bridge 2 bridge 3 bridge 4 current dac bridge 1 start up config. adc analog mux s/h (2x) 3.3v pass switch supervisory & reset manager thermal manager s s a a b b r r e e switching reg. controller int. ref. volt power sequencing digital compar. op.amps stepper circuitry digital auxiliary osc. spi rsense rsense
SABRE-LL-I s.a.b.re?s main features 13/141 2 s.a.b.re?s main features s.a.b.re includes the following circuits: four widely configurable full bridges: ? bridges 1 and 2: ? diagonal rdson: 0.6 ? typ. ? max operative current = 2.5a. ? bridges 3 and 4: ? diagonal rdson: 0.85 ? typ. ? max operative current = 1.5a. possible configurations for each bridge are the following: ? bridge 1: ? dc motor driver. ? super dc (bridge 1 and 2 paralleled form superbridge1). ? 2 independent half bridges. ? 1 super half bridge (bridge 1 side a and bridge 1 side b paralleled form superhalfbridge1). ? 2 independent switches (high or low side). ? 1 super switch (high or low side). ? bridge 2 has the same configurations of bridge 1. ? bridge 3 has the same configurations of bridge 1 (bridge 3 and 4 paralleled form superbridge2) plus the following: ? ? stepper motor driver. ? 2 buck regulators (v aux1_sw , v aux2_sw ). ? 1 super buck regulator (v aux1//2_sw ). ? bridge 4 has the same configurations of bridge 1 plus the following: ? ? stepper motor driver. ? 1 super buck regulator (v aux3_sw ). ? battery charger. one buck type switching regulator (v main_sw ) with: ? output regulated voltage range: 1-5 volts. ? output load current: 3.0 a. ? internal output power dmos. ? internal soft start sequence. ? internal pwm generation. ? switching frequency: ~250 khz . ? pulse skipping strategy control. one switching regulator controller (v ext_sw ) with: ? output regulated voltage range: 1-30 volts. ? selectable current limitation. ? internal pwm generation. ? pulse skipping strategy control.
s.a.b.re?s main features SABRE-LL-I 14/141 one linear regulator (v main_lin ) that can be used to generate low current/low ripple voltages. this regulator can be used to drive an external bipolar pass transistor to generate high current/low ripple output voltages. one bidirectional serial interface with address detection so that different ics can share the same data bus. integrated power sequencing and supervisory functions with fault signaling through serial interface and external reset pin. fourteen general purpose i/os that can be used to drive/read internal/external analog/logic signals. one 8-bit/9-bit a/d converter (100ks/sec @ 9-bit, 200ks/sec @8-bit). it can be used to measure most of the internal signals, of the input pins and a voltage proportional to ic temperature. ? current sink dac: ? three output current ranges: up to 0.64/6.4/64 ma. ? 64 (6-bit programmable) availabl e current levels for each range. ? 5v output tolerant. two operational amplifiers: ? 3.3v supply, rail to rail input comp atibility, internally compensated. ? they can have all pins externally accessible or can be internally configured as a buffer o make internal reference voltages available outside of the chip. ? unity gain bandwidth > 1mhz. ? they can also be set as comparators with 3.3v input compatib ility and low offset. two 3.3v pass switches with 1 ? rdson and short circuit protected. programmable watchdog function. thermal shutdown protection with thermal warning capability. very low power dissipation in ?low power mode? (~35mw) s.a.b.re is intended to maximize the use of its components, so when an internal circuit is not used it could be employed for other applications. bridge 3, for example, can be used as a full bridge or to implement two switching regulators with synchronous rectification: to obtain this flexibility s.a.b. re includes 2 separate regulation loops for these regulators; when the bridge is used as a motor driver, the 2 regulation loops can be redirected on general pur pose i/os to leave the possib ility to assembly a switching regulator by only adding an external fet.
SABRE-LL-I global specifications 15/141 3 global specifications 3.1 absolute maximum rating specifications the following specifications define the maximum range of voltages or currents for s.a.b.re. stresses above these absolute maximum specifications may cause permanent damage to the device. exposure to absolute maximum ratings for ex tended periods may affe ct device reliability. 3.2 operating ratings specifications table 2. absolute maximum rating parameter description test condition min max unit v supply_abs v supply voltage 40 v v gpio_spi_abs v gpio_spi voltage 3.9 v v 3v3pin_abs 3.3v pins input voltage 3.9 v v sw_abs switching regulators output pin voltage range -1 v supply v v sw_pulse switching regulators min pulsed voltage for less than 500ns -3 v v pump_abs charge pump pins voltage (1) 1. this value is useful to define the voltage rati ng for external capacitor to be connected from v pump to v supply . v pump is internally generated and can never be supplied by external voltage source nor is intended to provide voltage to external loads. 15 v t j_abs junction temperature (2) 2. tsd is the thermal shut do wn temperature of the device. storage -40 190 c operating 0 tsd c table 3. ic operating ratings parameter description test condition min max unit v supply_op v supply voltage range 23 38 v i supply_op v supply operative current (1) 1. operating supply current is measured with system regulators operating but not loaded. 15 ma i shut_down v supply shut down state current 1.5 ma v gpio_spi_op v gpio_spi voltage range 2.4 3.6 v i vgpio_spi_op v gpio_spi operative current (2) 2. operating v gpio_spi current is measured with all circuits supplied by v gpio_spi (gpio?s, operational amplifiers and pass switc hes) enabled but not loaded. tbd ma v 3v3pin_op 3.3v input pins voltage range -0.3 3.6 v t j_abs junction temperature operating 0 125. c
internal supplies SABRE-LL-I 16/141 4 internal supplies 4.1 overview s.a.b.re includes three internal regulators used to provide a regulated voltage to internal circuits. the internal regulators are the following: - v supplyint regulator. - charge pump regulator. - v 3v3 regulator. 4.2 v supplyint regulator v supplyint is the output of an internal regulator used to supply some internal circuits. this regulator is not intended to provide external current so it must not be used to supply external loads. an external capacitor must always be connected to this pin (preferably towards v supply pin). figure 2. v supplyint pin the v supplyint pin may also be externally connected to v supply pin by means of an external resistor r ext : this allows r ext , particularly when v supply is at the max values of the operative supply range, to dissipate power that otherwise would be dissipated inside the chip. the choice of the optimal resistor depe nds on the application since it is strictly depending on both v supply and the current used inside the chip (that is changing with the chosen configuration). sabre vsupplyint is_int_typ vsupply gnd sabre internal circuits
SABRE-LL-I internal supplies 17/141 4.3 v supplyint specifications 4.4 charge pump regulator s.a.b.re implements a charge pump regulator to generate a voltage over v supply .this voltage is used to drive internal circuits and the external fet driver and cannot be used for any other purpose. this circuit is always under the supervisory circuit control, so no regulator can start before the v pump voltage reaches its undervoltage rising threshold. if v pump voltage falls down below its under voltage falling threshold, all the regulators will be switched off. the charge pump circuit is disabled when s.a.b.re is in ?low power mode?. 4.5 v3v3 regulator v3v3 is the output of an internal regulator used to supply some low voltage internal circuits. this regulator is not intended to provide external current so it must not be used to supply external loads. an external capacitor must always be connected from this pin to gnd. table 4. v supplyint specification parameter description test condition min typ max unit v s_int_rng v supplyint output voltage (1) 1. this value is useful to define the voltage rati ng for external capacitor to be connected from v supply to v supplyint . 18 19.5 21 v i s_int_typ v supplyint operative current (2) 2. this typical value is only intended to give an exti mation of the current consumption when s.a.b.re is configured in simple regulators mode (see following chapter 8.7.4 ) at the end of the start up sequence and with no load on regulators. this typical value allows a ra w choose of the external re sistor but the definitive choose must be done according to following note 3). 11 ma r ext external resistor value v supply =32v i s_int =12ma (3) 3. rext could be chosen by applying this formula: rext = (v supply min - vs_int max)/(i s_int max). i s_int max is depending from the chosen conf iguration and represents the total current needed by the circuits connected to this pin. 1000 1.5 ? c ext external capacitor 80 100 120 nf table 5. v pump specification parameter description test condition min typ max unit v pump regulated voltage v supply =32v v supply +10.5 v supply +12.5 v supply +14.5 v f pump v pump clock frequency fosc = 16mhz typ fosc/64 khz c fly flying capacitor 100 nf c boost boost capacitor 1 f
internal supplies SABRE-LL-I 18/141 4.6 v3v3 specifications table 6. v supplyint specification parameter description test condition min typ max unit v 3v3 v 3v3 output voltage v supply =32v 3.15 3.3 3.45 v c ext external capacitor 80 100 120 nf
SABRE-LL-I supervisory system 19/141 5 supervisory system 5.1 overview the supervisory circuitry monitors the state of several functions inside s.a.b.re and resets the device (and other ics if connected to nreset pin) when the monitored functions are outside their normal range. supervisory circuitr y can be divided into three main blocks: ? power on reset (por) generation circuitry. ? nreset (nrst_int) generation circuitry. ? thermal shut down (tsd) generation circuitry. por circuitry monitors the voltages that s.a.b.re needs to guarantee its own functionality; nreset circuitry controls if s.a.b.re?s main vo ltages are inside their normal range; tsd is the thermal shut down of the chip in case of overheating. 5.2 power on reset (por) circuit power on reset circuit monitors v supply , and v3v3 voltages. the purpose of this circuit is to set the device is in a stable and controlled status until the minimum supply voltages that guarantee the device functionality are reached. the output signal of this circuit (in the following indicated as ?por?) becomes active when v supply or v3v3 go under their falling threshold. when por output signal is active, all functions and all flags inside s.a.b.re are set in their reset state; once por signal comes back from off state (meaning monitored voltages are above their rising threshold), the power up sequence is re-initialized . 5.3 nreset generation circuit the nreset circuit monitors v supply , v supply_int , v pump , v gpio_spi and all system regulators (vsystem) voltages. the purpose of this circuit is to prevent the device functionality until the monitored voltages reach their operative value (please note that v 3v3 table 7. power on reset specifications parameter description test condition min typ max unit v supply_por_valid v supply voltage for por valid i nreset = 1ma 4 v v supply_por_fall v supply por falling threshold v supply falling 6 9 v t supply_por_filt v supply por filter time 3s v 3v3_por_fall v 3v3 por falling threshold v 3v3 falling 1.9 2.2 v v 3v3_por_rise v 3v3 por rising threshold v 3v3 rising 2.7 v v 3v3_por_hys v 3v3 por hysteresis 0.5 v t 3v3_por_filt v 3v3 por filter time 1.5 s
supervisory sy stem SABRE-LL-I 20/141 is monitored by por, so it must be above it s minimum value, otherwise nreset circuit is not active). this circuit generates an internal reset signal (in the following indicated as ?nrst_int?) that will also be signaled to external ci rcuits by pulling low the nreset pin. the signal nrst_int becomes active in the following cases: 1. when one of the following voltages is lower than its own under voltage threshold: ?v supply and v supply_int . ?v pump . ?v system (all switching or linear sys tem regulators voltages). ?v gpio_spi . 2. when watchdog timer counter (see chapter 6 ) elapse the watchdog timeout time (only if watchdog function is enabled). 3. when s.a.b.re is in ?low power mode?. 4. when enextsoftrst bit in softresreg register is at logic level = ?1? and a ?softres? command is applied (see softresreg register description in chapter 25 ). when an nrst_int event is caused by abov e cases, the nreset pin will stay low for a ?stretch? time that starts from the moment that nrst_int signal returns in the operative state. this stretch time can be selected by setting the id[1:0] bits in the sampleid register according to following table: when nrst_int becomes active (logic level = ?0?) it sets in their reset state some of the functions inside s.a.b.re. the main functions that will be reset by nr st_int signal are the following: ? serial interface will be reset and will not accept any other command. ? the bridges 1 and 2 will place their ou tputs in high impe dance and pwm and direction signals will be reset. ? not system regulators will be powered off. ? ad converter will be powered off. ? gpios will be powered off. ? current dac will be powered off. ? operational amplifie rs will be powered off. ? watchdog count will be reset (while watchdog flags won?t be reset). ? interrupt controller will be powered off. ? digital comparator will be powered off. table 8. stretch time selection id[1] id[0] selected stretch time note typ 0 0 16ms default state 0132ms 1048ms 1164ms
SABRE-LL-I supervisory system 21/141 additionally the system regulators will be powered off but only if the voltage th at caused the nrst_int event is checked before the system regulator in the power up sequence. this means that: ? all system regulators will be powered off if nrst_int is caused by v supply , v supply_int , v pump (and also if v3v3 causes a por); ? no one of the system regulators will be powered off if nrst_int is caused by v gpio_spi ; ? only the system regulators that follows the system regulator that caused the nrst_int in power up sequence will be powered off. 5.4 nreset specifications table 9. nreset circuit specifications parameter description test condition min typ max unit nrst_vol nreset low level output voltage i=10ma 0.4 v nrst_fall nreset fall time i=1ma c=50pf (1) 1. measured between 10% and 90% of output voltage transition. 15 ns nrst_del nreset delay time (2) 2. measured from a fault detection to 50% of output voltage transition. 150 ns v supply_uv_f v supply falling threshold 18.5 v v supply_uv_r v supply rising threshold 23 v v supply_uv_hys v supply hysteresis 2 v t supply_uv v supply uv filter time 3.5 us v s_int_uv_f v supplyint falling threshold 14.0 v v s_int_uv_r v supplyint rising threshold 17.5 v v s_int_uv_hys v supplyint hysteresis 1.5 v t s_int_uv v supplyint uv filter time 3.5 s v pump_uv_f v pump falling threshold v supply +7 v v pump_uv_r v pump rising threshold v supply + 9.5 v v pump_uv_hys v pump hysteresis 1.5 v t pump_uv v pump uv filter time 3.5 us v gpio_spi_uv_f v gpio_spi falling threshold 1.8 v v gpio_spi_uvr v gpio_spi rising threshold 2.4 v v gpio_spi_hys v gpio_spi hysteresis 250 mv t gpio_spi_uv v gpio_spi uv filter time 3.5 us
supervisory sy stem SABRE-LL-I 22/141 figure 3. nreset generation circuit note: all regulator voltages included in power up sequence (v sysx ? v sysy in figure 3 ) will be considered as nreset circuit voltages. ngatectrl uv filter uv comparato r v supply v supply uv uv filter uv comparato r v pu mp v pu mp uv uv filter uv comparato r v supplyint v supplyint uv uv filter uv comparator v sysx to spi watchdo g elapsed system regulators uv wd_en_nrst nreset pin driver nreset p in nrst_in filter low power mode uv filter uv comparator v sysy por
SABRE-LL-I supervisory system 23/141 5.5 thermal shut down generation circuit the third component of the supervisory circuit is the thermal shut down generation circuit. this circuit generates two different flags depending on the ic temperature: ? the ?tsd? flag indicates that the ic temperature is greater than the maximum allowable temperature. ? the ?warm? flag, that can be read using serial interface, becomes active at a lower temperature respect to tsd signal, therefore it can be used to prevent the ic from reaching over temperature. when a tsd event occurs, s.a.b.re will enter in the reset state placin g the bridges in high impedance and turning off all regulators and other circuits until the internal temperature decreases below the warm temperature. at th is point, s.a.b.re will restart the power up sequence and tsd bit will be set and will be readable as soon as s.a.b.re will come out from the reset state. this tsd bit can be reset in three ways: ? by writing a logic level ?1? in the clea rtsd bit in the ictemp register (see chapter 25 ); ? by a por event; ? by entering in ?low power mode?. the warm bit, set by s.a.b.re when ic is working over the warming temperature, can be read using the spi interface. once this bit is set it can be reset in three ways: ? by writing a logic level ?1? in the clearwarm bit; ? by a por event; ? by entering in ?low power mode?. the thermal sensor voltage can be converted using the internal a/d: this way the microcontroller can directly measure the ic temperature. to avoid unwanted commutation especially when temperature is near the thresholds, the output signal is filtered for both tsd and warm. 5.6 tsd specifications table 10. tsd circuit specifications parameter description test condition min typ max unit t tsd thermal shut down temperature 170 c t warm warming temperature 140 c t diff thermal shut down to warming difference 30 c t tsd_filt thermal shut down filter time 8 us t warm_filt warming filter time 8 us
watchdog circuit SABRE-LL-I 24/141 6 watchdog circuit 6.1 overview the watchdog timer can be used to reset s.a.b.re if it is not serviced by the firmware that can periodically write at logic level ?1? t he clrwdog bit in the watchdogstatus register. this circuit is disabled by default; firmware c an enable it by setting at logic level ?1? the wdenable bit in the watchdogcfg register. when the watchdog timeout event happens, s.a.b.re sets to ?1? a latched bit wdtimeout in thewatchdogstatus register that can be read using spi interface; once this bit is set it can be cleared in three ways: ? by writing a ?1? in the wdclear bi t in the watchdogstatus register. ? by writing a ?1? in the softreset bit in the watchdogstatus register. ? by a por event. the watchdog function includes also a warning bit wdwarning to indicate, via serial interface or via the circuit called interrupt controller (see chapter 21 ) that the watchdog is near to its timeout; this bit is asserted to logic level ?1? exactly one watch dog clock period (wd_tclk) before the watchdog timeout happens. firmware can enable the wdtimeout signal to cause an ?nrst_int? event by setting to logic ?1? the wdennrst bit. figure 4. watchdog circuit block diagram the watchdog timeout has an imprecision of maximum one wd_tclk. the effective programmed wd time is changed in the register only when the watchdog circuit is serviced by firmware with clrwdog bit. at this time the watchdog timer is reset and the new value of the wd delay value is loaded. the watchdog timer can be programmed to generate different timeouts using the wddelay[3:0] bits in the watchdogcfg register according to following table: frequency divider fosc wd_clk watchdog counter wddelay[3:0 ] wdwarning wdtimeout to spi wd_en_nrs t wdenable wd_req_nrs t to nrstint g eneration circuit clrwdog
SABRE-LL-I watchdog circuit 25/141 6.2 watchdog specifications table 11. watchdog timeout specifications wddelay[3:0] wd timeout typ 0000 8*wd_tclk 0001 9*wd_tclk 0010 10*wd_tclk 0011 11*wd_tclk 0100 12*wd_tclk 0101 13*wd_tclk 0110 14*wd_tclk 0111 15*wd_tclk 1000 16*wd_tclk 1001 17*wd_tclk 1010 18*wd_tclk 1011 19*wd_tclk 1100 20*wd_tclk 1101 21*wd_tclk 1110 22*wd_tclk 1111 23*wd_tclk table 12. watchdog specifications parameter description test condition min typ max unit wd_tclk watchdog clock period tosc * 2 22 s
internal clock oscillator SABRE-LL-I 26/141 7 internal clock oscillator 7.1 overview s.a.b.re includes a free running oscillator that does not require any external components. this circuit is used to generate the time base needed to generate the internal timings; the typical frequency is 16mhz. the oscillator circuit starts as soon as the ic ex its from the power on re set condition and it is stopped only when in ?low power mode?. 7.2 internal clock specifications table 13. internal clock specifications parameter description test condition min typ max unit f osc oscillator frequency v 3v3 =3.3v 14.4 16 17.6 mhz t osc oscillator period 1/fosc
SABRE-LL-I start-up configurations 27/141 8 start-up configurations 8.1 overview s.a.b.re start-up configuration is selected by setting in different states the gpio[0], gpio[3] and gpio[4] pins. each of these is a three state input pin and is able to distinguish among the following situations: note: ?shorted? means: r 1kohm; ?z? means: r 10kohm, c 200pf 8.2 operation modes when v supply voltage is applied to s.a.b.re, the internal regulator v3v3, used to supply the logic circuits inside the device, starts its functionality. when it reaches its final value, s.a.b.re enables the gpio[0] pin state read ci rcuitry, and, after a time tpinsample, it will sample the gpio[0] state. if it is found to be in high impedance, s.a.b.re does not consider gpio[3] and gpio[4] pins state and starts its ?basic device? mode sequence. if gpio[0] is found to be connected to ground or to v3v3, s.a.b.re checks the state of gpio[3] and gpio[4] pins to select its start-up configuration. the possible configurations can be classified in four ?major? modes: 1. basic device. 2. slave device. 3. master device. 4. single device. hereafter is reported the correspondence table between gpio[x] state and s.a.b.re configurations. table 14. possible start-up pins state symbol pin condition state symbol shorted to ground 0 shorted to v 3v3 pin 1 floating z
start-up configur ations SABRE-LL-I 28/141 8.3 basic device mode the basic device mode is selected by leaving the gpio[0] pin floating. in this mode s.a.b.re doesn?t use gpio[3] and gpio[4] as configuration pins, leaving them free for other uses. when in this mode the regulators included in the start up sequence (except v main_sw ) are considered as system regulators and they start in the following sequence: 1. auxiliary switching regulator1 (v aux1_sw ). 2. auxiliary switching regulator2 (v aux2_sw ). 3. main linear regulator (v main_lin ). 4. main switch ing regulator (v main_sw ) (not system regulator). table 15. start-up correspondence pin state (1) 1. ?x? means ?don?t care?. major mode minor mode (2) 2. the description of these modes is in the following paragraph 9.7. gpio[0] gpio[3] gpio[4] zxxbasic 000 single bridge 0 0 z primary regulator 001 regulators 0 z 0 simple regulator 0 z z bridge + vext 0 z 1 secondary regulators 010 master bridge 0 1 z primary regulator 011 regulators 1 0 0 simple regulator 1 0 z bridge + vext 1 0 1 secondary regulators 1z0 slave bridge 1 z z primary regulator 1 z 1 regulators 1 1 0 simple regulator 1 1 z bridge + vext 1 1 1 secondary regulators.
SABRE-LL-I start-up configurations 29/141 8.4 slave device mode in slave device mode, s.a.b.re consider the nawake pin as an input enable. since this is now a digital pin, the current pull up source inside the nawake circuit is disabled. at the startup, if the nawake pin is foun d to be low for a period higher than t awakefilt seconds, s.a.b.re enters dire ctly in the ?low power mode ?; when nawake pin is pulled high for a period higher than t awakefilt seconds, s.a.b.re begins its start up procedure. 8.5 master device mode in master device mode, s.a.b.re begins its start up procedure without waiting for any external enable signal and it uses gpio[5] pin to drive the nawake pin of slave devices. during the whole start up time, it forces its gpio[5] pin at logic level ?0? in order to maintain all slave devices in ?low power mode? as previously described. when start up operations are completed, s.a.b.re forces the gpio[5] output to logic level ?1? to enable the slave devices and keeps gpio[5] output at high level until it senses an under-voltage on any of its system regulators. if firmware writes in the pwrctrl register to set master s.a.b.re in ?low power mode? it immediately forces gpio[5] output to logic level ?0? to force the slave devices to enter in ?low power mode?, then it waits for t mastwait time and it starts its ?low power mode? sequence. 8.6 single device mode in single device mode, the device behaves similarly to master device mode but: 1. it doesn?t use the gpio[5] pin to drive slave devices. 2. it doesn?t wait for t mastwait before entering in ?low power mode?. 8.7 sub-configurations for slave, master or single device modes each slave, master or single device modes can be divided in other minor modes depending on the start-up sequence needed for s.a.b.re internal regulators. unless otherwise specified, in all the following modes the regulators included in the start up sequence are considered system regulators and they start in the sequence indicated. 8.7.1 bridge mode in this configuration bridges 3 and 4 are not used as regulators and therefore can be configured by the firmware in any of their possible bridge modes. when in this mode the power-up sequence is: 1. main switching regulator (v main_sw ). 2. main linear regulator (v main_lin ). 8.7.2 primary regulator mode (kp) in this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators. the last regulator in the sequence (v aux2_sw ).is not considered a system regulator.
start-up configur ations SABRE-LL-I 30/141 when in this mode the power-up sequence is: 1. auxiliary switching regulator1 (v aux1_sw ). 2. main switch ing regulator (v main_sw ) together with main linear regulator (v main_lin ). 3. auxiliary switching regulator2 (v aux2_sw ) (not system regulator). 8.7.3 regulators mode in this configuration bridge 4 can be configured by firmware while bridge 3 is configured as two separate synchronous switching regulators, but the start up sequence is different previous one. when in this mode the power-up sequence is: 1. main switching regulator (v main_sw ). 2. auxiliary switching regulator1 (v aux1_sw ) 3. auxiliary switching regulator2 (v aux2_sw ) 8.7.4 simple r egulator mode (kt) also in this configuration bridge 4 can be configured by firmware while bridge3 is configured as two separate synchronous switching regulators. the last regulator in the sequence (v main_sw ).is not considered a system regulator. when in this mode the power-up sequence is: 1. auxiliary switching regulator1 (v aux1_sw ). 2. auxiliary switching regulator2 (v aux2_sw ) 3. main linear regulator (v main_lin ) 4. main switch ing regulator (v main_sw ) (not system regulator). 8.7.5 bridge+ v ext mode in this configuration bridges 3 and 4 are not used as regulators and the regulator obtained using the switching regulator controller (v ext ) is included in start-up. when in this mode the power-up sequence is: 1. main switching regulator (v main_sw ). 2. switching regulator controller regulator (v ext ). 3. main linear regulator (v main_lin ). 8.7.6 secondary regulators mode in this configuration, bridge 3 is configured as a single synchronous switching regulator using its two half bridges in parallel (v aux_(1//2)sw ). when in this mode the power-up sequence is: 1. main switching regulator (v main_sw ). 2. auxiliary switching regulator (v aux(1//2)_sw ). 3. main linear regulator (v main_lin ).
SABRE-LL-I power sequencing 31/141 9 power sequencing 9.1 overview as soon as v supply and v supplyint are above their power on reset level, s.a.b.re will start the charge pump circuit; once v pump voltage reaches its under voltage rising threshold, s.a.b.re begins a sequence that starts the regulators considered system regulators. a regulator is considered a system regulator if: ? it has to start in on state without any user action. ? it is included in the power-up sequence. ? its under-voltage event is considered by s.a.b.re as an error condition to be signaled through nreset pin. once v supply and v supplyint , v pump and all the system regulators are over their under voltage rising threshold, s.a.b.re enters in the normal operating state, that will release nreset pin and will wait for spi commands. s.a.b.re will reduce the noise introduced in th e system by switching out of phase all its power circuits (switching regulators, bridges and charge pump). the s.a.b.re's startup sequence of operation is the following: ? start v 3v3 internal linear regulator ? sample startup configuration ? wait enable if slave device ? start charge pump ? start system regulators (see order in section 8.7 ) ? send enable to slave device, if master ? wait until v gpio_spi becomes ok
power saving modes SABRE-LL-I 32/141 10 power saving modes 10.1 overview saving power is very important for today platforms: s.a.b.re implements different functions to achieve different levels of power saving. sections here below describe these different power saving modes. 10.2 standby mode almost all low voltage circuitry inside s.a.b.re are powered by v 3v3 internal regulator; this regulator is a linear regulator powered by v supplyint. this means that all the current provided by v 3v3 regulator is directly coming from v supplyint and therefore the total power consumption is: low voltage power = v supply * i v3v3 . because v supplyint is feeded by v supply , directly or with a resistor in series. this power could be reduced by using a switching buck regulator to supply v 3v3 : in this case, assuming the buck regulator efficiency near to 100%, the dissipated power would become: low voltage power 3.3v * i v3v3 . to achieve this result there is the need to switch off the internal v 3v3 linear regulator and to use an additional pin to provide a 3.3v supply to internal circuits. s.a.b.re can do this by using the low voltage switch implemented on gp io6 pin. this switch internally connects v gpiospi voltage to gpio6 output so, by externally connecting gpio6 to v 3v3 pin, the v gpiospi voltage can be provided to low voltage circuitry inside s.a.b.re. figure 5. standby mode function description 3.3v gpio6 vgpios p i power switch 1 vsu pp l y int v3v3 regulator - + stdbymode 3.3 v 1.9 v 0 1 external connection
SABRE-LL-I power saving modes 33/141 the stdbymode bit used to switch off v 3v3 and switch on the power switch can be set to ?1? by writing the standby command in the stdbymode register. s.a.b.re exits standby mode if a reset event happens or ?low power mode? is selected. because all internal low voltage circuitry powered by v 3v3 are designed to work with a 3.3v voltage rail, when the standby mode is used, v gpiospi is requested to be at 3.3v. 10.3 hibernate mode s.a.b.re?s hibernate mode allows the firmware to switch off some (or all) selected system regulators leaving in on stat e only those necessary to resume s.a.b.re to operative condition when waked-up by an external signal. hibernate mode is selected when the firmware writes the command word in the hibernatecmd register. when in hibernate mode s.a.b.re will force regu lators in the state (on/off) selected by the firmware by writin g in the hibernatecmd register and will force nreset pin low. the exiting from hibernate mode is achieved by forcing at low level nawake pin (or gpio5 pin if s.a.b.re is in slave mode); s.a.b.re will also exit from hi bernate mode if an undervoltage event happens on v supply , v supplyint , v pump or v 3v3 . when the exit from hibernate mode is due to an external command, s.a.b.re sets to ?1? the bit hibmodelth in the hibernatestatus register. 10.4 low power mode when in normal operating mode, the microcontroller can place s.a.b.re in ?low power mode?. in this condition s.a.b.re sets all bridges outputs in high impedance, powers down all regulators (including system regulators and charge pump) and disables almost all its circuits including internal clock reducing as much as possible power consumption. the only circuits that remain active are: ?v 3v3 internal regulator. ? nawake pin current pull-up. ? nreset pin that will be pulled low. ? por circuit. the entering in low power mode is obtained in different ways depending if s.a.b.re is configured as slave device or not. when s.a.b.re is configured as slave device the low power mode is directly controlled by nawake pin that acts as an enable: if this pin is low for a time longer then t awakefilt , low power mode is entered; if this pin is high s.a.b.re exits from low power mode. in all other start-up configurations, low power mode is entered by writing a low power mode command in the powermodecontrol register; once s.a.b.re is in low power mode it starts checking the nawake pin status: if it is found low for a time longer than t awakefilt , s.a.b.re exits from low power mode and restarts its startup sequence. when the nawake pin is externally pulled low, the ?aw ake? event is stored and it is readable through spi. s.a.b.re will also exit from low power mode if a por event is found. note: when in ?low power mode? v supply is monitored only for its power on reset level.
power saving modes SABRE-LL-I 34/141 10.5 nawake pin at the start up, before s.a.b.re has identified the required operation mode (see chapter 8 ), a current sink iinp is always active to pull down nawake pin. as soon as the operation mode (basic, slave, master or single device) is detected, the functionality of nawake pin will be different. if s.a.b.re is not configured as slave device a current source iout will be active on this pin, while the current sink iinp will be disabled. if s.a.b.re is configured as a slave device, the current sink iinp will be active until nawake pin is detected high for the first time; after that both current sources iinp and iout w ill be disabled and t he nawake pin can be considered as a digital input. here below is reported the na wake pin simplified schematic. figure 6. nawake function block diagram table 16. nawake function specifications parameter description test condition min typ max unit v il nawake logic low threshold 0.8 v v ih nawake logic high threshold 1.6 v v hys nawake input hysteresys 0.25 v i out nawake pin output current nawake=0v (1) 1. current is defined to be positive when flowing into the pin. - 0.72 - 2 ma i inp nawake pin input current nawake=0.8v (1 ) 0.2 0.4 ma t awakefilt filter time 1.2 ns v 3v3 i out awake_req awake slavemod e nawake seen high for the first time after start up. i inp
SABRE-LL-I linear main regulator 35/141 11 linear main regulator 11.1 overview the linear main regulator is directly powered by v supply voltage and it is one of the regulators that s.a.b.re could consider as a system regulator. this means that the voltage generated by this regulator is not used to powe r any internal circuit, but s.a.b.re will check that the feedback voltage v linmain_fb is in the good value range before enabling all its internal functions. when an under-voltage event (with a duration longer than period t linear_uv defined by the deglitch filter) is detec ted during normal operation, s.a.b.re will enter in reset state and it will signal this ev ent to the microcontroller by pulling low the nreset pin and disabling most of its internal blocks. here are summarized the primary features of the regulator: ? regulated output voltage from 0.8v to v supply -2v with a maximum load of 10ma. ? band gap generated internal reference voltage. ? short circuit protected (output current is clamped to 22ma typ). ? under voltage signal (both continuous and latched) accessible through serial interface. ? low power dissipation mode. the internal series element is a p-channel mos device. the voltage regulator will regulate its output so that feedback pin equals v linmain_fb , therefore the regulated voltage can be calculated using the formula: v linmain_out = v linmain_ref *(ra+rb)/rb figure 7. linear main regulator to extend the output current ca pability this regulator can be used as a controller for an external active component able to provide higher current (i.e. a darlington device); the external power element allows the handling of an higher current since it dissipates the driver v linmain_ref cc r a r b + - body diode v su pp l y v linmain_out v linmain_fb
linear main regulator SABRE-LL-I 36/141 power externally (the power dissipated by a linear driver supplied at v supply and regulating a voltage v linmain_out with an output current i out is about: pd= (v supply -v linmain_out )*i out . figure 8. linear main regulator external bipolar example whichever configuration is used (regulator or controller), a ceramic capacitor must be connected on the output pin to wards ground to guarantee the stability of the regulator; the value of this capacitance is in the range of 100nf to 1f depending on the regulated voltage. when this regulator is disabled, the whole circuit is switched off and the current consumption is reduced to a very low level both from v3v3 and from v supply . when in this condition, the output pin is pulled low by an internal switch. table 17. system linear regulator operating specifications parameter description test condition min typ max unit v linmain_out output pin voltage range (1) 0v supply v v drop drop out voltage v drop = v supply -v linmain_out 2v i pd internal switch pull down current linear main regulator disabled; v linmain_out =1v 3ma v linmain_fb feedback pin voltage range 03.6v v linmain_ref feedback reference voltage 0.776 0.8 0.824 v i linmain_ref feedback pin input current -2 2 a driver v linmain_ref + - body diode c load r a r b v linmain_fb v su pp l y v linmain_out cc
SABRE-LL-I linear main regulator 37/141 i outlinmax maximum output current regulated voltage = v supply -2v 10 ma i short output short circuit current v linmain_out =0v, v linmain_fb =0v 12 24 ma ? v out /v o load regulation 0 i load i outlinmax (2) 0.8 % ? v out / ? v supply line regulation i load =10ma (2) 0.2 % v loop_acc loop voltage accuracy 2.5 % v uvfall under voltage falling threshold (3) 84.5 87 89.5 % v uvrise under voltage rising threshold (3) 90.5 93 95.5 % v uvhys under voltage hysteresis (3) 6% t prim_uv under voltage deglitch filter 5us c c compensation capacitance v linmain_out =0.8v 0.8v 5v 1 0.68 0.33 0.1 f 1. the external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. load regulation is calculated at a fi xed junction temperature using shor t load pulses covering all the load current range. this is to avoid change on output voltage due to heating effect. 3. undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (v linmain_ref ). table 17. system linear regulator operating specifications (continued) parameter description test condition min typ max unit
main switching re gulator SABRE-LL-I 38/141 12 main switching regulator 12.1 overview main switching regulator is an asynchronous switching regulator intended to be the source of the main voltage in the system. it implements a soft start strategy and could be a system regulator so even if its output voltage v main_sw is not used to power any internal circuit, s.a.b.re will check that it is in the good value range before enabling all its internal functions. when s.a.b.re detects a system regulator under-voltage event with a duration longer than the period defined by the deglitch filter (t prim_uv ), it will enter in reset state signaling this event to the mi crocontroller by pullin g low the nreset pin and disabling most of its internal block (e.g. bridges, gpios, ?). the output voltage will be externally set by a di vider network connected to feedback pin. to reduce as much as possible the regulation voltage error s. a.b.re has the possibility to choose between four feedback voltage references (and, as a consequence, four under- voltage thresholds) using the serial interface. the feedback reference voltage selection is made by writing the selfbref bits in the mainswcfg register according to the table here below: reference voltage range can be changed by using a metal layer change in order to adapt them to cust omer system. here after are summarized the primary features of this regulator: ? internal power switch. ? soft start circuitry to limit inrush current flow from primary supply. ? internally generated pwm (250khz switching frequency). ? nonlinear pulse skipping control. ? protected against load short circuit. ? cycle by cycle current limiting using internal current sensor. ? under voltage signal (both continuous and latched) accessible through spi. when s.a.b.re is in ?low power mo de?, this regulator will be disabled. in order to save external components and power when using two or more s.a.b.re ic?s on the same board, the primary switching regulator can be disabled by serial interface. care must be paid using this function because an under-voltage on this regulator, as previously seen, will be read as a fault condition by s.a.b.re. table 18. switching regulator controller pwm specification mainswcfg register reference voltage (v fbref ) unit comments selfbref[1] selfbref[0] min typ max 0 0 0.776 0.8 0.824 v 0 1 0.97 1 1.03 v default state 1 0 2.425 2.5 2.575 v 1 1 2.910 3 3.09 v
SABRE-LL-I main switching regulator 39/141 12.2 pulse skipping operation pulse skipping is a well known, non linear, cont rol strategy used in switching regulators. in this technique (see figure 9 ) the feedback comparator output is sampled at the beginning of each switching cycle. at this time, if the sampled value shows that output voltage is lower than requested one, the complete pwm duty cycle is applied to power switch; otherwise no pwm is applied and the switching cycle is skipped. once pwm is applied to power element only a current limit event can disable the power switch before the whole duty cycle is finished. figure 9. main switching regulator functional blocks in pulse skipping control the duty cycle must be chosen by the user depending on supply voltage and output regulated voltage. therefore the switching regulator has 4 possible duty cycles that can be changed by writing the vmainswselpwm bits in the mainswcfg register according to following table. adjustable duty cycles can be changed by a metal layer change in order to adapt it to customer system. the only limitat ion is that all regulators share the same duty cycle bus, so any modification must consider all regulators duty cycles. table 19. main switching regulator pwm specification mainswcfg register duty cycle value comments vmainswselpwm[1:0] typical 00 12% 01 15% 10 26% default state 11 63.5% la vsupply c high side driver control logic current sense charge pump voltage vswmain_fb voltage loop control re g ulator ref - + under voltage threshold filter r a r b from central logic regulator freq - + to central logic under voltage flag vswmain_sw
main switching re gulator SABRE-LL-I 40/141 the output curr ent is limited to a value that can be set by means of selilimit bit in the mainswcfg register according to following table: table 20. main switching regulator current limit selilimit current limit (min) comments 0 3.3a default state 12.3a table 21. main switching regulator specifications parameter description test condition min typ max unit v main_sw output pin voltage range (1) -1 v supply v i q output leakage current t junction = 125c -40 +40 a i qlp output leakage current in ?low power mode? v supply = 36v t junction = 125c -15 +5 a i qfb feedback pin current t junction = 125c -10 +0 a v out output voltage range (2) 0.8 5 v i load output load current v supply = 36v 0.002 3 a r onh internal high side rdson iload=1a t junction = 125c 0.55 o v loop loop voltage accuracy 3% v regr output voltage ripple (rms) l =150u, c=330f/esr=0.54 ? (3) 28 mv rms v uvfall under voltage falling threshold (4) 84.5 87 89.5 % v uvrise under voltage rising threshold (4) 90.5 93 95.5 % v uvhys under voltage hysteresys 6 % t prim_uv under voltage deglitch filter 5us i limit current limit protection selilimit =?0? selilimit =?1? 3.3 2.3 5 3.5 tbd tbd a a t deglitch current limit deglitch time 50 ns t i_lim current limit response time in normal operating mode (no uv) (5) 650 ns t i_limuv current limit response time in uv condition. when in under voltage (6) 400 ns t r switching output rise time v supply = 36v, resistive load to gnd = 422 ? (7) 530ns t f switching output fall time v supply = 36v, resistive load to gnd = 10 ? (7) 530ns f regpwm operating frequency fosc/64 khz
SABRE-LL-I main switching regulator 41/141 1. the external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. the regulated voltage can be calculated using the formula: v main_sw = vfbref *(ra+rb)/rb. 3. the choice of proper values fo r l and c depends from the application. 4. undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (v sw_main_fb ). 5. this condition is intended to simulate an extra current on output. 6. this condition is intended to si mulate a short circuit on output. 7. rise time is measured between 10% and 90% of supply voltage.
switching regulator controller SABRE-LL-I 42/141 13 switching regulator controller 13.1 overview this circuit controls an external fet to implement a switching buck regulator using a non linear pulse skipping control with internally generated pwm signal. the output voltage will be externally set by a divider netwo rk connected on feedback pin. to reduce as much as possible the regulation voltage error s. a.b.re has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-voltage thresholds) using serial interface. the feedback reference voltage is selected by writing the selfbref bits in the swctrc fg register according to the following table. adjustable feedback voltages can be changed using a metal layer change in order to adapt it to customer system. this regulator is switched of f when s.a.b.re is powered up for the first time and can be enabled using s.a.b.re?s spi interface. here after are summarized the main features of the regulator: ? soft start circuitry to limit inrush current flow from primary supply. ? changeable feedback reference voltage ? internally generated pwm (250khz switching frequency). ? nonlinear pulse skipping control. ? protected against load short circuit. ? cycle by cycle current limiting using internal current sensor. ? under voltage signal (both continuous and latched) accessible through spi. table 22. switching regulator controller pwm specification swctrcfg register reference voltage (v fbref ) unit comments selfbref[1] selfbref[0] min typ max 0 0 0.776 0.8 0.824 v default state 0 1 0.970 1 1.030 v 1 0 2.425 2.5 2.575 v 1 1 2.910 3 3.09 v
SABRE-LL-I switching regulator controller 43/141 figure 10. switching regulator controller functional blocks 13.2 pulse skipping operation pulse skipping strategy has already been explained on main switching regulator section. this regulator has 4 possible pwm duty cyc les that can be changed writing in the selswctrpwm bits in the s wctrcfg register using spi. adjustable duty cycles can be changed using a metal layer change in order to adapt it to customer system. the only limitat ion is that all regulators share the same duty cycle bus, so any modification must consider all regulators needed duty cycles. v out la v suppl y c driver control logic current sense charge pump voltage voltage loop control vfbref - + under voltage threshold filter r a r b from central logic regulator freq - + to central logic under voltage flag r sense v swdrv_gate n-ch fet analog mux vref = 3 v vref=0.8v selfbref [1:0] analog mux uv threshold 1 selfbref uv threshold 2 vref = 3v vref=0.8v v swdrv fb v swdrv sw v swdrw_sns table 23. switching regulator controller pwm specification swctrcfg register duty cycle value comments selswctrpwm[1:0] typical 00 9% 01 12% 10 22.5% default state 11 58%
switching regulator controller SABRE-LL-I 44/141 13.3 output equivalent circuit the switching regulator controller output driving stage can be represented with an equivalent circuit as in the figure below: figure 11. switching regulator controller output driving equivalent circuit as can be seen from the above figure, the external switch gate is charged with a current generator i source and it is discharged towards ground with a current generator i sink that is applied for a t sink pulse while an equivalent resistor r sustain is connected between gate and source until the sink command is present. the table here below lists the values of the above mentioned parameters: table 24. switching regulator controller operating specification parameter description test condition min typ max unit i source source current v pump =v supply +12v v swctr_gate =0v 25 50 ma i sink sink current v swctr_gate = v supply 20 ma t sink sink discharge pulse time 600 ns r sustain gate-source sustain resistance (v swctr_gate - v swctr_src ) = 0.2v 650 ? v swdrv_gate vpump i sourc e v swdrv_sw r sustain source command sink pulse comman d i sink sink command tsink
SABRE-LL-I switching regulator controller 45/141 13.4 switching regulator controller specifications 13.5 switching regulator contro ller application considerations this controller can implement a step-down switching regulator used to provide a regulated voltage in the range 0.8v ? 32v. such kind of variation could be managed by considering table 25. switching regulator controller operating specification parameter description test condition min typ max uni t v swdrv_sw v swdrv_sw pin voltage range (1) 1. under voltage rising and falling thres holds are referred to feedback pin voltage. -1 v supply v v swdrv_gat e gate drive pin voltage 0 v pump v v swdrv_sns sense pin voltage v supply -3v v supply v v vgs_ext gate to source voltage for ext fet v pump v i q output leakage current v supply = 36v, t junction = 125c -15 +15 a i qlp output leakage current in ?low power mode? v supply = 36v, t junction = 125c -5 +5 a v swdrv_fb v swdrv_fb pin current v supply = 36v, t junction = 125c -10 +10 a v loop loop voltage accuracy 3% v uvfall (1) under voltage falling threshold 84.5 87 89.5 % v uvrise (1) under voltage rising threshold 90.5 93 95.5 % v uvhys (1) under voltage hysteresys 6 % t prim_uv under voltage deglitch filter 5 us v ovc over current threshold voltage 250 300 350 mv t deglitch current limit deglitch time 50 ns t i_lim current limit response time in normal operating mode (no uv) (2) 2. this condition is intended to simulate an extra current on output. 900 ns t i_limuv current limit response time in uv condition. when in under voltage (3) 3. this condition is intended to si mulate a short circuit on output. 550 ns f regpwm operating frequency fosc/6 4 khz
switching regulator controller SABRE-LL-I 46/141 some constraints in the application and part icularly by choosing the correct feedback reference voltage as indicated in the following table: typical application can be considered the following, supposing the external mosfet type std12nf06l: ? max dc current load = 3a ? typ over current threshold = 3a * 1.5 = 4.5a ? l = 150 h ? c = 220-330 f in this conditions the step-down regulator will result over-load protected, short-circuit protected over all the regulated voltage range and the v supply range. other application configurations could be evaluated before being implemented. table 26. switching regulator controller application feedback reference output regulated voltage range feedback voltage reference 0.8v v out < 5v 0.8v - 1v 5v v out 32v 2.5v - 3v
SABRE-LL-I power bridges 47/141 14 power bridges 14.1 overview s.a.b.re includes four h bridge power outputs (each one made by two independent half bridges) that are configurable in several different configurations. each half bridge is protected against: over-current, over-temperature and short circuit to ground, to supply or across the load. when an over current event occurs, all outputs are turned off (after a filter time), and the over current bit is stored in the internal status register that can be read through spi. positive and negative voltage spikes, which occur when switching inductive loads, are limited by integrated freewheeling diodes (see figure 12 ). figure 12. h bridge block diagram during the start up procedure the bridges are in high impedance and after that they can be enabled through spi. when a fault condition happens, i.e. an over-temperature event, the bridges return in their start-up condition and they need to be re-enabled from the micro controller. the bridges can use pwm signals internally generated or externally provided (supplied through the gpio pins). internally genera ted pwm signals will run at approximately 31.25khz with a duty cycle that, through serial interface, can be programmed and incremented in steps of 1/(512*fosc). to reduce the peak current requested from supply voltage when all bridges are switching, the four internally generated pwm signals are out- of-phase. each half bridge will use the pwm signal selected by the respective mtrxselpwmsidey[1:0] (x stands for 1, 2, 3 or 4; y stands for a or b) bits in the spi, but if high side driver low side driver control logic high side driver low side driver control logic
power bridges SABRE-LL-I 48/141 two half bridges are configured as a full brid ge, only the pwm signal chosen for side a will be used to drive the resulting h bridge. more in detail the pwm selection truth tabl e will be as describe in the following tables: here below is reported a block diagram representing the possible pwm choices for each s.a.b.re half bridges. the figure is related only to bridges 1 and 2, but it could be assumed to be valid also for bridges 3 and 4, with few differences due to different possible configurations of these last drivers. table 27. pwm selection truth for bridge 1 or 2 mtrxselpwmsidey [1] mtrxselp wmsidey [0] selected pwm (1) 1. in this table x stands for 1 or 2, y stands for a or b. 00 motorxpwm (configurable by means of mtrxcfg register). 01 auxxpwm (configurable by means of auxpwmxctrl register). 1 0 extpwm1 (from gpio 9 input) 1 1 extpwm2 (from gpio 10 input) table 28. pwm selection truth for bridge 3 or 4 mtrxselpwmsidey [1] mtrxselp wmsidey [0] selected pwm (1) 1. in this table x stands for 3 or 4, y stands for a or b. 00 motorxpwm (configurable by means of mtrxcfg register). 01 auxxpwm (configurable by means of auxpwmxctrl register). 1 0 extpwm3 (from gpio 2 input) 1 1 extpwm4 (from gpio 11 input)
SABRE-LL-I power bridges 49/141 figure 13. bridge 1 and 2 pwm selection 00 motor2 pwm 01aux2pwm 10extpwm1 11extpwm2 mtr2selpwmside a [1:0] 00 motor2 pwm 01 aux2pwm 10 extpwm1 11 extpwm2 mtr2selpwmside a [1:0] motor 2 side a logic table motor 2 side b logic table side a power section side b power section mtr2tablel[1:0] mtr1_2parallel mtr2tablel[1:0] mtr1_2parallel bridge 2 00 motor1 pwm 01 aux1pwm 10 extpwm1 11 extpwm2 mtr1selpwmside a [1:0] 00 motor1 pwm 01aux1pwm 10extpwm1 11extpwm2 mtr1selpwmsideb [1:0] mtr1tablel[1:0] motor 1 side a logic table motor 1 side b logic table side a power section side b power section mtr1_2parallel bridge 1
power bridges SABRE-LL-I 50/141 14.2 power bridges operating specifications table 29. power bridges operating specifications parameter description test condition min typ max unit r on_1_2 bridge 1 and 2 diagonal ron i = 1.4a, v supply = 36v, t junction = 125c 1.0 ? r on_3_4 bridge 3 and 4 diagonal ron i = 1a, v supply = 36v, t junction = 125c 1.5 ? i max bridge 1 and 2 max operative current 2.5 a i max bridge 3 and 4 max operative current 1.5 a i dss output leakage current. t junction = 125c -50 +50 a i qlp output leakage current in ?low power mode? v supply = 36v, t junction = 125c -10 +10 a i protl_1&2 low side current protection for bridges 1 & 2 (1) mtrxsideyilim sel[1:0]=00 mtrxsideyilim sel[1:0]=01 mtrxsideyilim sel[1:0]=10 mtrxsideyilimsel[1:0]=11 (2) 0.6 1.4 2.4 2.4 1.6 2.6 3.6 3.6 a i proth_1&2 high side current protection for bridges 1 & 2 (1) mtrxsideyilim sel[1:0]=00 mtrxsideyilim sel[1:0]=01 mtrxsideyilim sel[1:0]=10 mtrxsideyilimsel[1:0]=11 (2) 0.7 1.5 2.5 2.5 1.7 2.7 3.7 3.7 a i prot_3 low side current protection for bridges 3 & 4 (1) mtrxsideyilimsel[1:0]=11 (3)(4) 1.55 2.5 a i prot_4 high side current protection for bridges 3 & 4 (1) mtrxsideyilimsel[1:0]=11 (3)(4) 1.6 2.5 a t filter current limit filter time 25us t delay current limit delay time 5us t oc_off over current off time mtrxilimitofftimey[1:0]=00 mtrxilimitofftimey[1:0]=01 mtrxilimitofftimey[1:0]=10 mtrxilimitofftimey[1:0]=11 (5) 60 120 240 480 ns ns ns ns t r1_2 output rise time bridges 1 &2 v supply = 36v, resistive load between outputs: r= 25 ohm (6) 100 250 ns t r3_4 output rise time bridges 3 & 4 v supply = 36v, resistive load between outputs: r= 36 ohm (6) 50 200 ns t f1_2 output fall time bridges 1 & 2 v supply = 36v, resistive load between outputs: r= 25 ohm (6) 100 250 ns
SABRE-LL-I power bridges 51/141 14.3 possible configurations the selection of the bridge configuration is done through spi, by writing the mtrxtable[1:0] bits in the mtrxcfg register. the table below shows the correspondence between mtrxtable[1:0] bits and the bridge configuration. bridge 1 & 2 can be paralleled by means of mtr1_2parallel bit in the mtr1_2cfg register: bridge 1 and 2 paralleled will form superbridg e1, bridge x side a and bridge x side b paralleled form superhalfbridgex or superswitchx. bridge 3 & 4 can be configured by means of mtr3_4cfgtable[1:0] bits in the mtr3_4cfg register according to following table: t f3_4 output fall time bridges 3 & 4 v supply = 36v, resistive load between outputs: r= 36 ohm (6) 50 250 ns t deadrise anti crossover rising dead time 100 450 ns t deadfall anti crossover falling dead time 100 450 ns f pwm operating frequency fosc /512 khz t resp delay from pwm to output transition 500 ns 1. the current protection values must be intended as a protection for the chip and not as a continuous current limitation. the protection is perfo rmed by switching off the output br idge when current reaches values higher than the iprot max. no protection could be guaranteed for values in the middle range between ioperative max and iprot. 2. in this cell x stands for 1 or 2, y stands for a or b 3. in this cell x stands for 3 or 4, y stands for a or b 4. the current protection thresholds for bridge 3 an d 4 are not selectable so only the max current value (mtrxsideyilimsel[1:0] = 11) is available. 5. over current off time can be configured using spi. 6. rise and fall time are measured between 10% and 90% of supply voltage. with device in full bridge configuration (resistive load between outputs). table 29. power bridges operating specifications (continued) parameter description test condition min typ max unit table 30. bridge selection truth mtrxtable[1] mtrxtable[0] bridge truth 0 0 full bridge configuration 0 1 high or low side switch configuration 1 0 half bridge configuration 1 1 high or low side switch configuration
power bridges SABRE-LL-I 52/141 the possible configurations for the bridges are described in the following: 14.3.1 full bridge when in full bridge configuration, the driv ers will behave according to the following truth table: note: when ?low power mode? is active, the bridges will enter in low power state and will reduce its biasing thus contributing to the power saving. when a current limit event occurs this event wi ll be latched and the bridges will remain in high impedance state for the toff time. table 31. bridge 3 and 4 configuration mtr3_4cfgtable[1] mtr3_4cfgtable[0] bridge 3 and 4 configuration 0 0 two independent bridges 0 1 two bridges in parallel 1 0 stepper motor 1 1 stepper motor table 32. full bridge truth tsd nreset low power mode enable current limit mtrxctrl sidea mtrxctrl sideb pwm out+ out- 1x x xxx xxzz 00 x xxx xxzz 01 1 xxx xxzz 01 0 0xx xxzz 01 0 11 x xxzz 01 0 10 0 0 x00 01 0 10 0 1 011 01 0 10 0 1 101 01 0 10 1 0 011 01 0 10 1 0 110 01 0 10 1 1 x11
SABRE-LL-I power bridges 53/141 14.3.2 parallel configur ation (super bridge) bridges 1, 2, 3 and 4 can be configured to be us ed two by two (1 plus 2, 3 plus 4) as one super bridge thus enabling the driving of loads (motors) requiring high currents. in this configuration the half bridge s will be paralleled and will work as one phase of the super- bridge just created: the two phases + will become phase + of the newly created super- bridge while the two phases - will become phase ?. figure 14. super bridge configuration when this configuration is chosen for bridges 1 (3) and 2 (4), the resulting bridge will use the driving logic of bridge 1 (3) so for programming it must be used the bridge 1 (3) control and status bits (direction, pwm, ...): i. e. the used pwm si gnal will be chosen by mtr1sideapwmsel[1:0] (mtr3sideapwmsel[1:0]) bits in spi. if the bridges are not configured to be used in parallel, each side of the bridge will use the pwm selected by the respective mtrxpwmysel[1:0] bits in the spi, but if one of the two drivers is configured as a full bridge only one of the two selected pwm will be used to drive the motor and this is the pwm chosen for side a. in order to avoid any problem coming from different propagation times of pwm signals the anti-crossover dead times are slightly increased when the bridges are paralleled. 14.3.3 half bridge configuration each bridge can be configured to be used as 2 independent half bridges or as 1 super half bridge (see figure 15 ). it is also possible to parallel more than one bridge and use all of them as a single super half bridge. ph - ph + ph + ph - m bridge 2 (4) super bridge bridge 1 (3) ph - ph + ph + ph - m bridge 2 (4) super bridge bridge 1 (3) parallel full brid g e
power bridges SABRE-LL-I 54/141 figure 15. half bridge configuration in this case each half bridge will beha ve according to the following truth table. note: when ?low power mode? bit is active the bridges will reduce its biasing thus contributing to the power saving. when a current limit event occurs this event wi ll be latched and the bridges will remain in high impedance state for the toff time. table 33. half bridge truth tsd nreset low power mode enable current limit mtrxctrl sidea/b pwm out 1xxxxxxz 0 0xxxxxz 0 1 1xxxxz 0100xxxz 0101000z 01010010 0101010z 01010111 01011xxz high side driver low side driver control logic dcx phase output v supply v pump control signals from spi fault signals
SABRE-LL-I power bridges 55/141 14.3.4 switch configuration each bridge can be configured to be used as 2 independent switches that connects the output to supply or to ground. it is also possible to parallel the two switches and use them as a single super switch. all resulting switches will behave according to the following truth table. note: when ?low power mode? bit is active the bridge will reduce its biasing thus contributing to the whole power saving. when a current limit event occurs this event will be latched and the bridge will remain in high impedance state for the toff time. 14.3.5 bipolar stepper configuration the bridges 3 and 4 can be configured to be used as a micro-stepping, bidirectional driver for bipolar stepper motors. the primary features of the driver are the following: ? internal pwm current control. ? micro stepping. ? fast, mixed and slow current decay modes. each h-bridge is controlled with a fixed and se lectable off-time pwm current-control circuit that limits the load current to a value set by choosing v stepref voltage by means of the internal dac and an the external r sense value. the max current level could be calculated using the formula: i max =v stepref /r sense to obtain the best current profile, the user can choose three different current decay modes: slow, fast and mixed. initially, during ton, a diagonal pair of source and sink power mos is enabled and current flows through the motor winding and the sense resistor. when the voltage across the sense resistor reaches the programmed dac output voltage, the control logic will change the status of the bridge according to the selected decay mode (slow, fast or mixed). in slow decay mode the current is reci rculated through the path including both high side power mos for the whole toff time. in fast decay mode the current is recirculated through the high and low side power mos opposite respect to those forcing current to table 34. switch truth tsd nreset low power mode enable current limit mtrxctrl sidea/b pwm out 1xxxxxxz 0 0xxxxxz 0 1 1xxxxz 0100xxxz 010100xz 01010101 01010110 01011xxz
power bridges SABRE-LL-I 56/141 increase. mixed decay mode is a selectable mix of the previous two modes (fast decay followed by slow decay) and allows the user to find the best trade off between load current ripple and fast current levels transition. additionally, by setting the seqmixedonlyindecreasingph bit in the stpcfg1 register, the user can choose to apply the fast decay percentage in mixed mode always or only when the current is decreasing (i.e from 90 to 180 and from 270 to 360 of the sinusoidal wave). by using spi interface the user can choose: control type (external firmware control, half step, normal drive, wave drive, micro-step). up to 16 current levels (quasi-sin usoidal increments) for each bridge. current direction. decay mode. blanking time. off time (32 values from 2 s to 64 s). percentage of fast decay respect to toff (when in mixed decay mode).
SABRE-LL-I power bridges 57/141 figure 16. bipolar stepper configuration the operating characteristics remain the same (when applicable) already seen in the power bridges operating specifications with the addition of the following: table 35. stepper specifications parameter description test condition min typ max unit v stepref reference voltage selstepref =0 selstepref =1 0.480 0.720 0.50 0.75 0.520 0.780 v sense_off sense comparator offset -12 12 mv v supply sens e ph+ ph- suppl y dc3 _ph+ dc3 _ph- dc4 ph+ dc4 ph - dc3 sense dc4 sense stepper motor sens e ph+ ph- suppl y vrefb vrefa - control logic - toff generation - dac reference selection bridge drive r bridge drive r v stepref vrefb vrefa stepperdacpha stepperdacphb selstepre f ref1 ref2
power bridges SABRE-LL-I 58/141 using the stepctrlmode[2:0] bits in stepcfg1 register, s.a.b.re can be programmed to internally generate the stepping levels. in these cases and depending on the stepfromgpio bit in the stpcfg1 register the stepper driver will move to next step each time the stepcmd bit is set at logic level ?1? or at each pulse transition longer than ~1 s externally applied on gpio12 (stepreq signal), according to following table: the allowable control modes are as follows: 1. stepping sequence left to external microcontroller: in this mode the current level in each motor winding is set by the microcontroller via the serial interface. 2. full step: in this mode the electrical angle will change by 90 steps at each stepreq signal transition. ther e are two possibilities: ? normal step (two phases on): in normal step mode both windings are energized simultaneously and the current will be alte rnately reversed. the resulting electrical angles will be 45, 13 5, 225 and 315. ? wave drive (one phase on): in wave drive mode each winding is alternately energized and reversed. the resulting electr ical angles will be 90 , 180 and 270 and 360. 3. half step: in this mode, one motor winding is energized and then two windings alternately so the electrical angles the moto r will do when rotating in clockwise direction and using the same current limit in both the phases are: 45, 90, 135, 180, 225, 270, 315 and 360. 4. microstepping: in this mode the current in each motor winding has a quasi sinusoidal profile. the increment between each step is obtained at each transition of stepcmd bit in stepcmd register. the difference between each step could be chosen (4, 8 or 16 levels for each phase) according to following table: note: when in 1/16 step mode, the best phase approximati on of sinusoidal wave, is obtained by repeating the ?f? step as follows: 0, 1, 2, 3, ? , d, e, f, f, f, e, d, ? , 3, 2, 1, 0 when internal stepping sequence generation is used, the stepping direction is set by the stepdir bit according to the following table. table 36. sequencer drive stepfromgpio sequencer driven by 0 stepcmd bit in stepcmd register. 1 gpio12 input pin. table 37. stepper mode stepctrlmode[2:0] control mode description 000 or 111 no control stepping sequence control left to the external controller 001 half step half step 010 normal step full step (two phases on) 011 wave drive full step (one phase on) 100 1/4 step four micro steps 101 1/8 step eight micro steps 110 1/16 step sixteen micro steps
SABRE-LL-I power bridges 59/141 note: it is intended as clockwise the sequence that forces a clockwise rotation of the versors representing the current module and phase. an internal dac is used to digitally control the output regulated current. the available values are chosen to provide a quasi sinusoidal profile of the current. the current limit in each phase is decided by phadac[3:0] bits for phase a and phbdac[3:0] bits for phase b. the table below describes the relation between the value programmed in the stepper dac and the current level: note: the min and max values are guaranteed by testin g the percentage of vstepref that allows the commuatation of the rsense comparator. i max =v stepref / r sense . to obtain the best phase approximation of a sinusoidal wave, the user needs to repeat the final (100%) value. so the full values sequence shoul d be as follows: 0, 1, 2, 3 ? d, e, f, f, f, e, d ? 3, 2, 1, 0. even if the total spread shows overlapping between current steps, the monotonicity is guaranteed by design. table 38. stepper sequencer direction stepdir direction 0 counter clockwise (ccw) 1 clockwise (cw) table 39. dac phxdac [3:0] phase current rati o respect to i max min typ max unit 0000 (hi-z) 0001 7.8 9.8 11.8 % of i max 0010 17.5 19.5 21.5 % of i max 0011 27.0 29.0 31.0 % of i max 0100 36.3 38.3 40.3 % of i max 0101 45.1 47.1 49.1 % of i max 0110 53.6 55.6 57.6 % of i max 0111 61.4 63.4 65.4 % of i max 1000 68.7 70.7 72.7 % of i max 1001 75.3 77.3 79.3 % of i max 1010 81.1 83.1 85.1 % of i max 1011 86.2 88.2 90.2 % of imax 1100 90.4 92.4 94.4 % of i max 1101 93.7 95.7 97.7 % of i max 1110 96.5 98.1 99.7 % of i max 1111 i max
power bridges SABRE-LL-I 60/141 when the internal sequencer the minimum angle resolution is nominally 5.625, so depending on the control mode chosen, the selectable steps are the following: table 40. internal sequencer control mode typical output current (% of imax ) resulting electrical angle half step full step (2 phases on) full step (1 phase on) 1/4 step 1/8 step 1/16 step phase a (sin) phase b (cos) electrical degrees 1 1 1 1 1 70.7 70.7 45 2 77.3 63.4 50.6 2 3 83.1 55.6 56.2 4 88.2 47.1 61.9 2 3 5 92.4 38.3 67.5 6 95.7 29.0 73.1 4 7 98.1 19.5 78.8 8 100 9.8 84.4 2 1 3 5 9 100 hiz 90 10 100 -9.8 95.6 6 11 98.1 -19.5 101.2 12 95.7 -29.0 106.9 4 7 13 92.4 -38.3 112.5 14 88.2 -47.1 118.1 8 15 83.1 -55.6 123.8 16 77.3 -63.4 129.4 3 2 5 9 17 70.7 -70.7 135 18 63.4 -77.3 140.6 10 19 55.6 -83.1 146.2 20 47.1 -88.2 151.9 6 11 21 38.3 -92.4 157.5 22 29.0 -95.7 163.1 12 23 19.5 -98.1 168.8 24 9.8 -100 174.4 4 2 7 13 25 hiz -100 180 26 -9.8 -100 185.6 14 27 -19.5 -98.1 191.2 28 -29.0 -95.7 196.9
SABRE-LL-I power bridges 61/141 8 15 29 -38.3 -92.4 202.5 30 -47.1 -88.2 208.1 16 31 -55.6 -83.1 213.8 3 32 -63.4 -77.3 219.4 5 9 17 33 -70.7 -70.7 225 34 -77.3 -63.4 230.6 18 35 -83.1 -55.6 236.2 36 -88.2 -47.1 241.9 10 19 37 -92.4 -38.3 247.5 38 -95.7 -29.0 253.1 20 39 -98.1 -19.5 258.8 40 -100 -9.8 264.4 6 3 11 21 41 -100 hiz 270 42 -100 9.8 275.6 22 43 -98.1 19.5 281.2 44 -95.7 29.0 286.9 12 23 45 -92.4 38.3 292.5 46 -88.2 47.1 298.1 24 47 -83.1 55.6 303.8 48 -77.3 63.4 309.4 7 4 13 25 49 -70.7 70.7 315 50 -63.4 77.3 320.6 26 51 -55.6 83.1 326.2 52 -47.1 88.2 331.9 14 27 53 -38.3 92.4 337.5 54 -29.0 95.7 343.1 28 55 -19.5 98.1 348.8 56 -9.8 100 354.4 8 4 15 29 57 hiz 100 360/0 58 9.8 100 5.6 30 59 19.5 98.1 11.2 table 40. internal sequencer (continued) control mode typical output current (% of imax ) resulting electrical angle half step full step (2 phases on) full step (1 phase on) 1/4 step 1/8 step 1/16 step phase a (sin) phase b (cos) electrical degrees
power bridges SABRE-LL-I 62/141 the voltage spikes on rsense could be filtered by selecting an appropriate blanking time on the output of current sense comparator. the blanking time selection is made by using the stepblktime[1:0] bits in the stpcfg1 register, according to following table: the stepper driver toff time could be programmed by means of the stepofftime[4:0] bits in stpcfg1 register: 60 29.0 95.7 16.9 16 31 61 38.3 92.4 22.5 62 47.1 88.2 28.1 32 63 55.6 83.1 33.8 64 63.4 77.3 39.4 table 41. blanking times specification stepblktime[1] stepblktime[0] blanking time unit comments min typ max 0 0 0.6 0.95 1.2 us default value 0 1 0.95 1.4 1.85 us 101.52.253us 1 1 3 4.25 5.5 us table 42. stepper off time stepofftime[4:0] off time unit typ 00000 2 us 00001 4 us 00010 6 us 00011 8 us 00100 10 us 00101 12 us 00110 14 us 00111 16 us 01000 18 us table 40. internal sequencer (continued) control mode typical output current (% of imax ) resulting electrical angle half step full step (2 phases on) full step (1 phase on) 1/4 step 1/8 step 1/16 step phase a (sin) phase b (cos) electrical degrees
SABRE-LL-I power bridges 63/141 by means of mixdecpha[4:0] and mixdecphb[4: 0] in stepcfg2 register, the percentage of toff time during which each phase will stay in fast decay mode could be programmed according to following table: 01001 20 us 01010 22 us 01011 24 us 01100 26 us 01101 28 us 01110 30 us 01111 32 us 10000 34 us 10001 36 us 10010 38 us 10011 40 us 10100 42 us 10101 44 us 10110 46 us 10111 48 us 11000 50 us 11001 52 us 11010 54 us 11011 56 us 11100 58 us 11101 60 us 11110 62 us 11111 64 us table 42. stepper off time (continued) stepofftime[4:0] off time unit typ
power bridges SABRE-LL-I 64/141 14.3.6 synchronous buck regulator configuration bridge 3 can be configured to be used as 2 independent synchronous buck regulators or as a single high current synchronous buck regulator using gpios pins in order to close the voltage loop. the resulting re gulator(s) will implement a non linear, pulse skipping, control loop using an internally generated pwm signal. the voltag e will be set externally with a divider network and pwm duty cycle that can be programmed in order to ensure a proper regulation. the regulator will be enabled/disa bled using serial interface and will implement a soft start strategy similar to that used by primary switching regulator. table 43. stepper fast decay mixdecphx[4:0] fast decay percentage during toff unit typ 00000 0 % 00001 6.25 % 00010 12.5 % 00011 18.75 % 00100 25 % 00101 31.25 % 00110 37.6 % 00111 43.75 % 01000 50 % 01001 56.25 % 01010 62.5 % 01011 68.75 % 01100 75 % 01101 81.25 % 01110 87.5 % 01111 93.75 % 1xxxx 100 %
SABRE-LL-I power bridges 65/141 here after are summarized the primary features of the regulator(s): ? synchronous rectification ? automatic low side disabling when current in the inductance reaches 0 to optimize efficiency at low load ? pulse skipping control ? internally generated pwm ? cycle by cycle current limiting using internal current sensor ? protected against load short circuit ? soft start circuitry ? under voltage signal (both continuous and latched) accessible through serial interface. figure 17. regulator block diagram depending on the load current, there could be the necessity to add a schottky diode on output to reduce internal thermal dissipation. this diode must be placed near to the pin and must be fast recovery and low series resistance type. for detail about pulse skipping please refer to main switching regulator paragraph. the output voltage will be externally set by a divider netwo rk connected on feedback pin. to reduce as much as possible the regulation voltage error s. a.b.re has the possibility to switch between four regulator feedback voltage references (and, as a consequence, four under-voltage thresholds) using serial interface. the feedback reference voltage is selected v out la v suppl y half brid g e out c high sid e driver control logic current sense charge pump voltage gpio used as f b voltage loop control re g ulator ref - + under voltage threshold filter r a r b low side driver from central logic regulator freq - + to central logic obtained using spare analog /digital blocks brid g e sense vref= 0.8v n.c. n.c. vref=3v selfbref
power bridges SABRE-LL-I 66/141 by writing the selfbref[1:0] bits in the aux1swcfg or aux2swcfg registers according to the following table: the switching regulators have four possible pwm duty cycles that can be changed using spi according to following table: the operating characteristics remain the same (when applicable) already seen in the section 15.2 with the addition of the following: table 44. switching regulator controller pwm specification selfbref[1:0] reference voltage (v fbref ) comments selfbref[1] selfbref[0] min typ max unit 0 0 0.776 0.8 0.824 v 0 1 0.970 1 1.030 v default voltage for aux1 1 0 2.425 2.5 2.575 v default voltage for aux2 1 1 2.910 3 3.09 v table 45. pwm specification auxxpwmtable[1:0] typical duty cycle value comments 00 10% 01 13% default state for aux1 10 24% default state for aux2 11 61% table 46. operating specification parameter description test condition min typ max unit v aux_sw output pin voltage range (1) -1 v supply v i q output leakage current t junction = 125c -50 +50 a i qlp output leakage current in ?low power mode? v supply = 36v t junction = 125c -10 +10 a i qfb gpio feedback pin current t junction = 125c 0v feedback 3v -10 +10 a v out output voltage range v supply = 36v (2) 0.8 30 v i load output load current v supply = 36v 0.002 1.5 a r onh internal high/low side rdson t junction = 125c iload=1a 0.8 ? v loop loop voltage accuracy 3% v regr output voltage ripple (rms) l = tbd, c = tbd/esr=tbd m ? (3) tbd mv rms v uvfall under voltage falling threshold (4) 84.5 87 89.5 % v uvrise under voltage rising threshold (4) 90.5 93 95.5 %
SABRE-LL-I power bridges 67/141 14.3.7 regulation loop as seen before s.a.b.re contains 2 regulation loops for switching regulators that are used when bridge 3 is used as a regulator. these loops are assembled using internal comparators and filters similar to that used in main switching regulator. when bridge 3 is not used for this purpose or when only one regulation loop is needed, the control loop is available on a gpio output thus enabling the customer to assembly a basic buck switching regulator using an external power fet. the comparators used in the above mentioned regulation loops are general purpose low voltage (3.3 v) comparators; when the relative regulation loop is not used they can be accessed as shown in the diagram here below: v uvhys under voltage hysteresis 6 % t aux_uv under voltage deglitch filter 5s i limit current limit protection 1.6 2.5 a t deglitch current limit deglitch time 50 ns t i_lim current limit response time in normal operating mode (no uv) (5) 700 ns t i_limuv current limit response time in uv condition. when in under voltage (6) 500 ns t r switching output rise time v supply = 36v, resistive load to gnd: r=422 ? (7) 530ns t f switching output fall time v supply = 36v, resistive load to gnd = 10 ? (7) 10 50 ns t dead crossover dead time 100 ns f regpwm operating frequency fosc/64 khz 1. the external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. the regulated voltage can be calculated using t he formula: vmain_sw = vfbref *(ra+rb)/rb. 3. the choice of proper values fo r l and c depends from the application. 4. undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (vsw_main_fb). 5. this condition is intended to simulate an extra current on output. 6. this condition is intended to si mulate a short circuit on output. 7. rise time is measured between 10% and 90% of supply voltage. table 46. operating specification (continued) parameter description test condition min typ max unit
power bridges SABRE-LL-I 68/141 figure 18. internal comparator functional block diagram the functionality of this circuit is obtained by using the bridge 4 output stage. this circuit is powered directly from v supply and it is intended to be used as a battery charger or a switching regulator. the control loop block diagram is shown in the following figure: figure 19. battery charger control loop block diagram the battery charger control loop implements an asynchronous switching regulator intended to be used as a constant voltage/constant current programmable source. gpioz gpiox gpiox decode logic gpioy gpioy decode logic gpioz logic driver - + v 3 v 3 gpioz decode logic gpioz value from sp gpioxmode gpiozmo d e gpioymode iref_fb vref_fb sabre comp_i comp_v pulse skipping burst control logic peak current mode control logic bridge 4 paralleled power stage selfbref<1:0> dc4_plus dc4_minus selcurrref<1:0> diff ampli to load fbref currref ilimit pwm
SABRE-LL-I power bridges 69/141 when used as a simple switching regulator, it could be a system regulator depending on startup configurations when a system regulator under- voltage event is detected s.a. b.re will enter in reset state signaling this event to the mi crocontroller by pullin g low the nreset pin and disabling most of its internal blocks. battery charger regulator application (cc-cv). when the control loop is intended to be used as a battery charger, the aux3batterycharge bit must be written in the aux3swcfg1 register. this is because in this case the undervoltage event that will be sure present when charging a battery (see next battery charger profile) will not be considered during start up sequence. voltage regulation the regulated output voltage will be externally set by a resistor divider network connected to vref_fb pin. s.a.b.re has the possibility to ch oose between four volt age references (and, as a consequence, four under-voltage thresholds) using the serial interface. the feedback reference voltage selection is made by writing the selfbref[1:0] bits in the aux3swcfg1 register according to the table here below: reference voltages values can be changed using a metal layer change in order to adapt them to cust omer system. the first, second and third reference voltage has been chosen to regulate 3.3v, 4.2v and 5v with the same resistor divider network, such that the commutation between different regulated voltages can be done on the fly in the application. current regulation the regulation of the output current can be done externally, by using a sense resistor connected in series on the path that provides current to the load. by using an external differential amplifier the customer can set the desired v=f(i) characteristic, and therefore the regulated current: the voltage provided at the i ref_fb pin will be compared to the internal reference. s.a.b.re has the po ssibility to choose between four voltage references using the serial interface, writing the selcurrref[1:0] bits in the aux3swcfg1 register according to the following the table: table 47. battery charger control loop fbref specification aux3swcfg1 reference voltage (fbref) comments selfbref[1] selfbref[0] min typ max unit 0 0 1.370 1.412 1.455 v 0 1 1.746 1.8 1.854 v default state 1 0 2.079 2.143 2.207 v 1 1 2.425 2.5 2.575 v
power bridges SABRE-LL-I 70/141 adjustable reference voltages values can be changed using a metal layer change in order to adapt them to customer system. regardless of the currref voltage, if the i ref_fb pin remains below the chosen threshold, the internal current limitation will work (s ee dc motor paragraph, bridge4 ilimit). battery charge profile the battery charge profile can be chosen by fixing the desired currref and fbref internal reference voltages and by choosing the desired v=f(i) trans-characteristic of the external differential amplifier. the following is a typical li-ion battery charge profile: figure 20. li-ion battery charge profile table 48. battery charger control loop currref specification aux3swcfg1 reference voltage (currref) comments selcurrref[1] selcurr ref[0] min typ max unit 0 0 0.873 0.900 0.927 v default state 0 1 1.394 1.437 1.480 v 1 0 1.746 1.8 1.854 v 1 1 2.182 2.25 2.318 v rapid charge phase time voltage or current blue=battery voltage red=battery current fbref depending currref depending end of charge precharge phase ichrg iprechrg vchrg veochrg ieochrg constant v. phase
SABRE-LL-I power bridges 71/141 simple buck regulator application the battery charge loop control can be used to implement a buck type switching regulator. the regulated output voltage will be externally set by a resistor divider network connected to v ref_fb pin, as already described in voltage regulation section, and the current protection will be the one implemented intern ally in the bridge4 section. figure 21. simple buck regulator when this control loop is intended to be used as a simple buck regulator, the proper aux3batterycharge bit must be written in the aux3swcfg1 register. the regulator will also implem ent a soft start strategy. when s.a.b.re ?low power mode? is e nabled this regulator will be disabled. here after are summarized the primary features of the regulator: ? internal power switch. ? nonlinear pulse skipping control. ? internally generated pwm (250 khz switching frequency). ? cycle by cycle current limiting using internal current sensor/ external current sense differential amplifier. ? protected against load short circuit. ? soft start circuitry to limit inrush current flow from primary supply. ? under voltage signal (both continuous and latched) accessible through spi. ? over temperature protection. iref_fb vref_fb sabre comp_i comp_v pulse skipping burst control logic peak current mode control logic bridge 4 paralleled power stage selfbref<1:0> dc4_plus dc4_minus selcurrref<1:0> to load fbref currref ilimit pwm
power bridges SABRE-LL-I 72/141 in pulse skipping control pwm the duty cycle must be decided by the user depending on supply voltage and regulated voltage. therefore the switching regulator has 4 possible pwm duty cycles that can be changed writing in the aux3pwmtable[1:0] bits in the aux3swcfg1 register according to the following table. adjustable duty cycles can be changed using a metal layer change in order to adapt it to customer system. the only limitation is that all regulators share the same duty cycle bus, so any modification must consider all regulators needed duty cycles. aux3 control loop parameters specifications the following table assumes that dc4_plus and dc4_minus pins are externally shorted together. table 49. battery charger regulator controller pwm specification aux3pwmtable [1:0] typical duty cycle value comments 00 10% 01 13% 10 24% default state 11 61% table 50. battery charger operating specification parameter description test condition min typ max unit v aux_sw output pin voltage range (1) -1 v supply v i q output leakage current t junction = 125c -100 +100 a i qlp output leakage current in ?low power mode? v supply = 36v t junction = 125c -20 +20 a i qfb gpio feedback pin current t junction = 125c 0v=feedback=3v -10 +10 a v out output voltage range v supply = 36v (2) 1.412 30 v i load output load current v supply = 36v 0.002 3 a r onh internal high/low side rdson t junction = 125c iload=1.5a 0.4 ? v loop loop voltage accuracy 3% v regr output voltage ripple (rms) l = tbd, c = tbd,esr=tbd m ? (3) tbd mv rms v uvfall under voltage falling threshold (4) 84.5 87 89.5 % v uvrise under voltage rising threshold (4) 90.5 93 95.5 %
SABRE-LL-I power bridges 73/141 v uvhys under voltage hysteresis 6% t aux_uv under voltage deglitch filter 5s i limit current limit protection 3.1 5.3 a t deglitch current limit deglitch time 50 ns t i_lim current limit response time in normal operating mode (no uv) (5) 700 ns t i_limuv current limit response time in uv condition. when in under voltage (6) 500 ns t r switching output rise time v supply = 36v, resistive load to gnd = 422 ? (7) 530ns t f switching output fall time v supply = 36v, resistive load to gnd = 10 ? (6) 10 50 ns t dead crossover dead time 100 ns f regpwm operating frequency fosc/64 khz 1. the external components connected to the pin must be chosen to avoid that the voltage exceeds this operative range. 2. the regulated voltage can be calculated using t he formula: vmain_sw = vfbref *(ra+rb)/rb. 3. the choice of proper values fo r l and c depends from the application. 4. undervoltage rising and falling thresholds are intended as a percentage of feedback pin voltage (vsw_main_fb). 5. this condition is intended to simulate an extra current on output. 6. this condition is intended to si mulate a short circuit on output. 7. rise time is measured between 10% and 90% of supply voltage. table 50. battery charger operating specification (continued) parameter description test condition min typ max unit
ad converter SABRE-LL-I 74/141 15 ad converter 15.1 overview s.a.b.re integrates and makes accessible via spi a general purpose multi-input channel 3.3v analog to digital converter (adc). the adc can be configured to be used as: ? 8-bit resolution adc. ? 9-bit resolution adc. the result of the conversion will always be a 9-bit word; the difference between the two configurations is that, to speed up the conversion, the resolution is reduced when the adc is used in the 8-bit resolution mode. the adc is seen at software level as a 2 channel adc with different programmable sample times; a finite state machine will sample the requests done through th e spi interface on both the channel and will exec ute them in sequence. when used as 8-bit resolution the adc can achieve a higher throughput and, if the minimum sample time is used, one conversion is completed in t = 5.5s. when used as 9-bit resolution adc the circuit is slower and the minimum sample times are disabled. in that case the conversion will be comp leted in a time t= 10 s the use of adc type must be decided at the start-up by writing in the one time programmable adc configuration register; no a/d conversion will be enabled if this register is not set from last power-up sequence. this adc can be used to measure some external pins as well as some s.a.b.re?s internal voltages. the converter is based on a cyclic ar chitecture with an internal sample-and-hold circuit. sample time can be changed using seri al interface to enable good measure of higher impedance sources.
SABRE-LL-I ad converter 75/141 figure 22. a2d block diagram the a2d system is enabled by setting the a2de nable bit to ?1? in the a2dcontrol register. the a2dtype bit in the a2dconfigx registers selects the a2d active configuration (8-bit resolution or 9-bit) according to the following truth table: the multiplexer channel to be converted can be chosen by writing the a2dchannel1[4:0] or a2dchannel2[4:0] bits in the a2dconfigx register; the channel addresses table is reported in the following table. table 51. adc truth a2denable a2dtype0/1 a2d operation 0 x disabled 1 0 adc working as a 8-bit adc 1 1 adc working as a 9-bit adc s&h a2d to spi sample time 0 analog mux v supply v linmain fb v swmain fb gpio[13:0] v psw currdac temp sens o conversio n address 0 v pump v 3v3 conversio n address 1 conversion done 1 conversion result conversion done 0 swdrv_fb a2denabl selected a2dtype sample tim e 1 a2dtype 0 a2dtype 1
ad converter SABRE-LL-I 76/141 the sample time can be changed by modifying the a2dsamplex[2:0] bits in the a2dconfigx register; depending on which is the a2dtype bit, the available sample times are reported in the following tables. table 52. channel addresses a2dchannelx[4:0] (bin.) converted channel note 00000 v supply scaled see voltage divider specification. 00001 v supplyint scaled see voltage divider specification. 00010 v ref_2_5v 00011 temp sensor1 temperature sensor1 00100 temp sensor2 temperature sensor2 00101 v 3v3 scaled see voltage divider specification. 0011x not used 01000 not used 01001 gpio[0] 01010 gpio[1] 01011 gpio[2] 01100 gpio[3] 01101 gpio[4] 01110 gpio[5] 01111 gpio[6] 10000 gpio[7] 10001 gpio[8] clamp see current dac circuit 10010 gpio[9] 10011 gpio[10] 10100 gpio[11] 10101 gpio[12] 10110 gpio[13] 10111 gpio[14] 11000 muxrefopamp1 11001 muxrefopamp2 11010 outstripstepperpha 11011 outstripstepperphb 11100 not used 11101 st reserved references aux1 switching reg. 11110 st reserved 0.8v reference voltage 11111 st reserved 1.65v reference voltage
SABRE-LL-I ad converter 77/141 a conversion on channel 1 can be triggered by wr iting a logic ?1? in the a2dtrig1 bit in the a2dconfigx register and a conversion on channel 2 can be triggered writing a logic ?1? in the a2dtrig2 bit in the same register. while a request on a channel is pending but not yet completed s.a.b.re will force to logic ?0 ? the corresponding a2 ddonex bit in the a2dresultx registers and s.a.b.re will not accept other conversion request on that channel. continuous conversion on one channel can be accomplished by setting to logic ?1? the a2dcontinuousx bit in the a2dconfigx regist er. when a2dcontinuousx bit is set, other conversions can be accomplished on the other channel; these conversions will be inserted between two conversions of the other chann el and the end of th e conversion will be signaled using a2ddonex bit. of course when a channel is in continuous mode its sample time and channel address cannot be changed. continuous conversions on both 2 channels can be also accomplished by setting to logic ?1? the a2dcontinuous1 and a2dcontinuous2 bits; the conversions are made in sequence. table 53. adc sample times when working as a 8-bit adc a2dsamplex[2:0] (binary) sample time typ unit 000 16*tosc s 001 32*tosc s 010 64*tosc s 011 128*tosc s 100 256*tosc s 101 512*tosc s 110 1024*tosc s 111 2048*tosc s table 54. adc sample time when working as a 9-bit adc a2dsamplex[2:0] (binary) sample time typ unit 000 32*tosc s 001 64*tosc s 010 128*tosc s 011 256*tosc s 100 512*tosc s 101 1024*tosc s 110 2048*tosc s 111 4096*tosc s
ad converter SABRE-LL-I 78/141 15.2 a2d specification with a2dtype=0 table 55. adc sp ecification parameter description test condition min typ max unit (1) 1. the definition of lsb for this table is lsb=imrmax/(2 7.5 -1). imr measurement range a2dtype = 0 0 v 3v3 v inl integral non-linearity a2dtype = 0 (2)(3) 2. integral non linearity error (inl) is defined as the maximum distance between any point of the adc characteristic and the ?best straight li ne? approximating the adc transfer curve. 3. the adc ensures monotonic char acteristic and no missing codes. 1 lsb dnl differential non-linearity a2dtype = 0 (4)(3) 4. differential nonlinearity error (dnl ) is defined as the difference between an actual step width and the ideal width value of 1 lsb. 1 lsb oe offset error a2dtype = 0 (5) 5. offset error (oe) is the deviatio n of the first code transit ion (000...000 to 000...001) from the ideal (i.e. gnd + 0.5 lsb). 4 lsb oe drift offset error drift a2dtype = 0 over time and temperature 3 lsb ge gain error a2dtype = 0 (6) 6. gain error (ge) is the deviation of the last code tr ansition (111...110 to 111...111) from the ideal (v3v3 - 0.5 lsb), after adjusting for offset error. 4 lsb ge drift gain error drift a2dtype = 0 over time and temperature 4 lsb t conv minimum conversion time 5.5 s resolution (7) 7. please note that the result of the conversion will always be a 9-bit word: to speed up the conversion, the resolution is reduced when the adc is used in the 8- bit resolution mode. 8bits cin input capacitance (8) 8. actual input capacitance depends on the pin that must be converted. 4pf
SABRE-LL-I ad converter 79/141 15.3 a2d specification with a2dtype=1 15.4 voltage divider specifications as can be seen in the a2d block diagram, in order to report some voltages in the a2d working range, they are scaled with a resistor divider before the conversion. here below are reported the resistor voltage divider specifications: table 56. adc sp ecification parameter description test condition min typ max unit (1) 1. the definition of lsb for this table is lsb=imrmax/(2 9 -1). imr measurement range a2dtype = 1 0 v 3v3 v inl integral non-linearity a2dtype = 1 (2)(3) 2. integral non linearity error (inl ) is defined as the maximum distance between any point of the adc characteristic and the ?best straight li ne? approximating the adc transfer curve. 3. the adc ensures monotonic char acteristic and no missing codes. 1 lsb dnl differential non-linearity a2dtype = 1 (4)(3) 4. differential nonlinearity error (dnl ) is defined as the difference between an actual step width and the ideal width value of 1 lsb. 1 lsb oe offset error a2dtype = 1 (5) 5. offset error (oe) is the deviatio n of the first code transit ion (000...000 to 000...001) from the ideal (i.e. gnd + 0.5 lsb). 4 lsb oe drift offset error drift a2dtype = 1 over time and temperature 3 lsb ge gain error a2dtype = 1 (6) 6. gain error (ge) is the deviation of the last code tr ansition (111...110 to 111...111) from the ideal (v3v3 - 0.5 lsb), after adjusting for offset error. 4 lsb ge drift gain error drift a2dtype = 1 over time and temperature 4 lsb t conv minimum conversion time 10 s resolution 9 bits cin input capacitance (7) 7. actual input capacitance depends on the pin that must be converted. 4pf table 57. voltage divider specification parameter description notes min typ max unit r supply_ratio v supply divider ratio -10% 1/15 +10% r supplyint_rati o v supply int divider ratio -10% 1/15 +10% r v3v3_ratio v 3v3 divider ratio -10% 1/2 -10%
current dac circuit SABRE-LL-I 80/141 16 current dac circuit 16.1 overview s.a.b.re includes a multiple range 6-bit current sink dac. the lsb value of this dac can be selected using the dacrange[1:0] bits in the currdacctrl register. the output of this circuit is connected to gpio[8 ] that is a 5v tolerant pin. the value of this pin can be converted using adc. the pin value can be scaled before being converted by enabling the internal resistor divider connected to this pin. if the current sunk by resistor divider is not acceptable the pin voltage can be converted without scaling its value. when the conversion without scaling resistor is chosen a clamping connection is used to avoid voltage compatibility of the pin to the adc s ystem. the clamping circuit will sink a typical current of half microampere from the pin during the sampling time. figure 23. current dac block diagram the circuit is enabled by setting to logic ?1? th e endac bit in the currda cctrl register then the desired sunk current value is chosen by changi ng the value of the dacvalue[5:0] bits in the current sink dac dacvalue[5:0] endac a2dchannel1[4 :0] a2dchannel2[4 :0] combinatorial mask combinatorial mask address recognized address recognized endac clamp circuit gpio8 clamp (to adc) endacscale dacrange [1:0] reference current generator va3 gpio[8] dacrange [1:0] gpio[8] digital driver rcurrdac
SABRE-LL-I current dac circuit 81/141 same register being dacvalue[0] the least significant bit and dacvalue[5] the most significant bit. the current dac has three possible current ranges that can be selected using the dacrange[1:0] bits in the currdacctrl register . the dac range selection table is shown here below: by changing lsb current value, all st eps will change following this relation: i step (n) = n * i lsb where n is the value of dacvalue[5:0] bits. table 58. current dac truth dacrange[1] dacrange[0] lsb typical current i lsb typ full scale typical current i full typ 0 0 disabled disabled 0 1 10 a 0.63 ma 1 0 100 a 6.3 ma 111 ma63 ma table 59. current dac specification parameter description test condition min typ max unit v r pin voltage operative range (1) 1. all parameters are guaranteed in the range between v ol and v r max . 0.7 5.5 v i out_off output off leakage current dacvalue[5:0] = 000000 -1 +1 a i full_err_01 full scale current error dacrange[1:0] =01 dacvalue[5:0] = 111111 -10 10 % of i full typ i full_err_10 full scale current error dacrange[1:0] =10 dacvalue[5:0] = 111111 -13 13 % of i full typ i full_err_11 full scale current error dacrange[1:0] =11 dacvalue[5:0] = 111111 -12 12 % of i full typ inl 10_11 integral non-linearity for 10 and 11 ranges 2 lsb dnl 10_11 differential non-linearity for 10 and 11 ranges 2 lsb inl 01 integral non-linearity for 01 range 1 lsb dnl 01 differential non-linearity for 01 range 1 lsb r currdac_res gpio[8] divider total resistance -25% 45 +25% k ? r currdac_ratio gpio[8] divider ratio -2.5% 3/5 +2.5% t set settling time (2) 2. measured from dacvalue[5:0] change in spi interface. 5s
operational amplifiers SABRE-LL-I 82/141 17 operational amplifiers 17.1 overview s.a.b.re contains two rail to rail output, high bandwidth internally compensated operational amplifiers supplied by v gpio_spi pin. the operative supply range is 3.3v4.5% each operational amplifier can have all pin accessible or, to save pins, can be internally configured as a buffer. they can also be used as comparators; to do that the user must disable internal compensation by writing a logic level ?1? in the opxcompmode bit in the opampxctrl register. here below are reported the block diagrams of the two operational amplifiers
SABRE-LL-I operational amplifiers 83/141 figure 24. configurable 3.3v operational amplifiers note: op1enplusref and op2enplusref cannot be used to drive external pin so the user must be sure not to enable the path between one of these voltage references and the external pin. the operational amplifiers are capable to drive a capacitive load in buffer configuration up to a maximum of 100pf; for higher capacitance it is necessary to add resistive loads to increase the op output current, and/or to add a low resistor (10 ohm) in series to the load capacitance. the table here below describes the ma in operational amp lifier parameters. gpio[10] gpio[9] gpio[11] to a/d system v gpio_spi op1ref[1:0] op1bufconf op1enintref enop1 op1enminuspin op1enpluspin opamp 1 op1plusref + - - + enop2 op2enpluspin op2enminuspin op2bufconf op2enintref gpio[13] gpio[12] gpio[14] op1compmode op2compmode op2plus ref op2ref[1:0] + - v gpio_spi
operational amplifiers SABRE-LL-I 84/141 17.2 operational amp lifiers specifications table 60. configurable 3.3v operational amplifier specification (note: v gpio_spi =3.3v unless otherwise specified) parameter description test condition min typ max unit v gpio_spi supply voltage range 3.15 3.45 v v icm input common mode voltage range 0 v gpio_sp i v v out_max output voltage iload = 1ma 0.1 3.2 v v op1plusref operational amplifier 1 reference voltage op1ref[1:0]=00 op1ref[1:0]=01 op1ref[1:0]=10 op1ref[1:0]=11 0.970 1.600 1.940 2.425 1 1.65 2 2.5 1.030 1.700 2.060 2.575 v v op1plusref operational amplifier 2 reference voltage op2ref[1:0]=00 op2ref[1:0]=01 op2ref[1:0]=10 op2ref[1:0]=11 0.970 1.600 1.940 2.425 1 1.65 2 2.05 1.030 1.700 2.060 2.575 v open loop gain v icm =1.65v il oad = 0ma 90 db cmrr common mode rejection ratio 105 db psrr il oad = 6ma v icm =1.65v (1) 1. v icm is the input common mode voltage. 90 db i in _offs input offset current 150 na i in _bias input bias current 500 na v in _offs input offset voltage -5 5 mv gbwp gain bandwidth product cload=100pf v icm =1.65v rload=330 ohm to v gpio_spi 2mhz i out output current v out =1.65v 10 ma i short_max short circuit current 12 20 ma slew slew rate i load = 0 c load =100pf 1.3 1.75 v/s
SABRE-LL-I operational amplifiers 85/141 17.3 operational amplifiers used as comparators specifications to use the operational amplifiers as comparators the user must disable internal compensation writing a logic one in the opxdiscomp bit in the opampxctrl register. table 61. configurable 3.3v operational amplifier used as comparator specification (note: v gpio_spi =3.3v unless otherwise specified) parameter description test condition min typ max unit v gpio_spi supply voltage range 3.15 3.45 v v icm input common mode voltage range 0v gpio_spi v v out_max output voltage i load = 10ma 0.3 2.9 v i in _offs input offset current 150 na i in _bias input bias current 500 na v in _offs input offset voltage -5 5 mv i short_max short circuit current 12 20 ma t phl output falling delay v cm = 1.65v ? vi = -/+ 20mv c load =100pf (1)(2) 1. ? vi is the differential voltage applied to input pins across the common voltage v cm . 2. measured between 50% of input and output signal. 1s t fall fall time v cm = 1.65v ? vi = -/+ 20mv c load =100pf (1)(2) 0.4 s t plh output rising delay v cm = 1.65v ? vi = -/+ 20mv c load =100pf (1)(2) 0.5 s t rise rise time v cm = 1.65v ? vi = -/+ 20mv c load =100pf (1)(2) 0.4 s
low voltage power switches SABRE-LL-I 86/141 18 low voltage power switches 18.1 overview low voltage power switches are analog switches designed to operate from a single +2.4v to +3.6v v gpio_spi supply. they are intended to provide and remove power supply to low voltage devices. when switched on, they connect the v gpio_spi pin to their output pin (gpio[6] for low voltage power switch 1 or gp io[7] for low voltage power switch 2) thus powering the device connected to it. the turning on and off of each switch can be controlled through serial interface. s.a.b.re provides a total of 2 low voltage power switches, each of them has current limitation to minimum 150ma to limit inrush current when charging a capacitive load. when the limit current has been reached, for more than a tfilter time, then a flag is activated; this flag is latched in the central logic and can be cleared by the firmware. please note that, in case of capacitive load, the current limit is reached the first time the low power switch is turned on: therefor e the user will find a limit flag that must be cleared. the 2 low voltage power switches can be externally paralleled to obtain a single super low voltage power switch. low voltage pass switches sink current ipass needed for their functionality from pin v gpio_spi , they never inject current on this pin. figure 25. low power switch block diagram enlowvsw[x] gpio[6] (lps 1) or gpio [ 7 ] ( lps 2 ) current limit sensor driving circuit v gpio_s p lowvswilim[x] to sp i s r lowvswilimlth[x] clrlowvrswlth reset sta t gpio[6]/gpio[7] driver
SABRE-LL-I low voltage power switches 87/141 table 62. 3.3v low power switch specification parameter description test condition min typ max unit v psw input voltage range 2.4 3.6 v v out_max output voltage v gpio_spi v r dson on resistance i load =100ma 1 o i limit current limit 150 250 350 ma t deglitch current limit deglitch time 50 ns t i_lim current limit response time 650 ns c load max load capacitance 2.5 f t on on delay v gpio_spi =3.3v i load =1ma c load =100pf (1) 1. time measured from change in spi interf ace to 50% of exte rnal pin transition. 650 ns t off off delay v gpio_sp i=3.3v i load =1ma c load =100pf (1) 450 ns
general purpose pwm SABRE-LL-I 88/141 19 general purpose pwm 19.1 overview s.a.b.re includes three general purpose pwm generators that can be redirected on gpio pins (see chapter 23 ). two of these generators (aux_pwm_1 and aux_pwm_2) work with a fixed period fosc/512 and have a programmable duty cycle; the other one (gp_pwm) has a programmable base time clock and a programmable time for both high and low levels. 19.2 general purpose pwm generators 1 and 2 (auxpwm1 and auxpwm2) the duty cycle of these pwm generators can be changed by writing the auxpwmxctrl bits (where x can be 1 or 2) in the auxpwm1ctrl and auxpwm2ctrl registers. their positive duty cycle will change accord ing to the equation: according to this equation a programmed ?0? value will caus e a 0% duty cycle (output always at logic level 0). 19.3 programmable pwm generator (gppwm) gppwm has a programmable base clock that can be changed by programming the gppwmbase[6:0] bits in the gppwmbase register. the clock will change according to the equation: the high and low level duration (expressed in base clock periods), can be programmed writing the gppwmhigh[7:0] and gppwmlow[7:0] bits in the gppwmctrl register so they will change according to following equations: the resulting period of the pwm will be: and the positive duty cycle will result: a programmed value of 0 in gppwmhigh[7:0] and gppwmlow [7:0] bits will force the pwm generator output to be always at logic level ?0?. pwm_x_duty auxpwmxctrl 9:0 [] /512 = pwm_base_period gppwmbase 6:0 [] 1 + () tosc = high_level_time gppwmhigh 7:0 [] pwm_base_period = low_level_time gppwmlow 7:0 [] pwm_base_period = period gppwmhigh 7:0 [] gppwmlow 7:0 [] + () pwm_base_period + = dutycycle high_level_time high_level_time low_level_time + ---------------------------------------------------------------------------------------------- - gppwmhigh 7:0 [] gppwmhigh 7:0 [] gppwmlow 7:0 [] + --------------------------------------------------------------------------------------------------------- ==
SABRE-LL-I interrupt controller 89/141 20 interrupt controller 20.1 overview s.a.b.re contains one programmable interrupt controller that can be used to advice the firmware, through the serial interface, when a certain event happens inside the ic. the output of the interrupt circuit can be also redirected on a gpio pin therefore the event can be signaled directly to the external circuits. figure 26. low power switch block diagram decode logic monitored signals enable signal s enintctrl intctrlpolarity pulse generator enintctrlpulse intctrlautodisable enintctrlpulse disablemonitor disable pulse generation logi c disablesignals to gpio
interrupt controller SABRE-LL-I 90/141 20.2 interrupt contro ller monitored signal the table here below contains the events that can be monitored by the interrupt controller. any event detection can be enabled and disabled by setting at logic level 1 the relative enable bit in the interrupt controller configuration register (intcrtlcfg). the interrupt controller can be programmed to give a pulse when a monitored event happens or to continuously maintaining the output active until the interrupt condition is finished. when programmed to signal the enabled events by giving pulses, the interrupt controller can be configured to disable the event that caused the interrupt request until the firmware re-enables it writing the relative bit in the control register (intcrtlctrl) or to continue to monitor the event. the gpio output of this circuit can be programmed to be active high or active low. table 63. interrupt controller event event event description notes mtr1fault bridge 1 fault (ilimit event) mtr2fault bridge 2 fault (ilimit event) mtr3fault bridge 3 fault (ilimit event) mtr4fault bridge 4 fault (ilimit event) nawake nawake pin low swregctrl ilimit switching regul ator controller ilimit event. vmainsw ilimit main switching regulator ilimit event. lowpowsw 1 low voltage power switch 1 ilimit event. lowpowsw 2 low voltage power switch 2 ilimit event warm warming event wdwarn watch dog warning event wd watch dog event digcmp digital comparator adcdone1 adc conversion done 1 (1) 1. this event is disabled if the related adc channel is configur ed in continuous mode. adcdone2 adc conversion done 2 (1) vloop1ilim aux1 ilimit event. table 64. interrupt controller specification parameter description test condition min typ max unit t pulse pulse duration 16*tosc s t intfilt filter time 200 ns
SABRE-LL-I digital comparator 91/141 21 digital comparator 21.1 overview s.a.b.re includes one digital comparator that can be used to signal, through serial interface, that a channel converted by the ad c is greater, greater-equal, lesser, lesser equal, or equal than a fixed value set by serial interface or than the value converted by the other adc channel. this circuit can be used to monitor the temperat ure of the ic advising the firmware when it reaches a certain value decided by the firmware by setting one adc channel to do continuous conversions of the temperature sensor. the circuit operation can be enabled or disabled changing the endigcmp bit in the configuration register digcmpcfg. by setting the digcmpupdate[1:0] bits in the configuration register, the comparator can be programmed to update its output in one of the following ways: digcmpupdate[1:0]=00 ? continuously (each clock). digcmpupdate[1:0]=01 ? each time a conversion is performed on adc channel 0. digcmpupdate[1:0]=10 ? each time a conversion is performed on adc channel 1. digcmpupdate[1:0]=11 ? adc state machine driven. when the last option is selected, the digital comparator will update its output in two different ways depending on the configuration of the adc converter. if adc converter is configured to do continuous conversions on both channels, the output of the comparator will be updated when the double conversion is completed. if adc converter is not configured to do continuous conversions on both channels, the output of the co mparator will be updated each time a conver sion is completed. the comparator output can be digitally filtered so that the programmed condition has to be found for three consecutive checks before to be signaled. the picture here below is a block representation of the comparator.
digital comparator SABRE-LL-I 92/141 figure 27. digital comparator block diagram here below is reported the comparison type truth table: here below is reported the data0/data1 selection truth table: table 65. comparison type truth endigcmp selcmptype[1] selcmptype[0] comparison type 0 x x disabled 1 0 0 data0[9:0] 131 data1[9:0] 1 0 1 data0[9:0] = data1[9:0] 1 1 0 data0[9:0] > data1[9:0] 1 1 1 data0[9:0] = data1[9:0] table 66. datax selection truth digcmpselchx[1] digcmpselchx[0] datax[9:0] 0 x digcmpvalue[9:0] 1 0 a2dresult1[8:0] 1 1 a2dresult1[8:0] comparator a2dresult0[8:0 ] a2dresult1[8:0 ] digcmpupdate[1:0] selcmptype[ 1:0] a2ddone0 a2ddone1 adc fsm update signal logic ?1? cmpout digcmpselch1[0 ] digcmpselch1[1] data0 [9:0] data1[9:0] endigcmp digcmpselch0[0 ] digcmpvalue [9:0] digcmpselch0[1] three check s filter
SABRE-LL-I gpio pins 93/141 22 gpio pins 22.1 overview some of the pins of s.a.b.re are indicated as gpio (general purpose i/o). these pins can be configured to be used in different ways depending on customer application. all gpios can be used as digital input/output pins with digital value settable/readable using serial interface or as analog input pins that can be converted using the a2d system. some of the pins can be used for special purposes: i.e. two of them can be used to access to the pass switch function, other two are used as feedba ck pins for the auxiliary synchronous switching regulators. all input schmitt triggers and output circuitry used for start-up purposes are powered by the internally generated v 3v3 , while the digital output buffers are powered by v gpio_spi pin. to ensure independency between v 3v3 and v gpio_spi the gpios output drivers are open-drain driver or the high side mos is in back-to-back configuration to avoid the presence of the body diode between output and supply (all back-to-back drivers can be customized to become open-drain driv ers with a metal change). all digital output signals can be inverted before being provided on the relative gpio pins. here below is reported the table with gpio functions: table 67. gpio functions description pin name function (1) notes input output special analog digital analog digital gpio[0] - adc input - spi in - spi out - interrupt ctrl. - auxpwm1 - auxpwm2 start-up configuration pin open drain output gpio[1] - adc input - comp1 in- - vaux1 f.b. - spi in - spi out - interrupt ctrl. - auxpwm1 - auxpwm2 open drain output gpio[2] - adc input - comp2 in- - vaux2 f.b. - spi in - in pwm - spi out - interrupt ctrl. - auxpwm2 - auxpwm3 open drain output gpio[3] - adc input - spi in - spi out - auxpwm2 - auxgppwm3 start-up configuration pin open drain output gpio[4] - adc input - spi in - spi out - interrupt ctrl. - auxpwm1 - auxpwm3 start-up configuration pin open drain output
gpio pins SABRE-LL-I 94/141 gpio[5] - adc input - spi in - spi out - reg. loop 1 - comp1 out - auxpwm3 slave control full driver bb powered by v 3v3 gpio[6] - adc input - spi in - low pow sw 1 - spi out - a2dgpo - auxpwm2 - comp2 out full driver connected to v gpio_spi gpio[7] - adc input - spi in - low pow sw 2 - spi out - auxpwm1 - auxpwm3 - comp1 out full driver connected to v gpio_spi gpio[8] - adc input - spi in (2) - currdac - spi out - auxpwm1 - auxpwm3 - comp2 out 5 volt input tolerant open drain output gpio[9] - adc input - opamp1 in+ - spi in - id 1 - in pwm - spi out - interrupt contr. - auxpwm1 - reg. loop 3 full driver connected to v gpio_spi gpio[10] - adc input - opamp1 in- - spi in - id 2 - in pwm - spi out - interrupt ctrl. - auxpwm2 - auxpwm3 full driver connected to v gpio_spi gpio[11] - adc input - spi in - in pwm - opamp1 out - spi out - a2dgpo - auxpwm1 - auxpwm2 full driver connected to v gpio_spi gpio[12] - adc input - opamp2 in+ - spi in - step_req - spi out - interrupt ctrl - comp2 out - reg. loop 2 full driver bb (can be powered by v 3v3 with a metal change) table 67. gpio functions description (continued) pin name function (1) notes input output special analog digital analog digital
SABRE-LL-I gpio pins 95/141 gpio[13] - adc input - opamp2 in- - spi in - spi out - auxpwm1 - reg. loop 3 - auxpwm3 full driver connected to v gpio_spi gpio[14] - adc input - spi in - opamp2 out - spi out - interrupt ctrl. - auxpwm2 - auxpwm3 full driver connected to v gpio_spi 1. in the above table the following abbreviations were used. 2. gpio[8] input schmitt trigger is disabled by default (after a reset) to be able to read the digital value from this pin it ne eds to be enabled writing a logic ?1? in the engpio8digin in currdacctrl register. table 67. gpio functions description (continued) pin name function (1) notes input output special analog digital analog digital table 68. abbreviations abbreviation meaning adc input input to the adc system. spi in digital state of this pin is readable through spi. spi out digital state of this pin can be set through spi. bb back to back high side driver. comp1 in - this pin can be used as minus input for comparator 1. comp2 in - this pin can be used as minus input for comparator 2. vaux1 fb this pin can be used as feedback input for aux1 regulator obtained by using bridge 3. a2dgpo this pin can be used to carry out the a2dgpo value related to the adc conversion s.a.b.re is doing. reg. loop 3 this pin can be used as output of the regulation loop used by aux3 regulator obtained by using bridge 4. step_req this pin can be used to reques t a stepper sequencer evolution step. interrupt ctrl this pin can be used to carry out the interrupt controller circuit output. vaux2 fb this pin can be used as feedback pin by aux2 regulator obtained by using bridge 3 in pwm this pin can be used to provide an external pwm to bridges. reg. loop 1 this pin can be used as output of the regulation loop used by aux1 regulator. comp1 out this pin can be used as output of the comparator 1. auxpwm1 this pin can be used to carry out the pwm generated by auxpwm1 circuit. low volt. pow. sw. 1 this pin can be used as output of low voltage power switch 1.
gpio pins SABRE-LL-I 96/141 hereafter are reported the detailed specifications for each gpio. to enable the functionality of the gpio as output pin, the relative gpiooutenable[14:0] bit must be enabled in gpiooutenable register. each gpio could be configured by setting the appropriate gpioxmode[2:0] in the gpioctrlx register. reg. loop 2 this pin can be used as output of the regulation loop used by aux2 regulator. comp2 out this pin can be used as output of the comparator 2. auxpwm2 this pin can be used to carry out the pwm generated by auxpwm2 circuit. low volt. pow. sw. 2 this pin can be used as output of low voltage power switch 2. reg. loop 3 this pin can be used as output of the regulation loop used by aux3 regulator. auxpwm3 this pin can be used to carry out the pwm generated by auxpwm3 circuit. currdac this pin can be used to carry out the output of the current dac circuit. auxpwm4 this pin can be used to carry out the pwm generated by auxpwm4 circuit. opamp1 in+ this pin can be used as operational amplifier 1 non-inverting input. opamp1 in- this pin can be used as operational amplifier 1 inverting input. opamp1 out this pin can be used as operational amplifier 1 output. opamp2 in+ this pin can be used as operational amplifier 2 non-inverting input. opamp2 in- this pin can be used as operational amplifier 2 inverting input. opamp2 out this pin can be used as operational amplifier 2 output. id 1 this pin is used to determine the spi id1 bit value. id 2 this pin is used to determine the spi id2 bit value. slave control this pin is used as slave co ntrol when the ic is configured as master. table 68. abbreviations (continued) abbreviation meaning
SABRE-LL-I gpio pins 97/141 22.2 gpio[0] the gpio[0] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 69. gpio[0] truth state at startup gpio[0] spi bits function note gpioout enable [0] mode[2] mode[1] mode[0] 1 x x x x detection of startup config see chapter 8 0 0 x x x hiz (spi_in) 0 1 0 0 0 spi out (1) 1. in all configurations in whic h gpio[0] is enabled as output: a) the gpio[0] pin can be always used as an analog inpu t to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[0] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[0] pin is an open drain output. 0 1 0 0 1 interruptctrl (1) 01 0 1 0 auxpwm1 (1) 01 0 1 1 auxpwm2 (1) 0 1 1 0 0 spi out inverted (1) 0 1 1 0 1 interruptctrl inverted (1) 0 1 1 1 0 auxpwm1 inverted (1) 0 1 1 1 1 auxpwm2 inverted (1)
gpio pins SABRE-LL-I 98/141 figure 28. gpio[0] block diagram table 70. gpio[0] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 vout v 3v3 -1 1 a c load load capacitance 200 pf t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[0] logic decode gpio[0] driver from serial interface to control logic v 3v3 to adc to serial interfac e v 3v3 start-up pin state detect circuit v 3v3 enstartupdtc from power up fsm v 3v3
SABRE-LL-I gpio pins 99/141 22.3 gpio[1] the gpio[1] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 71. gpio[1] truth aux1enable or aux1system gpio[1] spi bits function note gpioout enable [1] mode[2] mode[1] mode[0] 1xxxxaux1 fb (1) 1. aux1enable or aux1system bit =1 represent the case in which aux1 is used as a system or not system regulator. 000xxhiz (spi_in) 0 0 1 x x comp1 in - (2) 2. in all configurations in whic h gpio[1] is enabled as output: a) the gpio[1] pin can be always used as an analog i nput to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[1] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[1] pin is an open drain output. 0 1000 spi out (2) 0 1001auxpwm1 (2) 0 1010auxpwm2 (2) 0 1 0 1 1 interruptctrl (2) 0 1100spi out inverted (2) 0 1101auxpwm1 inverted (2) 0 1 1 1 0 auxpwm2inverted (2) 0 1111intctrlinverted (2)
gpio pins SABRE-LL-I 100/141 figure 29. gpio[1] block diagram table 72. gpio[1] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 v out v 3v3 -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[1] logic decode gpio[1] driver from serial interface to aux1 feedback com p arator v 3v3 to adc to serial interfac e v 3v3 v 3v3
SABRE-LL-I gpio pins 101/141 22.4 gpio[2] the gpio[2] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 73. gpio[2] truth aux2enable or aux2system gpio[1] spi bits function note gpioout enable [1] mode[2] mode[1] mode[0] 1xxxxaux2 fb (1) 1. aux2enable or aux2system bit =1 represent the case in which aux1 is used as a system or not system regulator. 000xxhiz (spi_in) 0 0 1 x x comp1 in - (2) 2. in all configurations in whic h gpio[2] is enabled as output: a) the gpio[2] pin can be always used as an analog i nput to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[2] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) please note that gpio[2] output is directly connected to extpwm3 input for bridge 3 or 4 and therefore particular care must be taken in order to av oid wrong pwm signals when ex tpwm3 is selected for bridge 3 or 4; d) the gpio[2] pin is an open drain output. 0 1000 spi out (2) 0 1001auxpwm2 (2) 0 1010auxpwm3 (2) 0 1 0 1 1 interruptctrl (2) 0 1100spi out inverted (2) 0 1101auxpwm2 inverted (2) 0 1110auxpwm3 inverted (2) 0 1111intctrlinverted (2)
gpio pins SABRE-LL-I 102/141 figure 30. gpio[2] block diagram table 74. gpio[2] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 v out v 3v3 -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[2] logic decode gpio[2] driver from serial interface to aux2 feedback com p arator v 3v3 to adc to serial interfac e v 3v3 to extpwm3 v 3v3
SABRE-LL-I gpio pins 103/141 22.5 gpio[3] the gpio[3] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 75. gpio[3] truth state at startup gpio[3] spi bits function note gpioout enable [3] mode[2] mode[ 1] mode[0] 1 x x x x detection of startup config see chapter 8 0 0 x x x hiz (spi_in) 01000 spi out (1) 1. in all configurations in whic h gpio[3] is enabled as output: a) the gpio[3] pin can be always us ed as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[3] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[3] pin is an open drain output. 01001 auxpwm1 (1) 01010 auxpwm2 (1) 01011 auxpwm2 (1) 0 1 1 0 0 spi out inverted (1) 01101auxpwm1 inverted (1) 01110auxpwm2 inverted (1) 01111auxpwm3 inverted (1)
gpio pins SABRE-LL-I 104/141 figure 31. gpio[3] block diagram table 76. gpio[3] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 v out v 3v3 -1 1 a c load load capacitance 200 pf t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[3] logic decode gpio[3] driver from serial interface to control logic v 3v3 to adc to serial interfac e v 3v3 start-up pin state detect circ uit v 3v3 enstartupdtc from power up fsm v 3v3
SABRE-LL-I gpio pins 105/141 22.6 gpio[4] the gpio[4] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 77. gpio[4] truth state at startup gpio[4] spi bits function note gpioout enable [4] mode[2] mode[1] mode[0] 1 x x x x detection of startup config see chapter 8 0 0 x x x hiz (spi_in) 0 1 0 0 0 spi out (1) 1. in all configurations in whic h gpio[4] is enabled as output: a) the gpio[4] pin can be always us ed as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[4] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[4] pin is an open drain output. 0 1 0 0 1 interrupt ctrl (1) 01010 auxpwm1 (1) 01011 auxpwm3 (1) 01100spi out inverted (1) 0 1 1 0 1 interrupt ctrl (1) 01110auxpwm1 inverted (1) 01111auxpwm3 inverted (1)
gpio pins SABRE-LL-I 106/141 figure 32. gpio[4] block diagram table 78. gpio[4] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 v out v 3v3 -1 1 a c load load capacitance 200 pf t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[4] logic decode gpio[4] driver from serial interface to control logic v 3v3 to adc to serial interfac e v 3v3 start-up pin state detect circuit v 3v3 enstartupdtc from power up fsm v 3v3
SABRE-LL-I gpio pins 107/141 22.7 gpio[5] the gpio[5] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): figure 33. gpio[5] block diagram table 79. gpio[5] truth master (1) 1. master bit is at logic level ?1? when s.a.b.re is used as a master device (see chapter 8 ) aux1 system and vloop1 external (2) gpio[5] spi bits function note gpioout enable[5] mode[2] mode[1] mode[0] 1 x x x x x slave control 0 1 x x x x reg loop1 out (3) 0 0 0 x x x hiz (spi_in) 0 0 1 000 spi out (3) 0 0 1 001 comp1out (3) 0 0 1 0 1 0 reg loop1 out (3) 0 0 1 011 auxpwm3 (3) 0 0 1 100spi out inverted (3) 0 0 1 1 0 1 comp1out inverted (3) 0 0 1 110 reg loop1 out inverted (3) 0 0 1 1 1 1 auxpwm3 inverted (3) gpio[5] logic decode from control logic v 3v3 to adc to internal logic & spi back to back driver v 3v3 v 3v3
gpio pins SABRE-LL-I 108/141 2. this bit is at logic level ?1? if aux1 regulator is a system regulator but its power stage is externally realized (and therefore the regulation loop is not used to drive bridge 3). in this case vloop1issys bit will be at logic level ?1?, while vloop1onmtr3sidea and vloop1onmt r3sideb bits will be at logic level ?0? in coreconfigreg register. 3. in all configurations in whic h gpio[5] is enabled as output: a) the gpio[5] pin can be always used as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[5] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[5] pin is a rail to ra il, back to back output supplied by v 3v3 . table 80. gpio[5] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v v oh high level output voltage i out = 5ma 2.75 v i leakage leakage current 0 v out v 3v3 -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns
SABRE-LL-I gpio pins 109/141 22.8 gpio[6] the gpio[6] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 81. gpio[6] truth stdbymode aenlow vsw[1] gpio[6] spi bits function note gpioout enable[6] mode[2] mode[1] mode[0] 1 x x x x x low volt. pow. sw. 1 0 1 x x x x low volt. pow. sw. 1 (1) 1. when enlowvsw[1]= ?1? the gpiooutenable[6] bit is forced to 0. 0 0 0 x x x hiz (spi_in) 0 0 1 0 0 0 spi out (2) 2. in all configurations in whic h gpio[6] is enabled as output: a) the gpio[6] pin can be always used as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[6] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[6] pin is a rail to rail output supplied by v gpio_spi. 001001 a2dgpo (2) 0 0 1 0 1 0 auxpwm2 (2) 001011comp2out (2) 0 0 1 1 0 0 a2dgpo inverted (2) 0 0 1 1 0 1 auxgppwm2 inverted (2) 0 0 1 1 1 1 comp2out inverted (2)
gpio pins SABRE-LL-I 110/141 figure 34. gpio[6] block diagram table 82. gpio[6] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma 0.4 v i leakage leakage current 0 v out v 3v3 -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[6] logic decode from serial interface v 3v3 to adc to internal lo g ic & spi power switch 1 enpass 1 v 3v3 v gpio_spi stand by mod e gpio[6] driver v 3v3
SABRE-LL-I gpio pins 111/141 22.9 gpio[7] the gpio[7] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 83. gpio[7] truth enlowvsw[2] gpio[7] spi bits function note gpioout enable[7] mode[2] mode[1] mode[0] 1 x x x x low volt. pow. sw. 2 (1) 1. when enlowvsw[2] = ?1? the gpiooutenable[7] bit is forced to 0. 0 0 x x x hiz (spi_in) 0 1 000 spi out (2) 2. in all configurations in whic h gpio[7] is enabled as output: a) the gpio[7] pin can be always used as an analog i nput to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[7] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[7] pin is a rail to rail output supplied by v gpio_spi. 0 1 001 auxpwm1 (2) 0 1 010 auxpwm3 (2) 0 1 0 1 1 comp1out (2) 0 1 1 0 0 auxpwm1 inverted (2) 0 1 1 0 1 auxpwm3 inverted (2) 0 1 1 1 1 comp1out inverted (2)
gpio pins SABRE-LL-I 112/141 figure 35. gpio[7] block diagram table 84. gpio[7] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[7] logic decode from serial interface v 3v3 to adc to internal logic & spi power switch 2 enpass 2 v 3v3 v gpio_spi v gpio_spi
SABRE-LL-I gpio pins 113/141 22.10 gpio[8] the gpio[8] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 85. gpio[8] truth endac (1) 1. the endac bit in the currdacctrl register enables the current dac (see chapter 17 ) gpio[8] spi bits function (2) 2. this pin is 5 volt input tolerant. note gpioout enable[8] mode[2] mode[1] mode[0] 1 x x x x currdac (3) 3. when endac = ?1? the gpiooutenable[8] bit is forced to 0. the current dac circui t is directly connected to gpio[8] pin so as soon as it is enabl ed it will sink current from pin. 0 0 x x x hiz (spi_in) (4) 4. the gpio[8] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function). to avoid affecting the precision of currdac w hen this is used to sink very low currents, it is necessary to enable the digital input fu nctionality of gpio[8]. therefore to read their values through spi interface (spi_in function), it is necessary to enable the engpio8digin bit in the currdacctrl register. 0 1 0 0 0 spi out (4) 01001auxpwm1 (4) 01010auxpwm3 (4) 0 1 0 1 1 comp2out (4) 01100 auxpwm1 inverted (4) 01101 auxpwm3 inverted (4) 0 1 1 1 1 comp2out inverted (4)
gpio pins SABRE-LL-I 114/141 figure 36. gpio[8] block diagram table 86. gpio[8] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, 0.4 v i leak_0 leakage current engpio8digin=0, 0 vout 5v -1 1 a i leak_1 leakage current engpio8digin=1, 0 vout 5v -1 5 a i ad a/d path absorbed current adchannelx[4:0] =10001 and bit endacscale=0 -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[8] current sink circuit from serial interface v 3v3 to adc to internal logic & spi v 3v3 gpio[8] driver logic decode from serial interface engpio8 digin v 3v3
SABRE-LL-I gpio pins 115/141 22.11 gpio[9] the gpio[9] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 87. gpio[9] truth op1enpluspin (1) 1. the op1enpluspin bit in the opamp1ctrl register enabl es the connection of the positive input of op1 to gpio[9] pin. gpio[9] spi bits function (2) 2. the gpio[9] pin is used by the system w hen firmware requires the id read action ( chapter 25 ) note gpioout enable[9] mode[2] mode[ 1] mode[0] 1xxxxopamp1 in+ (3) 3. when op1enpluspin = ?1? the gpiooutenable[9] bit is forced to 0. 0 0 x x x hiz (spi_in) 0 1 0 0 0 spi out (4) 4. in all configurations in whic h gpio[9] is enabled as output: a) the gpio[9] pin can be always used as an analog input to the adc sys tem (adc function) by writing its address in the a2dchannelx[4:0] in the a2dco nfigx register and st arting a conversion; b) the gpio[9] pin can be always us ed as a digital input so its va lue can be always read through spi interface (spi_in function); c) please note that gpio[9] output is directly connect ed to extpwm1 input for bridge 1 or 2 and therefore particular care must be taken in order to av oid wrong pwm signals when ex tpwm1 is selected for bridge 1 or 2; d) the gpio[9] pin is a rail to rail output supplied by v gpio_spi. 0 1 0 0 1 interrupt ctrl (4) 01010auxpwm2 (4) 0 1 0 1 1 reg loop 3 (4) 0 1 1 0 0 interrupt ctrl inverted (4) 0 1 1 0 1 auxpwm2 inverted (4) 0 1 1 1 1 reg loop 3 inverted (4)
gpio pins SABRE-LL-I 116/141 figure 37. gpio[9] block diagram table 88. gpio[9] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[9] logic decode from spi v 3v3 to adc to internal logic & spi to opamp1 in + v 3v3 gpio[9] driver pin state sampl e circuit sampleid id1 v gpio_spi
SABRE-LL-I gpio pins 117/141 22.12 gpio[10] the gpio[10] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 89. gpio[10] truth op1enpluspin (1) 1. the op1enminuspin bit in the opam p1ctrl register enabl es the connection of the positive input of op1 to gpio[10] pin. gpio[10] spi bits function (2) 2. the gpio[10] pin is used by the system w hen firmware requires the id read action ( chapter 25 ) note gpioout enable[10] mode[2] mode[1] mode[0] 1xxxxopamp1 in- (3) 3. when op1enpluspin = ?1? the gpio outenable[10] bit is forced to 0. 0 0 x x x hiz (spi_in) 0 1 000 spi out (4) 4. in all configurations in which gpio[10] is enabled as output: a) the gpio[10] pin can be always used as an analog i nput to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[10] pin can be always used as a digital input so its va lue can be always read through spi interface (spi_in function); c) please note that gpio[10] output is directly c onnected to extpwm2 input for bridge 1 or 2 and therefore particular care must be taken in or der to avoid wrong pwm si gnals when extpwm2 is selected for bridge 1 or 2; d) the gpio[10] pin is a rail to rail output supplied by v gpio_spi. 0 1 0 0 1 interrupt ctrl (4) 0 1 010 auxpwm2 (4) 0 1 011 auxpwm3 (4) 0 1 1 0 0 interrupt ctrl inverted (4) 0 1 1 0 1 auxpwm2 inverted (4) 0 1 0 0 0 auxpwm3 inverted (4)
gpio pins SABRE-LL-I 118/141 figure 38. gpio[10] block diagram table 90. gpio[10] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[10] logic decode from spi v 3v3 to adc to internal logic & spi to opamp1 in - v 3v3 gpio[10] driver pin state sampl e circuit sampleid id2 v gpio_spi
SABRE-LL-I gpio pins 119/141 22.13 gpio[11] the gpio[11] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 91. gpio[11] truth enopl (1) 1. the enop1 bit in the opamp1ctrl regi ster enables the operational amplifier 1. gpio[11] spi bits function note gpioout enable[11] mode[2] mode[1] mode[0] 1 x x x x opamp1 out (2) 2. when enop1 = ?1? the gpiooutenable[11] bit is forced to 0. 0 0 x x x hiz (spi_in) 01000spi out (3) 3. in all configurations in which gpio[11] is enabled as output: a) the gpio[11] pin can be always used as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[11] pin can be always used as a digital input so its va lue can be always read through spi interface (spi_in function); c) please note that gpio[11] output is directly c onnected to extpwm4 input for bridge 3 or 4 and therefore particular care must be taken in or der to avoid wrong pwm si gnals when extpwm4 is selected for bridge 3 or 4; d) the gpio[11] pin is a rail to rail output supplied by v gpio_spi. 01001a2dgpo (3) 01010auxpwm1 (3) 01011auxpwm2 (3) 01100spi out inverted (3) 0 1 1 0 1 a2dgpo inverted (3) 01110auxpwm1 inverted (3) 01111auxpwm2 inverted (3)
gpio pins SABRE-LL-I 120/141 figure 39. gpio[11] block diagram table 92. gpio[11] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = -15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[11] logic decode from central logic v 3v3 to adc to internal logic & spi opamp 1 v 3v3 v gpio_spi
SABRE-LL-I gpio pins 121/141 22.14 gpio[12] the gpio[12] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 93. gpio[12] truth aux2enable or aux2syste m (1) 1. aux2enable or aux2system bit =1 represent the case in which aux2 is used as a regulator (system or not system). op2en pluspin gpio[12] spi bits function note gpioout enable[12] mode[2] mode[1] mode[0] 1 x x x x x regloop2 01xxxxopamp2 in+ (2) 2. when op2enpluspin = ?1? the gpio outenable[11] bit is forced to 0. 0 0 0 x x x hiz (spi_in) 0 0 1 0 0 0 spi out (3) 3. in all configurations in which gpio[12] is enabled as output: a) the gpio[12] pin can be always used as an analog input to the adc s ystem (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[12] pin can be always used as a digital input so its va lue can be always read through spi interface (spi_in function); c) please note that gpio[12] output is directly connected to stepcmd input for stepper driver and therefore particular care must be taken in or der to avoid wrong pwm si gnals when stepcmd is selected for stepper driver (step_request function) d) the gpio[12] pin is a rail to ra il, back to back output supplied by v gpio_spi. 0 0 1 0 0 1 interrupt ctrl (3) 0 0 1 0 1 0 comp2out (3) 0 0 1 0 1 1 regloop2 (3) 0 0 1 1 0 0 interrupt ctrl inverted (3) 0 0 1 1 0 1 comp2out inverted (3) 0 0 1 1 1 1 regloop2 inverted (3)
gpio pins SABRE-LL-I 122/141 figure 40. gpio[12] block diagram table 94. gpio[12] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[12] logic decode from spi v 3v3 to adc to internal logic & spi to opamp2 in + v 3v3 back to back driver v gpio_spi
SABRE-LL-I gpio pins 123/141 22.15 gpio[13] the gpio[13] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 95. gpio[13] truth op2en mimuspin (1) 1. the op2enminuspin bit in the opam p2ctrl register enabl es the connection of the positive input of op1 to gpio[13] pin. gpio[13] spi bits function note gpioout enable[13] mode[2] mode[1] mode[0] 1xxxxopamp2 in- (2) 2. when op2enminuspin = ?1? the gpio outenable[13] bit is forced to 0. 0 0 x x x hiz (spi_in) 0 1 0 0 0 spi out (3) 3. in all configurations in whic h gpio[9] is enabled as output: a) the gpio[13] pin can be always used as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[13] pin can be always used as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[13] pin is a rail to rail output supplied by v gpio_spi. 01001auxpwm1 (3) 0 1 0 1 0 reg loop 3 (3) 01011auxpwm3 (3) 0 1 1 0 0 auxpwm1 inverted (3) 0 1 1 0 1 reg loop 3 inverted (3) 0 1 1 1 1 auxpwm3 inverted (3)
gpio pins SABRE-LL-I 124/141 figure 41. gpio[13] block diagram table 96. gpio[13] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[13] logic decode from spi v 3v3 to adc to internal logic & spi to opamp2 in - v 3v3 gpio[13] driver v gpio_sp
SABRE-LL-I gpio pins 125/141 22.16 gpio[14] the gpio[14] truth table is (for the abbreviation list please refer to ta bl e 6 8 ): table 97. gpio[14] truth enop2 (1) 1. the enop2 bit in the opamp2ctrl regi ster enables the operational amplifier 2. gpio[14] spi bits function note gpioout enable[14] mode[2] mode[1] mode[0] 1 x xxx opamp2 out (2) 2. when enop2 = ?1? the gpiooutenable[14] bit is forced to 0. 0 0 x x x hiz (spi_in) 0 1 000 spi out (3) 3. in all configurations in which gpio[14] is enabled as output: a) the gpio[14] pin can be always used as an analog input to the adc system (adc function) by writing its address in the a2dchannelx[4:0] in the a2 dconfigx register and starting a conversion; b) the gpio[14] pin can be always used as a digital input so its va lue can be always read through spi interface (spi_in function); c) the gpio[14] pin is a rail to rail output supplied by v gpio_spi. 0 1 0 0 1 interrupt ctrl (3) 0 1 010 auxpwm2 (3) 0 1 011 auxpwm3 (3) 0 1 100spi out inverted (3) 0 1 1 0 1 interrupt ctrl inverted (3) 0 1 1 1 0 auxpwm2 inverted (3) 0 1 1 1 1 auxpwm3 inverted (3)
gpio pins SABRE-LL-I 126/141 figure 42. gpio[14] block diagram table 98. gpio[14] specification parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage 0.8 v v hys input voltage hysteresis 0.22 v v ol low level output voltage i out = 15ma, v gpio_spi = 3.15v 0.4 v v oh high level output voltage i out = 15ma, v gpio_spi = 3.15v 2.75 v i leakage leakage current 0 v out v gpio_spi , v gpio_spi = 3.15v -1 1 a t delay delay from serial write to pin low c load =50 pf (1) 1. measured between nss rising edge and 50% of v out . 500 ns gpio[14] logic decode from central logic v 3v3 to adc to internal logic & spi opamp 2 v 3v3 v gpio_sp gpio[14] driver
SABRE-LL-I serial interface 127/141 23 serial interface s.a.b.re can communicate with an external microprocessor by using an integrated slave spi (serial protocol interface). through this interface almost all s.a.b.re functionalities can be controlled and all the ics can be seen as a register map made by 128 register of 16-bit each. the spi is a simple industry standard communications interface commonly used in embedded systems and it has the following four i/o pins: ? miso (master input slave output) ? mosi (master output slave input) ? sclk (serial clock [controlled by the master]) ? nss (slave select active low [controlled by the master]) the ?miso? (master in, slave out) signal carries synchronous data from the slave to the master device. the mosi (master out, slave in) signal carries synchronous data from the master to the slave device. the sclk signal is driven by the master, synchronizing all data transfers. each spi slave device has one nss signal that is an active-low slave input/master output pin. slave devices do not respond to transactions unless their nss input signal is driven low. master device interfacing with multiple spi slave devices has an nss signal for each slave device. s.a.b.re will maintain its miso pin in high imped ance until it does no t recognize its address in serial frame. 23.1 read transaction a read transaction (see figure 43 ) is always started by the master device that lowers the nss pin. the other bits are then sent on the mosi pin with this order: 1. 7-bit representing the address of the register that must be read (msb first [a 6 ?a 0 ]); 2. 2-bit that must be ?10? for a read transaction; 3. 2-bit representing s.a.b.re ic address; 4. 1-bit reserved for future use that must be set at ?0?. at this point the data stored in the register at the selected add ress will be shifted out on the miso pin. the read operation is terminated by raising the signal on nss pin.
serial interface SABRE-LL-I 128/141 figure 43. spi read transaction 23.2 write transaction a write transaction (see figure 44 ) is always started by the master lowering the signal on nss pin. the other bits are then sent on the mosi pin with this order: 1. 7-bit representing the address of the register that must be written (msb first [a6?a0]); 2. 2-bit that must be ?01? for a read transaction; 3. 2-bit representing s.a.b.re ic address; 4. 1-bit reserved for future use that must be set at ?0?. the data to be written (msb first d15?d0) are then read from mosi pin. the length of data field can be 16 or 20 bits, but only the first 16-bit are accepted as valid data. data is latched on rising edge of the nss line. figure 44. spi write transaction the spi input and output timing definitions are shown in the following tables: ns s sclk mosi miso a6 a0 d15 d0 registe r address fiel d data field control field ic address hi g h im p edanc e nss sclk mosi miso a6 a0 d1 5 d0 register address fiel d data field control field ic addres hi g h im p edanc e
SABRE-LL-I serial interface 129/141 figure 45. spi input timing diagram figure 46. spi output timing diagram v il v ih v il v ih v il v ih nss sclk mos i t nss setu p t mosi setu p t mosi hold t sclk rise t sclk fall t sclk hi g t sclk low t nss hold t nss min t sclk p eriod v il v ih v il v ih nss sclk mos i t nss setu p t miso valid t sclk rise t sclk fall t sclk hi g h t sc l k l ow t nss hol d t nss min v ol v oh mis o t sclk p eriod t miso disable
serial interface SABRE-LL-I 130/141 table 99. spi interface specifications (note: v gpio_spi =3.3v unless otherwise specified) parameter description test condition min typ max unit v ih high level input voltage 1.6 v v il low level input voltage (1) 1. specification applies to n ss, sclk and mosi pins. 0.8 v v hys input voltage hysteresis (1) 0.22 v v oh high level output voltage i out = -10ma, (2) 2. current is considered to be pos itive when flowing towards the ic 2.75 v v ol low level output voltage i out = 10ma, (2) 0.4 v t sclk_period sclk period 62.5 ns t sclk_rise sclk rise time 2 ns t sclk_fall sclk fall time 2 ns t sclk_high sclk high time 20 ns t sclk_low sclk low time 20 ns t nss_setup nss setup time 10 ns t nss_hold nss hold time 10 ns t nss_min nss high minimum time 30 ns t mosi_setup mosi setup time 10 ns t mosi_hold mosi hold time 10 ns t miso_rise miso rise time c load =50pf (3) 3. these times are measured at t he pin output between specified v oh and v ol . 9ns t miso_fall miso fall time c load =50pf (3) 9ns t miso_valid miso valid from clock low 0 15 ns t miso_disable miso disable time 0 15 ns c load miso maximum load 200 pf
SABRE-LL-I registers list 131/141 24 registers list many of the s.a.b.re functionalities are controlled or can be supervised by accessing to the relative register through serial interface. all these registers can be seen from the user (microcontroller) point of view as a register table. each register is one word wide (16-bit) and can be read using a 7-bit address table 100. register address map address[6:0] (binary) name comment address[6:0] (binary) name comment 000_0000 devname read only 100_0000 auxpwm1ctrl 000_0001 coreconfigreg 100_0001 auxpwm2ctrl 000_0010 ictemp 100_0010 gppwm3base 000_0011 icstatus 100_0011 gppwm3ctrl 000_0100 entestregs 100_0100 000_0101 sampleid 100_0101 000_0110 watchdogcfg 100_0110 intctrlcfg 000_0111 watchdogstatus 100_0111 intctrlctrl 000_1000 softresreg 100_1000 digcmpcfg 000_1001 100_1001 digcmpvalue 000_1010 100_1010 000_1011 100_1011 000_1100 hibernatestatus 100_1100 000_1101 hibernatecmd 100_1101 000_1110 100_1110 000_1111 mtr1_2pwrctrl 100_1111 001_0000 mainvswcfg 101_0000 a2dcontrol 001_0001 101_0001 a2dconfig1 001_0010 mainlincfg 101_0010 a2dresult1 001_0011 101_0011 a2dconfig2 001_0100 swctrcfg 101_0100 a2dresult2 001_0101 101_0101 001_0110 101_0110 001_0111 101_0111 001_1000 stdbymode 101_1000 gpiooutenable 001_1001 101_1001 gpioctrl1 001_1010 101_1010 gpioctrl2 001_1011 101_1011 gpioctrl3
registers list SABRE-LL-I 132/141 001_1100 101_1100 gpiopadval read only 001_1101 101_1101 gpiooutval 001_1110 101_1110 001_1111 101_1111 010_0000 mtrs1_2cfg 110_0000 lowvswitchctrl 010_0001 mtr1cfg 110_0001 010_0010 mtr1ctrl 110_0010 010_0011 mtr1limit 110_0011 010_0100 mtr2cfg 110_0100 opampctrl1 010_0101 mtr2ctrl 110_0101 opampctrl2 010_0110 mtr2limit 110_0110 010_0111 110_0111 010_1000 mtrs3_4cfg 110_1000 010_1001 mtr3cfg 110_1001 010_1010 mtr3ctrl 110_1010 010_1011 mtr3ilimit 110_1011 010_1100 mtr4cfg 110_1100 010_1101 mtr4ctrl 110_1101 010_1110 mtr4ilimit 110_1110 010_1111 110_1111 011_0000 stpcfg1 111_0000 011_0001 stpcfg2 111_0001 011_0010 stpctrl 111_0010 011_0011 stpcmd 111_0011 011_0100 stptest 111_0100 011_0101 aux1swcfg 111_0101 011_0110 aux2swcfg 111_0110 011_0111 aux3swcfg1 111_0111 011_1000 aux3swcfg2 111_1000 011_1001 power mode control 111_1001 011_1010 111_1010 011_1011 111_1011 rev_mfct 011_1100 currdacctrl 111_1100 reserved table 100. register address map (continued) address[6:0] (binary) name comment address[6:0] (binary) name comment
SABRE-LL-I registers list 133/141 011_1101 111_1101 reserved 011_1110 111_1110 reserved 011_1111 111_1111 reserved table 100. register address map (continued) address[6:0] (binary) name comment address[6:0] (binary) name comment
schematic samples SABRE-LL-I 134/141 25 schematic samples figure 47. application with 2 dc motors, 1 stepper motor and 3 power supplies r40 560 + c27 10uf 10v v3v 3 device id r25 3.9 dc1_plus c29 100nf jp5 1 2 3 nss jp9 r39 open awake r43 22k r7 4.7k con3 1 2 3 gpio4 d6 led 1.2v 0.5a c22 1nf dc2_plus mosi + c16 680uf 50v c23 1nf c5 680nf gpio2 gpio12 gpio1 r23 2.2 c10 100nf c8 100nf sclk +3_3vs c21 1nf r38 open c11 100nf c15 100pf vlinmain mosi dc2_minus r44 39k j9 1 2 r22 1 jp6 1 2 3 c3 1uf 1210 r15 1k vsupply r37 2.2k gpio6 gpio11 + c26 330uf 25v j5 1 2 j1 con5x2 1 3 5 7 9 2 4 6 8 10 j6 1 2 r36 2.2k gnd sclk r27 1 r20 1k dc1_minus v3v 3 gpio14 l2 33uh 4.5a coilcraf t do5040h-333mld d7 6cwq06 mi so gpio12 r12 330 d4 led jp11 j3 1 2 reset gpio13 c12 100pf vswdrv id1 gpio10 r26 2.2 gpio5 gpio0 reset r18 1k q5 std12nf06l awake jp13 r21 1k gnd nss +3_3vs jp1 1 2 3 jp3 1 2 3 id2 gpio8 d5 led c14 100nf r11 330 jp16 c9 100nf r13 330 vsupply close on master c2 1uf jp4 1 2 3 j10 con17x2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 gpio14 j8 1 2 d3 stps3l60u c31 100nf r3 4.7k vsupply d2 led vsupply 12v 3a j4 1 2 +3_3vs d1 led c1 1uf c28 330nf nss j2 1 2 jp8 mosi c20 1nf nawake j11 con10 1 2 3 4 5 6 7 8 9 10 c18 1nf gnd nss r41 1k q2 bc846b 2 3 1 mi so r19 1k c24 1nf +3_3vs gnd +3_3vs jp12 nreset c13 100nf v3v 3 u1 sabre 17 18 19 20 27 28 23 25 24 22 21 26 29 30 31 32 33 34 37 36 35 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 61 62 60 58 59 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 66 67 68 69 70 71 72 73 dc2_plus vsupply mi so mosi vref_fb iref_fb gpio8 vsupply vswmain_sw vlinmain_out vlinmain_fb vswmain_fb sclk vsupply dc4_plus dc4_plus dc4_sense nawake gpio14 gpio13 gpio12 dc4_minus dc4_minus dc4_sense dc3_sense dc3_minus dc3_minus gpio11 gpio10 gpio9 gpio5 dc3_sense dc3_plus dc3_plus vsupply nreset v3v 3 vsupply int gpio7 vgpio_spi gpio6 cph cpl vpump vswdrv_sw vswdrv_gate vsupply dc1_plus dc1_plus vswdrv_sns vswdrv_fb gpio4 gpio3 dc1_minus dc1_minus gnd1 gnd2 dc2_minus dc2_minus gpio2 gpio1 gpio0 nss dc2_plus tab tab tab tab tab tab tab tab tab gpio6 vsupply r2 4.7k gpio1 stepper r8 4.7k gnd nreset jp2 1 2 3 r24 3.9 c19 1nf j7 1 2 r1 4.7k gpio7 sclk gpio8 phase a c7 100nf slave 3.3v 2.5a gpio3 +3_3vs jp14 jp7 q3 bc846b 2 3 1 r6 4.7k gpio5 r16 1k r9 4.7k c17 1nf +3_3vs nreset r17 1k phase b gpio13 vswmain nawake l1 33uh 3a coilcraf t do5010h-333mld q1 bc846b 2 3 1 gpio2 q4 bsp51 r14 1k gpio9 gpio7 jp15 start up configuration c4 1uf r5 4.7k + c25 470uf 16v c6 100nf r10 4.7k master gpio11 mi so r42 0.047 1w
SABRE-LL-I schematic samples 135/141 figure 48. application with 2 dc motors, a battery charger and 5 power supplies 3.3v 3a green gpio8 gpio5 r45 1k gpio2 slave q7 bc846b 2 3 1 r47 10k 1w + c24 470uf 16v d15 led gpio12 l4 33uh 2a coilcraf t do3316p-333mld mi so r2 1k q5 bc846b 2 3 1 r49 1k c25 100nf vswmain r43 1k red + c8 470uf 16v r41 1k d4 stps1l60u r22 1k gpio10 vsupply gpio6 jp2 1 2 3 start up configuration nreset d17 red led c14 100nf gnd red gpio12 nawake j6 1 2 gpio1 nawake r34 4.7k r17 0.1 1w j5 1 2 r29 4.7k mosi nss +3_3vs r38 4.7k v3v 3 +3_3vs vsupply + - u2a lm358 3 2 1 8 4 r42 680 1.8v 1a green vsupply d9 led nss j8 1 2 c26 100pf q9 bc857b 3 1 2 r21 1k d3 bzx284c15 d10 led d6 stps3l60u mosi r30 1k d1 stps3l60u master device id vsupply r8 15k j9 1 2 j11 1 2 vswdc3- d7 stps1l60u reset +vop d12 led j4 1 2 q4 bsp51 1 3 2 4 battery + c17 100nf dc1_plus r6 4.7k c5 10pf gnd j12 con8 1 2 3 4 5 6 7 8 reseton r35 330 q2 bsp51 j7 con10a 1 3 5 7 9 2 4 6 8 10 c4 1nf r13 4.7k d5 es3b v3v 3 sclk mosi r23 10k 0.1% dc2_plus gnd c12 100nf 5v 1a d14 led green q3 bc846b 2 3 1 + c9 330uf 25v d19 led gpio7 + - u2b lm358 5 6 7 8 4 gpio13 j1 con34a 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 gpio2 gpio9 r10 1k q6 bc846b 2 3 1 12v 1.5a max gpio5 dc2_minus r44 2.2k id1 jp5 1 2 3 r33 330 green vsupply nss awake jp1 1 2 3 c13 1uf r19 10k r36 2.2k dc1_minus 1.2v 0.5a id2 + c29 470uf 16v r31 4.7k gpio6 awake +3_3vs r16 820 + c19 10uf 10v +3_3vs r14 4.7k 1w r3 1k d11 led r11 560 vlinmain jp9 d20 led vswdrv reset c23 100nf d21 led close on master r12 4.7k r7 1k c32 100pf gpio8 green gpio4 c7 100nf l2 33uh 4.5a coilcraf t do5040h-333mld d16 y ellow led c30 100nf sclk nreset r37 330 c1 1nf gnd gpio0 +3_3vs r27 1k r18 1k vsupply r46 10k 1w r9 1k + c22 22uf 16v l1 33uh 3a coilcraf t do5010h-333mld + c27 470uf 16v green gpio3 r48 330 d18 led r24 10k gpio11 l3 33uh 2a coilcraf t do3316p-333mld to practispin gnd r5 2.2k gnd gpio7 c31 100pf jp7 1 2 3 green +3_3vs jp3 1 2 3 j3 1 2 j10 1 2 +3_3vs +vop c28 100nf d8 led 12.8v 3a v3v 3 l5 33uh 2a coilcraf t do3316p-333mld d2 6cwq06 c6 100pf charge in progress mi so gpio11 sclk r40 270 green gpio14 r26 4.7k jp6 1 2 3 c3 1nf gpio1 r25 150k 0.1% r20 10k 0.1% q1 std12nf06l r28 150k 0.1% jp8 con3 1 2 3 u1 sabre 17 18 19 20 27 28 23 25 24 22 21 26 29 30 31 32 33 34 37 36 35 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 61 62 60 58 59 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 66 67 68 69 70 71 72 73 dc2_plus vsupply mi so mosi vref_fb iref_fb gpio8 vsupply vswmain_sw vlinmain_out vlinmain_fb vswmain_fb sclk vsupply dc4_plus dc4_plus dc4_sense nawake gpio14 gpio13 gpio12 dc4_minus dc4_minus dc4_sense dc3_sense dc3_minus dc3_minus gpio11 gpio10 gpio9 gpio5 dc3_sense dc3_plus dc3_plus vsupply nreset v3v 3 vsupply int gpio7 vgpio_spi gpio6 cph cpl vpump vswdrv_sw vswdrv_gate vsupply dc1_plus dc1_plus vswdrv_sns vswdrv_fb gpio4 gpio3 dc1_minus dc1_minus gnd1 gnd2 dc2_minus dc2_minus gpio2 gpio1 gpio0 nss dc2_plus tab tab tab tab tab tab tab tab tab r15 1k vdc3+ disconnect the battery jp4 j2 1 2 c2 1nf c10 100pf gnd c15 680nf d13 red led green r1 1k nreset + c20 470uf 63v r32 10k 1w mi so +3_3vs c21 1uf c11 100pf c18 330nf r4 0.047 1w c16 100nf r39 680 nss
pin list SABRE-LL-I 136/141 26 pin list 26.1 pin list table 101. pins configuration pin # pin name description type 1 dc1_plus bridge 1 phase ?plus? output output 2v swdrv_sns switching regulator controller sense analog input 3v swdrv_fb switching regulator controller feedback analog input 4 gpio4 general purpose i/o a nalog in/out - cmos bi-dir 5 gpio3 general purpose i/o a nalog in/out - cmos bi-dir 6 dc1_minus bridge 1 phase ?minus? output output 7 dc1_minus bridge 1 phase ?minus? output output 8 gnd1 ground pin for bridge1 (1)(2)(3) power/digital 9 gnd2 ground pin for bridge2 (1)(2)(3) power/digital 10 dc2_minus bridge 2 phase ?minus? output output 11 dc2_minus bridge 2 phase ?minus? output output 12 gpio2 general purpose i/o a nalog in/out - cmos bi-dir 13 gpio1 general purpose i/o a nalog in/out - cmos bi-dir 14 gpio0 general purpose i/o analog input - cmos input 15 nss spi chip select pin cmos input 16 dc2_plus bridge 2 phase ?plus? output output 17 dc2_plus bridge 2 phase ?plus? output output 18 v supply main voltage supply power input 19 miso spi serial data output cmos output 20 mosi spi serial data input cmos input 21 v linmain_fb linear main regulator feedback analog input 22 v linmain_out linear main regulator output power output 23 gpio 8 general purpose i/ o analog in/out - cmos bi-dir 24 v swmain_sw main switching regulator switching output power output 25 v supply main voltage supply power input 26 v swmain_fb main switching regulator feedback pin analog input 27 v ref_fb regulator voltage feedback analog input 28 i ref_fb regulator current feedback analog input 29 sclk spi input clock pin cmos input 30 v supply main voltage supply power input 31 dc4_plus bridge 4 phase ?plus? output output
SABRE-LL-I pin list 137/141 32 n.c. not connected 33 dc4_sense bridge 4 sense output (4) output 34 nawake device wake up cmos input 35 gpio12 general purpose i/o a nalog in/out - cmos bi-dir 36 gpio13 general purpose i/o a nalog in/out - cmos bi-dir 37 gpio14 general purpose i/o a nalog in/out - cmos bi-dir 38 n.c. not connected 39 dc4_minus bridge 4 phase ?minus? output output 40 dc4_sense bridge 4 sense output (4) output 41 dc3_sense bridge 3 sense output (4) output 42 dc3_minus bridge 3 phase ?minus? output output 43 n.c. not connected 44 gpio11 general purpose i/o a nalog in/out - cmos bi-dir 45 gpio10 general purpose i/o a nalog in/out - cmos bi-dir 46 gpio9 general purpose i/o a nalog in/out - cmos bi-dir 47 gpio5 general purpose i/o a nalog in/out - cmos bi-dir 48 dc3_sense bridge 3 sense output (4) output 49 n.c. not connected 50 dc3_plus bridge 3 phase ?plus? output output 51 v supply main voltage supply power input 52 nreset open drain system reset pin cmos input/output 53 v 3v3 internal 3.3 volt regulator power input/output 54 v supplyint internal voltage supply power input 55 gpio7 general purpose i/o a nalog in/out - cmos bi-dir 56 v gpio_spi low voltage pins power supply power input 57 gpio6 general purpose i/o a nalog in/out - cmos bi-dir 58 v swdrv_sw switching regulator controller source input power input 59 v swdrv_gat e switching driver gate drive pin analog output 60 v pump charge pump voltage power input/output 61 cph charge pump high switch pin power input/output 62 cpl charge pump low switch pin power input/output 63 v supply main voltage supply power input 64 dc1_plus bridge 1 phase ?plus? output output e_pad gnd_pad (1)(2)(3) table 101. pins configuration (continued) pin # pin name description type
pin list SABRE-LL-I 138/141 1. these pins must be connected all together to a unique pcb ground. 2. bridges1 and 2 have 2 ground pads: one is bonded to the relative ground pin (gnd1 or gnd2) and the other is connected to exposed pad (e _pad) ground ring. this makes t he bond wires testing possible by forcing a current between e-pad and gnd1 or gnd2 pi ns and using the other pin as sense pin to measure the resistance of e-pad bonding. (n.b: grounds of two bridges are inter nally connected together). 3. the analog ground is connected to exposed pad e-pad. 4. the pin must be tied to ground if bridge is not used as a stepper motor.
SABRE-LL-I package information 139/141 27 package information in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 49. tqfp64 mechanical data & package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.20 0.0472 a1 0.05 0.15 0.002 0.006 a2 0.95 1.00 1.05 0.0374 0.0393 0.0413 b 0.17 0.22 0.27 0.0066 0.0086 0.0086 c 0.09 0.20 0.0035 0.0078 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d2 2.00 0.787 d3 7.50 0.295 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e2 2.00 0.787 e3 7.50 0.295 e 0.50 0.0197 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0?3.5?7? 0?3.5?7? ccc 0.080 0.0031 tqfp64 (10x10x1.0mm) exposed pad down 7278840 b
revision history SABRE-LL-I 140/141 28 revision history table 102. document revision history date revision changes 14-nov-2007 1 initial release.
SABRE-LL-I 141/141 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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