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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2004-2006, zarlink semiconductor inc. all rights reserved. features ? 32,768 channel x 32,768 channel non-blocking digital time division multiplex (tdm) switch at 65.536 mbps, 32.768 mbps or 16.384 mbps ? 16,384 channel x 16,384 channel non-blocking digital tdm switch at 8.192 mbps ? up to 128 serial tdm input streams, divided into 32 groups with 4 input streams per group ? up to 128 serial tdm output streams, divided into 32 groups with 4 output streams per group ? per-group input bit delay for flexible sampling point selection ? per-group output fractional bit advancement ? four sets of output timing signals for interfacing additional devices ? per-channel constant or variable throughput delay for frame integrity and low latency applications ? per-channel high impedance output control ? per-channel force-high output control ? per-channel message mode ? control interface compatible with intel and motorola selectable 32 bit and 16 bit non- multiplexed buses ? connection memory block programming ? supports st-bus and gci-bus standards for input and output timing ? ieee 1149.1 (jtag) test port ? 3.3 v i/o with 5 v tolerant inputs; 1.8 v core applications ? large switching platforms ? central office switches ? wireless base stations and controllers ? multi-service access platforms january 2006 ordering information ZL50074GAC 484 ball lbga trays zl50074gag2 484 ball pbga** trays **pb free tin/silver/copper -40 c to +85 c zl50074 32 k x 32 k channel tdm switch with 128 input and 128 output streams data sheet figure 1 - zl50074 functional block diagram test access vss vdd_io tdi tdo tck trst tms stoa0 pwr connection memory stia0 ode data memory s/p microprocessor interface stob0 stib0 vdd_core converter timing p/s converter d31-0 berr wait dta im ds cs r/w a18-0 fpi 2-0 cki 2-0 ck_sel1-0 fpo 3-0 cko 3-0 port siz1-0 stic0 stid0 stoc0 stod0 d16b and control registers output input timing timing stia31 stib31 stic31 stid31 : : input group 0 input group 31 output group 0 output group 31 stoa31 stob31 stoc31 stod31 : :
zl50074 data sheet 2 zarlink semiconductor inc. ? digital loop carriers ? time division multiplexers ? media gateways description the zl50074 is a non-blocking time division multiplex (t dm) switch with maximum 32,768 x 32,768 channels. the device can switch 64 kbps or nx64 kbps tdm cha nnels from any input stream to any output stream. all tdm input and output streams ope rate at the same rate, either 65.536 mbps, 32.768 mbps, 16.384 mbps or 8.192 mbps, programmed by the global rate control register. in 65 mbps mode, only stia and stoa streams are used, resulting in 32 input and 32 output streams. in 32 mbps mode, stia, stoa, stib, and stob streams are available, resulting in 64 input and 64 output streams. in 16 mbps or 8 mbps mode, stia, stoa, stib, stob, stic, stoc, stid and stod streams are all available, resulting in 128 input and 128 output streams. the full 32 k x 32 k channel switching capacity is maintained at bit rates of 65 mbps, 32 mbps and 16 mbps. the capacity reduces to 16 k x 16 k when operating at 8 mbps. the zl50074 uses a master clock (cki 0) and frame pulse (fpi 0) to define the tdm data stream frame boundary and timing. a high speed system clock is derived internally from cki 0 and fpi 0. the input and output data streams can independently reference their timings to one of th e input clocks or to the internal system clock. the zl50074 has a vari ety of user configurable options designed to provide fl exibility when data streams are connected to multiple tdm components or circuits. these include: ? two additional programmable reference inputs, cki 2 - 1 and fpi 2 - 1, which can be used to provide alternative sources for inpu t and output stream timing ? variable input bit delay and output advancement, to accommodate delays and frame offsets of streams connected through different data paths ? four timing outputs, cko 3 - 0 and fpo 3 - 0, which can be configured independently to provide a variety of clock and frame pulse options ? support of both st-bus and gci-bus formats ? per-channel variable delay mode for low latency applicat ions and constant delay mode for frame integrity applications the device contains two types of internal memory: data memory and connection memory. incoming tdm data is stored in the data memory. tdm data is read from the data memory controlled by the connection memory, and output on the tdm output streams. there are two major modes of operati on: connection mode and message mode. in connection mode, the contents of the connection memory define, for each output stre am and channel, the input source stream and channel. in message mode, the connection memory is used for the storage of microprocessor da ta. using zarlink's message mode capability, microprocessor data can be broadcas t to the data output stream s on a per-channel basis. this feature is useful for transferring c ontrol and status information for exte rnal circuits or other tdm devices. the non-multiplexed microprocessor port provides access to the internal data memory, connection memory and configuration registers used to program zl50074 options. the port is confi gurable to interface with either motorola or intel-type microprocessors and is se lectable to be either 32 bit or 16 bit. the mandatory requirements of ieee 11 49.1 (jtag) standard are supported via the dedicated test access port.
zl50074 data sheet table of contents 3 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 change summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 switching configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 stream provisioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.0 input clock (cki ) and input frame pulse (fpi ) timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0 output clock (cko ) and output frame pulse (fpo ) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0 output channel control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 data input delay and data output advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 input sampling point delay programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 fractional bit advancement on output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.0 message mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 data memory read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 connection memory block programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.0 data delay through the switching paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 constant delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.2 variable delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.0 microprocessor port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 32 bit bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.3 16 bit bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.4 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4.1 read cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4.2 write cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.0 power-up and initialization of the zl50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.1 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.2 power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.0 ieee 1149.1 test access port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.1 test access port (tap) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 10.2 instruction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.3 test data register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.4 boundary scan description language (bsdl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11.0 memory map of zl50074 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.0 detailed memory and register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.1 connection memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12.1.1 connection memory bit functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12.1.2 connection memory lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.2 data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 12.3 group control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.4 input clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.5 output clock control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12.6 block init register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.7 block init enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.8 global rate control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.0 dc/ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
zl50074 data sheet list of figures 4 zarlink semiconductor inc. figure 1 - zl50074 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - input sampling point delay programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3 - output bit advancement timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4 - data throughput delay for constant delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 5 - data throughput delay for variable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 6 - read cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7 - write cycle operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8 - frame pulse input and clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 9 - frame skew timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 10 - st-bus frame pulse and clock output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 11 - gci frame pulse and clock output timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 12 - serial data timing to cki . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 13 - serial data timing to cko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 14 - cko to other cko skew. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 15 - microprocessor bus interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 16 - intel mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 17 - jtag test port & pwr reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
zl50074 data sheet list of tables 5 zarlink semiconductor inc. table 1 - data rate and maximum switch size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 2 - tdm stream bit rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 - cki 0 and fpi 0 setting via ck_sel1 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 - example of address and byte significance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 5 - 32 bit motorola mode byte addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6 - 32 bit motorola mode access transfer size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7 - 32 bit intel mode bus enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 - byte enable signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9 - 16 bit mode word alignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10 - 16 bit mode example byte address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 11 - memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12 - connection memory group address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 13 - connection memory stream address offset at various ou tput rates . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14 - connection memory timeslot address offset range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15 - connection memory bits (cmb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16 - connection memory lsb group address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17 - connection memory lsb stream address offset at vari ous output rates . . . . . . . . . . . . . . . . . . . . . 34 table 18 - data memory group address mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 19 - data memory stream address offset at various output rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 20 - group control register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 21 - group control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 22 - input clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 23 - output clock control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 24 - block and power-up initialization status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
zl50074 data sheet 6 zarlink semiconductor inc. change summary the following table captures the changes from the april 2005 issue. the following table captures the changes from the july 2004 issue. page item change 24 8.4.1, ?read cycle? clarified wait signal description in read cycle. 25 figure 6 "read cycle operation" corrected wait signal tristate timing in read cycle. 25 8.4.2, ?write cycle? clarified wait signal description in write cycle. 26 figure 7 "write cycle operation" corrected wait signal tristate timing in write cycle. page item change 11 "pin description" - cko0-3 added specia l requirement for using output clock at 65.536 mhz. 12 "pin description" - dta , wait added more detailed description to the dta and wait pins. 48 ?ac electrical characteristics1 - fpi0-2 and cki0-2 timing? added t fpis , t fpih (input frame pulse setup and hold) maximum values. 49 figure 9 "frame skew timing diagram" added fp i1,2 frame pulse to figure ?frame skew timing diagram? to clarify frame boundary skew. 50 (1) ?ac electrical characteristics1 - fpo0-3 and cko0-3 (65.536 mhz) timing? (2) ?ac electrical characteristics1 - fpo0-3 and cko0-3 (32.768 mhz) timing? (3) ?ac electrical characteristics1 - fpo0-3 and cko0-3 (16.384 mhz) timing? (4) ?ac electrical characteristics1 - fpo0-3 and cko0-3 (8.192 mhz) timing? added cko 0-3 and fpo 0-3 setup and hold parameters for all different clock rates. 51 ?ac electrical char acteristics - output clock jitter generation? added this table to specify cko 0-3 jitter generation. 52 ?ac electrical char acteristics - serial data timing to cki? (1) values of parameters t sips, t siph, t sins, t sinh, t sipv, t sinv, t sipz and t sinz are revised. (2) separated parameter t ckd into t ckdp and t ckdn. 53 figure 12 "serial data timing to cki" added more detail to figure. 54 ?ac electrical char acteristics - serial data timing to cko? values of parameters t sops, t soph, t sons, t sonh, t sopv, t sonv, t sopz and t sonz are revised. 54 figure 13 "serial data timing to cko" added more detail to figure. 56 ?ac electrical characteristics - cko to other cko 1skew? added cko skew parameters, t ckos , (clock source to internal apll). 56 figure 14 "cko to other cko skew" added figure to show t ckos.
zl50074 data sheet 7 zarlink semiconductor inc. pin diagram - zl50074 23 mm x 23 mm 484 ball pbga (as viewed through top of package) a1 corner identified by metallized marking 12345678910111213141516171819202122 a cko [0] stia [0] d[30] d[25] d[20] d[16] d[15] d[11] d[7] d[4] d[0] a[18] a[14] a[10] a[7] a[2] a[1] ic dta pwr stoa [31] tck b stob [1] stid [1] stoa [0] d[31] d[26] d[21] d16b d[13] d[9] d[5] d[3] a[17] a[11] a[8] a[6] a[0] berr siz[0] stob [31] stia [31] tdo stia [30] c stia [2] stia [3] stib [1] stid [0] im d[27] d[22] d[19] d[12] d[6] d[1] a[15] a[9] a[3] r/w cs fpo [3] stid [31] trst stod [30] stib [30] stid [29] d stic [3] stid [2] stoc [1] stod [0] stob [0] stic [0] d[28] d[23] d[17] d[8] a[16] a[13] a[5] ds wait stod [31] stib [31] tdi stob [30] stic [30] stoa [29] stod [28] e stid [4] stob [3] stic [2] stoa [1] stia [1] stoc [0] stib [0] d[24] d[18] d[14] d[2] a[12] a[4] cko [3] siz[1] stic [31] tms stoc [30] stid [30] stod [29] stia [29] stib [28] f stob [4] stoc [3] stob [2] stod [1] stic [1] v ss v dd_ core d[29] v dd_ io v dd_ core d[10] v dd_ io v dd_ core stoc [31] v dd_ io v ss v dd_ core stoa [30] stoc [29] stic [29] stob [28] stia [28] g stod [4] stod [3] stod [2] stib [2] fpo [0] v dd_ io v ss v ss v dd_ core v dd_ io v ss v dd_ core v dd_ io v ss v dd_ core v dd_ io v ss stob [29] stib [29] stic [28] cki [2] stid [27] h stia [5] stia [4] stid [3] stoc [2] stoa [2] v dd_ core v dd_ io v ss v ss v dd_ core v dd_ io v ss v dd_ core v dd_ io v ss v dd_ core stoa [28] stoc [28] stid [28] stod [27] stic [27] stia [27] j stib [5] cki [1] stic [4] stoa [3] stib [3] v dd_ io v dd_ core v dd_ io v ss v ss v ss v ss v ss v ss v dd_ io v ss v dd_ io stob [27] stoc [27] stib [27] ic stoc [26] k stob [5] stid [5] fpi [1] stoc [4] stoa [4] stib [4] v ss v dd_ core v ss v ss v ss v ss v ss v ss v dd_ core v dd_ io v dd_ core stoa [27] fpi [2] stoa [26] stob [26] stid [26] l ode stod [5] stoc [5] stid [6] stic [5] v dd_ core v dd_ io v ss v ss v ss v ss v ss v ss v ss v ss v dd_ core stod [26] stic [26] stib [26] stia [26] stod [25] stoc [25] m stia [6] stib [6] stic [6] stic [7] stoa [5] v dd_ io v dd_ core v dd_ io v ss v ss v ss v ss v ss v ss v dd_ io v ss v dd_ io stia [25] stid [25] stob [25] stoa [25] ic n stob [6] stoc [6] stod [6] stoa [7] stoa [6] v ss v ss v dd_ core v ss v ss v ss v ss v ss v ss v dd_ core v dd_ io stod [23] stoc [24] stid [24] stob [24] stib [25] stic [25] p stia [7] stib [7] stob [7] stia [8] stoa [8] v dd_ core v dd_ io v dd_ io v ss v ss v ss v ss v ss v ss v dd_ io v dd_ core v dd_ core stoa [23] stic [23] stib [24] stoa [24] stod [24] r stid [7] stoc [7] ic stob [8] stib [8] v dd_ io v dd_ core v ss v ss v dd_ core v dd_ io v ss v dd_ core v dd_ io v ss v ss v dd_ io cko [2] stid [22] stib [23] stia [24] stic [24] t stod [7] v ss stoc [8] stid [9] stib [10] stod [9] v ss v ss v dd_ core v dd_ io v ss v dd_ core v ss v ss v dd_ core v dd_ io v ss stoa [21] fpo [2] stoc [22] stid [23] stoc [23] u stic [8] stod [8] stic [9] stia [10] stoc [10] v ss v dd_ io stoc [12] v dd_ io v dd_ core stia [16] v dd_ io v dd_ core stoa [18] v dd_ io stic [19] v dd_ core stoc [20] stid [21] stic [22] stod [22] stob [23] v stid [8] stib [9] stoc [9] stob [10] stod [10] stob [11] stic [12] stib [13] stoa [13] stic [15] stob [16] stoc [16] ic ck_ sel[1] stib [18] stoa [19] stia [20] stob [20] stod [20] stoc [21] stoa [22] stia [23] w stia [9] stob [9] stid [10] stia [11] stoa [11] stib [12] stod [12] stic [13] stia [14] stod [14] stoc [15] cki [0] ic stob [17] ck_ sel[0] stoc [18] stid [19] stod [19] stid [20] stic [21] stia [22] stob [22] y stoa [9] stoa [10] stib [11] stoc [11] stoa [12] fpo [1] stid [13] stib [14] stob [14] stid [15] stod [15] stod [16] ic stic [17] stoc [17] stia [18] stob [18] stib [19] stib [20] stoa [20] stob [21] stib [22] aa stic [10] stic [11] stod [11] stid [12] stia [13] stob [13] stod [13] stoa [14] stia [15] stoa [15] stib [16] stoa [16] fpi [0] stia [17] stoa [17] ic ic stod [18] stob [19] stoc [19] stia [21] stod [21] ab stid [11] stia [12] stob [12] cko [1] stoc [13] stic [14] stid [14] stoc [14] stib [15] stob [15] stic [16] stid [16] nc nc stib [17] stid [17] stod [17] stic [18] stid [18] stia [19] stic [20] stib [21]
zl50074 data sheet 8 zarlink semiconductor inc. pin description pin name description tdm interface f7, f10, f13, f17, g9, g12, g15, h6, h10, h13, h16, j7, k8, k15, k17, l6, l16, m7, n8, n15, p6, p16, p17, r7, r10, r13, t9, t12, t15, u10, u13, u17 v dd_core power supply for the core logic: +1.8 v f9, f12, f15, g6, g10, g13, g16, h7, h11, h14, j6, j8, j15, j17, k16, l7, m6, m8, m15, m17, n16, p7, p8, p15, r6, r11, r14, r17, t10, t16, u7, u9, u12, u15 v dd_io power supply for the i/o: +3.3 v f6, f16, g7, g8, g11, g14, g17, h8, h9, h12, h15, j9, j10, j11, j12, j13, j14, j16, k7, k9, k10, k11, k12, k13, k14, l8, l9, l10, l11, l12, l13, l14, l15, m9, m10, m11, m12, m13, m14, m16, n6, n7, n9, n10, n11, n12, n13, n14, p9, p10, p11, p12, p13, p14, r8, r9, r12, r15, r16, t2, t7, t8, t11, t13, t14, t17, u6 v ss ground a2, e5, c1, c2, h2, h1, m1, p1, p4, w1, u4, w4, ab2, aa5, w9, aa9, u11, aa14, y16, ab20, v17, aa21, w21, v22, r21, m18, l20, h22, f22, e21, b22, b20 stia0-31 serial tdm input data ?a? streams (5 v tolerant input with internal pull-down) 32 serial tdm input data streams. all streams are at the same rate: 65.536 mbps, 32.678 mbps, 16.384 mbps or 8.192 mbps, programmed by the global rate c ontrol register (section 12.8). the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused inputs are pulled low by in ternal pull-down resistors and may be left unconnected. e7, c3, g4, j5, k6, j1, m2, p2, r5, v2, t5, y3, w6, v8, y8, ab9, aa11, ab15, v15, y18, y19, ab22, y22, r20, p20, n21, l19, j20, e22, g19, c21, d17 stib0-31 serial tdm input data ?b? streams (5 v tolerant input with internal pull-down) 32 serial tdm input data streams. all streams are at the same rate: 32.678 mbps, 16.384 mbps or 8.192 mbps, programmed by the global rate control register (s ection 12.8). these streams are unused when the device data rate is 65.536 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused inputs are pulled low by in ternal pull-down resistors and may be left unconnected.
zl50074 data sheet 9 zarlink semiconductor inc. d6, f5, e3, d1, j3, l5, m3, m4, u1, u3, aa1, aa2, v7, w8, ab6, v10, ab11, y14, ab18, u16, ab21, w20, u20, p19, r22, n22, l18, h21, g20, f20, d20, e16 stic0-31 serial tdm input data ?c? streams (5 v tolerant input with internal pull-down) 32 serial tdm input data streams. all streams are at the same rate: 16.384 mbps or 8.192 mbps, programmed by the global rate control register (section 12.8). these streams are unused when the device data rate is 65.536 mbps or 32.678 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused inputs are pulled low by in ternal pull-down resistors and may be left unconnected. c4, b2, d2, h3, e1, k2, l4, r1, v1, t4, w3, ab1, aa4, y7, ab7, y10, ab12, ab16, ab19, w17, w19, u19, r19, t21, n19, m19, k22, g22, h19, c22, e19, c18 stid0-31 serial tdm input data ?d? streams (5 v tolerant input with internal pull-down) 32 serial tdm input data streams. all streams are at the same rate: 16.384 mbps or 8.192 mbps, programmed by the global rate control register (section 12.8). these streams are unused when the device data rate is 65.536 mbps or 32.678 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused inputs are pulled low by in ternal pull-down resistors and may be left unconnected. b3, e4, h5, j4, k5, m5, n5, n4, p5, y1, y2, w5, y5, v9, aa8, aa10, aa12, aa15, u14, v16, y20, t18, v21, p18, p21, m21, k20, k18, h17, d21, f18, a21 stoa0-31 serial tdm output data ?a? streams (5 v tolerant, 3.3 v tri-state slew-rate controlled outputs) 32 serial tdm output data streams. all streams are at the same rate: 65.536 mbps, 32.678 mbps, 16.384 mbps or 8.192 mbps, programmed by the global rate c ontrol register (section 12.8). the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). d5, b1, f3, e2, f1, k1, n1, p3, r4, w2, v4, v6, ab3, aa6, y9, ab10, v11, w14, y17, aa19, v18, y21, w22, u22, n20, m20, k21, j18, f21, g18, d19, b19 stob0-31 serial tdm output data ?b? streams (5 v tolerant, 3.3 v tri-state slew-rate controlled outputs) 32 serial tdm output data streams. all streams are at the same rate: 32.678 mbps, 16.384 mbps or 8.192 mbps, programmed by the global rate control register (section 12.8). these streams are unused when the device data rate is 65.536 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused outputs are tristated and may be left unconnected. e6, d3, h4, f2, k4, l3, n2, r2, t3, v3, u5, y4, u8, ab5, ab8, w11, v12, y15, w16, aa20, u18, v20, t20, t22, n18, l22, j22, j19, h18, f19, e18, f14 stoc0-31 serial tdm output data ?c? streams (5 v tolerant, 3.3 v tri-state slew-rate controlled outputs) 32 serial tdm output data streams. all streams are at the same rate: 16.384 mbps or 8.192 mbps, programmed by the global rate control register (section 12.8). these streams are unused when the device data rate is 65.536 mbps or 32.678 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused outputs are tristated and may be left unconnected. pin description (continued) pin name description
zl50074 data sheet 10 zarlink semiconductor inc. d4, f4, g3, g2, g1, l2, n3, t1, u2, t6, v5, aa3, w7, aa7, w10, y11, y12, ab17, aa18, w18, v19, aa22, u21, n17, p22, l21, l17, h20, d22, e20, c20, d16 stod0-31 serial tdm output data ?d? streams (5 v tolerant, 3.3 v tri-state slew-rate controlled outputs) 32 serial tdm output data streams. all streams are at the same rate: 16.384 mbps or 8.192 mbps, programmed by the global rate control register (section 12.8). these streams are unused when the device data rate is 65.536 mbps or 32.678 mbps. the data streams can be selected to be either inverted or non-inverted, programmed by the gr oup control registers (section 12.3). unused outputs are tristated and may be left unconnected. w12 cki 0 st-bus/gci-bus clock input (5 v tolerant schmitt-triggered input) this pin accepts an 8.192 mhz, 16.384 mhz, 32.678 mhz or 65.536 mhz clock. this clock must be provided for correct operation of the zl50074 . the frequency of the cki 0 input is selected by the ck_sel1-0 inputs. the active clock edge may be either rising or falling, program med by the input clock control register (section 12.4). aa13 fpi 0 st-bus/gci-bus frame pulse input (5 v tolerant input) this pin accepts the 8 khz frame pulse which marks the frame boundary of the tdm data streams. the pulse width is nominally one cki 0 clock period (assuming st-bus mode) selected by the ck_sel1-0 inputs. the active state of the frame pulse may be either high or low, programmed by the input clock control register (section 12.4). j2, g21 cki 1-2 st-bus/gci-bus clock inputs (5 v tolerant schmitt triggered inputs) these optional tdm clock inputs are at 8.192 mhz, 16.384 mhz, 32.678 mhz or 65.536 mhz. the frequency of each clock input is automatically detected by the zl 50074. refer to section 2.0 for tdm timing options. the active cl ock edge may be either rising or falling, programmed by the input clock control register (section 12.4). unused inputs must be c onnected to a defined logic level. k3, k19 fpi 1-2 st-bus/gci-bus frame pulse inputs (5 v tolerant inputs) these 8 khz input pulses correspond to the optional cki 2-1 clock inputs. the frame pulses mark the frame boundary of the tdm data streams. refer to section 2.0 for tdm timing options. each pulse width is nominally one cki clock period (assuming st-bus mode). the active state of the frame pul se may be either high or low, programmed by the input clock c ontrol register (section 12.4). unused inputs must be connected to a defined logic level. pin description (continued) pin name description
zl50074 data sheet 11 zarlink semiconductor inc. a1, ab4, r18, e14 cko 0-3 st-bus/gci-bus clock outputs (3.3 v outputs with slew-rate control) these clock outputs can be programmed to generate 8.192 mhz, 16.384 mhz, 32.678 mhz or 65.536 mhz tdm clock outputs. the active edge can be programmed to be either rising or falling. the source of the clock outputs can be derived from either the cki 2-0 inputs or the internal system cloc k. the frequency, active edge and source of each clock output can be programmed independently by the output clock control regist er (section 12.5). for 65.536 mhz output clock, the total loading on the output should not be larger than 10pf . g5, y6, t19, c17 fpo 0-3 st-bus/gci-bus frame pulse outputs (3.3 v outputs with slew-rate control) these 8 khz output pulses mark the frame boundary of the tdm data streams. the pulse width is nominally one clock period of the corresponding cko output. the active state of each frame pulse may be either high or low, independently programmed by the output clock control register (section 12.5). w15, v14 ck_sel0-1 master clock input select (5 v tolerant inputs) inputs used to select the frequency and frame alignment of cki 0 and fpi 0: ck_sel1 = 0, ck_sel0 = 0, 8.192 mhz ck_sel1 = 0, ck_sel0 = 1, 16.384 mhz ck_sel1 = 1, ck_sel0 = 0, 32.768 mhz ck_sel1 = 1, ck_sel0 = 1, 65.536 mhz l1 ode output drive enable (5 v tolerant input with internal pull-up) this is the asynchronous output enable control for the output streams. when it is hi gh, the streams are enabled. when it is low, the output streams are tristated. a18, j21, m22, r3, v13, w13, y13, aa16, aa17 ic internal connections in normal mode these pins must be connected low ab13, ab14 nc no connection in normal mode these pins must be left unconnected. microprocessor port and reset a11, c11, e11, b11, a10, b10, c10, a9, d10, b9, f11, a8, c9, b8, e10, a7, a6, d9, e9, c8, a5, b6, c7, d8, e8, a4, b5, c6, d7, f8, a3, b4 d0-31 microprocessor port data bus (5 v tolerant bi-directional with slew-rate output control) 32 or 16 bit bidirectional data bus. used for microprocessor access to internal memories and registers. when 16 bit mode is selected (d16b is logic 1), d31-16 are unused and must be connected to defined logic levels. b16, a17, a16, c14, e13, d13, b15, a15, b14, c13, a14, b13, e12, d12, a13, c12, d11, b12, a12 a0-18 microprocessor port address bus (5 v tolerant inputs) 19 bit address bus for the internal memories and registers. in 16 bit bus mode (d16b is logic 1), please note a0 is not used and must be connected to a defined logic level. in intel 32 bit mode: a1 = be 3 , a0 = be 2 c16 cs chip select input (5 v tolerant input) active low input used with ds to enable read and write access to the zl50074. pin description (continued) pin name description
zl50074 data sheet 12 zarlink semiconductor inc. d14 ds data strobe input (5 v tolerant input) active low input used with cs to enable read and write access to the zl50074. c15 r/w read/write input (5 v tolerant input) this input controls the direction of the data bus lines (d31 - 0) during a microprocessor access. this pin is set high and low for the read and write access respectively. a19 dta data transfer acknowledge (5 v tolerant, 3.3 v tri-state output with slew-rate) this active low output indicate s that a data bus transfer is complete. an external pull-up resi stor is required to hold this pin high when output is high-impedance. b17 berr transfer bus error output wi th slew rate control (5 v tolerant, 3.3 v tri-state outputs with slew-rate control) this pin goes low whenever the microprocessor attempts to access an invalid memory space inside the device. in motorola bus mode, if this bus error signal is activa ted, the data transfer acknowledge signal, dta , will not be generated. in intel bus mode, the generation of the dta is not affected by this berr signal. an external pull-up resistor is required to hold a high level when output is high-impedance. d15 wait data transfer wait output (5 v tolerant, 3.3 v tri-state output with slew rate) active low wait signal output. an ex ternal pull-up resistor is required to hold this pin high when output is high-impedance. b18, e15 siz0-1 data transfer size/upper and lower data strobe inputs (5 v tolerant inputs) motorola 32-bit mode - signals indi cate data transfer size, refer to section 8.0. motorola 16-bit mode:siz0 - lds , siz1 - uds . active low upper and lower data strobes, uds and lds , indicate whether the upper byte, d15 - 8, and/ or lower byte, d7 - 0, is being accessed. intel 32/16-bit mode: siz0 - be0 , siz1 - be1 active low intel type bus-enable signals, be1 and be0 c5 im microprocessor port bus mode select (5 v tolerant input) control input: 0 = motorola mode 1 = intel mode b7 d16b microprocessor port bus 16/32 bit mode select (5 v tolerant input with internal pull-down) control input: 0 = 32 bit data bus 1 = 16 bit data bus pin description (continued) pin name description
zl50074 data sheet 13 zarlink semiconductor inc. 1.0 functional description 1.1 overview the device has 128 st-bus/gci-bus inputs (stia0 - 31, stib0 - 31, stic0 - 31, stid0 - 31) and 128 st-bus/gci-bus outputs (stoa0 - 31, stob0 - 31, stoc0 - 31, stod0 - 31). it is a non-bl ocking digital switch with 32,768 64 kbps channels and is capable of operati ng at 8.192 mbps, 16.384 mbps, 32.768 mbps or 65.536 mbps. the inputs accept serial data streams and the outputs deliv er serial data streams at one of these data rates. all input and output streams operate at the same rate. there are 32 input gr oups with each group consisting of 4 streams (?a?, ?b?, ?c? and ?d?). if the data rate is set to 16.384 mbps or 8.192 mbps, stia0 - 31, stib0 - 31, stic0 - 31 and stid0 - 31 are used for the input traffic. when the data rate is set to 32.768 mbps, stia0 - 31 and stib0 - 31 are used for the input traffic; stic0 - 31 and stid0 - 31 are not used. when the data rate is set to 65.536 mbps, stia0 - 31 are used for the input traffic; stib0 - 31, stic0 - 31, and stid0 - 31 are not used. there are 32 output groups with each group consisting of 4 st reams (?a?, ?b?, ?c?, and ?d?). if the data rate is set to 16.384 mbps or 8.192 mbps, stoa0 - 31, stob0 - 31, stoc0 - 31 and stod0 - 31 are used for the output traffic. if the data rate is set to 32.768 mbps, stoa0 - 31 and stob0 - 31 are used for the output traffic; stic0 - 31 and stid0 - 31 are in high impedance. when the data rate is set to 65.536 mbps, stoa0 - 31 are used for the output traffic; stob0 - 31, stoc0 - 31, and stod0 - 31 are in high impedance. by using zarlink?s message mode capability, the microproce ssor can store data in the connection memory which can be broadcast to the output streams on a per-channel basi s. this feature is useful for transferring control and status information for external circui ts or other st-bus/gci-bus devices. a20 pwr device reset (5 v tolerant schmitt-triggered input) asynchronous reset input used to initialize the zl50074. 0 = reset 1 = normal see section 9.0, power-up and initialization of the zl50074 for detailed description of reset state. ieee 1149.1 test access port (tap) d18 tdi test data (5 v tolerant input with internal pull-up) serial test data input. when not used, this input may be left unconnected. b21 tdo test data (3.3 v output) serial test data output a22 tck test clock (5 v tolerant schmitt-triggered input with internal pull-up) provides the clock to the jtag test logic c19 trst test reset (5 v tolerant schmitt-triggered input with internal pull-up) asynchronously initializ es the jtag tap controller by putting it in the test-logic-reset state. this pin should be pulsed low during power-up to ensure that the devic e is in the normal functional mode. when jtag is not being used, this pin should be pulled low during normal operation. e17 tms test mode select (5 v tolerant input with internal pull-up) jtag signal that controls the state transitions of the tap controller. when not used, this pin is pulled high by an internal pull-up resistor and may be left unconnected. pin description (continued) pin name description
zl50074 data sheet 14 zarlink semiconductor inc. the zl50074 uses the st-bus/gci-bus master input frame pulse (fpi 0) and the st-bus/gci-bus master input clock (cki 0) to define the input frame boundar y and timing for sampling the st-bus/gci-bus input streams. the rate of the input clock is defined by setting the ck_sel1 - 0 pins. in addition, two more frame pulses and clocks can be accepted. the frequencies of these signals are automatically detected by the zl50074. a selectable motorola or intel compatible non-multiplexed microprocessor port allows users to program the device to operate in various modes under different switching c onfigurations. users can use the microprocessor port to perform internal register and memory read and write operations. the microprocessor port can be selectable to be either a 32 bit or 16 bit data bus and to have either a 19 bit or 17 bit address bus. this is selected by setting the d16b pin. there are seven control signals (cs , ds , r/w , dta , wait , berr and im). the device supports the mandatory requirements for the ieee 1149.1 (jtag) standard via the test port. 1.2 switching configuration the zl50074 switches 64 kbps and nx64 kbps data and voice channels from the tdm input streams, to timeslots in the tdm output streams. the device is non-blocki ng; all 32 k input channels can be switched through to the outputs. any input channel can be switched to any avail able output channel. the maximu m switching capacity and the number of channels per stream are shown in table 1 for diff erent data rates of operation. 1.3 stream provisioning the zl50074 is a large switch with a comprehensive list of user configurable, ?per-gro up? programmable features. in order to facilitate ease of use, the zl50074 offers a simple programming model. st reams are grouped in sets of four, with each group sharing the same c onfigured characteristics. in this wa y it is possible to reduce programming complexity, while still maintaining flex ible ?per-group? configuration options: ? input stream clock source selection, see section 2.0 ? output stream clock source selection, see section 2.0 ? input stream sampling point selection, see section 5.1 ? output stream fractional bit advance, see section 5.2 ? input and output stream inversion control; see section 12.3 there are 32 input and 32 output groups. depending on the data rate set for the device there will be either 1, 2 or 4 streams activated in each group. if the data rate is set for 65.536 mbps, the ?a? streams will be activated; the ?b?, ?c? and ?d? streams will not be ac tivated. if the data rate is set for 32.768 mbps, the ?a? and ?b? streams will be activated; the ?c? and ?d? streams will not be activated. if the data rate is set for 16.384 mbps or 8.192 mbps, the ?a?, ?b?, ?c? and ?d? streams will all be activated. the maximum chann el capacity of a group is 1024 channels when operating at any data rate except for 8.192 mbps, in which case t he maximum operating channel capacity decreases to 512 channels. tdm stream data rate number of input tdm data streams number of output tdm data streams number of 64 kbps channels per stream maximum switch capacity (streams x channels = total) 65 mbps 32 32 1024 32 x 1024 = 32,768 32 mbps 64 64 512 64 x 512 = 32,768 16 mbps 128 128 256 128 x 256 = 32,768 8 mbps 128 128 128 128 x 128 = 16,384 table 1 - data rate and maximum switch size
zl50074 data sheet 15 zarlink semiconductor inc. table 1 shows the maximum number of streams availabl e at different bit rates. the zl50074 deactivates unused streams when operating at the higher bit rates as shown in table 2. all tdm input and output data streams operate at the same rate, programmed by the global rate control register (section 12.8). 2.0 input clock (cki ) and input frame pulse (fpi ) timing the input timing for the zl50074 can be set for one of four different frequencies. they can also be set for st-bus or gci-bus mode with positive or negative input. the cki 0 and fpi 0 input timing must be pr ovided in order for the device to be used. there are two additional input clocks an d frame pulses that can be provided. cki0 is used to generate the internal clock. th is clock is used for all the internal logic and can be used as one of the clocks that defines the timing for the input and output data. the input st ream clock source is selected by the issrc1 - 0 (bits 1 - 0) in the group control register. the output stream clock source is selected by the ossrc1 - 0 (bits 17 - 16) in the group control register. the cki 0 and fpi 0 input frequency is set via the ck_sel1 - 0 pins as shown in table 3. by default the cki 0 and fpi 0 pins accept st-bus, negative input timing. the inpu t frame pulse format (st-bus/gci-bus), frame pulse polarity, and clock polarity can be programmed by the gcisel 0 (bit 2), fpipol0 (bit 1), and ckipsl0 (bit 0) in the input clock control register (i ccr), as described in section 12.4. two additional input clocks (cki 2 - 1) and frame pulses (fpi 2 - 1) can be accepted. these signals can be 8.192 mhz, 16.384 mhz, 32.768 mhz or 65.536 mhz and the rates are automatically detected by the device. these clocks and their frame boundaries must be phase aligned with the cki 0 and its frame boundary within a 30 ns skew but can have different jitter values. the clo cks do not have to have the same frequency. if these additional clocks are not used, the pins must be connected to a defined logic level. these additional input clocks and frame pulses can be used as alternative cl ock sources for the input streams, output streams, and output clocks / fr ame pulses. the input streams? clock s ources are controlled by the issrc1-0 (bits 1 - 0) in the group control registers (gcr). the output streams? clock sour ces are controlled by the ossrc1-0 (bits 17 - 16) in the group control registers (gcr). the output clocks? / frame pulses? clock sources are controlled by the cko3src1-0 (bits 22-21), cko2 src1-0 (bits 15-14), cko1src1-0 (bits 8-7), and cko0src1-0 (bits 1-0) in the output clock control regi ster (occr). the clock sources can be set to either the internal system clock or one of the thr ee input clock signals. these are used to provide a direct interface to jittery peripherals. input or output group n (n = 0 - 31) 65 mbps 32 mbps 16 mbps 8 mbps stian / stoan active active active active stibn / stobn not active active active active sticn / stocn not active not active active active stidn / stodn not active not active active active table 2 - tdm stream bit rates ck_sel1 ck_sel0 input cki 0 and fpi 0 00 8.192mhz 0 1 16.384 mhz 1 0 32.768 mhz 1 1 65.536 mhz table 3 - cki 0 and fpi 0 setting via ck_sel1 - 0
zl50074 data sheet 16 zarlink semiconductor inc. when the internal system clock is not used as the clock source, there are limitations to the data rate and the output clock rate. for all the input and output stream groups that do not use the intern al system clock as their clock source, the data rate is limited to be no higher than the selected clock source?s rate (e.g., if cki1 runs at 16.384 mhz and it is selected as the clock source for input stream group 3, then the maximum data rate of stia3, stib3, stic3, and stid3 is 16.384 mbps). similarly, for all the output clocks t hat do not use the internal system clock as their clock source, the clock rate is limited to be no higher t han the selected clock source?s rate (e.g., if cki1 runs at 32.768 mhz and it is selected as the clock source for output clock cko0 , then the maximum clock rate of cko0 is 32.768 mhz). 3.0 output clock (cko ) and output frame pulse (fpo ) timing there are four output timing pairs, cko 3 - 0 and fpo 3 - 0. by default these signals generate st-bus, negative timing, and use the internal system clock as reference cl ock source. their default clock rates are 65.536 mhz for cko0 , 32.768 mhz for cko1 , 16.384 mhz for cko2 , and 8.192 mhz for cko3 . their properties can also be individually programmed in the outp ut clock control register (occr) to control the frame pulse format (st-bus/gci-bus), frame pulse polar ity, clock polarity, clock rate (8.192 mhz, 16.384 mhz, 32.768 mhz or 65.536 mhz), and reference clock source. refer to secti on 12.5 for programming details. note that the reference clock source can be set to either the internal system clock or one of the three input clock signals. if one of the three input clock signals is selected as the reference sour ce, the output clock cannot be programmed to generate a higher clock frequency than the reference source. as each ou tput timing pair has its own bit settings, they can be set to provide different output timings. for 65.536 mhz output clock, the total loading on the output should not be larger than 10pf. 4.0 output channel control to be able to interface with external buffers, the outp ut signals can be set to enter a high impedance or drive high state on a per-channel basis. the per channel function (bits 31 - 29) in the connection memory bits can be set to 001 to drive the channel output high, or to 000, 110 or 111, to set the channel into a high impedance state. 5.0 data input delay and data output advancement the group control registers (gcr) are used to adjust the input delay and output advanc ement for each input and output data groups. each group is independently programmed. 5.1 input sampling point delay programming the input sampling point delay programmi ng feature provides users with the flexibility of handling different wire delays when incoming traffic is from different sources. by default, all input streams have zero delay, such that bit 7 is the first bit that appears after the input frame boundary (assuming st-bus formatting). the nominal input sa mpling point with zero delay is at the 3/4 bit time. the input delay is enabled by the input sample point dela y (bit 8 - 4) in the group control registers 0 - 31 (gcr0 - 31) as described in section 12.3 on page 36. the input sa mpling point delay can range from 0 to 7 3/4 bit delay with a 1/4 bit resolution on a per group basis.
zl50074 data sheet 17 zarlink semiconductor inc. figure 2 - input sampling point delay programming there are limitations when the zl50074 is programmed to use cki 2 - 0 as the input stream clock source as opposed to the internal clock: ? the granularity of the delay becomes 1/2 the selected re ference clock period, or 1/4 bit, whichever is longer. ? if the selected reference clock frequency is the same as the stream bit rate, the granularity of the delay is 1/2 bit. in this case, the least significant bit of the ispd register is not used; the rema ining 4 bits select the total delay in 1/2 bit increments, to a maximum of 7 1/2 bits. also, the 0 bit delay reference point changes from the 3/4 bit position to the 1/2 bit position. 5.2 fractional bi t advancement on output see section 12.3, group control regi sters, for programming details. this feature is used to advance the output data with respect to the output frame boundary. each group has its own bit advancement value which can be programmed in the group control registers 0 - 31 (gcr0 - 31). by default all output streams have zero bit advancement such that bit 7 is the first bi t that appears after the output frame boundary (assuming st-bus formatting). the output advancement is enabled by the output stream bit advancement (bits 21 - 20) of the group control register s 0 - 31 (gcr0 - 31), as described in section 12.3. the output delay can vary from 0 to 22.8 ns with a 7.6 ns increment. the exception to this is when the device is programmed at 65 mbps, in which case the increment is 3.8 ns with a total advancement of 11.4 ns. nominal channel n+1 boundary 6 00000 (default) 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 sti[n] nominal channel n boundary example: with a setting of 01111 the sampling point for bit 7 will be 3 1/2 bits 7 0 5 4 3 2 1 0 7 6 01110 01111 11110 11101 11100 11011 11010 11001 11000 10111 10110 10101 10100 10011 10010 10001 10000 11111
zl50074 data sheet 18 zarlink semiconductor inc. figure 3 - output bit advancement timing this programming feature is provided to assist in designs where per stream routing delays are significant and different. the osba bits in the group control registers are used to se t the bit-advancement for each of the corresponding serial output stream groups. figure 3 illustrates the effect of the o sba settings on the output timing. there are limitations when the zl50074 is programmed to use cki 2 - 0 as the output stream clock source: ? if the selected reference clock frequency is 65 mhz or 32 mhz, the granularity of the advancement is reduced to 1/2 the clock period. ? if the selected reference clock frequency is 16 mhz or 8 mhz, bit advancement is not available and the output streams are driven at the nominal times. 6.0 message mode in message mode (msg), microprocessor data can be br oadcast to the output data streams on a per-channel basis. this feature is useful for trans ferring control and status information to external circuits or other tdm devices. for a given output channel, when the corresponding per chann el function (bits 31 - 29) in the connection memory are set to message mode (010), the connection memory?s lowe st data byte (bits 7 - 0) is output in the timeslot. refer to section 12.1.1, connection memory bit functions, for programming details. nominal 32/65 mhz clock 7.6 ns (~3.8 ns at 65 mbps) 15.2 ns (~7.6 ns at 65 mbps) 22.8 ns (~11.4 ns at 65 mbps) nominal output bit timing level 1 advance level 2 advance level 3 advance osba = 00 osba = 01 osba = 10 osba = 11 nominal 16 mhz clock nominal 8 mhz clock
zl50074 data sheet 19 zarlink semiconductor inc. to increase programming bandwidth, the zl50074 has sepa rate addressable 32 bit memory locations, called connection memory least significant bytes (lsb), which pr ovide direct access to the connection memories? lowest data bytes (bits 7 - 0). up to four consecutive message mode channels can be set with one connection memory lsb access. refer to section 12.1.2, connection memory lsb, for programming details. 6.1 data memory read all tdm input channels can be read via the microprocessor port. this feature is useful for receiving control and status information from external circ uits or other tdm devices. each 32 bit data memory access enables up to four consecutive input channels to be monitored. the data me mory field is read only; any attempt to write to this address range will result in a bus error condition signa lled back to the host processor. refer to section 12.2, data memory, for programming details. the latency of data reads is up to 3 frames, depending on when the input timeslots are sampled. 6.2 connection memory block programming see section 12.6, block init register, and section 12.7 , block init enable register, for programming details. this feature allows for fast initialization of the connection memory after power up. when the block programming mode is enabled, the contents of bloc k init register are written to all connection memory bits. this operation completes in one 125 s frame. during connection memory initializat ion, all tdm output streams are set to high impedance. 7.0 data delay through the switching paths see section 12.1.1, connection memory bit functions, for programming details. the switching of information from the i nput serial streams to the output seri al streams results in a throughput delay. the device can be programmed to perform timeslot in terchange functions with different throughput delay capabilities on a per-channel basis. for voice applications , select variable throughput delay to ensure minimum delay between input and output data. in wideband data applic ation, select constant del ay to maintain the frame integrity of the information through the switch. the delay through the device varies according to the type of throughput delay selected by programmi ng the per channel function (bits 31 - 29) in the connection memories. when these bits are set to 011, the channel is in variabl e delay mode. when they are set to 100, the channel is in constant delay mode. 7.1 constant delay mode in this mode the frame integrity is maintained in all sw itching configurations. the delay though the switch is 2 frames - input channel + output channel. this can result in a minimum delay of 1 frame + 1 channel if the last channel of a stream is switched to the first channel of a stream. the maximum delay is 1 channel short of 3 frames delay. this occurs when the first channel of a stream is switched to the last channel of a stream. the data throughput delay is expressed as a function of st-bus/gci-bus frames, input channel number (n) and output channel number (m). the data throughput delay (t) is: t = 2 frames + (n - m)
zl50074 data sheet 20 zarlink semiconductor inc. figure 4 - data throughput delay for constant delay 7.2 variable delay mode variable delay mode causes the output channel to be transmi tted as soon as possible. this is a useful mode for voice applications where the minimum throughput delay is mo re important than data integrity. the delay through the switch is minimum 3 channels and maximum 1 frame + 2 channels. figure 5 - data throughput delay for variable delay n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n = last channel n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 n-2 n-1 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch4 ch5 ch6 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9 ch7 ch8 ch9
zl50074 data sheet 21 zarlink semiconductor inc. 8.0 microprocessor port the zl50074 has a generic microprocessor port that provides access to the internal data memory (read access only), connection memory and control registers. the port size can be configured to be either 32 bit or 16 bit, controlled by the d16b pin. the port works with either moto rola or intel type microprocessor buses, selected by the im pin. 8.1 addressing the data memory, connection memory and control regi sters are assigned 32 bit fields in the zl50074 memory space. the address bus, a18 - 0, controls access to eac h 32 bit location. byte addressing is also provided to give the user programming flexibility, if a ccess to less than 32 bits is required. each 32 bit memory or register location sp ans four consecutive addresses. example: ? the 32 bit group control register for tdm group 0 is located at address range 40200 - 40203 hex the least significant address i dentifies the most significant byte (msb) in the 32 bit field, as illustrated in table 4. 8.2 32 bit bus operation in 32 bit mode (d16b = 0), all 32 bits of the data bus, d31 - 0, may be used for write and read transfers. d31 on the bus maps to bit 31 of the internal memory or register, d30 maps to bit 30, etc. the leas t significant address bits, a1 - 0, and the data transfer size inputs, siz0 - 1, identify which bytes are being accessed. in motorola bus mode (im = 0), a1 - 0 identify the first byte in the 32 bit field to be transferred, as shown in table 5. the siz0 - 1 inputs indicate the access transfer size, as shown in table 6. address (hex) memory/register bits 40200 bits 31:24 (msb) 40201 bits 23:16 40202 bits 15:8 40203 bits 7:0 (lsb) table 4 - example of address and byte significance a1 a0 byte addressed 0 0 bit 31:24 0 1 bit 23:16 1 0 bit 15:8 11 bit 7:0 table 5 - 32 bit motorola mode byte addressing
zl50074 data sheet 22 zarlink semiconductor inc. for example, to transfer all 32 bits in a single access: a1 = 0. a0 = 0, siz1 = 0, siz0 = 0. to transfer d15 - 8 only: a1 = 1, a0 = 0, siz1 = 0, siz0 = 1. in intel bus mode (im = 1), a1 - 0, and siz1 - 0 form ac tive low byte enable signals, consistent with be3 - 0 available on the intel i960 processor, as shown in table 7. byte addressing applies only to write accesses. on read cycles, all 32 bits are output on every access. siz1 siz0 access transfer size 0 0 4 bytes 01 1 byte 10 2 bytes 11 3 bytes table 6 - 32 bit motorola mode access transfer size pin equivalent i960 signal byte addressed a1 be 3 bit 31:24 a0 be 2 bit 23:16 siz1 be 1 bit 15:8 siz0 be 0bit 7:0 table 7 - 32 bit intel mo de bus enable signals
zl50074 data sheet 23 zarlink semiconductor inc. 8.3 16 bit bus operation in 16 bit mode (d16b = 1), d15 - 0 are used for data tran sfers to/from the zl50074. d31 - 16 are unused and must be connected to a defined logic level. d15 on the bus maps to bit 31 and bit 15 of the internal 32 bit memory or register, d14 maps to bit 30 and bit 14, etc. in 16 bit mode, the least significant address bit, a0, is not used, and must be connected to defined logic level. in this case, address bit a1 and the data transfer size inputs, siz1 - 0, identify which bytes are being accessed. in motorola bus mode (im = 0), siz1 - 0 form ac tive low data strobe signals, consistent with uds and lds available on the mc68000 and mc68302 processors, as shown in table 8. in intel bus mode (im = 1), siz1 - 0 form active low byte enable signals, consistent with be1 and be0 available on the intel i960 processor, as shown in table 8. in both intel and motorola modes, the a1 address input is us ed to identify the word alignment in internal memory. 16-bit word alignment are shown in table 9. an example of byte addressing is given in table 10. pin name motorola mode mc68000, mc68302 equivalent function im = 0 intel mode i960 equivalent function im = 1 data bus bytes enabled siz1 uds be1 d15-8 siz0 lds be0 d7-0 table 8 - byte enable signals a1 = 0 bits 31:16 a1 = 1 bits 15:0 microprocessor 16 bit data bus siz1 siz0 a1 internal 32-bit memory or register d15 - 8 0 1 0 bits 31:24 011 bits 15:8 d7 - 0 1 0 0 bits 23:16 101 bits 7:0 d15 - 0 0 0 0 bits 31:16 001 bits 15:0 11x 1 1. x - don?t care no access table 9 - 16 bit mode word alignment
zl50074 data sheet 24 zarlink semiconductor inc. ? don?t care. a0 is not used 8.4 bus operation 8.4.1 read cycle the operation of a read cycle is illustrated in figure 6. ? the microprocessor asserts the r/w control signal high, to signal a read cycle. it also drives the address a, transfer size, siz1 - 0, and chip select logic drives the cs signal active low to select the zl50074. ? the microprocessor then drives the ds signal active low, to signal the start of the bus cycle. the ds signal is held low for the duration of the bus cycle. ?wait is asserted active low ? the zl50074 accesses the requested memory or register location(s), and places the requested data onto the data bus, d31 - 0 (d15 - 0 in 16 bit mode). all dat a bus pins are driven, whether or not they are being used for the specific data transfer. unused pins will present unknown data. if the address is to an unused area of the memory space, unknown data is presented on the data bus. ? the zl50074 then de-asserts wait , and asserts either dta or berr , depending on the validity of the data transfer ? when the microprocessor observes the active low state of the dta or the berr signal or the low to high transition of the wait signal, it terminates the bus cycle by driving the ds pin inactive high ? when the zl50074 sees the ds signal go inactive high, it removes the assertions on the dta or berr signals by driving them inactive high ? when the zl50074 sees the cs signal go inactive high, it tri-states the data bus, d31 - 0 (d15 - 0 in 16 bit mode) and the dta , b err and wait signals. however, if cs goes inactive high before ds goes inactive high, the dta , berr and wait signals are driven inactive hi gh before they are tri-stated. ? in intel mode, dta is always driven to signal the end of a bus cycle, regardless of berr address (hex) register description register byte a18 - 0 (binary) siz1 siz0 comments 40200 or 40201 group control register (group 0) bits 23:16 100 0000 0010 0000 000x ? 1 0 8 bit transfer 40282 or 40283 input clock control register bits 15:8 100 0000 0010 1000 001x ? 0 1 8 bit transfer 40286 or 40287 output clock control register bits 15:0 100 0000 0010 1000 011x ? 0 0 16 bit transfer 40284 or 40285 output clock control register bits 31:16 100 0000 0010 1000 010x ? 0 0 16 bit transfer table 10 - 16 bit mode example byte address
zl50074 data sheet 25 zarlink semiconductor inc. figure 6 - read cycle operation 8.4.2 write cycle the operation of the write cycle is illustrated in figure 7. ? the microprocessor asserts the r/w control signal low, to signal a write cycle. it also drives the address a, data transfer size, siz1 - 0, and chip select logic drives the cs signal active low to select the zl50074 ? the microprocessor then drives the data bus, d31 - 0 (d 15 - 0 in 16 bit mode) with the data to be written, and then drives the ds signal active low, to signal the start of the bus cycle. the ds signal is held low for the duration of the bus cycle ?wait is asserted active low ? the zl50074 transfers the data presented on the data bus pins into the indicated memory or register location(s). if the address is to an unused area of the memory space, or to the data memory, no data is transferred. the microprocessor port cannot write to the data memory. ? the zl50074 then de-asserts wait , and asserts either dta or berr , depending on the validity of the data transfer ? when the microprocessor observes the active low state of the dta or the berr signal or the low-to-high transition of the wait signal, it terminates the bus cycle by driving the ds pin inactive high ? when the zl50074 sees the ds signal go inactive high, it removes the assertions on the dta or berr signals by driving them inactive high ? when the zl50074 sees the cs signal go inactive high, it tri-states the dta , b err and wait signals. however, if cs goes inactive high before ds goes inactive high, the dta , berr and wait signals are driven inactive high before they are tri-stated. ? in intel mode, dta is always driven to signal the end of a bus cycle, regardless of berr address a, siz1 - 0 r/w ds data cs dta berr hi-z hi-z wait the cycle termination signals wait & dta are provided for all bus configurations. hi-z hi-z
zl50074 data sheet 26 zarlink semiconductor inc. figure 7 - write cycle operation 9.0 power-up and initialization of the zl50074 9.1 device reset and initialization the pwr pin is used to reset the zl50074. when this pin is low, the following functions are performed: ? asynchronously puts the microprocessor port in a reset state ? tristates all of the output streams (stoa0 - 31, stob0 - 31, stoc0 - 31, stod0 - 31) ? preloads all of the registers with their default values (refer to the individual registers for default values) ? clears all internal counters 9.2 power supply sequencing the zl50074 has two separate power supplies: v dd_io (3.3 v) and v dd_core (1.8 v). the recommended power-up sequence is for v dd_io to be applied first, followed by the v dd_core supply. v dd_core should not lead v dd_io supply by more than 0.3 v. both supplies may be powered-down simultaneously. 9.3 initialization upon power up, the zl50074 should be initialized as follows: ?assert pwr to low immediately after power is applied ? set the trst pin low to disable the jtag tap controller ? deassert the pwr pin. ? apply the master clock input (cki 0) and master frame pulse input (fpi 0) to the values defined by the ck_sel1 - 0 pins ? set the ode pin low to disable the output streams hi-z address siz1 - 0 r/w ds data cs dta berr wait the cycle termination signals wait & dta are provided for all bus configurations. hi-z hi-z
zl50074 data sheet 27 zarlink semiconductor inc. note: after the pwr reset is removed, and on the application of a suitable master clock input, it takes approximately 1ms for the internal initialization to complete ? automatic block initialization of the connection memory to all zeros occurs, without microprocessor intervention ? all group control registers are preset to 000c000c h , corresponding to no link inversions, no fractional output bit advancements, internal clock source, and no input sample point delays ? the input clock control register is preset to 0db h , corresponding to: - all clock inputs set to negative logic sense - all frame pulse inputs set to negative logic sense - all input frame pulses set to st-bus timing ? the output clock control register is pre-set to 060d1c3c h , corresponding to: - all clock outputs set to negative logic sense - all frame pulse outputs set to negative logic sense - all output frame pulses set to st-bus timing - all output clock source selections to internal - clock outputs, cko 0 - 3 are preset to rates of 65 mhz, 32 mhz, 16 mhz and 8 mhz, respectively ? global rate control register is set to 00, corresponding to a bit rate of 8 mbps note : if the master clock input, cki 0, is not available, the micr oprocessor port will assert berr on all accesses and read cycles. 10.0 ieee 1149.1 test access port the jtag test port is implemented to meet the mandator y requirements of the ieee 1 149.1 (jtag) standard. the operation of the boundary-scan circuity is controlled by an external test access port (tap) controller. the zl50074 uses the public instructions defined in ieee 1149.1, with the provis ion of a 16-bit inst ruction register, and three scannable test data regist ers: boundary scan register, bypass register and device identification register. 10.1 test access port (tap) the test access port (tap) accesses the zl50074 test functions. the interface consists of 4 input and 1 output signal. as follows: ? test clock (tck) - tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remains independent in the functional mode. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. ? test mode select (tms) - the tap controller uses the logic signals received at the tms input to control test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to v dd_io when it is not driven from an external source. ? test data input (tdi) - serial input data applied to this port is fed ei ther into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to v dd_io when it is not driven from an external source.
zl50074 data sheet 28 zarlink semiconductor inc. ? test data output (tdo) - depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are se rially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) - resets the jtag scan structure. this pin is internally pulled to v dd_io when it is not driven from an external source. when jtag is not in use, this pin must be tied low for normal operation. the tap signals are only applied when the zl50074 is requi red to be in test mode. when in normal, non-test mode, trst must be connected low to disable the test logic. the remaining test pins may be left unconnected. 10.2 instruction register the zl50074 uses the public instructi ons defined in the ieee 1149.1 standar d. the jtag interface contains a 16-bit instruction regist er. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-or state. these instructions are subsequently decoded to achieve two basic functions: to select the test data register that may operate while the in struction is current and to define the serial test data register path that is used to shift data between tdi and tdo during register scanning. 10.3 test data register as specified in the ieee 1149.1 standard, the zl50074 jtag interf ace contains three test data registers: ? the boundary-scan register - the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the zl50074 core logic ? the bypass register - the bypass register is a single stage shift register that provides a one-bit path from tdi to tdo ?t he device identification register - the jtag device id for the zl50074 is c39a14b h 10.4 boundary scan de scription language (bsdl) a boundary scan description language (bsdl) file is availabl e from zarlink semiconductor to aid in the use of the ieee 1149.1 test interface. version <31:28> 0000 part number <27:12> 1100 0011 1001 1010 manufacturer id <11:1> 0001 0100 101 lsb <0> 1
zl50074 data sheet 29 zarlink semiconductor inc. 11.0 memory map of zl50074 the memory map for the zl50074 is given in table 11. 12.0 detailed memory and register descriptions this section describes all the memories and registers that are used in this device. 12.1 connection memory address range 00000 - 1ffff hex. on power-up, all connection memory locati ons are initialized automatically to 00000000 h , using the block initialization feature, as descri bed in section 12.6 and section 12.7. the 32 bit connection memory has 32,768 locations. each 32 bit long-word is used to program the desired source data and any other per-channel characte ristics of one output time-slot. the memory map for the connection memory is sub-divi ded into 32 blocks, each corresponding to one of the possible 32 output st ream group numbers . the address ranges for these bl ocks are illustrated in table 12. address (hex) description 00000 - 1ffff connection memory 20000 - 27fff connection memory lsb 28000 - 2ffff data memory: read only; bus error on write (berr) 30000 - 401ff invalid address. access causes bus error (berr) 40200 - 4027f group control registers 40280 - 40283 input clock control register 40284 - 40287 output clock control register 40288 - 4028b block init register 4028c - 4028f block init enable 40290 - 40293 global rate control register 40294 - 7ffff invalid address. access causes bus error (berr) table 11 - memory map
zl50074 data sheet 30 zarlink semiconductor inc. the mapping of each output stream, stoa n , stob n , stoc n and stod n , depends on the programmed bit rate in the global rate control register. the address offset range fo r each stream is illu strated in table 13. output group start address (hex) address range (hex) output group start address (hex) address range (hex) 0 000000 000000 - 000fff 16 010000 010000 - 010fff 1 001000 001000 - 001fff 17 011000 011000 - 011fff 2 002000 002000 - 002fff 18 012000 012000 - 012fff 3 003000 003000 - 003fff 19 013000 013000 - 013fff 4 004000 004000 - 004fff 20 014000 014000 - 014fff 5 005000 005000 - 005fff 21 015000 015000 - 015fff 6 006000 006000 - 006fff 22 016000 016000 - 016fff 7 007000 007000 - 007fff 23 017000 017000 - 017fff 8 008000 008000 - 008fff 24 018000 018000 - 018fff 9 009000 009000 - 009fff 25 019000 019000 - 019fff 10 00a000 00a000 - 00afff 26 01a000 01a000 - 01afff 11 00b000 00b000 - 00bfff 27 01b000 01b000 - 01bfff 12 00c000 00c000 - 00cfff 28 01c000 01c000 - 01cfff 13 00d000 00d000 - 00dfff 29 01d000 01d000 - 01dfff 14 00e000 00e000 - 00efff 30 01e000 01e000 - 01efff 15 00f000 00f000 - 00ffff 31 01f000 01f000 - 01ffff table 12 - connection memory group address mapping device data rate timeslot range output stream stream address offset range (hex) 65 mbps 0 - 1023 stoa n 00000 - 00fff stob n, c n, d n n/a 32 mbps 0 - 511 stoa n 00000 - 007ff stob n 00800 - 00fff stoc n, d n n/a 16 mbps 0 - 255 stoa n 00000 - 003ff stob n 00400 - 007ff stoc n 00800 - 00bff stod n 00c00 - 00fff 8 mbps 0 - 127 stoa n 00000 - 001ff stob n 00200 - 003ff stoc n 00400 - 005ff stod n 00600 - 007ff n/a berr 00800 - 00fff table 13 - connection memory stream address offset at various output rates
zl50074 data sheet 31 zarlink semiconductor inc. the address range for a particular stream is given by a dding the group start address, as indicated in table 12, to the appropriate stream offset range, as indicated in table 13. for exampl e, the connection memory address range for stob12 operating at 32 mbps is 00c800-00cfff; the connection memory addres s range for stoc4 operating at 8 mbps is 004400-0045ff. each output channel timeslot occupies a range of 4 addr esses in the connection memories. the timeslot address offset is illustrated in table 14. it shows the maximum nu mber of timeslots that a st ream can have, but the actual number of timeslots available depends on the output data rates, as illustrated in table 1 and table 13. timeslot address offset hex stoa n stob n stoc n stod n 0000 000 1111 004 2222 008 ---- - 126 126 126 126 1f8 127 127 127 127 1fc 128 128 128 128 200 129 129 129 129 204 ---- - 254 254 254 254 3f8 255 255 255 255 3fc 256 256 400 257 257 404 -- - -- 510 510 7f8 511 511 7fc 512 800 513 804 - - 1021 ff4 1022 ff8 1023 ffc table 14 - connection memory timeslot address offset range
zl50074 data sheet 32 zarlink semiconductor inc. 12.1.1 connecti on memory bit functions the bit functions of the connection me mory are illustrated in table 15. bit name description 31 - 29 pcf2 - 0 per channel function 28 - 15 unused reserved. in normal functional mode, these bits must be set to zero. 14 - 10 gp4 - 0 source group selection. these bits define the input/ source group number (31 - 0). 9 - 0 stch 9 - 0 source stream and channel selection / message mode data in connection mode (constant/variable delay), these bits define the input/source stream and channel number, depending on the data rate. for 65.536 mbps, bits 9 - 0 select the input channel (0 - 1023). for 32.768 mbps, bits 9 - 1 select the input channel (0 - 511). bit 0 selects stream stia (0) or stib (1) for 16.869 mbps, bits 9 - 2 select the input channel (0 - 255). bits 1 - 0 select stream stia (00), stib (01), stic (10), or stid (11) for 8.192 mbps, bits 9 - 3 select the input channel (0 - 127). bit 2 must be set to 0. bits 1 - 0 select stream stia (00), stib (01), stic (10), or stid (11). in message mode, bits 7 - 0 define the output data. the data is output sequentially with bit 7 being output first. bits 9 - 8 are not used. table 15 - connection memory bits (cmb) external read/write address: 000000 h reset value: 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 pcf 2 pcf 1 pcf 0 00000 00000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0gp 4 gp 3 gp 2 gp 1 gp 0 stch 9 stch 8 stch 7 stch 6 stch 5 stch 4 stch 3 stch 2 stch 1 stch 0 pcf2 - 0 function description 000 ot output is tri-stated 001 fh output drives high always 010 msg output is in message mode 011 var variable delay connection mode 100 cd constant delay connection mode 101 reserved reserved. do not use. 110 ot output is tri-stated 111 ot output is tri-stated
zl50074 data sheet 33 zarlink semiconductor inc. 12.1.2 connection memory lsb the connection memory least significant byte field is prov ided to give a convenient alternative way to modify the output data for a stream in message mode. in this memory address range, all of the connection memory least significant bytes (bits 7 - 0) are availabl e for read/write in consecutive address lo cations. this featur e is provided for programming convenience. it can al low higher programming bandwidth on me ssage mode streams. for example, one longword access to this memory space can read or set the message bytes in four consecutive connection memory locations. access to this memory space is big- endian, with the most significant bytes on the data bus accessing the lower address of the connection memory. for ex ample, for 32-bit data bus, to access the connection memory lsb associated with channels 3 - 0 on a particular stream, the data bu s d31 - 24 carry data for channel 0, d23 - 16 carry data for channel 1, d15 - 8 carry data for channel 2, and d7 - 0 carry data for channel 3. addressing into each of the streams is illustrated in table 16. output group start address (hex) address range (hex) output group start address (hex) address range (hex) 0 020000 020000 - 0203ff 16 024000 024000 - 0243ff 1 020400 020400 - 0207ff 17 024400 024400 - 0247ff 2 020800 020800 - 020bff 18 024800 024800 - 024bff 3 020c00 020c00 - 020fff 19 024c00 024c00 - 024fff 4 021000 021000 - 0213ff 20 025000 025000 - 0253ff 5 021400 021400 - 0217ff 21 025400 025400 - 0257ff 6 021800 021800 - 021bff 22 025800 025800 - 025bff 7 021c00 021c00 - 021fff 23 025c00 025c00 - 025fff 8 022000 022000 - 0223ff 24 026000 026000 - 0263ff 9 022400 022400 - 0227ff 25 026400 026400 - 0267ff 10 022800 022800 - 022bff 26 026800 026800 - 026bff 11 022c00 022c00 - 022fff 27 026c00 026c00 - 026fff 12 023000 023000 - 0233ff 28 027000 027000 - 0273ff 13 023400 023400 - 0237ff 29 027400 027400 - 0277ff 14 023800 023800 - 023bff 30 027800 027800 - 027bff 15 023c00 023c00 - 023fff 31 027c00 027c00 - 027fff table 16 - connection memory lsb group address mapping
zl50074 data sheet 34 zarlink semiconductor inc. within each stream group, the mapping of each of the actual output streams, stoa n , stob n , stoc n and stod n , depends on the device data rate programmed into the global rate control register. the address offsets to these control areas for each of the output streams are illustrated in table 17. 12.2 data memory the data memory field is a read only address range used to monitor the data being received by the input streams. addressing into each of the streams is illustrated in table 18. device data rate timeslot range output stream stream address offset range (hex) 65 mbps 0 - 1023 stoa n 00000 - 003ff stob n, c n, d n n/a 32 mbps 0 - 511 stoa n 00000 - 001ff stob n 00200 - 003ff stoc n, d n n/a 16 mbps 0 - 255 stoa n 00000 - 000ff stob n 00100 - 001ff stoc n 00200 - 002ff stod n 00300 - 003ff 8 mbps 0 - 127 stoa n 00000 - 0007f stob n 00080 - 000ff stoc n 00100 - 0017f stod n 00180 - 001ff n/a berr 00200 - 003ff table 17 - connection memory lsb stream address offset at various output rates input group start address (hex) address range (hex) input group start address (hex) address range (hex) 0 028000 028000 - 0283ff 16 02c000 02c000 - 02c3ff 1 028400 028400 - 0287ff 17 02c400 02c400 - 02c7ff 2 028800 028800 - 028bff 18 02c800 02c800 - 02cbff 3 028c00 028c00 - 028fff 19 02cc00 02cc00 - 02cfff 4 029000 029000 - 0293ff 20 02d000 02d000 - 02d3ff 5 029400 029400 - 0297ff 21 02d400 02d400 - 02d7ff 6 029800 029800 - 029bff 22 02d800 02d800 - 02dbff 7 029c00 029c00 - 029fff 23 02dc00 02dc00 - 02dfff 8 02a000 02a000 - 02a3ff 24 02e000 02e000 - 02e3ff 9 02a400 02a400 - 02a7ff 25 02e400 02e400 - 02e7ff 10 02a800 02a800 - 02abff 26 02e800 02e800 - 02ebff 11 02ac00 02ac00 - 02afff 27 02ec00 02ec00 - 02efff table 18 - data memory group address mapping
zl50074 data sheet 35 zarlink semiconductor inc. within each stream group, the mapping of each of the actual input streams, stia n , stib n , stic n and stid n , depends on the device data rate programmed into the global rate control register. the address offsets to these data areas for each of the input streams are illustrated in table 19. the address ranges for the data memory portion corr esponding to each of the actual input streams, stia n , stib n , stic n and stid n , for any particular input group number is calcul ated by adding the start address for the particular group, as indicated in table 18, to t he appropriate address offset range, as indicated in table 19. the time-slots map linearly into the appropriate address offset range. (i.e., timeslots 0, 1, 2, ... map into addresses 00000, 00001, 00002, ...) the entire data memory is a read only structure. any write attempts will result in a bus error. berr is driven active low to terminate the bus cycle. 12 02b000 02b000 - 02b3ff 28 02f000 02f000 - 02f3ff 13 02b400 02b400 - 02b7ff 29 02f400 02f400 - 02f7ff 14 02b800 02b800 - 02bbff 30 02f800 02f800 - 02fbff 15 02bc00 02bc00 - 02bfff 31 02fc00 02fc00 - 02ffff device data rate time-slot range output streams address offset range (hex) 65 mbps 0 - 1023 stia n 00000 - 003ff stib n, c n, d n n/a 32 mbps 0 - 511 stia n 00000 - 001ff stib n 00200 - 003ff stic n, d n n/a 16 mbps 0 - 255 stia n 00000 - 000ff stib n 00100 - 001ff stic n 00200 - 002ff stid n 00300 - 003ff 8 mbps 0 - 127 stia n 00000 - 0007f stib n 00080 - 000ff stic n 00100 - 0017f stid n 00180 - 001ff n/a berr 00200 - 003ff table 19 - data memory stream address offset at various output rates input group start address (hex) address range (hex) input group start address (hex) address range (hex) table 18 - data memory group address mapping (continued)
zl50074 data sheet 36 zarlink semiconductor inc. 12.3 group control registers the zl50074 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate of 65.536 mbps and by groupi ng the i/o streams. each tdm i/o group contains 4 input and 4 output streams. the 4 i nput streams in the same group have identical input characteristics, and similarly, the 4 output streams in the same group have identical output characteristics. howe ver, input and output streams in the same group can have different input and output operation characteristics. the group control registers ar e provided for setting the operating ch aracteristics of the tdm input and output streams. all of the group control registers are m apped long-word aligned on 32 bit boundaries in the memory space. each of the 32 registers is used to control one gr oup. the mapping of the group c ontrol registers to the i/o group numbers is illustrated in table 20. the bit functions of each of the group contro l registers are illustrated in table 21. tdm group group control register address (hex) 0 40200-40203 1 40204-40207 2 40208-4020b 3 4020c-4020f :: :: 29 40274-40277 30 40278-4027b 31 4027c-4027f table 20 - group control register addressing bit name description 31 - 23 unused reserved. in normal functional mode, these bits must be set to zero. 22 osi output stream inversion for normal operation, this bit is set low. to invert the output stream, set this bit high. table 21 - group control register external read/write address: 40200 h - 4027f h reset value: 000c000c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 0 0 0 0 0 0 0 osi osba 1 osba 0 11 ossrc 1 ossrc 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 isi ispd 4 ispd 3 ispd 2 ispd 1 ispd 0 1 1 issrc 1 issrc 0
zl50074 data sheet 37 zarlink semiconductor inc. 21 - 20 osba1 - 0 output stream bit advancement 19 - 18 unused reserved. in normal functional mode, these bits must be set to 11. 17 - 16 ossrc1 - 0 output stream clock source select 15 - 10 unused reserved. in normal functional mode, these bits must be set to zero. 9isi input stream inversion for normal operation, this bit is set low. to invert the input stream, set this bit high. 8 - 4 ispd4 - 0 input sampling point delay default sampling point is 3/4. adjust according to figure 2 on page 17. 3 - 2 unused reserved. in normal functional mode, these bits must be set to 11. bit name description table 21 - group control register (continued) external read/write address: 40200 h - 4027f h reset value: 000c000c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 0 0 0 0 0 0 0 osi osba 1 osba 0 11 ossrc 1 ossrc 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 isi ispd 4 ispd 3 ispd 2 ispd 1 ispd 0 1 1 issrc 1 issrc 0 osba1 - 0 non-65 mbps 65 mbps 00 0 ns 0 ns 01 7.6 ns 3.8 ns 10 15.2 ns 7.6 ns 11 22.8 ns 11.4 ns ossrc1 - 0 output timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 38 zarlink semiconductor inc. the group control register is a static control register. cha nges to bit settings may disr upt data flow on the selected port for a maximum of 2 frames. 1 - 0 issrc1 - 0 input stream clock source select bit name description table 21 - group control register (continued) external read/write address: 40200 h - 4027f h reset value: 000c000c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 0 0 0 0 0 0 0 osi osba 1 osba 0 11 ossrc 1 ossrc 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 isi ispd 4 ispd 3 ispd 2 ispd 1 ispd 0 1 1 issrc 1 issrc 0 issrc1 - 0 input timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 39 zarlink semiconductor inc. 12.4 input clock control register the input clock control register is used to select the logic sense of the input clock. bit name description 31 - 9 unused reserved. in normal functional mode, these bits must be set to zero. 8 gcisel2 gci-bus selection for fpi2 when this bit is low, fpi 2 is set for st-bus mode. when this bit is high, fpi 2 is set for gci-bus mode. 7 fpipol2 frame pulse polarity selection for fpi2 when this bit is low, fpi 2 is set for active high. when this bit is high, fpi 2 is set for active low. 6ckipol2 clock polarity selection for cki2 when this bit is low, cki 2 is set for the positive clock edge. when this bit is high, cki 2 is set for the negative clock edge. 5 gcisel1 gci-bus selection for fpi1 when this bit is low, fpi 1 is set for st-bus mode. when this bit is high, fpi 1 is set for gci-bus mode. 4 fpipol1 frame pulse polarity selection for fpi1 when this bit is low, fpi 1 is set for active high. when this bit is high, fpi 1 is set for active low. 3ckipol1 clock polarity selection for cki1 when this bit is low, cki 1 is set for the positive clock edge. when this bit is high, cki 1 is set for the negative clock edge. 2 gcisel0 gci-bus selection for fpi0 when this bit is low, fpi 0 is set for st-bus mode. when this bit is high, fpi 0 is set for gci-bus mode. 1 fpipol0 frame pulse polarity selection for fpi0 when this bit is low, fpi 0 is set for active high. when this bit is high, fpi 0 is set for active low. 0ckipol0 clock polarity selection for cki0 when this bit is low, cki 0 is set for the positive clock edge. when this bit is high, cki 0 is set for the negative clock edge. table 22 - input clock control register external read/write address: 40280 h reset value: 0db h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 0 0000 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 0000gci sel2 fpi pol2 cki pol2 gci sel1 fpi pol1 cki pol1 gci sel0 fpi pol0 cki pol0
zl50074 data sheet 40 zarlink semiconductor inc. 12.5 output clock control register the output clock control register is used to select the desired source, frequency, and logic sense of the output clocks. the bit functions of t he output clock control register are illustrated in table 23. bit name description 31 - 28 unused reserved. in normal functional mode, these bits must be set to zero. 27 gco sel3 gci-bus selection for fpo3 when this bit is low, fpo 3 is set for st-bus mode. when this bit is high, fpo 3 is set for gci-bus mode. 26 fpo pol3 frame pulse polarity selection for fpo3 when this bit is low, fpo 3 is set for active high. when this bit is high, fpo 3 is set for active low. 25 cko pol3 clock polarity selection for cko3 when this bit is low, cko 3 is set for the positive clock edge. when this bit is high, cko 3 is set for the negative clock edge. 24 - 23 cko3 rate 1 - 0 output clock rate for cko 3 and fpo 3 the output clock rate can not exceed the selected clock source rate. all rates are avail- able when the internal system cl ock is selected as clock source. 22 - 21 cko3 src 1 - 0 output clock source for cko 3 and fpo 3 table 23 - output clock control register external read/write address: 40284 h reset value: 060d1c3c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 00 gco sel3 fpo pol3 cko pol3 cko3 rate1 cko3 rate0 cko3 src1 cko3 src0 gco sel2 fpo pol2 cko pol2 cko2 rate1 cko2 rate0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cko2 src1 cko2 src0 gco sel1 fpo pol1 cko pol1 cko1 rate1 cko1 rate0 cko1 src1 cko1 src0 gco sel0 fpo pol0 cko pol0 cko0 rate1 cko0 rate0 cko0 src1 cko0 src0 cko3rate1 - 0 cko 3fpo 3 00 8.192 mhz 120 ns 01 16.384 mhz 60 ns 10 32.768 mhz 30 ns 11 65.536 mhz 15 ns cko3src1 - 0 output timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 41 zarlink semiconductor inc. 20 gco sel2 gci-bus selection for fpo2 when this bit is low, fpo 2 is set for st-bus mode. when this bit is high, fpo 2 is set for gci-bus mode. 19 fpo pol2 frame pulse polarity selection for fpo2 when this bit is low, fpo 2 is set for active high. when this bit is high, fpo 2 is set for active low. 18 cko pol2 clock polarity selection for cko2 when this bit is low, cko 2 is set for the positive clock edge. when this bit is high, cko 2 is set for the negative clock edge. 17 - 16 cko2 rate 1 - 0 output clock rate for cko 2 and fpo 2 the output clock rate can not exceed the selected clock source rate. all rates are avail- able when the internal system cl ock is selected as clock source . 15 - 14 cko2 src 1 - 0 output clock source for cko 2 and fpo 2 13 gco sel1 gci-bus selection for fpo1 when this bit is low, fpo 1 is set for st-bus mode. when this bit is high, fpo 1 is set for gci-bus mode. bit name description table 23 - output clock control register (continued) external read/write address: 40284 h reset value: 060d1c3c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 00 gco sel3 fpo pol3 cko pol3 cko3 rate1 cko3 rate0 cko3 src1 cko3 src0 gco sel2 fpo pol2 cko pol2 cko2 rate1 cko2 rate0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cko2 src1 cko2 src0 gco sel1 fpo pol1 cko pol1 cko1 rate1 cko1 rate0 cko1 src1 cko1 src0 gco sel0 fpo pol0 cko pol0 cko0 rate1 cko0 rate0 cko0 src1 cko0 src0 cko2rate1 - 0 cko 2fpo 2 00 8.192 mhz 120 ns 01 16.384 mhz 60 ns 10 32.768 mhz 30 ns 11 65.536 mhz 15 ns cko2src1 - 0 output timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 42 zarlink semiconductor inc. 12 fpo pol1 frame pulse polarity selection for fpo1 when this bit is low, fpo 1 is set for active high. when this bit is high, fpo 1 is set for active low. 11 cko pol1 clock polarity selection for cko1 when this bit is low, cko 1 is set for the positive clock edge. when this bit is high, cko 1 is set for the negative clock edge. 10 - 9 cko1 rate 1 - 0 output clock rate for cko 1 and fpo 1 the output clock rate can not exceed the selected clock source rate. all rates are avail- able when the internal system cl ock is selected as clock source . 8 - 7 cko1 src 1 - 0 output clock source for cko 1 and fpo 1 6gco sel0 gci-bus selection for fpo0 when this bit is low, fpo 0 is set for st-bus mode. when this bit is high, fpo 0 is set for gci-bus mode. 5fpo pol0 frame pulse polarity selection for fpo0 when this bit is low, fpo 0 is set for active high. when this bit is high, fpo 0 is set for active low. bit name description table 23 - output clock control register (continued) external read/write address: 40284 h reset value: 060d1c3c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 00 gco sel3 fpo pol3 cko pol3 cko3 rate1 cko3 rate0 cko3 src1 cko3 src0 gco sel2 fpo pol2 cko pol2 cko2 rate1 cko2 rate0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cko2 src1 cko2 src0 gco sel1 fpo pol1 cko pol1 cko1 rate1 cko1 rate0 cko1 src1 cko1 src0 gco sel0 fpo pol0 cko pol0 cko0 rate1 cko0 rate0 cko0 src1 cko0 src0 cko1rate1 - 0 cko 1fpo 1 00 8.192 mhz 120 ns 01 16.384 mhz 60 ns 10 32.768 mhz 30 ns 11 65.536 mhz 15 ns cko1src1 - 0 output timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 43 zarlink semiconductor inc. 4cko pol0 clock polarity selection for cko0 when this bit is low, cko 0 is set for the positive clock edge. when this bit is high, cko 0 is set for the negative clock edge. 3 - 2 cko0 rate 1 - 0 output clock rate for cko 0 and fpo 0 the output clock rate can not exceed the selected clock source rate. all rates are avail- able when the internal system cl ock is selected as clock source. 1 - 0 cko0 src 1 - 0 output clock source for cko 0 and fpo 0 bit name description table 23 - output clock control register (continued) external read/write address: 40284 h reset value: 060d1c3c h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 00 gco sel3 fpo pol3 cko pol3 cko3 rate1 cko3 rate0 cko3 src1 cko3 src0 gco sel2 fpo pol2 cko pol2 cko2 rate1 cko2 rate0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cko2 src1 cko2 src0 gco sel1 fpo pol1 cko pol1 cko1 rate1 cko1 rate0 cko1 src1 cko1 src0 gco sel0 fpo pol0 cko pol0 cko0 rate1 cko0 rate0 cko0 src1 cko0 src0 cko0rate1 - 0 cko 0fpo 0 00 8.192 mhz 120 ns 01 16.384 mhz 60 ns 10 32.768 mhz 30 ns 11 65.536 mhz 15 ns cko0src1 - 0 output timing source 00 internal system clock 01 cki 0 and fpi 0 10 cki 1 and fpi 1 11 cki 2 and fpi 2
zl50074 data sheet 44 zarlink semiconductor inc. 12.6 block init register the block init register is a 32 bit r ead/write register at address 040288 - 04028b h . the block init register is used during block initializ ation of the connection memory. a block initialization automatically occurs at power-up. however, it is possible to perform a block initialization at any time. during block initialization, the value of the block init register is copied to all connecti on memory locations in an operation that runs in about 120 s. if the block init register is modified duri ng a block initialization, the new value used is ignored. 12.7 block init enable register the block init enable register is a 32 bit read/write register at address 04028c - 04028f h . the block init enable register is used to initiate a block initialization of the connection memory. a block initialization automatically occurs at power-up. sinc e the block init register is cleared at power-up this automatic block initialization will write all zeros to all connection memory bi ts. however, it is possible to perform a block initialization at any time. to begin a block initialization, the hex value 31415926 must be written to t he block init enable register. if a block initialization is signaled while one is in progr ess, the signal is ignored, and the currently active block initialization is a llowed to complete. the value read back from the block init enable register is different from the value writ ten. it represents both the block initialization status, and the power- up reset initialization status. the meaning of the initialization status bits is illustrated in table 24. the bits 31 - 2 always read back 0. any access to the connection memory or the data memory du ring a block initialization or a reset initialization will result in a bus error, berr . all tdm outputs are tri-stated dur ing any block initialization. bit name description 0 block init status 0 if block initialization is completed; 1 if block initializat ion is in progress. 1 reset init status 0 if reset initialization is completed; 1 if reset initialization is in progress. table 24 - block and power-up initialization status bits
zl50074 data sheet 45 zarlink semiconductor inc. 12.8 global rate control register the global rate control register is us ed to select the data rate of all t he input and output st reams. on power-up, the gbr bits are both reset to 0, corresponding to a rate of 8.192 mbps. bit name description 31 - 2 unused reserved. in normal functional mode, these bits must be set to zero. 1 - 0 gbr1 - 0 global bit rate selection each input and output group can individually se lect different clock sources. if the internal system clock is used as the clock source, al l the above data rates are available. other- wise, the data rate cannot exceed the selected clock source?s rate. external read/write address: 040290 - 040293 h reset value: 0000 h 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 00 0 0000 0 0 000 0 000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 00 0 0000 0 0 000 0 0 gbr 1 gbr 0 gbr 1 - 0 input and output data rate 00 8 mbps - group a, b, c and d 01 16 mbps - group a, b, c and d 10 32 mbps - group a and b group c and d inputs are unused group c and d outputs are tristated 11 65 mbps - group a group b, c and d inputs are unused group b, c and d outputs are tristated
zl50074 data sheet 46 zarlink semiconductor inc. 13.0 dc/ac electrical characteristics note 1: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. note 2: typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. note 1: typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings 1 - voltages are with respect to groun d (vss) unless ot herwise stated . characteristics sym. min. typ. 2 max. unit 1 chip i/o supply voltage v dd_io -0.5 5.0 v 2 chip core supply voltage v dd_core -0.5 5.0 v 3 input voltage (non-5 v tolerant inputs) v i_3v -0.5 v dd_io + 0.5 v 4 input voltage (5 v tolerant inputs) v i_5v -0.5 7.0 v 5 continuous current at digital outputs i o 15 ma 6 package power dissipation p d 2.1 w 7 storage temperature t s - 55 +125 c recommended operating conditions - voltages are with respect to grou nd (vss) unless ot herwise stated. characteristics sym. min. typ. 1 max. unit 1 operating temperature t op -40 25 +85 c 2 positive supply core v dd_core 1.71 1.8 1.89 v 3 positive supply i/o v dd_io 3.0 3.3 3.6 v 4 input voltage (non-5v tolerant inputs) v i_3v 0v dd_io v 5 input voltage (5v tolerant inputs) v i_5v 05.5
zl50074 data sheet 47 zarlink semiconductor inc. dc electrical ch aracteristics - voltages are with respect to ground (vss) unless otherwise stated. characteristics sym. min. typ. 1 1. typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. max. unit test conditions 1 core supply current 2 2. stoa = 65 mbps with random patterns. cko0 = 65 mhz, cko1 = 32 mhz i dd_core 500 ma 2 i/o supply current i dd_io 62 ma outputs unloaded 3 leakage current i ddq 105 a 4 dynamic power dissipation p dd 1.2 w outputs unloaded 5 input high voltage v ih 2.0 v 6 input low voltage v il 0.8 v 7 input leakage (input pins) 3 3. maximum leakage on pins (output or i/o pins in high impedance state) is over an applied voltage (vin). i il 5 a0 zl50074 data sheet 48 zarlink semiconductor inc. note 1: characteristics are over recommended operating conditions unless otherwise stated. note 2: typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. note 3: when using internal apll clock source and the cki0 frequency is less than or equal to the data rate. note 4: when using in put clock source cki 2-0 instead of the internal apll clock source. note 5: when using internal apll clock source and the cki0 frequency is higher than or equal to twice the data rate. ac electrical ch aracteristics 1 - fpi 0-2 and cki 0-2 timing no. characteristic (figure ) sym. min. typ. 2 max. units notes 1fpi 0-2 input frame pulse setup time t fpis 312nscki = 65.536 mhz 325nscki = 32.768 mhz 355nscki = 16.384 mhz 3115nscki = 8.192 mhz 2fpi 0-2 input frame pulse hold time t fpih 212nscki = 65.536 mhz 225nscki = 32.768 mhz 255nscki = 16.384 mhz 2115nscki = 8.192 mhz 3fpi 0-2 input frame pulse width t fpiw 524nscki = 65.536 mhz 550nscki = 32.768 mhz 5110nscki = 16.384 mhz 5230nscki = 8.192 mhz 4cki 0-2 input clock period (average value, does not consider the effects of jitter) t ckip 15 15.26 15.5 ns 65.536 mhz 30 30.5 31 ns 32.768 mhz 60 61.0 62 ns 16.384 mhz 120 122 124 ns 8.192 mhz 5cki input clock high time t ckih 4ns 6cki input clock low time t ckil 4ns 7cki input clock rise/fall time t rcki , t fcki 06ns 8cki input clock cycle to cycle variation t cvc 2 ns p-p standard rating 3 . sti at 65 mbps 4 ns p-p standard rating 3 . sti at 32 mbps 10 ns p-p standard rating 3 . sti at 16 mbps 20 ns p-p standard rating 3 . sti at 8 mbps 20% of t ckip p-p extended rating. with alternate clock source 4 or high cki0 rate 5
zl50074 data sheet 49 zarlink semiconductor inc. figure 8 - frame pulse input and clock input figure 9 - frame skew timing diagram ac electrical ch aracteristics 1 - fpi and cki skew 1. characteristics are over recommended operating conditions unless otherwise stated. no. characteristic (figure 9) sym. min. typ. 2 2. typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. max. units notes 1cki0 to cki1 , 2 skew t cksk -30 +30 ns c l 50 pf assume no jitter on input clocks fpi t fph t ckih t ckil t fpis t ckip cki input frame boundary t rcki t fcki t fpiw fpi0 cki0 frame boundary t cksk cki1 , 2 fpi 1, 2
zl50074 data sheet 50 zarlink semiconductor inc. note 1: characteristics are over recommended operating conditions unless otherwise stated. note 2: typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. note 3: cko clock source set to internal 131 mhz apll, and cki0 and fpi0 meet all the timing requirements. note 4: when cko source is set to one of the cki/ fpi, its output timings di rectly follow its source. ac electrical characteristics 1 - fpo 0-3 and cko 0-3 (65.536 mhz) timing no. characteristic sym. min. typ. 2 max. units notes 3 1fpo 0-3 output frame pulse setup time t fpos 5.5 9.5 ns c l =30 pf 2fpo 0-3 output frame pulse hold time t fpoh 5.5 9.5 ns c l =30 pf 3cko 0-3 output clock period t ckop 14.5 15.5 ns c l =30 pf ac electrical characteristics 1 - fpo 0-3 and cko 0-3 (32.768 mhz) timing no. characteristic sym. min. typ. 2 max. units notes 3 1fpo 0-3 output frame pulse setup time t fpos 14.0 16.5 ns c l =30 pf 2fpo 0-3 output frame pulse hold time t fpoh 14.0 16.5 ns c l =30 pf 3cko 0-3 output clock period t ckop 30.0 31.0 ns c l =30pf ac electrical characteristics 1 - fpo 0-3 and cko 0-3 (16.384 mhz) timing no. characteristic sym. min. typ. 2 max. units notes 3 1fpo 0-3 output frame pulse setup time t fpos 29.0 31.0 ns c l =30 pf 2fpo 0-3 output frame pulse hold time t fpoh 29.0 31.0 ns c l =30 pf 3cko 0-3 output clock period t ckop 60.5 61.5 ns c l =30 pf ac electrical characteristics 1 - fpo 0-3 and cko 0-3 (8.192 mhz) timing no. characteristic sym. min. typ. 2 max. units notes 3 1fpo 0-3 output frame pulse setup time t fpos 60.0 62.0 ns c l =30 pf 2fpo 0-3 output frame pulse hold time t fpoh 60.0 62.0 ns c l =30 pf 3cko 0-3 output clock period t ckop 121.5 122.5 ns c l =30 pf
zl50074 data sheet 51 zarlink semiconductor inc. figure 10 - st-bus frame pulse and clock output timing figure 11 - gci frame pulse and clock output timing note 1: cki at 8 mhz, output clock source set to internal apll. no jitter presented on the cki0 input. note 2: for 65.536 mhz output clock, the total loading on the output should not be larger than 10pf. ac electrical ch aracteristics - output clock jitter generation no. characteristic max. units notes 1,2 1 jitter at cko 0-3 (8.192 mhz) 1050 ps-pp 2 jitter at cko 0-3 (16.384 mhz) 1030 ps-pp 3 jitter at cko 0-3 (32.768 mhz) 920 ps-pp 4 jitter at cko 0-3 (65.536 mhz) 810 ps-pp fpo 0-3 t fpoh t fpos t ckop cko 0-3 output frame boundary fpo 0-3 t fpoh t fpos t ckop cko 0-3 output frame boundary
zl50074 data sheet 52 zarlink semiconductor inc. ac electrical ch aracteristics 1 - serial data timing 2 to cki 1. characteristics are over recommended operating conditions unless otherwise stated. 2. all of these specifications refer to st-bus inputs and outputs with clock source set to cki . no. characteristic (figure 12) sym. min. typ. 3 3. typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. max. units notes 4 4. loads on all serial outputs set to 30 pf 1cki to cko positive edge propagation delay t ckdp 3.5 8 ns cko clock source = cki 4.1 9.2 ns cko clock source = internal 131 mhz apll output 2cki to cko negative edge propagation delay t ckdn 4.5 9.2 cko clock source = cki 510.1cko clock source = internal 131 mhz apll output 3 sti to posedge cki setup t sips -0.8 ns 4 sti to posedge cki hold t siph 5.9 ns 5 sti to negedge cki setup t sins -0.8 ns 6 sti to negedge cki hold t sinh 5.9 ns 7 posedge cki to output data valid t sipv 4.8 11.6 ns stoa 5 5. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 4.1 13.7 ns stob, c, d 5 8 negedge cki to output data valid t sinv 5.8 12.9 ns stoa 5 4.5 14.8 ns stob, c, d 5 9 posedge cki to output data tri-state t sipz 4.3 14.6 ns stoa 5 4.6 14.5 ns stob, c, d 5 10 negedge cki to output data tri-state t sinz 5.3 13 ns stoa 5 5.7 13.6 ns stob, c, d 5 11 ode to output data tri-state t soz 10 ns stoa c l = 30pf, r l =1k 5 11 ns stob, c, d c l = 30pf, r l =1k 5 12 ode to output data enable t soe 4.5 15 ns stoa 5 620nsstob, c, d 5
zl50074 data sheet 53 zarlink semiconductor inc. figure 12 - serial data timing to cki ck i sto n t sinz sto n fpi fpi ck o t ckdn ode t soe (negative sense) (negative sense) (negative sense) (negative sense) ck o (positive sense) t sins t sinh sti n * t sinv valid data ck i sto n t sipz sto n t sipv (positive sense) valid data t sips t siph sti n * t soz t ckdp note 1: c ki frequency is assumed to be twice of the stin data rate, so that the sampling point is at the note 2: if c ki frequency is the same as the stin data rate, the sampling point moves to the 1/2 point of 3/4 point of the bit cell, or 1 1/2 clock period after the active clock edge the bit cell, or 1/2 clock period after the active clock edge.
zl50074 data sheet 54 zarlink semiconductor inc. ac electrical ch aracteristics - serial data timing 1 to cko 2 1. data capture points vary with respect to cko edge depending on clock rates & fractional delay settings. 2. all of these specifications refer to st-bus inputs, st-bus outputs and cko outputs set to internal clock source. no. characteristic (figure ) sym. min. typ. max. units notes 3 3. typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing 1 sti to posedge cko setup t sops 7.3 ns 2 sti to posedge cko hold t soph -2.0 ns 3 sti to negedge cko setup t sons 7.3 ns 4 sti to negedge cko hold t sonh -2.0 ns 5 posedge cko to output data valid t sopv 0.1 2.7 ns stoa 4 4. loads on all serial outputs set to 30 pf 0 4.6 ns stob, c, d 4 6 negedge cko to output data valid t sonv -1.2 1.7 ns stoa 4 -1.6 3.7 ns stob, c, d 4 7 posedge cko to output data tri-state t sopz 0.9 4.9 ns stoa 4 0.1 5.1 ns stob, c, d 4 8 negedge cko to output data tri-state t sonz 0.4 4.7 ns stoa 4 0 4.8 ns stob, c, d 4
zl50074 data sheet 55 zarlink semiconductor inc. figure 13 - serial data timing to cko cko valid data t sons t sonh sti n sto n t sonz sto n t sonv fpo cko sto n t sopz sto n t sopv fpo (negative sense) (negative sense) (negative sense) (positive sense) valid data t sops t soph sti n * * note 1: c k o frequency is assumed to be twice of the stin data rate, so that the sampling point is at the note 2: if c k o frequency is the same as the stin data rate, the sampling point moves to the 1/2 point of 3/4 point of the bit cell, or 1 1/2 clock period after the active clock edge the bit cell, or 1/2 clock period after the active clock edge.
zl50074 data sheet 56 zarlink semiconductor inc. note 1: all of these specifications refer to st-bus inputs, st-bus outputs and cko outputs set to internal clock source. note 2: typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing. figure 14 - cko to other cko skew ac electrical ch aracteristics - cko to other cko 1 skew no. characteristic (figure 12) sym. min. typ. 2 max. units notes 1cko 1 to cko 0 skew t ckos1-0 01.2ns 2cko 2 to cko 0 skew t ckos2-0 01.2ns 3cko 1 to cko 3 skew t ckos1-3 01.2ns 4cko 2 to cko 3 skew t ckos2-3 01.2ns 5cko 3 to cko 0 skew t ckos3-0 -0.6 0.6 ns 6cko 2 to cko 1 skew t ckos2-1 -0.6 0.6 ns cko 3 cko 0 t ckos3-0 cko 2 cko 1 t ckos2-1 t ckos1-3 t ckos1-0 t ckos2-0 t ckos2-3
zl50074 data sheet 57 zarlink semiconductor inc. ac electrical characteristics - microprocessor bus interface no characteristics (figure , & figure 16) sym. min. typ. 1 1. typical figures are at 25 c, v dd_core at 1.8 v and v dd_io at 3.3 v and are for design aid only: not guaranteed and not subject to production testing max. units notes 1ds recovery t dsre 5ns 2cs recovery t csre 0ns 3cs asserted setup to ds asserted t css 0ns 4 address, siz0-1, r/w setup to ds asserted t ads 0ns 5cs hold from ds deasserted t csh 0ns 6 address, siz0-1, r/w hold from ds deasserted t adh 0ns 7 data valid to dta asserted on read t dsr 0nsc l =50pf, r l =1k 2 2. high impedance is mea sured by pulling to the ap propriate rail with r l , with timing corrected to cancel time taken to discharge c l . 8cs deasserted to data tri-stated on read t dz 5nsc l =50pf, r l =1k 2 9 data setup to ds asserted on write t wds 0ns 10 cs asserted to wait deasserted t cswa 9nsc l = 30 pf, r l = 1k 2 11 data hold from dta asserted on write t dhw 0ns 12 ds asserted to wait asserted t wdd 9nsc l =50pf, r l =1k 2 13 wait deasserted to dta /berr asserted skew t aks 010nsc l =50pf, r l =1k 2 14 ds asserted to dta asserted t akd 35 155 ns connection memory 50 75 ns all other registers 15 ds deasserted to dta deasserted t akh 7nsc l =30pf, r l =1k 2 16 cs deasserted to dta tri-stated t dthz 13 ns c l =30pf, r l =1k 2 17 cs deasserted to wait tri-stated t wahz 6nsc l = 30 pf, r l = 1k 2 18 be or uds /lds skew t dsk 20 ns 19 be or uds /lds to ds set-up t beds 0
zl50074 data sheet 58 zarlink semiconductor inc. figure 15 - microprocessor bus interface timing figure 16 - intel mode timing ds a18-a0 cs d31-d0 d31-d0 read write t csh t adh t dz t ads t dhw t akd t wds t dsr t akh dta valid valid read data t css t wdd wait t dthz hi-z valid write data rwn,siz berr hi-z t csre t aks t wahz hi-z hi-z t cswa t dsre ds t dsre t dsk t beds siz1-siz0 (be1 -be0 or uds, lds )
zl50074 data sheet 59 zarlink semiconductor inc. figure 17 - jtag test port & pwr reset timing ac electrical ch aracteristics 1 - jtag test port and reset pin timing 1. characteristics are over recommended operating conditions unless otherwise stated. no. characteristic (figure 17) sym. min. typ. max. units notes 1 tck clock period t tckp 100 ns 2 tck clock frequency t tckf 10 mhz 3 tck clock pulse width high t tckh 20 ns 4 tck clock pulse width low t tckl 20 ns 5 tms set-up time t tmss 10 ns 6 tms hold time t tmsh 10 ns 7 tdi input set-up time t tdis 20 ns 8 tdi input hold time t tdih 60 ns 9 tdo output delay t tdod 20 ns c l =30pf 10 trst pulse width t trstw 20 ns 11 pwr pulse width t tpwr 20 ns t tmsh t tmss t tckl t tckh t tckp t tdis t tdih t tdod t trstw tms tck tdi tdo trst t tpwr pwr

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