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january 2015 docid026804 rev 1 1/46 1 AN4570 application note using the high-density stm32f30xxd/e fmc peripheral to drive external memories introduction this application note describes how to use the high-density stm32f30xxd/e fmc (flexible memory controller) peripheral to drive a set of external memories. for that aim, it gives an overview of the stm32f30xxd/e fmc. the document also presents memory interfacing examples that include the typical fmc configuration, the timing computation method and the hardware connection. this application note considers a 16-bit asynchronous nor flash memory, an 8-bit nand flash memory and a 16-bit asynchronous sram. the stm32f30xxd/e firmware library and the different memory drivers corresponding to the memory types presented in this application note are available for download on stmicroelectronics website at www.st.com . table 1 provides the list of products to which this application note applies. table 1. applicable products reference part number stm32f30xxd/e stm32f302rd, stm32f302vd, stm32f302zd, stm32f302re, stm32f302ve, stm32f302ze, stm32f303rd, stm32f303vd, stm32f303zd, stm32f303re, stm32f303ve, stm32f303ze. www.st.com
contents AN4570 2/46 docid026804 rev 1 contents 1 overview of the stm32f30xxd/e flexible static memory controller . . 5 1.1 interfacing asynchronous static memories (nor flash, sram) . . . . . . . . 7 2 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 fmc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 typical use of the fmc to interface with a nor flash memory . . . . . . 10 2.2 timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 interfacing with a non-multiplexed, asynchronous 16-bit sram . . . . 22 3.1 fmc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1.1 typical use of the fmc to interface with an sram . . . . . . . . . . . . . . . . 23 3.2 timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3 hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 interfacing with an 8-bit nand flash memory . . . . . . . . . . . . . . . . . . . 30 4.1 fmc configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 typical use of the fmc to interface with a nand memory . . . . . . . . . . 32 4.2 timing computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.3 hardware connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.4 error correction code computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.4.1 error correction code (ecc) computation overview . . . . . . . . . . . . . . . 41 4.4.2 error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 stm32f30xxd/e fmc configuration in 100-pin packages . . . . . . . . . . 43 5.1 interfacing the fmc with a nand flash memory . . . . . . . . . . . . . . . . . . 43 5.2 interfacing the fmc with a nor flash memory . . . . . . . . . . . . . . . . . . . . 44 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
docid026804 rev 1 3/46 AN4570 list of tables 3 list of tables table 1. applicable products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. fmc operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. stm32f30xxd/e fmc asynchronous timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. nor flash memory timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 5. m29w128fl signal to fmc pin correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. is61wv51216bl sram timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. is61wv51216bll signal to fmc pin correspondence. . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. nand512w3a2c flash memory timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. nand512w3a signal to fmc pin correspondence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 10. nand flash memory connection to the fmc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 11. nor flash memory connection to the fmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 12. document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
list of figures AN4570 4/46 docid026804 rev 1 list of figures figure 1. fmc block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. fmc memory banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. asynchronous nor flash read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. asynchronous nor flash write access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. 16-bit nor flash: m29w128fl/gl connection to stm32f30xxd/e . . . . . . . . . . . . . . . . . 14 figure 6. sram asynchronous read access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 7. sram asynchronous write access timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. 16-bit sram: is61wv51216bll connection to stm32f30xxd/e . . . . . . . . . . . . . . . . . . . 25 figure 9. fmc nand bank sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 figure 10. nand memory access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 11. 8-bit nand flash: nand512w3a2c/nand512w3a2b connection to stm32f30xxd/e . 36 figure 12. error detection flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
docid026804 rev 1 5/46 AN4570 overview of the stm32f30xxd/e flexible static memory controller 45 1 overview of the stm32f30xxd/e flexible static memory controller the fmc has the following main features: ? interface with static-memory mapped devices including: ? static random access memory (sram), ? nor flash memory/onenand flash memory, ? psram (4 memory banks), ? 16-bit pc card compatible devices, ? two banks of nand flash memory with ecc hardware to check up to 8 kbyte of data ? supports burst mode access to synchronous devices (nor flash and psram) ? 8- or 16-bit wide data bus ? independent chip select control for each memory bank ? independent configuration for each memory bank ? programmable timings to support a wide range of devices, in particular: ? programmable wait states (up to 15) ? programmable bus turnaround cycles (up to 15) ? programmable output enable and write enable delays (up to 15) ? independent read and write timings and protocol, so as to support the widest variety of memories and timings ? write enable and byte lane select outputs for use with psram and sram devices ? translation of 32-bit wide ahb transactions into consecutive 16-bit or 8-bit accesses to external 16-bit or 8-bit devices ? the fmc embeds two write fifos: ? write data fifo with 16x33-bit depth, ? write address fifo with 16x30-bit depth). ? external asynchronous wait control the fmc registers that define the external device type and associated characteristics are usually set at boot time and do not change until the next reset or power-up. however, it is possible to change the settings at any time. figure 1 illustrates the fmc block diagram.
overview of the stm32f30xxd/e flexible static memory controller AN4570 6/46 docid026804 rev 1 figure 1. fmc block diagram from the fmc point of view, the external memory is divided into four fixed-size banks of 256 mbyte each, as shown in figure 2 : ? bank 1 used by the nor flash/sram controller to address up to 4 memory devices. this bank is split into 4 regions with 4 dedicated chip select signals. ? banks 2 and 3 used by the nand flash/pc card controller to address nand flash devices. ? bank 4 used by the nand flash/pc card controller to address a pc card device. for each bank, the type of memory to be used is user-defined in the configuration register. 069 125365$0 vljqdov )0&b1(>@ )0&b1/ru1$'9 )0&b'>@ )0&b12( )0&b1:( )0&b1,25' )0&b15(* )0&b&' )0&b1%/>@ )0&b1&(>@ )0&b,17>@ )0&b,175 )0&b1&(b )0&b1&(b )0&b1,2:5 )0&b&/. )0&b$>@ )0&lqwhuuxswvwr19,& )urpforfn frqwuroohu 125365$0 phpru\ frqwuroohu &rqiljxudwlrq uhjlvwhuv 1$1'3& fdugphpru\ frqwuroohu +&/. )0&b1:$,7 3&fdugvljqdov 1$1'vljqdov 125365$065$0 vkduhgvljqdov 6kduhgvljqdov 125365$065$0 vkduhgvljqdov
docid026804 rev 1 7/46 AN4570 overview of the stm32f30xxd/e flexible static memory controller 45 figure 2. fmc memory banks 1.1 interfacing asynchronous static memories (nor flash, sram) the interface signals are synchronized by the internal clock hclk. this clock is not output to the memory the fmc always samples the data before de-asserting the chip select signal ne. this guarantees that the memory data-hold timing constraint is met (chip enable high to data transition, usually 0 ns min.). ? if extended mode is enabled (extmod: bit is set in the fsmc_bcrx register), there are up to four extended modes (a, b, c and d) and it is possible to mix modes a, b, c and d in read and write access. for example, read operation can be performed in mode a and write in mode b. ? if extended mode is disabled, the fmc operates in mode1 or mode2 as follows: ? mode 1 is the default mode when sram/ psram memory type is selected (bits 3:2 mtyp = 0x0 or 0x01 in the fsmc_bcrx register). ? mode 2 is the default mode when nor memory type is selected (bits 3:2 mtyp = 0x10 in the fsmc_bcrx register). 069 125365$065$0 6xssruwhgphpru\w\sh %dqn [ $gguhvv 3&&dug [))))))) [ [))))))) [ [))))))) [ [))))))) 1$1')odvkphpru\ %dqn [0% %dqn [0% %dqn [0% %dqn [0% table 2. fmc operating modes asynchronous mode memory type sram/psram nor extended mode disabled mode 1 mode2 extended mode enabled mode a mode b, c, d
overview of the stm32f30xxd/e flexible static memory controller AN4570 8/46 docid026804 rev 1 note: these timings extracted from stm32f30xxd/e datasheet are needed to compute the nor and sram asynchronous mode timings. table 3. stm32f30xxd/e fmc asynchronous timings symbols parameter value unit hclk internal ahb clock frequency 72 mhz t hclk internal ahb clock cycle 13.88 ns t su(data_ne) + t v(a_ne) data to fsmc_nex high setup time + fsmc_nex low to fsmc_a valid 1t hclk + 9 ns
docid026804 rev 1 9/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 2 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 2.1 fmc configuration to control a nor flash memory, the fmc provides the following possible features: ? select the bank to be used to map the nor flash memory: there are 4 independent banks which can be used to interface with nor flash/sram/psram memories, each bank has a separate chip select pin. ? enable or disable the address/data multiplexing feature ? select the memory type to be used: nor flash/sram/psram ? define the external memory data bus width: 8/16 bits ? enable or disable the burst access mode for synchronous nor flash memories ? configure the use of the wait signal: enable/disable, polarity setting and timing configuration. ? enable or disable the extended mode: this mode is used to access the memory with a different timing configuration for read and write operations. as the nor flash/psram controller can support asynchronous and synchronous memories, the user should select only the used parameters depending on the memory characteristics. the fmc also provides the possibility of programming several parameters to correctly interface with the external memory. depending on the memory type, some parameters are not used. in the case where an external asynchronous non-multiplexed memory is used, the user has to compute and set the following parameters depending on the information in the memory datasheet: ? addset: address setup time ? datast: data setup time ? accmod: access mode this parameter gives the fmc the flexibility to access a wide variety of asynchronous static memories. there are four extended access modes (a, b, c and d) that allow write access while reading the memory with different timings, if the memory supports this kind of feature. when the extended mode is enabled, the fmc_btrx register is used for read operations and the fmc_bwtrx register is used for write operations. in the case where a synchronous memory is used, the user has to compute and set the following parameters: ? clkdiv: clock divide ratio ? datlat: data latency note that nor flash memory read operations can be synchronous if the memory supports this mode, while write operations usually remain asynchronous. when programming a synchronous nor flash memory, the memory automatically switches between the synchronous and the asynchronous mode, so in this case, all parameters have to be set correctly.
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 10/46 docid026804 rev 1 figure 3 and figure 4 show the different timings during a typical nor flash memory access. figure 3. asynchronous nor flash read access timing figure 4. asynchronous nor flash write access timing 2.1.1 typical use of the fmc to interface with a nor flash memory the stm32f30xxd/e fmc has four different banks of 64 mbyte to support nor flash memories/psram and similar external memories. the external memories share the address, data and control signals with the controller. each external device is accessed by means of a unique chip select signal, but the fmc performs only one access at a time to an external device. each bank is configured by means of dedicated registers. configuration includes the different features and the timing parameters. $>@ 12( $''6(7 '$7$67 0hpru\wudqvdfwlrq 1([ '>@ +&/.f\fohv +&/.f\fohv 1:( 1$'9 gdwdgulyhq e\phpru\ 069 +ljk $>@ 12( $''6(7 '$7$67 0hpru\wudqvdfwlrq 1([ '>@ +&/.f\fohv +&/.f\fohv 1:( 1$'9 gdwdgulyhqe\)0& 069 +&/.
docid026804 rev 1 11/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 in this application note, the m29w128fl memory is used as a reference. the m29w128fl memory is a 16-bit, asynchronous, non-multiplexed nor flash memory. based on these data, the fmc is configured as follows: bank 2 is selected to support the nor flash memory device: ? bank 2 is enabled: bcr2_mbken bit set to ?1? ? memory type is nor: bcr2_mtyp is set to ?10? to select the nor memory type ? data bus width is 16-bit: bcr2_mwid is set to ?01? to select the 16-bit width ? it is a non-multiplexed memory: bcr2_muxen is reset. all remaining parameters must be kept cleared. 2.2 timing computation as described above, for asynchronous nor flash-like memories, there are different possible access protocols. the first step is therefore to define the kind of protocol that should be used with the specific memory. the choice depends on the different control signals and the behavior of the memory during read and write transactions. in the case of an asynchronous nor flash memory, the mode2 protocol will be used. if the used memory can provide an nadv signal, the extended mode b protocol should be used. with the m29w128fl, we will use the mode2 protocol. we will therefore not use any extended mode and the timings will be the same for read and write operations. in this case, the nor memory controller needs two timing parameters: addset and datast. these parameters are computed according to the nor flash memory characteristics and according to the hclk clock of the stm32f30xxd/e. based on the nor flash memory access timings illustrated in figure 3 and figure 4 , the following equations are found: ? the write or read access time is the time between the falling edge and the rising edge of the memory chip select signal. this time is computed as a function of the fmc timing parameter: ((addset + 1) + (datast + 1)) t hclk write access time ? in write operations, the datast parameter is measured between the falling edge and the rising edge of the write signal as follows: t wp = datast t hclk write enable signal low to high to have a correct configuration of the fmc timings, the timings have to take into account: ? the maximum read/write access time ? the different internal fmc delays ? the different internal memory delays hence, we have: ((addset + 1) + (datast + 1)) t hclk = max (t wc ) datast hclk = t wp for read access, datast must verify: datast (t avqv + t su(data_ne) + t v(a_ne) )/t hclk ? addset ? 4 table 4 gives the meanings and values of the nor flash memory parameters.
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 12/46 docid026804 rev 1 using the memory timings in table 4 and the fmc asynchronous timings in table 3 , we can compute the following values: ? for the m29w128 nor flash memory, the timings are: ? address setup time: 0x0 ? data setup time: 0x3 ? for the s29gl128p nor flash memory, the timings are: ? address setup time: 0x2 ? data setup time: 0x3 note: the s29gl128p nor flash memory timings are also valid for the m29w128 nor flash memory. table 4. nor flash memory timings symbols parameter value unit m29w128xx70 s29gl128p90 t wc address valid to next address valid for write operation 70 90 ns t rc address valid to next address valid for read access 70 90 ns t wp write enable low to write enable high 45 35 ns t avqv address valid to output valid 70 90 ns
docid026804 rev 1 13/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 2.3 hardware connection table 5 gives the correspondence between the nor flash memory pins and the fmc pins and shows the gpio configuration for each fmc pin. in case of an 8-bit nor flash memory, the data/address bus is 8-bit wide and d8-d15 should not be connected to the fmc. the unused fmc pins can be used for general purpose i/o. in case of a synchronous memory, the fsmc_clk pin should be connected to the memory clock pin. figure 5 shows a typical connection between an stm32f30xxd/e microcontroller and the m29w128fl nor flash memory. table 5. m29w128fl signal to fmc pin correspondence memory signals fmc signals pin / port assignment pin / port configuration signal description a0-a22 a0-a22 port f/port g/port e/port d/porth af push-pull address a0-a22 dq0-dq7 d0-d7 port d/port e af push-pull data d0-d7 dq8-dq14 d8-d14 port d/port e af push-pull data d8-d14 dq15a-1 d15 pd10 af push-pull data d15 e ne2 pg9 af push-pull chip enable g noe pd4 af push-pull output enable w nwe pd5 af push-pull write enable
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 14/46 docid026804 rev 1 figure 5. 16-bit nor flash: m29w128fl/gl connection to stm32f30xxd/e note: the gpio pd6 pin is used to provide a ready/busy output signal for nor flash memories (in this case the application needs to poll on the state of this pin to guarantee correct operation). in the example shown below, this pin is not used with the m29w128fl and m29w128gl nor flash memories. it is however required for the s29gl128p nor flash memory. a firmware example is available hereafter. the main goal of this example is to provide the basics of how to use the fmc firmware library and the associated nor flash memory driver to perform erase/read/write operations on the m29w128fl, m29w128gl or s29gl128p nor flash memories. for the fmc timings, the fmc nor flash firmware driver uses the highest timing values, that is those of the s29gl128p nor flash memory. 9 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 9 )0&b1( )0&b1:( )0&b12( )0&b1:$,7 5 n ? & q) 9 5 n ? 9 & q) 5 n ? & q) 5 n ? 9 -3 $ 9 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 5 n ? 'hidxowvhwwlqj2shq $ % $ ' $ & $ $ $ % $ ' $ & $ $ $ % $ ' $ ' : $ 53 % $ & 9ss:3 % 5% $ $ & $ % $ $ $ & $ ' $ % $ $ $ & $ ' 9&& ' $ ( ( ) 966 ( * * '4 ( '4 ) '4 + '4 * '4 ( '4 ) '4 + '4 * 9&& ) '4 + '4 ) '4 ( '4 * '4 + '4 ) '4 ( '4$ * 966 + %<7( ) $ ( 9&& * 966 + 8 0:)/=$( & q) 0:*/=$( 3' 3* 3' 3' 3+ 3) 3+ 3) 3) 3) 3) 3) 3) 3) 3* 3* 3* 3* 3* 3* 3' 3' 3' 3( 3( 3( 3( 3' 3' 3' 3' 3( 3( 3( 3( 3( 3( 3( 3( 3( 3' 3' 3' 6*/3)),5 069
docid026804 rev 1 15/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 /* includes --------------------------------------------------------------- ---*/ #include "stm32f3xx_hal.h" /* private define --------------------------------------------------------- ---*/ #define nor_device_addr ((uint32_t)0x64000000) /* #define nor_memory_width fmc_norsram_mem_bus_width_8 */ #define nor_memory_width fmc_norsram_mem_bus_width_16 #define nor_burstaccess fmc_burst_access_mode_disable /* #define nor_burstaccess fmc_burst_access_mode_enable*/ #define nor_writeburst fmc_write_burst_disable /* #define nor_writeburst fmc_write_burst_enable */ /* nor operations timeout definitions */ #define blockerase_timeout ((uint32_t)0x00a00000) /* nor block erase timeout */ #define chiperase_timeout ((uint32_t)0x30000000) /* nor chip erase timeout */ #define program_timeout ((uint32_t)0x00004400) /* nor program timeout */ #define buffer_size ((uint32_t)16) #define write_read_addr ((uint32_t)0x20800) /* nor ready/busy signal gpio definitions */ #define nor_ready_busy_pin gpio_pin_6 #define nor_ready_busy_gpio gpiod #define nor_ready_state gpio_pin_set #define nor_busy_state gpio_pin_reset #define nor_ok 0x00 #define nor_error 0x01 /* private variables ------------------------------------------------------ ---*/ static nor_handletypedef norhandle; static fmc_norsram_timingtypedef timing; static nor_idtypedef nor_id; static uint16_t nor_atxbuffer[buffer_size] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f};
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 16/46 docid026804 rev 1 static uint16_t nor_arxbuffer[buffer_size]= {0}; /* private function prototypes -------------------------------------------- ---*/ static uint8_t nor_writedata(uint32_t uwstartaddress, uint16_t* pdata, uint32_t uwdatasize); static uint8_t nor_readdata(uint32_t uwstartaddress, uint16_t *pdata, uint32_t uwdatasize); extern int main_nor(void); int main_nor(void) { norhandle.instance = fmc_norsram_device; norhandle.extended = fmc_norsram_extended_device; /*##-1- configure the nor device ###########################################*/ /* nor device configuration */ timing.addresssetuptime = 2; timing.addressholdtime = 1; timing.datasetuptime = 3; timing.busturnaroundduration = 0; timing.clkdivision = 2; timing.datalatency = 2; timing.accessmode = fmc_access_mode_b; norhandle.init.nsbank = fmc_norsram_bank2; norhandle.init.dataaddressmux = fmc_data_address_mux_disable; norhandle.init.memorytype = fmc_memory_type_nor; norhandle.init.memorydatawidth = nor_memory_width; norhandle.init.burstaccessmode = nor_burstaccess; norhandle.init.waitsignalpolarity = fmc_wait_signal_polarity_low; norhandle.init.wrapmode = fmc_wrap_mode_disable; norhandle.init.waitsignalactive = fmc_wait_timing_before_ws; norhandle.init.writeoperation = fmc_write_operation_enable; norhandle.init.waitsignal = fmc_wait_signal_disable; norhandle.init.extendedmode = fmc_extended_mode_disable; norhandle.init.asynchronouswait = fmc_asynchronous_wait_disable; norhandle.init.writeburst = nor_writeburst; /* nor controller initialization */ if(hal_nor_init(&norhandle, &timing, &timing) != hal_ok) {
docid026804 rev 1 17/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 return nor_error; } /*##-2- read & check the nor device ids ####################################*/ /* initialize the id structure */ nor_id.manufacturer_code = (uint16_t)0x00; nor_id.device_code1 = (uint16_t)0x00; nor_id.device_code2 = (uint16_t)0x00; nor_id.device_code3 = (uint16_t)0x00; /* read the nor memory id */ if(hal_nor_read_id(&norhandle, &nor_id) != hal_ok) { return nor_error; } /*##-3- erase nor memory ###################################################*/ /* return to read mode */ hal_nor_returntoreadmode(&norhandle); /* send nor erase block operation */ hal_nor_erase_block(&norhandle, write_read_addr, nor_device_addr); /* return the nor memory status */ if(hal_nor_getstatus(&norhandle, nor_device_addr, blockerase_timeout) != nor_success) { return nor_error; } /*##-4- nor memory read/write access ######################################*/ /* write data to the nor memory */ if(nor_writedata(write_read_addr, nor_atxbuffer, buffer_size) != nor_ok) { return nor_error; } /* read back data from the nor memory */
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 18/46 docid026804 rev 1 if(nor_readdata(write_read_addr, nor_arxbuffer, buffer_size) != nor_ok) { return nor_error; } return nor_ok; } /** * @brief initializes the nor msp. * @param none * @retval none */ void hal_nor_mspinit(nor_handletypedef *hnor) { gpio_inittypedef gpio_init_structure; /* enable fmc clock */ __fmc_clk_enable(); /* enable gpios clock */ __gpiod_clk_enable(); __gpioe_clk_enable(); __gpiof_clk_enable(); __gpiog_clk_enable(); __gpioh_clk_enable(); /* common gpio configuration */ gpio_init_structure.mode = gpio_mode_af_pp; gpio_init_structure.pull = gpio_pullup; gpio_init_structure.speed = gpio_speed_high; gpio_init_structure.alternate = gpio_af12_fmc; /*## data bus #######*/ /* gpiod configuration */ gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1 | gpio_pin_8 | gpio_pin_9 | gpio_pin_10 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpiod, &gpio_init_structure); /* gpioe configuration */
docid026804 rev 1 19/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 gpio_init_structure.pin = gpio_pin_7 | gpio_pin_8 | gpio_pin_9 | gpio_pin_10 | gpio_pin_11 | gpio_pin_12 | gpio_pin_13 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpioe, &gpio_init_structure); /*## address bus #######*/ /* gpiof configuration */ gpio_init_structure.pin = gpio_pin_2 | gpio_pin_3 | gpio_pin_4 | gpio_pin_5 | gpio_pin_12 | gpio_pin_13 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpiof, &gpio_init_structure); gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1; hal_gpio_init(gpioh, &gpio_init_structure); /* gpiog configuration */ gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1 | gpio_pin_2 | gpio_pin_3 | gpio_pin_4 | gpio_pin_5; hal_gpio_init(gpiog, &gpio_init_structure); /* gpiod configuration */ gpio_init_structure.pin = gpio_pin_11 | gpio_pin_12 | gpio_pin_13; hal_gpio_init(gpiod, &gpio_init_structure); /* gpioe configuration */ gpio_init_structure.pin = gpio_pin_3 | gpio_pin_4 | gpio_pin_5 | gpio_pin_6; hal_gpio_init(gpioe, &gpio_init_structure); /*## noe and nwe configuration ######*/ gpio_init_structure.pin = gpio_pin_4 | gpio_pin_5; hal_gpio_init(gpiod, &gpio_init_structure); /*## ne2 configuration ######*/ gpio_init_structure.pin = gpio_pin_9; hal_gpio_init(gpiog, &gpio_init_structure); /*## configure pd6 for nor memory ready/busy signal ######*/ gpio_init_structure.pin = gpio_pin_6; gpio_init_structure.mode = gpio_mode_af_pp; gpio_init_structure.pull = gpio_pullup; gpio_init_structure.alternate = gpio_af12_fmc; hal_gpio_init(gpiod, &gpio_init_structure); }
interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory AN4570 20/46 docid026804 rev 1 /** * @brief nor bsp wait for ready/busy signal. * @param hnor: pointer to nor handle * @param timeout: timeout duration * @retval none */ void hal_nor_mspwait(nor_handletypedef *hnor, uint32_t timeout) { uint32_t timeout = timeout; /* polling on ready/busy signal */ while((hal_gpio_readpin(nor_ready_busy_gpio, nor_ready_busy_pin) != nor_busy_state) && (timeout > 0)) { timeout--; } timeout = timeout; /* polling on ready/busy signal */ while((hal_gpio_readpin(nor_ready_busy_gpio, nor_ready_busy_pin) != nor_ready_state) && (timeout > 0)) { timeout--; } } /** * @brief writes an amount of data to the nor device. * @param uwstartaddress: write start address * @param pdata: pointer to data to be written * @param uwdatasize: size of data to write * @retval nor memory status */ uint8_t nor_writedata(uint32_t uwstartaddress, uint16_t* pdata, uint32_t uwdatasize) { uint32_t index = uwdatasize; while(index > 0)
docid026804 rev 1 21/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit nor flash memory 45 { /* write data to nor */ hal_nor_program(&norhandle, (uint32_t *)(nor_device_addr + uwstartaddress), pdata); /* read nor device status */ if(hal_nor_getstatus(&norhandle, nor_device_addr, program_timeout) != nor_success) { return nor_error; } /* update the counters */ index--; uwstartaddress += 2; pdata++; } return nor_ok; } /** * @brief reads an amount of data from the nor device. * @param uwstartaddress: read start address * @param pdata: pointer to data to be read * @param uwdatasize: size of data to read * @retval nor memory status */ uint8_t nor_readdata(uint32_t uwstartaddress, uint16_t* pdata, uint32_t uwdatasize) { if(hal_nor_readbuffer(&norhandle, nor_device_addr + uwstartaddress, pdata, uwdatasize) != hal_ok) { return nor_error; } else { return nor_ok; } }
interfacing with a non-multiplexed, asynchronous 16-bit sram AN4570 22/46 docid026804 rev 1 3 interfacing with a non-multiplexed, asynchronous 16- bit sram 3.1 fmc configuration sram and nor flash memories share the same fmc banks. the protocol to be used depends on the selected memory type. to control an sram, the fmc provides the following possible features: ? enable or disable the address/data multiplexing feature ? select the memory type to be used: nor/sram/psram ? define the external memory data bus width: 8/16 bits ? enable or disable the extended mode: this mode is used to access the memory with a different timing configuration for read and write operations. like for nor flash memories, the user has to compute and set the following parameters as a function of the information in the sram datasheet: addset: address setup time datast: data setup time figure 6 and figure 7 show the different timings for a typical sram access. figure 6. sram asynchronous read access timing $>@ 12( $''6(7 '$7$67 0hpru\wudqvdfwlrq 1([ '>@ +&/.f\fohv +&/.f\fohv 1:( 1%/>@ gdwdgulyhq e\phpru\ 069 +ljk
docid026804 rev 1 23/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit sram 45 figure 7. sram asynchronous write access timing 3.1.1 typical use of the fmc to interface with an sram in this application note, the is61wv51216bll memory is used as the reference. the is61wv51216bll memory is a non-multiplexed, asynchronous, 16-bit memory. bank3 is selected to support the sram device. based on these data, the fmc is configured as follows: ? bank3 is enabled: bcr3_mbken bit set to ?1? ? memory type is sram: bcr3_mtyp is set to ?00? to select the sram memory type ? data bus width is 16 bits: bcr3_mwid is set to ?01? to select the 16-bit width ? the memory is non-multiplexed: bcr3_muxen is reset all remaining parameters must be kept cleared. 3.2 timing computation the sram shares the same banks and configuration register as the nor flash memory. as a result, the timing computation method is the same as described in detail in the nor flash section ( section 2.2: timing computation on page 11 ). the fmc is configured on the basis of the sram access timings illustrated in figure 6 and figure 7 , and taking into account the following: ? the maximum read/write access time ? the different internal fmc delays ? the different internal memory delays hence the following equations: ((addset + 1) + (datast + 1)) t hclk max (t wc ) datast t hclk = t pwe1 $>@ 12( $''6(7 '$7$67 0hpru\wudqvdfwlrq 1([ '>@ +&/.f\fohv +&/.f\fohv 1:( 1%/>@ gdwdgulyhqe\)0& 069 +&/.
interfacing with a non-multiplexed, asynchronous 16-bit sram AN4570 24/46 docid026804 rev 1 for read access, datast must verify: datast (t aa + t su(data_ne) + t v(a_ne) )/t hclk ? addset ? 4 table 6 gives the meanings and values of the sram parameters. using the above described formulas, the memory timings in table 6 and the asynchronous timings in table 3 , we have: ? address setup time: 0x0 ? data setup time: 0x1 3.3 hardware connection table 7 gives the correspondence between sram pins and fmc pins and shows the gpio configuration for each fmc pin. in case of an 8-bit sram, the data/address bus is 8 bits wide and d8-d15 should not be connected to the fmc. the unused fmc pins can be used as general purpose i/o pins figure 8 shows a typical connection between an stm32f30xxd/e microcontroller and an is61wv51216bll sram. table 6. is61wv51216bl sram timings symbols parameter value unit t wc write cycle time 12 ns t rc read cycle time 12 ns t pwe1 write enable low pulse width 8 ns t aa address access time 12 ns table 7. is61wv51216bll signal to fmc pin correspondence memory signals fmc signals pin / port assignment pin / port configuration signal description a0-a18 a0-a18 port f/port g/port e/ port d/port h af push-pull address a0-a18 i/o0-i/o15 d0-d15 port d/port e af push-pull data d0-d15 ce ne3 pg10 af push-pull chip enable oe noe pd4 af push-pull output enable we nwe pd5 af push-pull write enable lb nbl0 pe0 af push-pull lower byte control ub nbl1 pe1 af push-pull upper byte control
docid026804 rev 1 25/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit sram 45 figure 8. 16-bit sram: is61wv51216bll connection to stm32f30xxd/e a firmware example is available hereafter. the main goal of this example is to provide the basics of how to use the fmc firmware library and the associate sram driver to perform read/write operations on the is61wv51216bll sram memory. /* includes --------------------------------------------------------------- ---*/ #include "stm32f3xx_hal.h" /* private define --------------------------------------------------------- ---*/ #define sram_device_addr ((uint32_t)0x68000000) #define sram_device_size ((uint32_t)0x200000) /* sram device size in mbytes */ /* #define sram_memory_width fmc_norsram_mem_bus_width_8 */ #define sram_memory_width fmc_norsram_mem_bus_width_16 #define sram_burstaccess fmc_burst_access_mode_disable /* #define sram_burstaccess fmc_burst_access_mode_enable*/ #define sram_writeburst fmc_write_burst_disable /* #define sram_writeburst fmc_write_burst_enable */ /* dma definitions for sram dma transfer */ #define __sram_dmax_clk_enable __dma2_clk_enable #define sram_dmax_stream dma2_channel1 $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ 9 )60&b1( )60&b1:( )60&b12( & q) & q) $ $ $ ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 5 . 9 $ % $ % $ $ $ $ $ $ &( % ,2 % ,2 & ,2 & ,2 ' 9&& ' 966 ' ,2 ( ,2 ) ,2 ) ,2 * :( * $ ( $ ) $ ) $ * $ * $ + $ + $ + $ + ,2 % ,2 & ,2 & ,2 ' 9&& ( ,2 ( ,2 ) ,2 ) ,2 * /% $ 8% % 2( $ $ ' $ & $ & $ ' $ + 966 ( 8 ,6:9%//0/, 3( 3( 3' 3' 3* )60&b1%/ )60&b1%/ 3) 3) 3' 3) 3) 3) 3) 3) 3) 3) 3) 3* 3* 3* 3* 3* 3* 3' 3' 3' 3' 3' 3' 3( 3( 3( 3( 3( 3( 3( 3( 3( 3' 3' 3' 069
interfacing with a non-multiplexed, asynchronous 16-bit sram AN4570 26/46 docid026804 rev 1 #define sram_dmax_irqn dma2_channel1_irqn #define sram_dmax_irqhandler dma2_channel1_irqhandler #define buffer_size ((uint32_t)16) #define write_read_addr ((uint32_t)0x0800) #define sram_ok 0x00 #define sram_error 0x01 /* private variables ------------------------------------------------------ ---*/ sram_handletypedef sramhandle; static fmc_norsram_timingtypedef timing; static uint16_t sram_atxbuffer[buffer_size] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; static uint16_t sram_arxbuffer[buffer_size]= {0}; /* private function prototypes -------------------------------------------- ---*/ extern int main_sram(void); int main_sram(void) { sramhandle.instance = fmc_norsram_device; sramhandle.extended = fmc_norsram_extended_device; /*##-1- configure the sram device ##########################################*/ /* sram device configuration */ timing.addresssetuptime = 0; timing.addressholdtime = 1; timing.datasetuptime = 2; timing.busturnaroundduration = 1; timing.clkdivision = 2; timing.datalatency = 2; timing.accessmode = fmc_access_mode_a; sramhandle.init.nsbank = fmc_norsram_bank3; sramhandle.init.dataaddressmux = fmc_data_address_mux_disable; sramhandle.init.memorytype = fmc_memory_type_sram; sramhandle.init.memorydatawidth = sram_memory_width; sramhandle.init.burstaccessmode = sram_burstaccess; sramhandle.init.waitsignalpolarity = fmc_wait_signal_polarity_low;
docid026804 rev 1 27/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit sram 45 sramhandle.init.wrapmode = fmc_wrap_mode_disable; sramhandle.init.waitsignalactive = fmc_wait_timing_before_ws; sramhandle.init.writeoperation = fmc_write_operation_enable; sramhandle.init.waitsignal = fmc_wait_signal_disable; sramhandle.init.extendedmode = fmc_extended_mode_disable; sramhandle.init.asynchronouswait = fmc_asynchronous_wait_disable; sramhandle.init.writeburst = sram_writeburst; /* sram controller initialization */ if(hal_sram_init(&sramhandle, &timing, &timing) != hal_ok) { return sram_error; } /*##-2- sram memory read/write access ######################################*/ /* write data to the sram memory */ if(hal_sram_write_16b(&sramhandle, (uint32_t *)(sram_device_addr + write_read_addr), sram_atxbuffer, buffer_size) != hal_ok) { return sram_error; } /* read back data from the sram memory */ if(hal_sram_read_16b(&sramhandle, (uint32_t *)(sram_device_addr + write_read_addr), sram_arxbuffer, buffer_size) != hal_ok) { return sram_error; } return sram_ok; } /** * @brief initializes the sram msp. * @param none * @retval none */ void hal_sram_mspinit(sram_handletypedef *hsram) { static dma_handletypedef dmahandle;
interfacing with a non-multiplexed, asynchronous 16-bit sram AN4570 28/46 docid026804 rev 1 gpio_inittypedef gpio_init_structure; /* enable fmc clock */ __fmc_clk_enable(); /* enable chosen dmax clock */ __sram_dmax_clk_enable(); /* enable gpios clock */ __gpiod_clk_enable(); __gpioe_clk_enable(); __gpiof_clk_enable(); __gpiog_clk_enable(); __gpioh_clk_enable(); /* common gpio configuration */ gpio_init_structure.mode = gpio_mode_af_pp; gpio_init_structure.pull = gpio_pulldown; gpio_init_structure.speed = gpio_speed_high; gpio_init_structure.alternate = gpio_af12_fmc; /*## data bus #######*/ /* gpiod configuration */ gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1 | gpio_pin_8 | gpio_pin_9 | gpio_pin_10 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpiod, &gpio_init_structure); /* gpioe configuration */ gpio_init_structure.pin = gpio_pin_7 | gpio_pin_8 | gpio_pin_9 | gpio_pin_10 | gpio_pin_11 | gpio_pin_12 | gpio_pin_13 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpioe, &gpio_init_structure); /*## address bus #######*/ /* gpiof configuration */ gpio_init_structure.pin = gpio_pin_2 | gpio_pin_3 | gpio_pin_4 | gpio_pin_5 | gpio_pin_12 | gpio_pin_13 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpiof, &gpio_init_structure); gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1; hal_gpio_init(gpioh, &gpio_init_structure);
docid026804 rev 1 29/46 AN4570 interfacing with a non-multiplexed, asynchronous 16-bit sram 45 /* gpiog configuration */ gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1 | gpio_pin_2 | gpio_pin_3 | gpio_pin_4 | gpio_pin_5; hal_gpio_init(gpiog, &gpio_init_structure); /* gpiod configuration */ gpio_init_structure.pin = gpio_pin_11 | gpio_pin_12 | gpio_pin_13; hal_gpio_init(gpiod, &gpio_init_structure); /*## noe and nwe configuration #######*/ gpio_init_structure.pin = gpio_pin_4 |gpio_pin_5; hal_gpio_init(gpiod, &gpio_init_structure); /*## ne3 configuration #######*/ gpio_init_structure.pin = gpio_pin_10; hal_gpio_init(gpiog, &gpio_init_structure); /*## nbl0, nbl1 configuration #######*/ gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1; hal_gpio_init(gpioe, &gpio_init_structure); /* configure common dma parameters */ dmahandle.init.direction = dma_memory_to_memory; dmahandle.init.periphinc = dma_pinc_enable; dmahandle.init.meminc = dma_minc_enable; dmahandle.init.periphdataalignment = dma_pdataalign_halfword; dmahandle.init.memdataalignment = dma_mdataalign_halfword; dmahandle.init.mode = dma_normal; dmahandle.init.priority = dma_priority_high; dmahandle.instance = sram_dmax_stream; /* associate the dma handle */ __hal_linkdma(hsram, hdma, dmahandle); /* deinitialize the stream for new transfer */ hal_dma_deinit(&dmahandle); /* configure the dma stream */ hal_dma_init(&dmahandle); /* nvic configuration for dma transfer complete interrupt */ hal_nvic_setpriority(sram_dmax_irqn, 5, 0); hal_nvic_enableirq(sram_dmax_irqn); }
interfacing with an 8-bit nand flash memory AN4570 30/46 docid026804 rev 1 4 interfacing with an 8-bit nand flash memory nand flash memories are accessed in accordance with a specific protocol. to write to or read from the nand flash memory, it is necessary to: 1. send a command to the nand flash memory 2. send the address to write to or read from 3. read or write the data the fmc nand banks are divided into three sections to allow the user to easily program the nand flash memory: data section, address section, and command section. figure 9. fmc nand bank sections in fact, the three sections are the representation of the real nand flash memory. by writing to any location in the command section, the user writes the command to the nand flash memory. by writing to any location in the address section, the user specifies the address of the read or write operation. depending on the structure of the used nand flash memory, four or five operations are required to write the address. by writing to or reading from any location in the data section, the data are written to or read from the address previously sent to the address section. command section address section data section 0x02 0000 0x03 ffff 0x01 0000 0x00 0000 ai15182
docid026804 rev 1 31/46 AN4570 interfacing with an 8-bit nand flash memory 45 4.1 fmc configuration to control a nand flash memory, the fmc provides the following possible features: ? enable or disable the use of the memory ready/ busy signal as the wait input for the fmc. ? enable or disable the use of the memory ready/ busy signal as the interrupt source for the fmc: the interrupt can be generated with three possible configurations: ? on the rising edge of the ready/ busy signal: when the memory has just completed an operation and the new status in ready. ? on the falling edge of the ready/ busy signal: when the memory starts the new operation ? on the high level of the ready/ busy signal: when the memory is ready. ? select the nand flash data bus width: 8- or 16-bit width. ? enable or disable the ecc computation logic. ? specify the ecc page size: it can be 256, 512, 1024, 2048, 4096 or 8192 bytes. the fmc also provides the possibility of programming the timings for the different nand flash sections separately: common section and attribute section. the timings are the following: ? setup time : it is the time (in hclk) required to set up the address before the command assertion. that is, it is the time from address valid to the start of the read or write operation. ? wait time : it is the time (in hclk) required to assert the command. that is, it is the time taken by the noe and nwe signals to become deasserted. ? hold time : it is the time (in hclk) during which the address is held after the command deassertion. that is, it is the time between the deassertion of the noe and nwe signals and the end of the operation cycle. ? data-bus hiz time : it is only valid for write operations and corresponds to the time (in hclk) during which the data bus is kept in the high-impedance state after the start of a write access. that is, it is the time from address valid to data bus driven. figure 10 shows the different timings for a typical nand flash memory access.
interfacing with an 8-bit nand flash memory AN4570 32/46 docid026804 rev 1 figure 10. nand memory access timing 1. noe remains high (inactive) during write accesses. nwe remains high (inactive) during read accesses. 4.1.1 typical use of the fmc to interface with a nand memory the stm32f30xxd/e fmc nand flash controller can configure bank2 or bank3 to support nand flash memories. the banks are selected using the chip select signals, as each bank is associated with a specific chip select. to enable communication with the nand flash devices, the fmc nand flash controller has to be initialized to meet the characteristics of the nand flash devices: features, timings, data width, etc. in this application note, the numonyx nand512w3a is used as the reference. this memory has the same access protocol as many other nand flash memories on today?s market. nand512w3a characteristics: ? nand interface: x8 bus width, multiplexed address/ data ? page size: x8 device: (512 + 16 spare) bytes ? page read/program timings: ? random access: 12 s (3 v)/15 s (1.8 v) (max) ? sequential access: 30 ns (3 v)/50 ns (1.8 v) (min) ? page program time: 200 s (typ.) 069 +&/. $>@ 1&([ 15(* 1,2: 1,25 1:( 12( zulwhbgdwd uhdgbgdwd +ljk 9dolg 0(0[6(7 0(0[:$,7 0(0[+2/' 0(0[+,=
docid026804 rev 1 33/46 AN4570 interfacing with an 8-bit nand flash memory 45 bank2 is selected to support the nand flash device. based on these data, the fmc is configured as follows: ? bank2 is enabled: pcr2_pbken bit set to ?1? ? memory type is nand flash: pcr2_ptyp is set to ?1? to select the nand flash memory type. ? data bus width is 8 bit: pcr2_pwid is set to ?00? to select 8-bit width. ? ecc page size is 512 bytes: pcr2_eccps is set to ?001? to set the ecc computation page size to 512 bytes. ? ecc hardware calculation on/off as needed: pcr2_eccen is set or reset accordingly. ? wait feature may or not be enabled depending on the user?s application: pcr2_pwaiten is set or reset as needed. the ready/ busy memory signal can be connected to the fsmc_nwait pin, and in this case the wait feature must be used to manage the nand flash operations. when using the nand flash memory with the wait feature enabled, the controller waits for the nand flash to be ready to become active before starting a new access. while waiting, the controller maintains the nce signal active (low). generally, the ready/ busy signal is an open-drain output. to connect this signal to the stm32f30xxd/e microcontroller, the corresponding pin must be configured as input pull-up. the ready/ busy signal can be used as an interrupt source for the fmc and, in this case, the cpu can perform other tasks during nand flash operations. three fmc configurations make it possible to use this signal as an interrupt. for that purpose, the iren, ifen or ilen bits in the sr2 register are used to select the rising edge, the falling edge or the high level of the nand flash ready/ busy signal . 4.2 timing computation besides configuring the different features that are to be used with the nand flash memory, the user has to initialize the controller to meet the memory timings. as described in section 4.1 , the fmc is able to program four different timings for the common space and the attribute space independently: setup time, wait time, hold time and data-bus hiz time . these parameters are computed according to the nand flash memory characteristics and the stm32f30xxd/e hclk clock.
interfacing with an 8-bit nand flash memory AN4570 34/46 docid026804 rev 1 based on the nand flash memory access timings shown in figure 10 , the following equations are found: ? the write or read access time is the time between the falling edge and the rising edge of the nand flash memory chip select signal. it is computed as a function of the fmc timing parameter: ((set + 1) + (wait + 1) + (hold + 1)) t hclk write/read access ? the wait time is measured between the falling edge and the rising edge of the write/read enable signal: write/read enable signal low to high = (wait + 1) t hclk ? for write access, the hiz parameter is the time measured between the falling edge of the chip select signal and the data setup on bus: (hiz+1) x t hclk chip select setup time to data setup. ? the hold timing is given in the nand datasheet as follows: (hold +1) x t hclk = write enable high to chip enable / address/command latch high to make sure of the correct timing configuration of the fmc, the timings have to take into consideration: ? the maximum read/write access time ? the different internal fmc delays ? the different internal memory delays hence, we have the following equations following the nand512w3a nand datasheet: ? (set + 1) x t hclk max (t cs , t cls , t als , t clr , t ar ) - t wp ? (wait + 1) x t hclk max (twp, trp) ? (hiz + 1) x t hclk max (t cs , t als , t cls ) + (t wp - t ds ) ? (hold + 1) x t hclk max (t ch , t clh , t alh ) ? ((wait + 1) + (hold + 1) + (set + 1)) x t hclk max (t wc/rc ) considering the different timings in the fmc and the memory, the equations become: ? wait must verify: (wait + 1) t hclk (t rea + t su(d-noe) ) wait (t rea + t su(d-noe) ) /t hclk - 1 note: t su(d-noe) is specified in the stm32f30xxd/e datasheets. t su(d-noe) = 25 ns table 8 gives the meanings and values of the nand512w3a2c memory parameters. table 8. nand512w3a2c flash memory timings symbol parameter value unit t cea chip enable low to output valid 35 ns t wp write enable low to write enable high 15 ns
docid026804 rev 1 35/46 AN4570 interfacing with an 8-bit nand flash memory 45 using the above described formulas, the memory timings in table 8 and the asynchronous timings in table 3 , we have: ? setup time: 0x0 ? wait time: 0x2 ? hold time: 0x1 ? hiz time: 0x0 4.3 hardware connection table 9 gives the correspondence between the nand flash memory pins and the fmc pins and shows the gpio configuration for each fmc pin. in case of a 16-bit nand flash memory, the data/address bus is 16 bits wide and the remaining fmc data/address bus are used. t rp read enable low to read enable high 15 ns t cs chip enable low to write enable high 20 ns t als al setup time 15 ns t cls cl setup time 15 ns t ch e hold time 5 ns t alh al hold time 5 ns t clh cl hold time 5 ns t ds data valid to write enable high 15 ns t wc write enable low to write enable low 30 ns t rc read enable low to read enable low 30 ns t rea read enable low to output valid 18 ns table 8. nand512w3a2c flash memory timings (continued) symbol parameter value unit table 9. nand512w3a signal to fmc pin correspondence memory signals fmc signals pin / port assignment pin / port configuration signal description al ale/a17 pd11 af push-pull address latch enable cl cle/a16 pd12 af push-pull command latch enable i/o0-i/o7 d0-d7 port d/port e af push-pull data d0-d7 e nce2 pd7 af push-pull chip enable r noe pd4 af push-pull output enable w nwe pd5 af push-pull write enable r b nwait/int2 pd6/pg6 input pull-up ready/ busy signal
interfacing with an 8-bit nand flash memory AN4570 36/46 docid026804 rev 1 figure 11 illustrates a typical connection between the stm32f30xxd/e microcontroller and the nand512w3a memory. figure 11. 8-bit nand flash: nand512w3a2c/nand512w3a2b connection to stm32f30xxd/e a firmware example is available hereafter. the main goal of this example is to provide the basics of how to use the fmc firmware library and the associated nand flash memory driver to perform erase/read/write operations using the fmc wait feature on the nand512w3a2 memory. 5% 5 ( 9'' 966 &/ $/ : :3 ,2 ,2 ,2 ,2 966 9'' ,2 ,2 ,2 ,2 8 1$1':$&1( 9 $ $ )0&b1&( )0&b1:( )0&b12( )0&b1:$,7 -3 & q) & q) 5 . 9 & q) 5 . 9 5 . 9 ' ' ' ' ' ' ' ' 5 . 5 grqrwilw 'hidxowvhwwlqj! 1$1':$%1( 3' 3' 3' 3* )0&b,17 3' 3' 3' 3' 3( 3( 3( 3( 3' 3' 3' 069
docid026804 rev 1 37/46 AN4570 interfacing with an 8-bit nand flash memory 45 /* includes --------------------------------------------------------------- ---*/ #include "stm32f3xx_hal.h" /* private define --------------------------------------------------------- ---*/ #define nand_device_addr ((uint32_t)0x70000000) #define buffer_size ((uint32_t)16) #define write_read_addr ((uint32_t)0x20800) #define nand_ok 0x00 #define nand_error 0x01 /* private variables ------------------------------------------------------ ---*/ static nand_handletypedef nandhandle; static fmc_nand_pcc_timingtypedef timing; static nand_idtypedef nand_id; static uint8_t nand_atxbuffer[buffer_size] = {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; static uint8_t nand_arxbuffer[buffer_size]= {0}; /* private function prototypes -------------------------------------------- ---*/ extern int main_nand(void); int main_nand(void) { nand_addresstypedef address; nandhandle.instance = fmc_nand_device; /*##-1- configure the nand device ###########################################*/ /*nand configuration */ timing.setuptime = 0; timing.waitsetuptime = 2; timing.holdsetuptime = 1; timing.hizsetuptime = 0; nandhandle.init.nandbank = fmc_nand_bank2; nandhandle.init.waitfeature = fmc_nand_pcc_wait_feature_enable;
interfacing with an 8-bit nand flash memory AN4570 38/46 docid026804 rev 1 nandhandle.init.memorydatawidth = fmc_nand_pcc_mem_bus_width_8; nandhandle.init.ecccomputation = fmc_nand_ecc_enable; nandhandle.init.eccpagesize = fmc_nand_ecc_page_size_512byte; nandhandle.init.tclrsetuptime = 0; nandhandle.init.tarsetuptime = 0; nandhandle.info.blocknbr = 0x04; nandhandle.info.blocksize = 0x20; nandhandle.info.zonesize = 0x400; nandhandle.info.pagesize = 0x200; nandhandle.info.spareareasize = 0x10; /* nand controller initialization */ if(hal_nand_init(&nandhandle, &timing, &timing) != hal_ok) { return nand_error; } /*##-2- read & check the nand device ids ####################################*/ /* initialize the id structure */ nand_id.maker_id = (uint16_t)0x00; nand_id.device_id = (uint16_t)0x00; nand_id.third_id = (uint16_t)0x00; nand_id.fourth_id = (uint16_t)0x00; /* read the nand memory id */ if(hal_nand_read_id(&nandhandle, &nand_id) != hal_ok) { return nand_error; } /*##-3- erase nand memory ###################################################*/ address.page = 3; address.zone = 1; address.block = 5; /* send nand erase block operation */ if (hal_nand_erase_block(&nandhandle, &address) != hal_ok) { return nand_error; } /*##-4- nand memory read/write access ######################################*/
docid026804 rev 1 39/46 AN4570 interfacing with an 8-bit nand flash memory 45 /* write data to the nand memory */ if (hal_nand_write_page(&nandhandle, &address, nand_atxbuffer, 1) != hal_ok) { return nand_error; } /* read back data from the nand memory */ if (hal_nand_read_page(&nandhandle, &address, nand_arxbuffer, 1) != hal_ok) { return nand_error; } return nand_ok; } /** * @brief initializes the nand msp. * @param none * @retval none */ void hal_nand_mspinit(nand_handletypedef *hnand) { gpio_inittypedef gpio_init_structure; /* enable fmc clock */ __fmc_clk_enable(); /* enable gpios clock */ __gpiod_clk_enable(); __gpioe_clk_enable(); __gpiog_clk_enable(); /* common gpio configuration */ gpio_init_structure.mode = gpio_mode_af_pp; gpio_init_structure.pull = gpio_nopull; gpio_init_structure.speed = gpio_speed_high; gpio_init_structure.alternate = gpio_af12_fmc; /* data d0->d7 */
interfacing with an 8-bit nand flash memory AN4570 40/46 docid026804 rev 1 gpio_init_structure.pin = gpio_pin_0 | gpio_pin_1 | gpio_pin_14 | gpio_pin_15; hal_gpio_init(gpiod, &gpio_init_structure); gpio_init_structure.pin = gpio_pin_7 | gpio_pin_8 | gpio_pin_9 | gpio_pin_10; hal_gpio_init(gpioe, &gpio_init_structure); /* address command latch enable - address latch enable */ gpio_init_structure.pin = gpio_pin_11 | gpio_pin_12; hal_gpio_init(gpiod, &gpio_init_structure); /* nwe pin configuration */ gpio_init_structure.pin = gpio_pin_5; hal_gpio_init(gpiod, &gpio_init_structure); /* noe pin configuration */ gpio_init_structure.pin = gpio_pin_4; hal_gpio_init(gpiod, &gpio_init_structure); /* nce2 pin configuration */ gpio_init_structure.pin = gpio_pin_7; hal_gpio_init(gpiod, &gpio_init_structure); /* nwait nand pin configuration */ gpio_init_structure.pin = gpio_pin_6; gpio_init_structure.mode = gpio_mode_af_pp; gpio_init_structure.pull = gpio_pullup; gpio_init_structure.alternate = gpio_af12_fmc; hal_gpio_init(gpiod, &gpio_init_structure); /* int2 nand pin configuration */ gpio_init_structure.pin = gpio_pin_6; gpio_init_structure.mode = gpio_mode_input; gpio_init_structure.pull = gpio_pullup; hal_gpio_init(gpiog, &gpio_init_structure); }
docid026804 rev 1 41/46 AN4570 interfacing with an 8-bit nand flash memory 45 4.4 error correction code computation 4.4.1 error correction code (ecc) computation overview the fmc nand flash controller includes two pieces of error correction code computation hardware, one for each nand flash memory block. the ecc can be performed for page sizes of 256, 512, 1024, 2048, 4096 or 8192 bytes, depending on the ecc page size configured by the user. depending on the configured page size, the ecc code will be 22, 24, 26, 28, 30 or 32 bits. to even improve the error coverage, the user can read/write the nand flash page with a reduced ecc page size. this is possible when starting and stopping the ecc computation after the desired number of bytes to check. in this case, the ecc code is only calculated for the bytes written and read. the error correction code algorithm implemented in the fmc can perform 1-bit error correction and 2-bit error detection per page read from or written to the nand flash memory. it is based on the hamming algorithm and consists in calculating the row and column parity. 4.4.2 error detection figure 12. error detection flowchart program nand page operation successful read ecc value during program operation read written nand page read new ecc value during read operation xor operation between the two ecc values all ecc bits are zero ye s no no error error detected ai15185
interfacing with an 8-bit nand flash memory AN4570 42/46 docid026804 rev 1 when an error occurs during the write operation, this error is either correctable or uncorrectable depending on the ecc xor operation: ? case of a correctable error the ecc xor operation contains 11-bit data at 1. and each pair parity is 0x10 or 0x01. ? case of an ecc error the ecc xor operation contains only one bit at 1. ? case of an uncorrectable error the ecc xor operation is random data. in this case the page data cannot be corrected. based on the flowchart shown in figure 12 , the correction software is easy to implement. the first step consists in detecting whether an error occurred during the write operation. if that was the case, the second step consists in determining if the error is correctable or not. if it is correctable, then the third step consists in correcting the error. the error correction is based on the second ecc generated after the read operation. the error location can be identified from this code. usually, the following data are extracted from the ecc: p1024, p512, p256, p128, p64, p32, p16, p8, p4, p2, p1, where px are the line and column parity. in case of an 8-bit memory, p4, p2, p1 define the error bit position. and p1024, p512, p256, p128, p64, p32, p16, p8 define the error byte position.
docid026804 rev 1 43/46 AN4570 stm32f30xxd/e fmc configuration in 100-pin packages 45 5 stm32f30xxd/e fmc configuration in 100-pin packages the fmc is present in devices delivered in both 144-pin and 100-pin packages. for devices in 100-pin packages, however, only some fmc banks can be used because not all pins are available. 5.1 interfacing the fmc with a nand flash memory in devices that come in 100-pin packages, only bank2 can be used to interface the fmc with an 8-/16-bit nand flash memory. this is because the nce3 pin is not available in these packages. likewise, no interrupt can be used because the two interrupt pins int2 and int3 are not available in 100-pin packages. table 10 shows how to connect an 8-/16-bit nand flash memory to the fmc peripheral of devices delivered in 100-pin packages. table 10. nand flash memory connection to the fmc 8-/16-bit nand memory pins fmc pins 100-pin package e nce2/nce3 nce2 r noe noe w nwe nwe al a17 a17 cl a16 a16 r/ b nwait/int2/int3 nwait i/o0-i/o7 d0-d7 d0-d7 i/o8-i/o15 d8-d15 d8-d15
stm32f30xxd/e fmc configuration in 100-pin packages AN4570 44/46 docid026804 rev 1 5.2 interfacing the fmc with a nor flash memory in devices that come in 100-pin packages, only bank 1 (nor/psram 1) can be used to interface with a nor flash memory. this is because the ne2, ne3 and ne4 pins are not available in these packages. likewise, the a0-a15 pins are not available, so the nor flash controller should be used in multiplexed mode to use the data bus for both address and data. in 8-bit muxed mode, the fmc address signals a[15:8] are available on the ad[15:8] pins. table 11 shows how to connect a nor flash memory to the fmc peripheral of devices delivered in 100-pin packages. table 11. nor flash memory connection to the fmc 8-/16-bit nor/psram pins fmc pins 100-pin package a[15:0] a[15:0] da[15:0] a[23:16] a[23:16] a[23:16] dq[15:0] d[15:0] d[15:0] w nwe nwe e ne1/ne2/ne3/ne4 ne1 g noe noe adv nadv nadv r/b nwait nwait ub, lb nbl[1:0] nbl[1:0]
docid026804 rev 1 45/46 AN4570 revision history 45 6 revision history table 12. document revision history date revision changes 28-jan-2015 1 initial release.
AN4570 46/46 docid026804 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved

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