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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 2002 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com CDB61884 octal t1/e1/j1 line interface evaluation board features socketed cs61884 octal line interface unit binding post connectors for power and line interface connections components supplied for all operational modes e1 75 ? , e1 120 ? and t1/j1 100 ? socketed termination circuitry for easy testing connector for ieee 1149.1 jtag boundary scan led indicators for loss of signal (los) and power supports hardware, serial, and parallel host modes easy-to-use evaluation software on-board socketed reference clock oscillator description the cs61884 evaluation board is used to demostrate the functions of a cs61884 octal line interface unit in either e1 75 ? , e1 120 ? , or t1/j1 100 ? applications. the evaluation board can be operated in either hard- ware mode or host mode. in hardware mode, switches and bed stake headers are used to control the line con- figuration and channel operations for all eight channels. in host mode (serial or parallel), the evaluation soft- ware, switches, and bed stake headers are used to control the line configuration and operating mode set- tings for each channel. in both hardware and host modes, the board may be configured for e1 75 ? , e1 120 ?, or t1/j1 100 ? oper- ating modes. in both modes binding post connectors provide easy connections between the line interface connections of the cs61884 and any e1/t1 analyzing equipment, which may be used to evaluate the cs61884 device. bed stake headers allow easy access to each channel?s clock and data i/o digital interface. eight led indictors display the loss of signal (los) conditions for each channel during hardware and host modes. an l ed indictor is used on the interrupt pin to indicate a change of state. ordering information cs61884-iq -40 to 85 c 144-pin lqfp CDB61884 evaluation board mar ?02 ds485db1
CDB61884 2 ds485db1 table of contents 1. CDB61884 evaluation board layout .......................................................................... 4 2. board component descriptions ................................................................................. 5 2.1 power connections ............................................................................................................ 5 2.2 master clock selection ...................................................................................................... 5 2.3 operating mode selection ................................................................................................. 6 2.4 line interface connections ................................................................................................ 6 2.5 txoe selection ................................................................................................................. 6 2.6 clock edge selection ......................................................................................................... 7 2.7 jitter attenuator selection .................................................................................................. 7 2.8 loopback mode selection .................................................................................................. 7 2.9 line length selection ........................................................................................................ 7 2.10 line impedance selection ................................................................................................ 8 2.11 coder/motorola/intel selection ......................................................................................... 8 2.12 g.772 monitoring address selection ............................................................................... 8 2.13 mux/non-mux/bits clock selection ................................................................................ 8 2.14 digital signal connections ............................................................................................... 9 2.15 los i ndicators .............................................................................................................. ... 9 2.16 jtag connection ............................................................................................................. 9 2.17 host interface connection ............................................................................................... 9 3. host setup description .................................................................................................. 9 4. host software interface ............................................................................................. 9 4.1 starting the software ....................................................................................................... 10 4.2 software i nterface buttons ............................................................................................... 10 4.2.1 bit indicator description ...................................................................................... 10 4.3 set all button description ................................................................................................ 10 4.3.1 clear all button description ................................................................................ 11 4.3.2 write all button description ................................................................................ 11 4.3.3 read all button description ................................................................................ 11 4.4 write button description .................................................................................................. 11 4.5 read button description .................................................................................................. 11 4.6 program exit function ..................................................................................................... 11 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm important notice "preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "advan ce" product infor- mation describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries ("cirrus") believe th at the infor- mation contained in this document is accurate and reliable. however, the information is subject to change without notice and is provided "as is" witho ut warranty of any kind (express or implied). customers are advised to obtain the latest version o f relevant information to verify, before placing orders, that in formation being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, inclu ding those pertaining to warranty, patent infringement, and limitation of liability. no responsibility is assumed by cirrus for the use of this information, in cluding use o f this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the prop erty of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the info rmation only for use within your organization with respect to cirrus integrated circuits or other parts of cirrus. this consent does not extend to other copying suc h a s copying for general distribution, advertising or promotional purposes, or for creating any work for resale. an export permit needs to be obtained from the competent authorities of the japanese government if any of the products or technologies described in thi sma- terial and controlled under the "foreign exchange and foreign trade law" is to be exported or taken out of japan. an export license and/or quota needs to be obtained from the competent authorities of the chinese government if any o f the products or technologies described in this material is subject to the p rc foreign trade law and is to be exported or taken out of the prc. certain applications using semiconductor products may involve potential r isks of death, personal injury, or severe p r o p e r t y o r e n v i r on m e n t a l d a m a g e ( " cr i t i c a l a p p l i c a t i o n s " ) . c i rrus p r o duc t s a re n o t d e s i g n e d , a u t h o r i z e d, o r w a rr a n t - ed to be suitable for u se in life-support devices or systems or other critical applications. inclusion of c irrus products in such applications is understood to be fully at the customer's r isk. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be tr ade- marks or service marks of their respective owners.
CDB61884 ds485db1 3 5. cs61884 configuration screens ............................................................................... 12 5.1 choose parallel port settings .......................................................................................... 12 5.2 access and configure the read / write registers .......................................................... 12 5.2.1 access configuration screens ............................................................................ 12 5.2.2 select register to configure ............................................................................... 12 5.3 loopback /bits clock screen ........................................................................................... 13 5.4 los/ais/dfm/ja register screen .................................................................................. 14 5.5 transmitter register screen ............................................................................................ 15 5.6 awg register screen ..................................................................................................... 16 5.7 global control register screen ....................................................................................... 17 6. board configurations ................................................................................................. 18 6.1 e1 75 ? mode setup ....................................................................................................... 18 6.2 e1 120 ? mode setup ..................................................................................................... 19 6.3 t1/j1 100 ? mode setup ................................................................................................ 20 7. evaluation hints ............................................................................................................. 2 1 list of figures figure 1. CDB61884 board layout ................................................................................................. 4 figure 2. on-board logic power selection ..................................................................................... 5 figure 3. master clock selections .................................................................................................. 5 figure 4. hardware/host mode selection ....................................................................................... 6 figure 5. transmitter enable selection........................................................................................... 7 figure 6. clock edge selection..................................................................................................... .. 7 figure 7. jitter attenuator selection.............................................................................................. .. 7 figure 8. loopback mode selection................................................................................................ 7 figure 9. switch s9 settings ....................................................................................................... .... 8 figure 10. digital signal control/access......................................................................................... 9 figure 11. CDB61884 software opening screen ......................................................................... 10 figure 12. register bit box ........................................................................................................ ... 10 figure 13. set all button .......................................................................................................... ..... 10 figure 14. clear all button ........................................................................................................ .... 11 figure 15. write all button ........................................................................................................ .... 11 figure 16. read all button ......................................................................................................... ... 11 figure 17. write button ........................................................................................................... ...... 11 figure 18. read button ............................................................................................................ ..... 11 figure 19. opening screen for port and address selection screen............................................. 12 figure 20. loopback/g.703 bits clock selection screen ............................................................. 13 figure 21. los/ais/dfm/ja err status/enable selection screen............................................. 14 figure 22. transmitter register screen ........................................................................................ 15 figure 23. awg registers screen................................................................................................ 16 figure 24. global control screen.................................................................................................. 1 7 list of tables table 1. external impedance resistor values ...................................................................................... 6 table 2. protection resistor selection ............................................................................................. .... 6 table 3. switch settings for host mode ............................................................................................... .9 table4.e175 ? operational mode switch/jumper position ............................................................. 18 table5.e1120 ? operational mode switch/jumper position ........................................................... 19 table 6. t1/j1 100 ? operational mode switch/jumper position ....................................................... 20
CDB61884 4 ds485db1 1. CDB61884 evaluation board layout figure 1. CDB61884 board layout
CDB61884 ds485db1 5 2. board component descriptions 2.1 power connections power for the evaluation board is supplied by an external +3.3 v dc power supply. a +5 v dc power supply can also be connected to the on-board control logic. the led labeled ?d3? will illumi- nate when power is supplied to the on-board con- trol logic. ? connect the +3.3 vdc power supply to the +3v binding post and the +5 vdc power supply to the +5 v binding post if 5 volt logic is required ? jumper j13 shown in figure 2 allows all the external logic on the evaluation board to be connected to either +3 v or +5 v binding post. ? to measure the current consumption of only the cs61884 device, place a short block on jumper j13 to connect the vlogic power supplies to the +5 v binding post. this will isolate the cs61884 device from all the on- board logic, to allow the current measurement to be made at the +3 v binding post. 2.2 master clock selection in both hardware and host modes, the mclk pin is configured by placing a short block on one of the positions of bed stake header j1. figure 3 shows the different positions of the j1 bed stake header. ? a 2.048 mhz clock oscillator is provided on the evaluation board for use as the on-board clock source for all e1 modes. ? a 1.544 mhz clock oscillator is also provided with the evaluation board for use as the on- board clock source for the t1/j1 operation modes. ? a bnc connector (labeled j16) provides the connection for an external clock source. j13 3v 5v on-board logic connected to +3 v binding post on-board logic connected to +5 v binding post vlogic j13 3v 5v vlogic figure 2. on-board logic power selection mclk j1 data recovery mode external source high oscillator gnd mclk j1 external clock source high oscillator gnd j1 receivers powered down high oscillator gnd j1 high oscillator gnd on-board oscillator mclk mclk external source external source external source figure 3. master clock selections
CDB61884 6 ds485db1 2.3 operating mode selection the operating mode for the cs61884 can be select- ed by setting switch s15 to one of the positions shown in figure 4 . 2.4 line interface connections in both hardware and host modes, the receive line signals (rtip/rring) are connected to the bind- ing post labeled rxt 0-7 and rxr 0-7. the line signals from the binding posts are coupled to the device through two octal transformers (t1 and t9). the receivers of the device use external resistors to match the line impedance. these resistors are sock- eted for ease in changing the line impedance, for in- ternal or external line impedance matching. during internal line impedance matching mode, the resis- tor values are the same (15 ? ) for all modes of op- eration: e1 75 ? , e1 120 ? or t1/j1 100 ? . during external line impedance matching mode the receiv- er resistors need to be change to the values shown in table 1 . the jumpers listed in table 2 areusedtoplaceor bypass 1 k ? protection resistors in series with the receive line signals (rtip/rring). these resis- tors are used for receiver protection while in exter- nal line impedance matching mode and should not be used during internal line impedance matching mode. to place the 1 k ? resistors in series with the receive line signals, remove the short blocks from each of the jumpers described in table 2 . to by- pass the 1 k ? resistors, place a short block on each jumper shown in table 2 . the transmit line signals (ttip/tring) from the device are coupled to the line binding post (txt 0- 7 and txr 0-7) through two octal transformers (t1 and t9). external protection circuitry such as di- odes or chokes are recommended for protection. for further information on line protection refer to application note an34, ?secondary line protec- tion for t1 and e1 line cards? (an34rev1 sep '94). 2.5 txoe selection jumper j23 is used to enable or high-z all eight transmitters in both hardware and host mode. a shorting block on jumper j23 places all the trans- table 1. external impedance resistor values t1/j1 100 ? e1 75 ? e1 120 ? 12.5 ? 9.31 ? 15 ? s15 hardware serial host parallel host selects hardware mode selects serial host mode selects parallel host mode mode s15 hardware serial host parallel host s15 hardware serial host parallel host mode mode figure 4. hardware/host mode selection table 2. protection resistor selection jumper description j29 channel 0 rring signal j30 channel 0 rtip signal j37 channel 1 rtip signal j38 channel 1 rring signal j46 channel 2 rring signal j47 channel 2 rtip signal j54 channel 3 rtip signal j55 channel 3 rring signal j65 channel 4 rring signal j66 channel 4 rtip signal j73 channel 5 rtip signal j74 channel 5 rring signal j81 channel 6 rring signal j82 channel 6 rtip signal j89 channel 7 rtip signal j90 channel 7 rring signal
CDB61884 ds485db1 7 mitters in a high impedance state. removing the shorting block, enables the transmitters. see figure 5. 2.6 clock edge selection in clock/data recovery mode, jumper j93 selects the edge of rclk and sclk on which the rpos/rdata, rneg, and sdo data signals are valid. when in data recovery mode, jumper j93 se- lects the output polarity of rpos/rneg. the func- tion of j93 applies to both the hardware and host mode. figure 6 shows the settings for jumper j93 and the effect in both clock/data recovery and data recovery only mode. 2.7 jitter attenuator selection in hardware mode, switch s10 (jasel) controls the position of the jitter attenuator for all eight channels. the corner frequency and fifo length can not be changed in hardware mode. figure 7 shows the settings for switch s10. in host mode, switch s10 has no effect on the cs61884 device and should be set to the open (middle) position. 2.8 loopback mode selection in hardware mode, the loopback modes are config- ured with switches s1 through s8 (0-7). figure 8 shows the three different settings for all eight loop back switches. in host mode, switches s1 through s8 must be set to the none (middle) position to allow host inter- face control. 2.9 line length selection in hardware mode, the transmit pulse shapes for e1 75 ? , e1 120 ? and t1(j1) 100 ? are selected with switches s12 through s14 (len 2-0). refer to the cs61884 data sheet for the correct settings. hi lo enable all eight transmitters hi-z all eight transmitters j23 txoe hi lo txoe j23 figure 5. transmitter enable selection j93 hi lo clock/data recovery - rpos/rneg = falling edge rclk sdo = rising edge sclk clock/data recovery - rpos/rneg = rising edge rclk sdo = falling edge sclk data recovery - rpos/rneg polarity active high data recovery - rpos/rneg polarity active low ckle j93 hi lo ckle figure 6. clock edge selection s10 hardware mode -japlacedin transmit path s10 s10 high open low high open low high open low hardware mode - ja disabled hardware mode -japlacedin receive path jasel jasel jasel figure 7. jitter attenuator selection hardware mode - selects remote loopback hardware mode - selects local loopback hardware mode - selects no loopback 0-7 0-7 0-7 s1 - s8 s1 - s8 s1 - s8 lloop none rloop lloop none rloop lloop none rloop figure 8. loopback mode selection
CDB61884 8 ds485db1 in host mode, switches s12 through s14 (len2-0) must be set to the open (middle) position to allow host processor control. 2.10 line impedance selection in hardware mode, switch s11 (cblsel), in com- bination with the len 2-0 switches are used to set the internal or external line impedance for all eight channels. refer to the cs61884 data sheet for the cblsel settings. in host mode, switch s11 has no effect on the cs61884 device and should be set to the nc (mid- dle) position. 2.11 coder/motorola/intel selection in hardware mode, switch 1 (mot /intl) inside switch block s9 (s9 #1) is used to enable ami or hdb3/b8zs line coding. setting switch s9 #1 to the open (high) position enables ami coding and the closed (low) position enables hdb3/b8zs cod- ing. inhostmode,switchs9#1isusedtoselecteither motorola or intel parallel host mode. when set to the open (high) position intel mode is selected and the closed (low) position enables motorola mode. figure 9 shows the settings for switch s9 #1 in hardware and parallel host mode. 2.12 g.772 monitoring address selection in hardware mode, the address for the g.772 non- intrusive monitoring feature is selected by switches 3 through 7 (a4-a0) inside switch block s9. when switches 3 through 7 inside switch block s9 are all set to the closed ?low? position, the g.772 non- intrusive monitoring function is disabled. refer to the cs61884 data sheet for more address settings. in host mode, switches 3 through 7 inside switch block s9 must be set to the open (high) position so that the host interface can have control over the ad- dress signals during parallel host modes. 2.13 mux/non-mux/bits clock selection in hardware mode, switch 2 (mux) inside switch block s9 enables or disables the channel #0 g.703 bits clock function. placing switch s9 #2 in the open ?high? position enables channel #0 g.703 bits clock function and the closed ?low? posi- tion disables this function. in host mode, switch s9 #2 (mux) is used to select multiplex or non-multiplex. placing switch s9 #2 hardware mode - enables ami coding & enables channel 0 g.703 bits clock function hardware mode - enables hdb3/b8zs coding & disables channel 0 g.703 bits clock function parallel host mode - enables motorola non- multiplex parallel host mode lo s9 open hi mot_\intl mux a0 a1 a2 a3 a4 1234567 lo s9 open hi mot_\intl mux a0 a1 a2 a3 a4 1234567 lo s9 open hi mot_\intl mux a0 a1 a2 a3 a4 1234567 figure 9. switch s9 settings
CDB61884 ds485db1 9 in the open ?high? position selects multiplex and the closed ?low? position selects non-multiplex 2.14 digital signal connections there are eight fourteen pin bed stake headers (la- beled j4 through j11) that provide access to the digital signals used to interface with back-end de- vices (framers, mappers, asic, etc.) and all eight los signals, in both hardware and host mode. figure 10 shows the layout for one of the eight 14- pin bed stake headers used to access the back-end digital signals, los signals and the different set- tings for the tclk/tneg pins. 2.15 los indicators the two 4-led packs d1 and d2 (labeled alos 0-7) represent the los signal status for los 0-7 pins. the alos 0-7 leds will illuminate when the corresponding receiver has detected a loss of signal condition. refer to the cs61884 data sheet for los conditions. 2.16 jtag connection a 5-pin bed stake header (j60) is provided to allow easy access to the ieee 1149.1 jtag boundary scan signals from the device. 2.17 host interface connection connector j12 is used to connect the cs61884 evaluation board to the host computer, through a standard 25 pin male to female parallel port cable. no external controller board is required for host interface connection. this connector is used for both serial and parallel interface. 3. host setup description place the switches shown in table 3 to the stated configuration before setting the mode switch (s15) to serial or parallel host mode. refer to the figure 4 on page 6 for switch s15 settings. ? switches #1 and #2 inside of switch block s9 are used in parallel host mode to select motorola, intel, multiplex or non-multiplex modes. switch s9 #1 and #2 are not used in serial host mode. 4. host software interface the software provided with the CDB61884 evalu- ation board is used to control and monitor the cs61884 device. the program is designed to auto- matically read back each bit after each write. if the bit is read back incorrectly an error will occur. the j1 tclk # tclk # tclk # tpos # tneg # tneg # los # rclk # gnd rpos # rneg # vlogic gnd j1 tclk # tclk # tclk # tpos # tneg # tneg # los # rclk # gnd rpos # rneg # vlogic gnd j1 tclk # tclk # tclk # tpos # tneg # tneg # los # rclk # gnd rpos # rneg # vlogic gnd bi-polar mode taos active when mclk present rz mode active when mclk absent j1 tclk # tclk # tclk # tpos # tneg # tneg # los # rclk # gnd rpos # rneg # vlogic gnd transmitters high-z uni-polar mode active vlogic vlogic vlogic vlogic figure 10. digital signal control/access table 3. switch settings for host mode switch position s1 through s8 none (middle) s9 # 3 through # 7 open (low) s10 open (middle) s11 nc (middle) s12 through s14 open (middle)
CDB61884 10 ds485db1 following registers do not have the automatic read back function: ?awgphaseaddress ? awg phase data, ? software reset registers. 4.1 starting the software there is no installation procedure associated with the cs61884 software, simply click on the appro- priate cs61884 software icon (95/98 or nt) on the cd in the CDB61884 kit. note: the software can be used with windows ? 95 ? , 98 ? ,nt ? or 2000 ? . figure 11 shows the opening screen that appears after you have launched the software. 4.2 software interface buttons the following subsections explain the functions of buttons that are common to the register configura- tion screens in the cs61884 software. 4.2.1 bit indicator description the register bit checkbox shown in figure 12 shows one bit, each register consists of eight bits (0 through 7). the grayed-out bits in some registers are bits that can not be accessed. figure 12 shows a bit with a check mark and without a check mark. a check represents a ?1? and no check mark equals a ?0?. 4.3 set all button description the set all button shown in figure 13 is used to set all the bits in the corresponding register to 1s. this button is placed to the left of each register that has write access. figure 11. CDB61884 software opening screen figure 12. register bit box figure 13. set all button
CDB61884 ds485db1 11 4.3.1 clear all button description the clr all button shown figure 14 is used to set all the bits in the corresponding register to 0s. this button is placed to the left of each register that has write access. 4.3.2 write all button description the write all button shown in figure 15 writes every bit of every register on the current register screen. this button is located in the bottom right corner of each register screen. 4.3.3 read all button description the read all button shown in figure 16 reads ev- ery bit of every register on the current register screen. this button is located in the bottom left cor- ner of each register screen. 4.4 write button description the write button shown in figure figure 17 writes the bits of the corresponding register. this button is located to the right of every register that allows write access. 4.5 read button description the read button shown in figure 18 reads the bits of the corresponding register. this button is located to the right of every register. 4.6 program exit function to exit any of the register screens simple press the x in the top right hand corner of each screen. this figure 14. clear all button figure 15. write all button figure 16. read all button figure 17. write button figure 18. read button
CDB61884 12 ds485db1 5. cs61884 configuration screens 5.1 choose parallel port settings the opening screen shown before in figure 11 and now in figure 19 is used for the following configu- ration activities: ? select the parallel port mode of operation ? select the parallel port address click the appropriate radio button to choose the op- erational modes you wish to use. important notes: 1. if the mode of operation does not match the mode switches on the evaluation board, an error will occur. 2. if the parallel port address does not match the address of the control parallel port, access to the register bits will not be permitted. 5.2 access and configure the read / write registers you also use the opening screen to access the tabbed configuration screens for the read / write registers. 5.2.1 access configuration screens click on the read/ write registers button on the opening screen to start configuring these registers. 5.2.2 select register to configure when the next screen appears, select the desired register screen by clicking on one of the tabs la- beled loopback/bits clk , los/ais/dfm , xmit , awg, or gcr at the top of the read/write register screen. figure 19. opening screen for port and address selection
CDB61884 ds485db1 13 5.3 loopback /bits clock screen the loopback /bits clock register tabbed screen shown in figure 20 allows access to the following reg- isters: ?remoteloopback ?analogloopback ? digital loopback ? g.703 bits clock figure 20. loopback/g.703 bits clock selection screen
CDB61884 14 ds485db1 5.4 los/ais/dfm/ja register screen the los/ais/dfm/ja register tabbed screen shown in figure 21 allows access to the following regis- ters: ?losstatus ? los interrupt enable ? los interrupt status ? los/ais mode enable ?dfmstatus ? dfm interrupt status ? dfm interrupt enable ? ais status ? ais interrupt enable ? ais interrupt status ? ja error interrupt enable ? ja error interrupt status . figure 21. los/ais/dfm/ja err status/enable selection screen
CDB61884 ds485db1 15 5.5 transmitter register screen the transmitter register screen shown in figure 22 consists of the following registers: ? automatic taos ? taos enable ? performance monitor ?linelengthchannelid ? line length data ? output disable. note: some indictor boxes (bits) in the performance monitor, line length channel id, and line length data registers are grayed out, this means that these bits can not be accessed. figure 22. transmitter register screen
CDB61884 16 ds485db1 5.6 a wg register screen the awg register screen shown in figure 23 allows access to the following awg registers: ? awg broadcast ? awg enable ? awg overflow interrupt enable ? awg overflow interrupt status ? awg phase address ? awg phase data. the awg phase address register is broken up into two easy-to-use data input boxes: the chan address ( i . e . , chann e l a dd r e s s ) and t he sample a d d r e s s . f or exa m p l e, t o acce s s t he a w g f u n c t i o n f or channel 5 , write 05 into the chan address input box. this is the same for every channel. the chan address , sam- ple address ,and phase data input boxes use the values discussed in the awg section of the cs61884 data sheet . figure 23. awg registers screen
CDB61884 ds485db1 17 5.7 global control register screen figure 24 shows the global control register (gcr) register screen, the gcr register screen consists of the following registers: ? software reset ? id registers. each bit in the global control register can be access by writing directly to the bit in the global control register on the top of this screen or by changing the radio buttons in one of the following windows: ? jitter attenuator ? ja fifo length ?awgautoincrement ?raisen ? coden ? jitter corner freq. the variables listed above change the corresponding bit in the global control register. the software re- set register is a write only register and will clear after the write. the id register is a read only register. figure 24. global control screen
CDB61884 18 ds485db1 6. board configurations 6.1 e1 75 ? mode setup table 4 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate in e1 75 ? hardware, serial host and parallel host operational modes. before selecting host mode, the switches in table 4 in bold should be set to the position stated. 3. connect a standard 25-pin male to female parallel port cable to connector j12 and the control pc. 4. set ?high? to enable bits clock recovery function for only channel #0 in hardware mode. 5. other settings may be used to enter g.772 non-intrusive monitoring in hardware mode. refer to the cs61884 data sheet for other settings. 6. set ?low? to disable receiver internal line impedance matching function. the external resistors for all eight receivers must be changed to 9.31 ? to properly match the input line impedance. table 4. e 1 75 ? operational mode switch/jumper position switches/jumpers hardware serial host (note 3) parallel host (note 3) s15 (mode) hardware serial host parallel host s1 (0) loop function none none s2 (1) loop function none none s3 (2) loop function none none s4 (3) loop function none none s5 (4) loop function none none s6 (5) loop function none none s7 (6) loop function none none s8 (7) loop function none none s9 #1 (mot_\intl) high high motorola/intel s9 #2 (mux) low (note 4) high mux/non-mux s9 #3 (a4) low (note 5) high high s9 #4 (a3) low (note 5) high high s9 #5 (a2) low (note 5) high high s9 #6 (a1) low (note 5) high high s9 #7 (a0) low (note 5) high high s10 (jasel) any position open open s11 (cblsel) high (note 6) nc nc s12 (len 2) low open open s13 (len 1) low open open s14 (len 0) low open open j13(vlogic)3v3v3v j1 (mclk) oscillator oscillator oscillator j93 (clke) open open open j23 (txoe) open open open
CDB61884 ds485db1 19 6 . 2 e1 1 20 ? mode setup table 5 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate in e1 120 ? hardware, serial host and parallel host operational modes. before selecting host mode, the switches in table 5 in bold should be set to the position stated. 7. set to ?nc? to disable receiver internal line impedance matching function. the external resistors for all eight receivers must be changed to 15 ? to properly match the input line impedance. table 5. e1 120 ? operational mode switch/jumper position switches/jumpers hardware serial host (note 3) parallel host (note 3) s15 (mode) hardware serial host parallel host s1 (0) loop function none none s2 (1) loop function none none s3 (2) loop function none none s4 (3) loop function none none s5 (4) loop function none none s6 (5) loop function none none s7 (6) loop function none none s8 (7) loop function none none s9 #1 (mot_\intl) high open motorola/intel s9 #2 (mux) low (note 4) open mux/non-mux s9 #3 (a4) low (note 5) open open s9 #4 (a3) low (note 5) open open s9 #5 (a2) low (note 5) open open s9 #6 (a1) low (note 5) open open s9 #7 (a0) low (note 5) open open s10 (jasel) any position open open s11 (cblsel) nc (note 7) nc nc s12 (len 2) low open open s13 (len 1) low open open s14 (len 0) low open open j13(vlogic)3v3v3v j1 (mclk) oscillator oscillator oscillator j93 (clke) open open open j23 (txoe) open open open
CDB61884 20 ds485db1 6 . 3 t1/j1 100 ? m o de setup table 6 shows the position of the different switches and jumpers used to set up the CDB61884 evaluation board to operate in t1/j1 100 ? hardware, serial host and parallel host operational modes. before se- lecting host mode the switches in table 6 in bold should be set to the position stated. 8. set ?low? to disable receiver internal line impedance matching function. the external resistors for all eight receivers must be changed to 12.5 ? to properly match the input line impedance. 9. selects t1/j1 100 ? 0ft-133ft line length settings. these p ins can be changed to select other t1/j1 100 ? line length settings. refer to the cs61884 data sheet for other settings. table 6. t1/j1 100 ? operational mode switch/jumper position switches/jumpers hardware serial host (note 3) parallel host (note 3) s15 (mode) hardware serial host parallel host s1 (0) loop function none none s2 (1) loop function none none s3 (2) loop function none none s4 (3) loop function none none s5 (4) loop function none none s6 (5) loop function none none s7 (6) loop function none none s8 (7) loop function none none s9 #1 (mot_\intl) open (high) high motorola/intel s9 #2 (mux) low (note 4) high mux/non-mux s9 #3 (a4) low (note 5) high high s9 #4 (a3) low (note 5) high high s9 #5 (a2) low (note 5) high high s9 #6 (a1) low (note 5) high high s9 #7 (a0) low (note 5) high high s10 (jasel) any position open open s11 (cblsel) nc or high (note 8) nc nc s12(len2) low(note9) open open s13 (len 1) high (note 9) open open s14 (len 0) high (note 9) open open j13(vlogic)3v3v3v j1 (mclk) oscillator oscillator oscillator j93 (clke) open open open j23 (txoe) open open open
CDB61884 ds485db1 21 7. evaluation hints ? pin #1 of the socket is indicated by an arrow with u1 below it. ? a short in the desired position must be placed on jumper j13 to connect the cs61884 to one of the power supply binding post. led d3 will illuminate when jumper j13 is connected to a power supply. ? before selecting any host mode place the cblsel, loop, address, len and jasel switches in the open or none position. ? when using the cs61884 device in internal match impedance mode, be sure that the 1 k ? resistors are not in series with the receivers.

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