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r08ds0132ej0100 rev.1.00 page 1 of 19 aug 31, 2015 1. v dd 1 2. v in+ 3. v in ? 4. gnd1 5. gnd2 6. v out ? 7. v out+ 8. v dd 2 pin connection (top view) 12 4 3 65 87 shield + ? + ? preliminary data sheet ps8352al2 analog output type optical coupled isolation amplifier description the ps8352al2 is an optically coupled isolation amplifier that uses an ic with a high-accuracy sigma-delta a/d converter and a gaaias light-emitting diode with high-speed response and high luminance efficiency on the input side, and an ic with a high-accuracy d/ a converter on the output side. the ps8352al2 is designed specifically for high common mode transient immunity (cmti) and high linearity (non- linearity). the ps8352al2 is designed for current and voltage sensing. features ? non-linearity (nl200 = 0.35% max.) ? high common mode transient immunity (cmti = 10 kv/ ? s min.) ? high isolation voltage (bv = 5 000 vr.m.s.) ? gain tolerance (g = 7.92 to 8.08 ( ? 1%)) gain: 8 v/v typ. ? package: 8-pin dip lead bending type for long creepage distance for surface mount (l2) ? embossed tape product: ps8352al2-e3: 2 000 pcs/reel ? pb-free product ? safety standards ? ul approved: no. e72422 ? csa approved: no. ca 101391 (ca5a, can/csa-c22.2 60065, 60950) ? din en 60747-5-5 (vde 0884-5) approved (option) applications ? ac servo, inverter ? solar power conditioner ? measurement equipment start of mass production 2015-09 r08ds0132ej0100 rev.1.00 a ug 31, 2015
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 2 of 19 aug 31, 2015 package dimensions (unit: mm) lead bending type (gull-wing) for long creepage distance for surface mount (l2) 8 1 5 4 5.850.25 6.80.25 (0.82) 3.50.2 3.70.25 1.27 0.40.1 0.25 m 11.50.3 0.750.25 (7.62) 0.250.15 0.20.15 s 0.1 s weight: 0.316g (typ.) photocoupler construction parameter unit (min.) air distance 8 mm outer creepage distance 8 mm isolation distance 0.4 mm
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 3 of 19 aug 31, 2015 marking example ordering information part number order number solder plating specification packing style safety standard approval application part number* 1 ps8352al2 ps8352al2-ax pb-free magazine case 50 pcs standard products ps8352al2 ps8352al2-e3 PS8352AL2-E3-AX (ni/pd/au) embossed tape 1 000 pcs/reel (ul, csa approved) ps8352al2-v ps8352al2-v-ax magazine case 50 pcs ul, csa approved ps8352al2-v-e3 ps8352al2-v-e3-ax embossed tape 1 000 pcs/reel din en 60747-5-5 (vde 0884-5) 2011-11 approved (option) *1 for the application of the safety standard, following part number should be used. 9332 r n304 3 n 04 no. 1 pin mark year assembled (last 1 digit) rank code week assembled assembly lot type number company initial 8352 a
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 4 of 19 aug 31, 2015 absolute maximum ratings (t a = 25 ? c, unless otherwise specified) parameter symbol ratings unit operating ambient temperature t a ?40 to +110 ? c storage temperature tstg ?55 to+125 ? c supply voltage v dd1 , v dd2 0 to 5.5 v input voltage v in ? , v in ? ?2 to v dd1 +0.5 v 2 seconds transient input voltage v in ? , v in ? ?6 to v dd1 +0.5 v output voltage v out ? , v out ? ?0.5 to v dd2 +0.5 v isolation voltage *1 bv 5 000 vr.m.s. *1 ac voltage for 1 minute at t a = 25 ? c, rh = 60% between input and output. pins 1-4 shorted together, 5-8 shorted together. recommended operating conditions parameter symbol min. max. unit operating ambient tem perature ta ?40 110 ? c supply voltage v dd1 , v dd2 4.5 5.5 v input voltage (accurate and linear) *1 v in ? , v in ? ?200 200 mv *1 using v in ? = 0 v (to be connected to gnd1) is recommended. avoid using v in ? of 2.5 v or more, because the internal test mode is activated when the voltage v in ?? reaches more than 2.5 v.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 5 of 19 aug 31, 2015 electrical characteristics (dc characteristics) (typ.: t a = 25 ? c, v in ? = v in ? = 0 v, v dd 1 = v dd 2 = 5 v, min., max.: refer to recommended operating conditions, unless otherwise specified) parameter symbol conditions min. typ. max. unit input offset voltage vos t a = 25 ? c ? 2 ? 0.25 2 mv ? 3 ? 0.25 3 input offset voltage drift vs. temperature ? dvos/dt a ? 1.6 10 ? v/ ? c gain *1 g ? 200 mv ? v in ? ? 200 mv, t a = 25 ? c 7.92 8 8.08 v/v gain drift vs. temperature ? dg/dt a ? 0.0006 v/v ? c v out non-linearity (200 mv) *2 nl200 ? 200 mv ? v in ? ? 200 mv 0.014 0.35 % v out non-linearity (200 mv) drift vs. temperature ? dnl200/dt a ? 0.0001 %/ ? c v out non-linearity (100 mv) *2 nl100 ? 100 mv ? v in ? ? 100 mv 0.011 0.2 % maximum input voltage before v out clipping ? v in ? ? max. 320 mv input supply current i dd1 v in ? = 400 mv 13.5 16 ma output supply current i dd2 v in ? = ? 400 mv 7.8 16 ma input bias current i in ? v in ? = 0v ? 1 ? 0.65 1 ? a input bias current drift vs. temperature ? di in ? /dt a ? 0.3 na/ ? c low level saturated output voltage v ol v in ? = ? 400 mv 1.29 v high level saturated output voltage v oh v in ? = 400 mv 3.8 v output voltage (v in ? = v in ? = 0 v) v ocm v in ? = v in ? = 0 v 2.2 2.55 2.8 v output short-circuit current ? i osc ? 20 ma equivalent input resistance r in 450 k ? v out output resistance r out 4 ? input dc common-mode rejection ratio *3 cmrr in 76 db *1 the differential output voltage (v out+ ? v out ? ) with respect to the differential input voltage (v in+ ? v in ? ), where v in+ = ? 200 mv to 200 mv and v in ? = 0 v) is measured under the circuit shown in fig. 2 nl200, g test circuit . upon the resulting chart, the gain is defined as the slope of the optimum line obta ined by using the method of least squares. *2 the differential output voltage (v out+ ? v out ? ) with respect to the differential input voltage (v in+ ? v in ? ) is measured under the circuit shown in fig. 2 nl200, g test circuit . upon the resulting chart, the optimum line is obtained by using the method of least squares. non-linearity is def ined as the ratio (%) of the optimum line obtained by dividing [half of the peak to peak value of the (residu al) deviation] by [full-scale differential output voltage]. for example, if the differential output voltage is 3.2 v, and the peak to peak value of the (residual) deviation is 22.4 mv, while the input v in+ is ? 200 mv, the output non-linearity is obtained as follows: nl200 = 22.4/(2 ? 3 200) = 0.35% *3 cmrr in is defined as the ratio of the differential signal gain (when the differential signal is applied between the input pins) to the common-mode signal gain (when both input pins are connected and the signal is applied). this value is indicated in db.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 6 of 19 aug 31, 2015 electrical characteristics (ac characteristics) (typ.: t a = 25 ? c, v in ? = v in ? = 0 v, v dd 1 = v dd 2 = 5 v, min., max.: refer to recommended operating conditions, unless otherwise specified) parameter symbol conditions min. typ. max. unit v out bandwidth ( ? 3 db) f c v in ? = 200 mvp-p, sine wave 50 100 khz v out noise n out v in ? = 0 v 15.6 mvr.m.s. v in to v out signal delay (50 to 10%) t pd10 v in ? = 0 to 150 mv step 2.4 3.3 ? s v in to v out signal delay (50 to 50%) t pd50 4.2 5.6 v in to v out signal delay (50 to 90%) t pd90 6.1 9.9 v out rise time/fall time (10 to 90%) t r /t f v in ? = 0 to 150 mv step 3.1 6.6 ? s common mode transient immunity *1 cmti v cm = 0.5 kv, t r = 20 ns, t a = 25 ? c 10 28 kv/ ? s power supply noise rejection *2 psr f = 1 mhz 40 mvr.m.s. *1 cmti is tested by applying a pulse that rises and falls suddenly (v cm = 0.5 kv) between gnd1 on the input side and gnd2 on the output side (pins 4 and 5) by using the circuit shown in fig. 9 cmti test circuit . cmti is defined at the point where the differential output voltage (v out+ ? v out ? ) fluctuates 200 mv (>1 ?? s) or more from the average output voltage. *2 this is the value of the transient vo ltage at the differential output when 1 v p-p , 1 mhz, and 40 ns rise/fall time square wave is applied to both v dd 1 and v dd 2.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 7 of 19 aug 31, 2015 test circuit fig. 1 v os test circuit fig. 2 nl200, g test circuit fig. 3 i dd 1 test circuit fig. 4 i dd 2 test circuit v dd1 v dd2 10 k 10 k 0.1 f shield + ? + ? 0.1 f 0.47 f 0.47 f v out +15 v ?15 v 0.1 f 0.1 f ad624cd (x100) v dd1 v in v dd2 10 k 10 k 0.1 f shield + ? + ? 0.1 f 0.47 f 0.01 f 0.47 f 0.47 f 10 k 13.2 404 +15 v ?15 v 0.1 f 0.1 f ad624cd (x4) v out +15 v ?15 v 0.1 f 0.1 f ad624cd (x10) 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 0.01 f shield + ? + ? 1 5 v i dd 1 400 mv 2 3 4 8 7 6 5 0.1 f 0.01 f shield + ? + ? 1 5 v ? 400 mv 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v i dd 2 ? + ? + ? +
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 8 of 19 aug 31, 2015 fig. 5 i in+ test circuit fig. 6 v out test circuit v ol v ocm v oh 0.01 f shield + ? + ? 1 ? 400 mv 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v 5 v 0.01 f shield + ? + ? 1 5 v i in+ 2 3 4 8 7 6 5 0.1 f v ol 0.01 f shield + ? + ? 1 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v 5 v v ocm 0.01 f shield + ? + ? 1 400 mv 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v 5 v v oh
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 9 of 19 aug 31, 2015 fig. 7 |i osc | test circuit fig. 8 t pd test circuit fig. 9 cmti test circuit v dd1 v in v dd2 2 k 10 k 2 k 0.1 f shield + ? + ? 0.1 f 0.01 f +15 v ?15 v 0.1 f 0.1 f ne5534 v out 1 2 3 4 8 7 6 5 i osc 0.01 f shield + ? + ? 1 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v 9 v 78l05 5 v i osc 0.01 f shield + ? + ? 1 2 3 4 8 7 6 5 0.1 f 0.1 f 5 v 5 v 10 k v dd2 2 k 2 k 0.1 f 0.1 f shield + ? + ? 0.1 f pc813 v out 1 2 3 4 8 7 6 5 10 k 150 pf 10 k 150 pf in out v cm +15 v ?15 v ? + 0.1 f 0.1 f + ? + ?
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 10 of 19 aug 31, 2015 typical characteristics (t a = 25 ? c, unless otherwise specified) ambient temperature ta (c) supply voltage v dd1 , v dd2 (v) supply voltage v dd1 , v dd2 (v) ambient temperature ta (c) ambient temperature ta (c) supply voltage v dd1 , v dd2 (v) input offset voltage vs. ambient temperature gain vs. ambient temperature non-linearity vs. ambient temperature gain vs. supply voltage non-linearity vs. supply voltage input offset voltage v os (mv) input offset voltage v os (mv) gain g (v/v) non-linearity nl200 (%) non-linearity nl200 (%) gain g (v/v) input offset voltage vs. supply voltage -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -50 -25 0 25 50 75 100 125 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 4.5 4.75 5 5.25 5.5 7.8 7.9 8.0 8.1 8.2 -50 -25 0 25 50 75 100 125 7.8 7.9 8.0 8.1 8.2 4.5 4.75 5 5.25 5.5 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 -50 -25 0 25 50 75 100 125 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 4.5 4.75 5 5.25 5.5 v dd1 = v dd2 = 5 v v in+ = v in- = 0 v v in+ = v in- = 0 v v dd1 = v dd2 = 5 v v in+ = -200 mv to +200 mv, v in- = 0 v v in+ = -200 mv to +200 mv, v in- = 0 v v dd1 = v dd2 = 5 v v in+ = -200 mv to +200 mv, v in- = 0 v v in+ = -200 mv to +200 mv, v in- = 0 v remark the graphs indicate nominal characteristics.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 11 of 19 aug 31, 2015 input voltage v in+ (v) frequency f (hz) supply voltage v dd1 , v dd2 (v) input voltage v in (v) ambient temperature ta (c) input voltage v in (v) output voltage vs. input voltage input current vs. input voltage frequency vs. ambient temperature gain vs. frequency frequency vs. supply voltage output voltage v o (v) supply current i dd (ma) input current i in+ (a) frequency f c -3 db (hz) frequency f c -3 db (hz) gain g v (db) supply current vs. input voltage 1 1.5 2 2.5 3 3.5 4 -0.4 -0.2 0 0.2 0.4 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 -0.4 -0.2 0.0 0.2 0.4 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 -0.4 -0.2 0.0 0.2 0.4 -8 -7 -6 -5 -4 -3 -2 -1 0 1 10 100 1000 10000 100000 1000000 0.0 20.0 40.0 60.0 80.0 100.0 120.0 -50 -25 0 25 50 75 100 125 0.0 20.0 40.0 60.0 80.0 100.0 120.0 4.5 4.75 5 5.25 5.5 v out+ v out- i dd1 i dd2 v dd1 = v dd2 = 5 v v dd1 = v dd2 = 5 v v dd1 = v dd2 = 5 v v in- = 0 v v dd1 = v dd2 = 5 v v in- = 0 v v in+ = 200 mvp-p sine wave v dd1 = v dd2 = 5 v v in- = 0 v v in+ = 200 mvp-p sine wave v dd1 = v dd2 = 5 v v in- = 0 v v in+ = 200 mvp-p sine wave remark the graphs indicate nominal characteristics.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 12 of 19 aug 31, 2015 signal delay time vs. ambient temperature signal delay time pd (s) ambient temperature ta (c) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 -50-25 0 255075100125 t pd90 t pd50 t pd10 t f t r v dd1 = v dd2 = 5 v v in- = 0 v v in+ = 0 to 150 mv step remark the graphs indicate nominal characteristics.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 13 of 19 aug 31, 2015 taping specifications (unit: mm) tape direction outline and dimensions (tape) outline and dimensions (reel) packing: 2 000 pcs/reel 3302.0 1001.0 2.00.5 13.00.2 r 1.0 21.00.8 2.00.5 23.9 to 27.4 outer edge of flange 25.51.0 29.51.0 2.00.1 4.00.1 6.350.1 8.00.1 2.0 +0.1 ?0 1.5 +0.1 ?0 +0.3 ?0.1 4.050.1 1.750.1 24.0 4.5 max. 12.0 0.1 0.35 11.50.1 ps9332l2-e3 ps8352al2-e3
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 14 of 19 aug 31, 2015 recommended mount pad dimensions (unit: mm) part number lead bending a bcd d c b a ps9307l2 lead bending type (gull-wing) for long creepage distance (surface mount) 10.2 1.27 0.8 2.2 ps9332l2 ps8352al2
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 15 of 19 aug 31, 2015 notes on handling 1. recommended soldering conditions (1) infrared reflow soldering ? peak reflow temperature 260 ? c or below (package surface temperature) ? time of peak reflow temperature 10 seconds or less ? time of temperature higher than 220 ? c 60 seconds or less ? time to preheat temperature from 120 to 180 ? c 120 ? 30 s ? number of reflows three ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) 12030 s (preheating) 220 c 180 c package surface temperature t ( c) time (s) recommended temperature profile of infrared reflow (heating) to 10 s to 60 s 260 c max. 120 c (2) wave soldering ? temperature 260 ? c or below (molten solder temperature) ? time 10 seconds or less ? preheating conditions 120 ? c or below (package surface temperature) ? number of times one (allowed to be dipped in solder including plastic mold portion.) ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) (3) soldering by soldering iron ? peak temperature (lead part temperature) 350 ? c or below ? time (each pins) 3 seconds or less ? flux rosin flux containing small amount of chlorine (the flux with a maximum chlorine content of 0.2 wt% is recommended.) (a) soldering of leads should be made at the poi nt 1.5 to 2.0 mm from the root of the lead
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 16 of 19 aug 31, 2015 (4) cautions ? fluxes avoid removing the residual flux with freon-based and chlorine-based cleaning solvent. 2. cautions regarding noise be aware that when voltage is applied suddenly between the photocoupler?s input and output at startup, the output transistor may enter the on state, even if the voltage is within the absolute maximum ratings. usage cautions 1. usage cautions (1) this product is weak for static electricity by designed wi th high-speed integrated circuit so protect against static electricity when handling. (2) when the primary power supply (v dd 1) is off and only the secondary power supply (v dd 2) is being applied (v dd 1 = 0 v and v dd 2 = 5 v), v out+ outputs a low level, and v out ? outputs a high level (v out+ = 1.3 v typ., v out? = 3.8 v typ.), regardless of the input voltages (v in+ and v in ? ). (3) the output level of v out+ and v out ? might be unstable for several seconds immediately after the secondary power supply (v dd 2) is applied while the primary power supply (v dd 1) is being applied. 2. board designing (1) by-pass capacitor of more than 0.1 ? f is used between v cc and gnd near device. also, ensure that the distance between the leads of the photocouple r and capacitor is no more than 10 mm. (2) keep the pattern connected the input (v in+ , v in- ) and the output (v out+ , v out- ), respectively, as short as possible. (3) do not connect any routing to the portion of t he frame exposed between the pins on the package of the photocoupler. if connected, it will affect the photocoupler's internal voltage and the photocoupler will not operate normally. (4) because the maximum frequency of the signal input to the photocoupler must be lower than the allowable frequency band, be sure to connect an anti-a liasing filter (an rc filter with r = 68 ?? and c = 0.01 ? f, for example). (5) the signals output from the ps8352a include noise el ements such as chopping noise and quantization noise generated internally. therefore, be sure to restrict t he output frequency to the required bandwidth by adding a low-pass filter function (an rc filter with r =10 k ? and c = 150 pf, for example) to the operational amplifier (post amplifier) in the next stage to the ps8352a. 3. avoid storage at a high temperature and high humidity.
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 17 of 19 aug 31, 2015 specification of vde marks license document parameter symbol spec. unit climatic test class (iec 60068-1/din en 60068-1) 40/110/21 dielectric strength maximum operating isolation voltage test voltage (partial discharge test, procedure a for type test and random test) u pr = 1.5 ? u iorm , p d ? 5 pc u iorm u pr 1 130 1 695 v peak v peak test voltage (partial discharge te st, procedure b for all devices) u pr = 1.875 ? u iorm , p d ? 5 pc u pr 2 119 v peak highest permissible overvoltage u tr 8 000 v peak degree of pollution (din en 60664-1 vde0110 part 1) 2 comparative tracking index (iec 60112/din en 60112 (vde 0303 part 11)) cti 175 material group (din en 60664-1 vde0110 part 1) iii a storage temperature range t stg ?55 to +125 c operating temperature range t a ?40 to +110 c isolation resistance, minimum value v io = 500 v dc at t a = 25c v io = 500 v dc at t a max. at least 100c ris min. ris min. 10 12 10 11 ? ? safety maximum ratings (maximum permi ssible in case of fault, see thermal derating curve) package temperature current (input current i f , psi = 0) power (output or total power dissipation) isolation resistance v io = 500 v dc at t a = tsi tsi isi psi ris min. 175 400 700 10 9 c ma mw ? dependence of maximum safety ratings with package temperature 0 100 200 300 400 500 600 700 800 900 1000 0 25 50 75 100 125 150 175 200 package temp tsi (c) total power dissipation psi (mw) input current isi (ma) psi: total power dissipation isi: input current
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 18 of 19 aug 31, 2015 method a destructive test , type and sample test t 1 t ini t 2 t 3 t m t 4 v initial =8000v v pr =1808v v iorm =1130v v t t 1 ,t 2 = 1 to 10 sec t 3 ,t 4 = 1 sec t m(partial discharge) = 10 sec t test = 12 sec t ini = 60 sec t test method b non-destructive test, 100% production test v pr =2119v v iorm =1130v t 3 t p t 4 v t 3 ,t 4 = 0.1 sec t m(partial discharge) = 1.0 sec t test = 1.2 sec t test t
ps8352al2 chapter title r08ds0132ej0100 rev.1.00 page 19 of 19 aug 31, 2015 caution gaas products this product uses gallium arsenide (gaas). gaas vapor and powder are hazardous to human health if inhaled or ingested, so please observe the following points. ? follow related laws and ordinances when disposi ng of the product. if there are no applicable laws and/or ordinances, dispose of the product as recommended below. 1. commission a disposal company able to (with a license to) collect, transport and dispose of materials that contain arsenic and other such industrial waste materials. 2. exclude the product from general industrial waste and household garbage, and ensure that the product is controlled (as industrial waste subjec t to special control) up until final disposal. ? do not burn, destroy, cut, crush, or chemically dissolve the product. ? do not lick the product or in any way allow it to enter the mouth.
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(note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. california eastern laboratories, inc. 4590 patrick henry drive, santa clara, california 95054-1817, u.s.a. tel: +1-408-919-2500, fax: +1-408-988-0279 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-6503-0, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. room 1709, quantum plaza, no.27 zhichunlu haidian district, beijing 100191, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 301, tower a, central towers, 555 langao road, putuo district, shanghai, p. r. china 200333 tel: +86-21-2226-0888, fax: +86-21-2226-0999 renesas electronics hong kong limited unit 1601-1611, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2265-6688, fax: +852 2886-9022 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei 10543, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre, singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 1207, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics india pvt. ltd. no.777c, 100 feet road, hal ii stage, indiranagar, bangalore, india tel: +91-80-67208700, fax: +91-80-67208777 renesas electronics korea co., ltd. 12f., 234 teheran-ro, gangnam-gu, seoul, 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2016 renesas electronics corporation. all rights reserved. colophon 5.0

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