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benefit s and features ? easily add traceability and relevant information to any individual system o 1k - bit eprom with page - level write prot ection and guaranteed unique 64 -b it rom id chip for absolute traceability o 1024 b its electrically programmable read only memory (eprom) o unique, factory - lasered and tested 64 -b it registration number (8 -b it family code + 48 -b it serial number + 8 -b it crc tester) o eprom partitioned i nto four 256 -b it pages for randomly accessing packetized data o each memory page can b e permanently write - protected to prevent tampering o device is an add only memory where additional data c an b e programmed i nto eprom without disturbing existing data o architecture allows software to patch data by superseding an old page in favor of a newly pro grammed page o 8-b it family code specifies ds2502 communications requirements to reader ? minimalist 1 - wire interface lowers cost and interface complexity o reduces control, address, data, power, and programming signals to a single data pin o directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kb per second o built - in multidrop controller ensures compatibility with other 1 - wire net products o presence pulse acknowledges when the reader first applies voltage o low cost to - 92, sfn, or 8 - pin so, sot - 23 (3 p in), tsoc and wlp surface mount package ? wide voltage and temperature operating ranges provide robust system performance o reads over voltage range of 2.8v to 6.0v at - 40c to +85c o zero standby power required o programs at 11.5v to 12.0v f rom - 40c to +50c pin assignment 1 2 +09rrd wlp , top view with laser mark, contacts not visible. rrd = revision/date 1 a, 1b = data 2 a, 2b = gnd a b sfn (approx. 6.0mm x 6.0mm x 0.9mm) bottom view side view 1 2 sfn pinout: pin 1: io pin 2: gnd note: the sfn package is qualified for electro - mechanical contact applications only, not for soldering. for more information, ref er to application note 4132: attachment methods for the electro - mechanical sfn packag e. data 1 2 3 6 5 4 top view tsoc package gnd nc nc nc nc 1 2 3 4 8 7 6 5 nc nc nc nc nc nc data gnd 8- pin so (150 mil) ds2502 1kb add - only memory gnd data nc bottom view to - 92 ds2502 2 3 1 sot - 23 package top view 1 2 3 09rr 1 = data; 2, 3 = gnd rr = revision 19 - 5075; rev 3/15 1 of 2 4 downloaded from: http:///
ds2502 ordering information part temp range pin - package ds2502+ -40c to +85c 3 to -92 (straight leads) ds2502+t&r -40c to +85c 3 to -92 (for med leads, 2k pieces ) ds2502g +t&r -40c to +85c 2 sfn ( 2.5k pieces) ds2502p+ -40c to +85c 6 tsoc ds2502p+t&r -40c to +85c 6 tsoc (4k pieces) ds2502r+ t&r -40c to +85c 3 sot -23 (3k pieces) ds2502s+ -40c to +85c 8 so ds2502s+t&r -40c to +85c 8 so (2.5k pieces) ds2502x1+ -40c to +85c 4 wlp (10k pieces) + denotes a lead (pb) - free /rohs - complian t package. t&r = t ape and reel . description the ds2502 1kb add - only memory identifies and stores relevant information about the product to which it is associate d. this lot - or product - specific information can be accessed with minimal interface - for example, a single port pin of a microcontroller. the ds2502 consists of a factory - lasered registration number that includes a unique 48 - bit serial number, an 8 - bit crc, and an 8 - bit family code (09h) plus 1kb of eprom which is user - programmable. the power to program and read the ds2502 is derived entirely from the 1 - wire ? communication line. data is transferred serially via the 1 - wire protocol which requires only a single data lead and a ground return. the entire device can be programmed and then write - protected if desired. alternatively, the part may be programmed multiple times with new data being appended to, but not overwr iting, existing data with each subsequent programming of the device. note: individual bits can be changed only f rom a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provision is also included f or indicating that a certain page or pages of data are no longer valid and have been replaced with new or updated data that is now residing at an alternate page address. this page address redirec tion allows software to patch data and enhance the flexibility of the device as a stand - alone database. the 48 - bit serial number that is factory - las ered into each ds2502 provides a guaranteed unique identity which allows for absolute traceability. the familiar to - 92 or soic or tsoc packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printe d circuit boards or wiring. typical applications include storage of calibration constants, maintena nce records, asset tracking, product revision status, and access codes. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2502. the ds2502 has three main data components: 1) 64 - bit lasered rom, 2) 1024 - bit eprom, and 3) eprom status bytes. the device derives its power for read operations ent irely from the 1 - wire communication line by storing energy on an internal capacitor during periods of time when the signal l ine is high and continues to operate off of this parasite power source during the low tim es of the 1 - wire line until it returns high to replenish the parasite (capacitor) su pply. during programming, 1 - wire communication occurs at normal voltage levels and then is pulsed momentarily to the pro gramming voltage to cause the selected eprom bits to be programmed. the 1 - wire line must be able to provide 12 volts and 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltages are present on the 1 - wire line a special high voltage detect circuit within the ds2502 generates an internal logic signal to indicate this condition. the hierarc hical str ucture of the 1 - wire protocol is shown in figure 2. the bus master must first provide one of the six rom f unction commands, 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64 - bit lasered rom portion of each device and can singulate a specific device if many are present on 1- wire is a registered trademark of maxim integrated products, in c. 2 of 2 4 downloaded from: http:///
ds2502 the 1 - wire line as well as indicate to the bus master how many and what types of devices are p resent. the protocol required for these rom function commands is described in figure 9. after a rom functi on command is successfully executed, the memory functions that operate on the eprom portions of the ds2502 become accessible and the bus master may issue any one of the five memory fu nction commands specific to the ds2502 to read or program the various data fields. the protocol f or these memory function commands is described in figure 5. all data is read and written lea st significant bit first. 64 - bit lasered rom each ds2502 contains a unique rom code that is 64 bits long. the first 8 bits are a 1 - wire fam ily code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3). the 64 - bit rom and rom function control section allow the ds2502 to operate as a 1 - wire device and follow the 1 - wire protocol detailed in the section 1 - wire bus system. the memory functions required to read and program the eprom sections of the ds2502 are not accessible until the ro m function protocol has been satisfied. this protocol is described in the rom functions flow char t (figure 9). the 1 - wire bus master must first provide one of four rom function commands: 1) read rom, 2) m atch rom, 3) search rom, or 4) skip rom. after a rom function sequence has been successfully e xecuted, the bus master may then provide any one of the memory function commands specific to the ds2502 (figure 6). the 1 - wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. figure 4 shows a hardware implementation of this crc generator. additional information about the maxim 1- wire cyclic redundancy check is available in application note 27 . the shift register acting as the crc accumulator is initialized to 0. then starting with the least significant bit of the f amily code, 1 bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all 0s. ds 2502 block diagram figure 1 parasite power data 1- wire bus 64 - bit lasered rom 1- wire function control program voltage detect memory function control 8- bit scratchpad 8- bit crc generator 1024 - bit eprom (4 pages of 32 bytes) status bytes eprom 3 of 24 downloaded from: http:///
ds2502 hierarchical structure for 1 - wire protocol figure 2 64 - bit lasered rom figure 3 8C bit crc code 48C bit serial number 8Cbit family code (09h) msb lsb msb lsb msb lsb 1- wire crc generator figur e 4 4 of 24 downloaded from: http:///
ds2502 1024 - bits eprom the memory map in figure 5 shows the 1024 - bit eprom section of the ds2502 which is configured as four pages of 32 bytes each. the 8 - bit scratchpad is an additional register that acts as a buffer when programming the memory. data is first written to the scratchpad and then verified by reading an 8 - bit crc from the ds2502 that confirms proper receipt of the data. if the buffer contents are correct, a programming voltage should be applied and the byte of data will be written into the s elected address in memory. this process ensures data integrity when programming the memory. t he details for reading and programming the 1024 - bit eprom portion of the ds2502 are given in the memory function commands section. eprom status bytes in addition to the 1024 bits of data memory the ds2502 provides 64 bits of status memory accessible with separate commands. the eprom status bytes can be read or programmed to indicate various conditions to the software interrogating the ds2502. the first byte of the eprom status memory contain the write protect page bits which inhibit programming of the corresponding page in the 1024 - bit main memory area if the appropriate write protection bit is programmed. once a bit has been programmed i n the write protect page byte, the entire 32 - byte page that corresponds to that bit can no longer be altered but may still be read. the next 4 bytes of the eprom status memory contain the page address redirect ion bytes, which indicate if one or more of the pages of data in the 102 4- bit eprom section have been invalidated and redirected to the page address contained in the appropriate redirection byte. the hardware of the ds2502 makes no decisions based on the contents of the page address redirection bytes. t hese additional bytes of status eprom technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space permitting, an entire page of data can be redirected to another page within the ds2502 by writing the ones complement of the new page addr ess into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the u sers software to make a data patch to the eprom by indicating that a particular page or pages should be replaced with those indicated in the page addres s redirection bytes. if a page address redirection byte has an ffh value, the data in the main memor y that corresponds to that page is valid. if a page address redirection byte has some other hex valu e, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the ones complement of the page address indicated by the hex value stored in the associated pag e address redirection byte. a value of fdh in the redirection byte for page 1, for exam ple, would indicate that the updated data is now in page 2. the details for reading and programming the eprom s tatus memory portion of the ds2502 are given in the memory function commands section. memory function commands the memory function flow chart (figure 6) describes the protocols necessa ry for accessing the various data fields within the ds2502. the memory function control section, 8 - bit scratchpad, and the program voltage detect circuit combine to interpret the commands issued by the bu s master and create the correct control signals within the device. a 3-byte protocol is issued by the bus ma ster. it is comp rised of a command byte to determine the type of operation and two address bytes to determine t he specific starting byte location within a data field. the command byte indicates if the device is to be read or 5 of 24 downloaded from: http:///
ds2502 written. writing data involves not only issuing the correct command sequence by also providing a 12 -volt programming voltage at the appropriate times. to execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into the selected address. write sequ ences always occur a byte at a time. to execute a read sequence, the starting address is issued by the bus master and data is read from the part beginning at that initial location and continuing to the end of the sele cted data field or until a reset sequence is issued. a ll bits transferred to the ds2502 and received back by the bus master are sent least significant bit first. ds2502 memory map figure 5 6 of 24 downloaded from: http:///
ds2502 memory function flow chart figure 6 7 of 24 downloaded from: http:///
ds2502 memory function flow chart figure 6 (contd) legend: decision made by the master decision made by ds2502 8 of 24 downloaded from: http:///
ds2502 memory function flow chart figure 6 (contd) 9 of 24 downloaded from: http:///
ds2502 read memory [ f0h ] the read memory command is used to read data from the 1024 - bit eprom data field. the bus master follows the command byte with a 2 - byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte loca tion within the data field. an 8 - bit crc of the command byte and address bytes is computed by the ds2502 and read back by the bus master to confirm that the correct command word and starti ng address were received. if the crc read by the bus master is incor rect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is corr ect, the bus master issues read time slots and receives data from the ds2502 starting at the initial address a nd continuing until the end of the 1024 - bit data field is reached or until a reset pulse is issued. if reading occurs throu gh the end of memory space, the bus master may issue eight additional read time slots and the ds2502 will respond with a 8 - bit crc of all data bytes read fro m the initial starting byte through the last byte of memory. after the crc is received by the bus master, any subsequent read time slots wi ll appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the e nd of memory will not have the 8 - bit crc available. typically a 16 - bit crc would be stored with each page of data to ensure rapid, error - free data transfers that eliminate having to read a page multiple times to determine if the received data is corr ect or not. (see application note 114 for the recommended file structure.) if crc values are imbedded within the dat a, a reset pulse may be issued at the end of memory space during a read memory command. read status [ aah] the read status command is used to read data from the eprom status data field. the bus master follows the command byte with a 2 - byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data field. an 8 - bit crc of the command byte and address bytes is computed b y the ds2502 and read back by the bus master to confirm that the correct command word and starti ng address were received. if the crc read by the bus master is incorrect, a reset puls e must be issued and the entire sequence must be repeated. if the crc received by the bus master is corr ect, the bus master issues read time slots and receives data from the ds2502 starting at the supplied address and continuing until the end of the eprom status data field is reached. at that point the bus master will r eceive an 8- bit crc that is the result of shifting into the crc generator all of the data bytes from the initial s tarting byte through the final factory-programmed byte that contains the 00h value. this feature is provided since the eprom status information may ch ange over time making it impossible to program the data once and include an accompanying crc that will always be vali d. therefore, the read status command supplies a 8 - bit crc that is based on and always is consistent with the current data stored in the ep rom status data field. after the 8 - bit crc is read, the bus master will receive logical 1s from the ds2502 until a res et pulse is issued. the read status command sequence can be ended at any point by issuing a reset pulse. read data/generate 8 - bit crc [ c3h ] the read data/generate 8 - bit crc command is used to read data from the 1024 - bit eprom data field. the bus master follows the command byte with a 2 - byte address (ta1=(t7:t0), ta2=(t15:t8)) that indicates a starting byte location within the data fiel d. an 8 - bit crc of the command byte and address bytes is computed by the ds2502 and read back by the bus master to confirm that the corre ct command word and starting address were received. if the crc read by the bus master is i ncorrect, a reset pulse must be issued and the entire sequence must be repeated. if the crc received by the bus m aster is correct, the bus master issues read time slots and receives data from the d s2502 starting at the initial address and continuing until the end of a 32 - byte page is reached. at that point the bus master will send 10 of 24 downloaded from: http:///
ds2502 eight additional read time slots and receive an 8 - bit crc that is the result of shifting into the crc generator all of the data bytes from the initial starting byte to the last byte of the cu rrent page. once the 8 - bit crc has been received, data is again read from the 1024 - bit eprom data field starting at the next page. this sequence will continue until the final page and its accompanying crc are read by the bus master. thus each page of data can be considered to be 33 bytes long: the 32 bytes of user - programmed eprom data and an 8 - bit crc that gets generated automatically at the end of each page. this type of read differs from the read memory command which simple reads each pa ge until the end of address space is reached. the read memory command only generates an 8 -bit crc at the end of memory space that often might be ignored, since in many applications the user would store a 16 - bit crc with the data itself in each page of the 1024 - bit eprom data field at the time the page was programmed. the read data/generate 8 - bit crc command provides and alternate read capability for applications that are bit - oriented rather than page - oriented where the 1024 - bit eprom information may change over time within a page boundary making it impossible to program the page once and include an accompanying crc that will always be valid. therefore, the read data/generate 8 - bit crc command concludes each page with the ds2502 generating and supplying an 8 - bit crc that is based on and therefore is always consistent with the current data stored in each page of the 1024 - bit eprom data field. after the 8 - bit crc of the last page is read, the bus master will receive logical 1s from the ds25 02 until a reset pulse is issued. the read data/generate 8 - bit crc command sequence can be exited at any point by issuing a reset pulse. write memory [ 0fh ] the write memory command is used to program the 1024 C bit eprom data field. the bus master will follow the command byte with a 2 - byte starting addr ess (ta1 = (t7:t0), ta2 = (t 1 5:t8)) and a byte of data (d7:d0). an 8 - bit crc of the command byte, address bytes, and data byte is computed by the ds2502 and read back by the bus master to confirm that the correct command word, sta rting address, and data byte were received. the highest starting address within the ds2502 is 007fh. if the bus master sends a st arting address higher than this, the nine 9 most significant address bits are set to 0 by the internal circuitry of the chip. this will result in a mism atch between the crc calculated by the ds2502 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a reset pulse must be issued and th e entire sequence must be repeated. if the crc receiv ed by the bus master is correct, a programming pulse (12 volts on the 1 - wire bus for 480 s) is issued by the bus master. prior to programming, the entire unpr ogrammed 1024 - bit eprom data field will appear as logical 1s. for each bit in the data byte prov i ded by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 1024 - bit eprom will be programmed to a logical 0 after the programming pulse has been applied at tha t byte location. after the 480 s programming pulse is applied and the data line returns to a 5 - volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programm ed. the ds2502 responds with the data from the selected eprom address sent least significa nt bit first. t his byte contains the logical and of all bytes written to this eprom data address. if the eprom data byte contains 1s in bit positions where the byte issued by the master contains 0s, a reset pulse should be i ssued and the current byte address should be programmed again. if the ds2502 eprom data byte conta ins 0s in the same bit positions as the data byte, the programming was successful and the ds 2502 will automatically increment its address counter to select the next byte in the 1024 - bit eprom data field. the least 11 of 24 downloaded from: http:///
ds2502 significant byte of the new two - byte address will also be loaded into the 8 - bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2502 receives this byte of data into the scratchpad, it also shifts the data into the crc generator that has been preloaded with the lsb of the current address; the result is an 8 - bit crc of the new data byte and the lsb of the new address. after supplying the data byte, the bu s master will read th is 8 - bit crc from the ds2502 with eight read time slots to confirm that the address increme nted properly and the data byte was received correctly. if the crc is incorrect, a reset pulse mu st be issued and the write memory command sequence must be restarted . if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write memory flow chart will generate an 8 - bit crc value that is the result of shifting the c ommand byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write memory flow chart due t o the ds2502 automatically incrementing its address counter will generate an 8 - bit crc that is the result of loading (not shifting) the lsb of the new (incremented) address into the crc generator and t hen shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2502) i s made entirely by the bus master, since the ds2502 will not be able to determine if the 8 - bit crc calculated by the bus master agrees with the 8 - bit crc calculated by the ds2502. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorrect programming could occur within the ds2502. also note that the ds2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the dec ision to continue is again made e ntirely by the bus master, therefore if the eprom data byte does not match the supplied data byte does not match the supplied data byte but the master but the master continues with the write memory command, incorrect programming could occur within the ds2502. the write m emory command sequence can be exited at any point by issuing a reset pulse. write status [ 55h ] the write status command is used to program the eprom status data field. the bu s master will follow the command byte with a 2 - byte starting ad dress (ta1=(t7:t0), ta2=(t15:t8)) and a byte of status data (d7:d0). an 8 - bit crc of the command byte, address bytes, and data byte is computed by the ds2502 and read back by the bus master to confirm that the correct command word, starting a ddress, and da ta byte were received. if the crc read by the bus master is incorrect, a reset pulse must be issued and th e entire sequence must be repeated. if the crc received by the bus master is correct, a progra mming pulse (12 volts on the 1 - wire bus for 480 s) is issued by the bus master. prior to programming, the first 7 bytes of the epro m status data field will appear as logical 1s. for each bit in the data byte provide d by the bus master that is set to a logical 0, the corresponding bit in the selected byte of t he eprom status data field will be programmed to a logical 0 after the programming pulse has been applied at t he byte location. the 8 th byte of the eprom status byte data field is factory -programmed to contain 00h. after the 480 s programming pulse is applied and the data line returns to a 5 - volt level, the bus master issues eight read time slots to verify that the appropriate bits have been programm ed. the ds2502 responds with the data from the selected eprom status address sent least sign ificant bit first. this byte contains the logical and of all bytes written to this eprom status byte address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a r eset pulse should be 12 of 24 downloaded from: http:///
ds2502 issued and the current byte address should be programmed again. if the ds2502 eprom st atus byte contains 0s in the same bit positions as the data byte, the programming was success ful and the ds2502 will automatically increment its address counter to select the next byte in the epro m statu s data field. the least significant byte of the new 2 - byte address will also be loaded into the 8 - bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2502 receives this byte of data into the scratchpad, it also shifts the data into the crc generator that has been preloaded with the lsb of the current address and the result is a n 8-bit crc of the new data byte and the lsb of the new address. after supplying the data byte, the bus ma st er will read this 8 - bit crc from the ds2502 with eight read time slots to confirm that the address increme nted properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be issued and the write status command sequence mu st be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write status flow chart will generate an 8 - bit crc value that is the result of shifting the command byte into the crc generator, followed by the 2 address b ytes, and finally the data byte. subsequent passes through the write status flow chart due to the ds2502 aut omatically incrementing its address counter will generate an 8 - bit crc that is the result of loading (not shifting) the lsb of the new (incremented) address into the crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2502) i s made entire ly by the bus master, since the ds2502 will not be able to determine if the 8 - bit crc calculated by the bus master agrees with the 8 - bit crc calculated by the ds2502. if an incorrect crc is ignored and a program pulse is applied by the bus master, incorrect programming could occur within t he ds2502. also note that the ds2502 will always increment its internal address counter after the receipt of the eight read time slots used to confirm the programming of the selected eprom byte. the dec ision to continue is again made entirely by the bus master, therefore if the eprom data byte does no t match the supplied data byte but the master continues with the write status command, incorrect progr amming could occur within the ds2502. the write status command sequence can be ended at any point by issui ng a reset pulse. 1-w ire bus system the 1 - wire bus is a system which has a single bus master and one or more slaves. in all inst ances, the ds2502 is a slave device. the bus master is typically a microcontroller. the disc ussion of this bus system is broken down into three topics: hardware configuration, transaction se quence, and 1 - wire signaling (signal type and timing). a 1 - wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, ea ch device attached to the 1 - wire bus must have an open drain connection or three - state outputs. the ds2502 is an open drain part with an internal circuit equivalent to that shown in figure 7. the bus master can be the same equivalent circuit. if a bi - direc tional pin is not available, separate output and input pins can be tied together. the bus master requires a pullup resistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figures 8a and 8b. the value of the pullup resistor should be approximately 5 k? for short line lengths. 13 of 24 downloaded from: http:///
ds2502 a multidrop bus consists of a 1 - wire bus with multiple slaves attached. at regular speed the 1 - wire bus has a maximum data rate of 16.3 kbits per second. if the bus master is also required to p erform programming of the eprom portions of the ds2502, a programming supply capable of delive ring up to 10 milliamps at 12 volts for 480 s is required. the idle state for the 1 - wire bus is high. if, for any reason, a transaction needs to be suspended, th e bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of t he devices on the bus may be reset. transaction sequence the sequence for accessing the ds2502 via the 1 - wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization sequence consists of a re set pulse transmitted by the bus master followed by a presence pulse(s) tran smitted by the slave(s). the presence pulse lets the bus master know that the ds2502 is on the bus and is ready to oper ate. for more details, see the 1 - wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the six rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 9): read rom [ 33h ] this command allows the bus master to read the ds2502s 8 - bit family code, unique 48 - bit serial number, and 8 - bit crc. this command can be used only if there is a single ds2502 on the bus. if more than one slave is present on the bus, a data collision will occur wh en all slaves try to transmit at the same time (open drain will produce a wired- and result). match rom [ 55h ] the match rom command, followed by a 64 - bit rom sequence, allows the bus master to address a specific ds2502 on a multidrop bus. only the ds250 2 that exactly matches the 64 - bit rom sequence will respond to the subsequent memory function command. all slaves that do not match the 64 - bit rom sequence will wait for a reset pulse. this command can be used with a single or multipl e devices on the bus. 14 of 24 downloaded from: http:///
ds2502 ds2502 equivalent circuit figure 7 bus master circuit figure 8 15 of 24 downloaded from: http:///
ds2502 rom functions flow chart figure 9 16 of 24 downloaded from: http:///
ds2502 skip rom [ cch ] this command can save time in a single - drop bus system by allowing the bus master to access the memory functions without providing the 64 - bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on t he bus as multiple slaves transmit simultaneously (open drain pulldowns will produce a wired- a nd result). search rom [ f0h ] when a system is initially brought up, the bus master might not know the number of devices on the 1 - wire bus or their 64 - bit rom codes. the search rom command allows the bus master to use a process of elimination to identif y the 64 - bit rom codes of all slave devices on the bus. the rom search process is the repetition of a simple, three - step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, thr ee - step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. t he remaining number of devices and their rom codes may be identified by additional passes. see application note 187 for a comprehe nsive discussion of a rom search, including an actual example. 1- wire signaling the ds2502 requires strict protocols to ensure data integrity. the protocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse , write 0, write 1, read data and program pulse. all these signals except presence pulse are initiated by t he bus master. the initialization sequence required to begin any communication with the ds2502 is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds2502 is ready to accep t a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1 - wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data pin, the ds2502 waits (t pdh , 15 - 60 s) and then transmits the presence pulse (t pdl , 60-240 s). read/write time slots the definitions of write and read time slots are illustrated in figure 11. a ll time slots are initiated by the master driving the data line low. the falling edge of the data line synchronize s the ds2502 to the master by triggering a delay circuit in the ds2502. during write time slots, the delay cir cuit determines when the ds2502 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the de lay circuit determines how long the ds2502 will hold the data line low overriding the 1 generat ed by the master. if the data bit is a 1, the device will leave the read data time slot unchanged. program pulse to copy data from the 8 - bit scratchpad to the 1024 - bit eprom memory or status memory, a program pulse of 12 volts is applied to the data line after the bus master has confirmed that t he crc for the current byte is correct. during programming, the bus master controls the transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively dr iven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the ds2502. this programming voltag e (figure 12) should be applied for 480 s, after which the bus master returns the data li ne to an idle high state controlled by the pullup resistor. note that due to the high - voltage programming requi rements for any 1 - wire eprom device, it is not possible to multidrop non - eprom based 1 - wire devices with the ds2502 during programming. an internal diode within the non - eprom based 1 - wire devices will attempt to clamp the data line at approximately 8 volt s and could potentially damage these devices. 17 of 24 downloaded from: http:///
ds2502 crc generation the ds2502 has an 8 - bit crc stored in the most significant byte of the 64 - bit rom. the bus master can compute a crc value from the first 56 bits of the 64 - bit rom and compare it to the value sto red within the ds2502 to determine if the rom data has been received error - free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 +1. under certain conditions, the ds2502 also generates an 8 - bit crc value using the same po lynomial function shown above and provides this value to the bus master to validate the transfer of command, address, and data bytes from the bus master to the ds2502. the memory function flow chart of figure 6 indicates that the ds2502 computes an 8 - bit c rc for the command, address, and data bytes received for the write memory and the write status commands and then outputs this value to the bus mas ter to confirm proper transfer. similarly the ds2502 computes an 8 - bit crc for the command and address bytes r eceived from the bus master for the read memory, read status, and read data/generat e 8 - bit crc commands to confirm that these bytes have been received correctly. the crc gen erator on the ds2502 is also used to provide verification of error - free data transf er as each page of data from the 1024 - bit eprom is sent to the bus master during a read data/generate 8 - bit crc command, and for the 8 bytes of information in the status memory field. in each case where a crc is used for data transfer validation, the bus master must calculate a crc value using the polynomial function given above and compare the calculated value to either the 8 - bit crc value stored in the 64 - bit rom portion of the ds2502 (for rom reads) or the 8 - bit crc value computed within the ds2502. the comparison of crc values and decision to continue with an operation are determined entirely by the bus master. there is no circuitry on the ds2502 that pre vents a command sequence from proceeding if the crc stored in or calculated by the ds2502 does not match t he value generated by the bus master. proper use of the crc as outlined in the flow chart of f igure 6 can result in a communication channel with a very high level of integrity. for more details on ge nerating crc values including example implementati ons in both hardware and software, see application note 27 . initialization procedure reset and presence pulses figure 10 resistor master ds2502 480s t rstl < 960s 480s t rsth < (includes recovery time) 15s t pdh < 60s 60s t pdl < 240s 18 of 24 downloaded from: http:///
ds2502 read/write timing diagram figure 11 write - one time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < writ e- zero time slot 60 s t low0 < t slot < 120 s 1 s t rec < read - data time slot 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s ds2502 sampling window ds2502 sampling window resistor master ds2502 19 of 24 downloaded from: http:///
ds2502 program pulse timing diagram fi gure 12 20 of 24 downloaded from: http:///
ds2502 absolute maximum ratings voltage on any pin relative to ground -0.5v to +12.0v operating temperature -40c to +85c storage temperature -55c to +125c lead temperature (to -92, tsoc, sot23-3, soic only, soldering 10s) +300c soldering temperat ure (reflow) to -92 +250c tsoc, sot -23, soic , wlp +260c sfn refer to application note 4132: attachment methods for the electro -mechanical sfn package. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods of time may affect reliability. dc electrical characteristics (t a = - 40c to +85c) parameter symbol min typ max units notes pullup voltage v pup 2.8 6 v 1, 2 logic 1 v ih 2.2 v 1, 6 logic 0 v il -0.3 +0.8 v 1, 11 output logic low @ 4 ma v ol 0.4 v 1 input load current i l 5 a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v valid eprom read voltage v epr 2.8 6.0 v 13 capacitance (t a =25c) parameter symbol min typ max units notes data (1 - wire) c in/out 800 pf 9 ac electrical c haracteristics (t a = - 40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s write 0 low time t low0 60 120 s read data valid t rdv exactly 15 s release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 reset time low t rstl 480 960 s 14 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s delay to program t dp 5 s 10 delay to verify t dv 5 s 10 program pulse width t pp 480 5000 s 10, 12 program voltage rise time t rp 0.5 5.0 s 10 program voltage fall time t fp 0.5 5.0 s 10 21 of 24 downloaded from: http:///
ds2502 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. 3. input load is to ground. 4. an additional reset or communication sequence cannot begin until the reset high time has expired. 5. read data setup time refers to the time the host must pull the 1 - wire bus low to read a bit. data is guaranteed to be valid within 1 s of th is falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1 -wire bus.) 6. v ih is a function of the external pullup resistor and the pull-up voltage. 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5 k ? pullup to v cc and a maximum time slot of 120 s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? resistor is used to pullup the data line to v cc , 5 s after power has been applied the parasite capacitance will not affect nor mal communications. 10. maximum 1 - wire voltage for programming parameters is 11.5v to 12.0v; temperature range is -40c to +50c. 11. under certain low - voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 12. the accumulative duration of the programming pulses for each address must not exce ed 5 ms. 13. ic operation and 1 - wire communication is valid at v pup =2.5v or higher, but eprom data read is only valid when v pup =2.8v or higher. 14. reset low pulse on dq must be preceded by a valid t rec recovery time above the minimum v pup voltage of 2.5v. 22 of 24 downloaded from: http:///
ds2502 package information for the latest package outline information and land patterns (footprints) , go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardl ess of rohs status. package type package code outline no. land pattern no. 3 to -92 (straight leads) q3+1 21 - 0248 3 to -92 (formed leads) q3+4 21-0250 2 sfn g266n+1 21-0390 6 tsoc d6+1 21-0382 90-0321 3 sot -23 u3+5 21-0051 90-0179 8 so s8+2 21-0041 90-0096 4 wlp n40d1+1 21 - 0723 refer to 21-0723 23 of 24 downloaded from: http:///
ds2502 r evision history revision date description pages changed 102199 conversion to new template. a ll 030806 sot -23 package added, lead (pb)-free part numbers added. 1, 2 032307 flip chip package added. 1, 2 071107 note added that to-92 tape & reel has formed leads. 1 12/09 added note to figure 10 that changed t rstl to 960 s maximum. 18 added v epr specification. changed t rstl to 960 s maximum. 21 added notes 13 and 14 to electrical characteristics table. 22 12/11 added sfn package, cleaned up ordering information ; t ypo corrections. 1, 2, 5, 9, 11 updated lead temperature and soldering information. 21 moved v pup from electrical characteristics table header to table body, deleted v oh from the electrical characteristics table. 21 added package information section ; extended revision history . 23, 24 8/14 replaced flip chip variant with wlp package 1, 2, 21, 23 3/15 updated benefits and features section 1 24 of 2 4 maxim cannot assume responsibility for use of any circuitry other than circuitry ent irely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametr ic values (min and max limits) shown in the electrical characteristics table are gua ranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 2015 maxim integrated products the maxim logo and maxim integrated are trademarks of maxim integr ated products, inc. downloaded from: http:///

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