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as1339 650ma rf step-down dc-dc for pa, with two ldos www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 1 - 25 datasheet 1 general description the as1339 is a high-frequency step-down converter optimized for dynamically powering the power amplifier (pa) in wcdma or ncdma handsets. the device uses a 110m typical bypass fet to power the pa directly from the battery during high-power transmission. the ic integrates two 10ma low-noise, low-dropout regulators (ldos) for pa biasing. with a switching frequency of 2mhz, the device allows optimization for smallest solution size or highest efficiency. the as1339 supports fast switching using small ceramic 10 f input and 4.7f output capacitors to maintain low ripple voltage. the as1339 uses an analog input driven by an external dac to control the output vo ltage linearly for continuous pa power adjustment. the gain from refin to out is 2.5v/v. at high-duty cycle, the device automatically switches to a bypass mode, connecting the input to the output through a low-impedance mosfet. the ldos are designed for low-noise operation, wherein each ldo in the device is individually enabled through its own logic control interface. the device is available in a 16-pin wlp (2x2mm) package. figure 1. as1339 - typical operating circuit 2 key features fixed switching frequency: 2mhz pa step-down converter low dropout voltage low output-voltage ripple dynamic output voltage control (0.8v to 3.75v) 30s settling time for 0.8v to 3.4v output voltage change 650ma output drive capability two 10ma low-noise ldos low shutdown current supply voltage range: 2.7v to 5.5v thermal shutdown 16-pin wlp (2x2mm) package 3 applications the as1339 is ideal for wcdma/ncdma cellular handsets, wireless pdas, and smartphones. ldo2 on/off ldo1 on/off analog control pa on/off in2 en2 en1 refin pa_en in1b in1a pab paa lx pgnd nc ldo1 ldo2 2.85v 2.85v v pa 0.8v to 3.75v v in 2.7v to 5.5v 4.7f 10f v in 2.7v to 5.5v 2.2h as1339 agnd 0.1f 0.1f 1f test nc ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 2 - 25 as1339 datasheet - pinout 4 pinout figure 2. pin assignments (top view) pin description table 1. pin description pin name pin number description nc a1 not connected. free, high impedance for normal operation. used for internal test purpose. agnd a2 low-noise analog ground refin a3 dac-controlled input. reference voltage for buck converter. the output of the pa step-down converter is regulated to 2.5 x v refin . bypass mode is enabled when v in 2.69v x v refin . pgnd a4 power ground for pa step-down converter ldo2 b1 10ma ldo regulator 2 output. connect ldo2 with a 0.1 f ceramic capacitor as close as possible to ldo2 and agnd. ldo2 is internally pulled down through a 100 resistor when this regulator is disabled. pa_en b2 pa step-down converter enable input. for normal operation, connect to logic-high. for shutdown mode, connect to logic-low. the pin is internally pulled down through a 110k resistor. en2 b3 enable input for ldo2. for normal operation, connect to logic-high. for shutdown mode, connect to logic-low. the pin is internally pulled down through a 110k resistor. lx b4 inductor connection. connect an inductor from lx to the output of the pa step-down converter. nc agnd refin pgnd a1 a2 a3 a4 ldo2 pa_en en2 lx b1 b2 b3 b4 in2 test in1b in1a c1 c2 c3 c4 ldo1 en1 pab paa d1 d2 d3 d4 ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 3 - 25 as1339 datasheet - pinout in2 c1 supply voltage input for ldo1 and ldo2. connect in2 to a battery or supply voltage from 2.7v to 5.5v. decouple in2 with a 1 f ceramic capacitor as close as possible to in2 and agnd. connect in2 to the same source as in1a and in1b. test c2 nc. used for internal test purpose. the pin is internally pulled down with a 110k resistor. in1b, in1a c3, c4 supply voltage input for pa step-down converter. connect in1a/b to a battery or supply voltage from 2.7v to 5.5v. decouple in1a/b with a 10 f ceramic capacitor as close as possible to in1a/b, and pgnd. in1a and in1b are internally connected together. connect in1a/b to the same source as in2. ldo1 d1 10ma ldo regulator 1 output. decouple ldo1 with a 0.1 f ceramic capacitor as close as possible to ldo1 and agnd. ldo1 is internally pulled down through a 100 resistor when this regulator is disabled. en1 d2 enable input for ldo1. for normal operation, connect to logic-high. for shutdown mode, connect to logic-low. the pin is internally pulled down through a 110k resistor. pab, paa d3, d4 pa connection for bypass mode. internally connected to in1a/b using the internal bypass mosfet during bypass mode. connect paa/b with a 4.7 f ceramic capacitor as close as possible to paa/b and pgnd. table 1. pin description pin name pin number description ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 4 - 25 as1339 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other cond itions beyond those indicated in electrical character- istics on page 5 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments in1a, in1b, in2 to agnd -0.3 +7 v paa, pab, pa_en, test, refin, nc to agnd -0.3 v in1a / v in1b + 0.3 v ldo1, ldo2, en1, en2 to agnd -0.3 v in2 + 0.3 v refin common-mode range 0 v in v in2 to in1b/in1a -0.3 +0.3 v pgnd to agnd -0.3 +0.3 v lx current 0.8 a rms bypass current 1.6 a rms human body model 1kv hbm mil-std. 883e 3015.7 methods storage temperature range -65 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020d ?moisture/reflow sensitivity classi fication for no n-hermetic solid state surface mount devices?. continuous power dissipation p d-max 0.75 w t a = +65oc; derate 12.5mw/oc above +65oc junction temperature (t j ) range -40 +125 oc ambient temperature (t a ) range -40 +85 oc in applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be derated. maximum ambient temperature (t a-max ) is dependent on the maximum operating junction temperature (t j-max-op = 125oc), the maximum power dissipation of the device in the application (p d-max ), and the junction-to ambient thermal resistance of the part/package in the application ( ja ), as given by the following equation: t a-max = t j-max-op ? ( ja p d-max ). ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 5 - 25 as1339 datasheet - electrical characteristics 6 electrical characteristics v in1a = v in1b = v in2 = v pa_en = v en1 = v en2 = 3.6v, t a = -40oc to +85oc. typical values are at t a =+25oc, (unless otherwise specified), for external components refer to table 5 on page 7 . table 3. electrical characteristics symbol parameter condition min typ max unit input supply v in input voltage range 2.7 5.5 v i shdn shutdown supply current v pa_en = v en1 = v en2 = 0v 1 0.1 1 a i q dc-dc no-load supply current v en1 = v en2 = 0v, i load(dcdc) = 0ma, switching, v in = 4.5v, v out = 3.4v 4.5 6 ma dcdc output voltage i load load current 650 ma v out output voltage range pwm mode 0.8 3.85 v output voltage v refin = 0.32v, v in = 3.9v 0.75 0.8 0.85 v v refin = 0.84v, v in = 3.9v 2.05 2.1 2.15 v v refin = 1.36v, v in = 3.9v 3.319 3.4 3.481 v thermal protection thermal shutdown t a rising, 10oc typical hysteresis +140 oc logic control pa_en, en1, en2, logic- input high voltage 2.7v v in 5.5v 1.4 v pa_en, en1, en2, logic- input low voltage 2.7v v in 5.5v 0.5 v logic-input current (pa_en, en1, en2) v il = 0v -1 +1 a v ih = v in = 5.5v 50 75 a refin refin operating common-mode range 0.32 1.5 v refin gain v out /v refin 2 v refin = 0.32v 2.35 2.50 2.65 v/v v refin = 0.84v, 1.36v 2.44 2.50 2.56 v/v refin current v refin = v in = 5.5v -1 +1 a lx r dsonp pin-pin resistance for pfet i sw = 200ma; t a = +25c 110 200 m i sw = 200ma 230 r dsonn pin-pin resistance for nfet i sw = -200ma; t a = +25c 230 415 m i sw = -200ma 485 pfet leakage current v in = 5.5v, v lx = 0v 0.1 3 a nfet leakage current v in = v lx = 5.5v 0.1 3 a pfet peak current limit v lx = 0v 1100 ma ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 6 - 25 as1339 datasheet - electrical characteristics system characteristics v in1a = v in1b = v in2 = v pa_en = v en1 = v en2 = 3.9v, t a = -40oc to +85oc. typical values are at t a =+25oc, (unless otherwise specified), for external components refer to table 5 on page 7 . the following parameters are verified by characterisation and are not production tested. f osc internal oscillator frequency 1.8 2 2.2 mhz bypass bypass activation factor v refin rising, 50mv hysteresis 2.56 2.69 2.78 v/v on-resistance bypass pfet i sw = 200ma; t a = +25c 110 200 m i sw = 200ma 230 pfet bypass off-leakage current v in = 5.5v, v paa = v pab = 0v 0.1 3 a ldo1/2 output voltage i out = 0ma, 10ma; 2.75 2.85 2.95 v quiescent current one ldo enabled i out = 0ma 25 50 a both ldos enabled 40 80 output current 10 ma current limit v out = 0v 20 35 50 dropout voltage 3 i out = 10ma 20 50 mv r off shutdown output impedance v en1/2 = 0v 100 1. current into supply pins without leakage of dcdc switches. 2. limited by the 50mv output voltage accuracy for v refin < 0.84v 3. the dropout voltage is the input to output difference at which the output is 100mv below its nominal value. table 4. system characteristics symbol parameter condition min typ max unit refin refin gain variation; relative linearity 1 0.32v v refin 1.4v 3% refin gain variation; absolute linearity 2 0.84v v refin 1.4v -2.4 2.4 % 0.32v v refin 0.84v -50 10 50 mv lx ripple voltage, pwm mode 3 v out = 0.8 to 3.4v, r load = 8 , no bypass mode, no pulse-skip condition 10 25 mvp-p line_tr line transient response v in = 3.4 to 3.9v, v out = 3.0v, i out = 300ma, v in increase 300mv in 10s 30 50 load_tr load transient response v in = 3.4 to 4.2v, v out = 3.0v, t rise = t fall = 10s, i out = 100 to 300ma 50 70 table 3. electrical characteristics (continued) symbol parameter condition min typ max unit ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 7 - 25 as1339 datasheet - electrical characteristics start-up time from pa_en switch from 0v to 1.7v, v out = 3.4v, i load = 0ma, within 50mv regulation error 100 150 s regulation time; rise time v out from 0.8v to 3.4v, r load = 8 , within 50mv regulation error 30 50 regulation time; fall time v out from 3.4v to 0.8v, r load = 8 , within 50mv regulation error 30 50 ldo start-up time i out =10ma, within 100mv of v out 30 50 s shut-down time i out =0ma, within 100mv of gnd 50 100 line regulation 4 v in = 4v to 3.5v; i out = 10ma; 10 mv load regulation i out stepped from 50a to 10ma 25 ripple rejection 5 i out = 4ma, v in = 3.2v, f = 100khz 45 db i out = 4ma, v in = 3.2v, f = 2mhz 45 output noise 6 10hz to 100khz, i out = 10ma 50 100 v rms 1. the relative linearity is defined as the difference of the minimum to the maximum gain over the entire refin range. 2. the absolute linearity is defined as the actual gain error (ae) of every applied v refin voltage between 0.32v and 1.4v. 3. the ripple voltage should measured at c out electrode on good layout pc board and under condition using sug- gested inductors and capacitors. 4. for dynamic change in v out (line transient response) when v in drops 500mv from 4v (see figure 48 on page 15) ; slew rate= 40mv/s. 5. v ripple = 200mvpp; t a = +25c; c in1 , c in2 removed; pa_en = 0v; 6. v in = 3.2v; t a = +25c; pa_en = 3.2v; table 5. external components used for characterisation name part number value rating type size manufacturer c in1 grm21br60j106ke01 10f 6.3v x5r 0805 murata www.murata.com c in2 grm155r61a105ke15 1f 10v x5r 0402 c out c0603c475k8pac7867 4.7f 10v x5r 0603 kemet www.kemet.com c ldo1 , c ldo2 c0402c104k4rac 100nf 16v x7r 0402 l mlp2520s3r3s 3.3h 1a 110m 2.2x2.0x1.4mm tdk www.coilcraft.com table 4. system characteristics (continued) symbol parameter condition min typ max unit ae v out 25 , v refin --------------------------------- 1? ?? ?? 100 = ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 8 - 25 as1339 datasheet - typical operation characteristics 7 typical operation characteristics figure 3. dc-dc efficiency vs. v out ; r load = 5 figure 4. dc-dc efficiency vs. v out ; r load = 7.5 60 65 70 75 80 85 90 95 100 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v bypass mode 60 65 70 75 80 85 90 95 100 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v bypass mode figure 5. dc-dc efficiency vs. v out ; r load = 10 figure 6. dc-dc refin vs. v out ; r load = 5 60 65 70 75 80 85 90 95 100 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v bypass mode 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) refin (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v figure 7. dc-dc refin vs. v out ; r load = 7.5 figure 8. dc-dc refin vs. v out ; r load = 10 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) refin (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 0.6 1 1.4 1.8 2.2 2.6 3 3.4 3.8 output voltage (v) refin (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 9 - 25 as1339 datasheet - typical operation characteristics figure 9. dc-dc efficiency vs. i out ; v out = 0.8v figure 10. dc-dc efficiency vs. i out ; v out = 1.2v 40 50 60 70 80 90 100 1 10 100 1000 output current (m a) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 40 50 60 70 80 90 100 1 10 100 1000 output current (m a) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v figure 11. dc-dc efficiency vs. i out ; v out = 1.8v figure 12. dc-dc efficiency vs. i out ; v out = 2.2v 40 50 60 70 80 90 100 1 10 100 1000 output current (m a) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 40 50 60 70 80 90 100 1 10 100 1000 output current (ma) efficiency (%) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v figure 13. dc-dc load regulation, v out vs. i out ; v out = 0.8v figure 14. dc-dc load regulation, v out vs. i out ; v out = 1.2v 0.76 0.77 0.78 0.79 0.8 0.81 0.82 1 10 100 1000 output current (ma) output voltage (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 1.16 1.17 1.18 1.19 1.2 1.21 1.22 1 10 100 1000 output current (ma) output voltage (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 10 - 25 as1339 datasheet - typical operation characteristics figure 15. dc-dc load regulation, v out vs. i out ; v out = 1.8v figure 16. dc-dc load regulation, v out vs. i out ; v out = 2.2v 1.77 1.78 1.79 1.80 1.81 1.82 1.83 1 10 100 1000 output current (ma) output voltage (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 2.17 2.18 2.19 2.20 2.21 2.22 2.23 1 10 100 1000 output current (ma) output voltage (v) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v figure 17. dc-dc efficiency vs v in ; v out = 3.8v figure 18. dc-dc efficiency vs v in ; v out = 3.4v 80 85 90 95 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) efficiency (%) iout = 300ma iout = 400ma iout = 500ma iout = 600ma pwm mode bypass mode 80 85 90 95 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) efficiency (%) iout = 300ma iout = 400ma iout = 500ma iout = 600ma pwm mode bypass mode figure 19. dc-dc efficiency vs v in ; v out = 2.0v figure 20. dc-dc efficiency vs v in ; v out = 1.5v 60 70 80 90 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) efficiency (%) iout = 300ma iout = 400ma iout = 500ma iout = 600ma 60 70 80 90 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) efficiency (%) iout = 300ma iout = 400ma iout = 500ma iout = 600ma ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 11 - 25 as1339 datasheet - typical operation characteristics figure 21. dc-dc efficiency vs input voltage; v out = 1.0v figure 22. dc-dc line regulation, v out vs. v in ; v out = 3.8v 60 70 80 90 100 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) efficiency (%) iout = 300ma iout = 400ma iout = 500ma iout = 600ma 2 2.5 3 3.5 4 4.5 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 300ma iout = 400ma iout = 500ma iout = 600ma pwm mode bypass mode figure 23. dc-dc line regulation, v out vs. v in ; v out = 3.4v figure 24. dc-dc line regulation, v out vs. v in ; v out = 2.0v 2 2.5 3 3.5 4 4.5 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 300ma iout = 400ma iout = 500ma iout = 600ma pwm mode bypass mode 1.97 1.98 1.99 2.00 2.01 2.02 2.03 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 300ma iout = 400ma iout = 500ma iout = 600ma figure 25. dc-dc line regulation, v out vs. v in ; v out = 1.5v figure 26. dc-dc line regulation, v out vs. v in ; v out = 1.0v 1.47 1.48 1.49 1.50 1.51 1.52 1.53 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 300ma iout = 400ma iout = 500ma iout = 600ma 0.97 0.98 0.99 1 1.01 1.02 1.03 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 300ma iout = 400ma iout = 500ma iout = 600ma ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 12 - 25 as1339 datasheet - typical operation characteristics figure 27. dc-dc output voltage error vs. reference voltage figure 28. dc-dc bypass dr opout voltage vs. output current -4 -2 0 2 4 6 8 0.25 0.5 0.75 1 1.25 1.5 reference voltage (v) output voltage error (mv) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v vin = 3.9v 0 20 40 60 80 100 0 100 200 300 400 500 600 700 800 900 output current (ma) dropout voltage (mv) vin = 2.7v vin = 3.0v vin = 3.3v vin = 3.6v figure 29. dc-dc no-load supply current vs. v in figure 30. shutdown supply current vs. v in 0 1 2 3 4 5 6 123456 input voltage (v) quiescent current (ma) vout = 3.4v pwm mode bypass mode 0 20 40 60 80 100 120 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) shutdown current (na) figure 31. dc-dc switching; v in =3.6v, v pa =1.2v, i out =50ma figure 32. dc-dc switching; v in =3.6v, v pa =1.2v, i out =500ma 1s/div v lx 2v/div 20mv/div 200ma/div v pa i lx 1s/div v lx 2v/div 20mv/div 500ma/div v pa i lx ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 13 - 25 as1339 datasheet - typical operation characteristics figure 33. dc-dc soft-start; r load = 7.5 figure 34. dc-dc shutdown 20s/div v pa 1v/div 2v/div 200ma/div pa_en i lx 20s/div v pa 1v/div 2v/div 200ma/div pa_en i lx figure 35. dc-dc sine wave output in pwm mode ; v in = 4.5v, r load = 7.5 figure 36. dc-dc sine wave output in bypass mode ; v in = 3.6v, r load = 7.5 200s/div v pa 1v/div 1v/div 500ma/div refin i lx 200s/div v pa 1v/div 1v/div 500ma/div refin i lx figure 37. dc-dc rectangular wave output in pwm mode ; v in = 4.5v, r load = 7.5 figure 38. dc-dc rectangular wave output in bypass mode ; v in = 3.6v, r load = 7.5 10s/div v pa 2v/div 2v/div 1a/div refin i lx 10s/div v pa 2v/div 1v/div 1a/div refin i lx ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 14 - 25 as1339 datasheet - typical operation characteristics figure 39. dc-dc line transient ; v in = 4.0v to 3.5v, v out = 1.2v, r load = 10 figure 40. dc-dc load transient ; i out = 0ma to 500ma, v in = 3.6v, v out = 2.5v 50s/div v in 50mv/div v pa i lx 500mv/div 200ma/div 50s/div i out 100mv/div v pa i lx 500ma/div 500ma/div figure 41. ldo quiescent current vs. v in figure 42. ldo line regulation, v out vs. v in 0 10 20 30 40 50 60 70 80 123456 input voltage (v) quiescent current (a) both ldo's one ldo 2.7 2.72 2.74 2.76 2.78 2.8 2.82 2.84 2.86 2.88 2.9 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 input voltage (v) output voltage (v) iout = 0ma iout = 1ma iout = 10ma iout = 20ma figure 43. ldo psrr vs. freq.; v in = 3.2v, v out = 2.85v, v ripple = 200mv pp , c out =100nf figure 44. ldo output noise vs. freq.; v in = 3.2v, v out = 2.85v, c out =100nf -80 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 frequency (hz) psrr (db) 4ma no load 0.01 0.1 1 10 10 100 1000 10000 100000 frequency (hz) noise (v / hz) 10ma no load ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 15 - 25 as1339 datasheet - typical operation characteristics figure 45. ldo turn on / off response ; v in = 3.6v, no load figure 46. ldo load transient ; i out = 0ma to 10ma, v in = 3.6v 50s/div en2 2v/div 2v/div v ldo 20s/div i out 5ma/div 20mv/div v ldo figure 47. ldo line transient ; v in = 5.5v to 3.5v, i out = 10ma figure 48. ldo line transient ; v in = 4.0v to 3.5v, i out = 10ma 50s/div v in 2v/div 20mv/div v ldo 50s/div v in 1v/div 20mv/div v ldo ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 16 - 25 as1339 datasheet - detailed description 8 detailed description the as1339 is designed to dynamically power the pa in wcdma and ncdma handsets. the device is empowered with a high-frequency, high-efficiency step-down converter, and two ldos. the step-down converters are capable of delivering 650ma. the pwm control scheme provides fast tr ansient response, while 2mhz switching frequency allows the trade-off between efficiency and small external components. a 110m bypass fet connects the pa directly to the battery during high-power transmission. figure 49. as1339 - block diagram operating the as1339 the as1339?s control block turns on the internal pfet (p-channel mosfet) switch during the first part of each switching cycle, thus allowing cu rrent to flow from the input through the induct or to the output filt er capacito r and load. the inductor limits the current to a ramp with a slope of (v in - v out ) / l, by storing energy in a magnetic field. during the second part of each cycle, the controller turns the pfet switch off, blocking current flow from the input, and then turns the nfet (n-channel mosfet) synchronous rectifier on. as a result, the inductor?s magnetic field collapses, generating a voltage that forces current from ground through the synchronous rectifier to the output filter capacitor and load. while the stored energy is transferred back into the circuit and depleted, the inductor current ramps down with a slope of v out / l. the output filter capacitor stores charge when the inductor current is high, and releases it when low, smoothing the voltage across the load. the output voltage is regulated by modulating the pfet switch on-time to control the average current sent to the load. the output voltage is equal to the average voltage at the lx pin. while in operation, the output voltage is regulated by switching at a constant frequency and then modulating the energy per cycle to control the power to the load. energy per cycle is set by modulating the pfet switch on-time pulse width to control the peak inductor current. this is done by comparing the signal from the current-sense amplifier with a slope compensated error signal from the voltage-feedback error amplifier. at the beginning of each cycle, the clock turns on the pfet switch, causing the inductor current to ramp up. when the current sense signal ramps past the error amplifier signal, the pwm comparator turns off the pfet switch and turns on the nfet synchronous rectifier, ending the first part of the cycle. if an increase in load pulls the output down, the error amplifier output increases, which allows the inductor current to ramp higher before the comparator turns off the pfet. this increases the average current sent to the output and as1339 ldo2 ref 2mhz buck control logic ldo1 baseband processor gpio gpio gpio dac + pa_en en1 en2 test in2 refin in1b in1a li+ battery 1f 10f ldo2 ldo1 agnd nc pgnd lx pab paa 2.2h 4.7f 0.1f 0.1f pfet nfet bypass fet roff roff 2.5x refin 2.85v 2.85v not connected ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 17 - 25 as1339 datasheet - detailed description adjusts for the increase in the load. before appearing at the pwm comparator, a slope compensation ramp from the oscillator is subtracted from the error signal for stability of the current feedback loop. internal synchronous rectifier to reduce the rectifier forward voltage drop and the associated power loss, the as1339 uses an internal nfet as a synchronous rectifier. the big advantage of a synchronous rectification is the higher efficiency in a condition where the output voltage is low compared to the voltage drop across an ordinary rectifier diode. during the inductor current down slope in the second part of each cycle t he synchronous rectifier is turned on. before the next cyc le the synchronous rectifier is turned off. there is no need for an external diode because the nfet is conducting through its intrinsic body diode during the transient intervals before it turns on. bypass mode this mode connects in1a and in1b directly to paa and pab with the internal 110m (typ) bypass fet, while the step- down converter is forced in to 100% duty-cycle opera tion during high- power transmission. due to the low on-resistance in this mode, the result is low dropout, high efficiency and a high output current capability. the as1339 enters bypass mode automatically when v in 2.69 x v refin and thus prevents excessive output ripple as the step-down converter approaches dropout. due to an internal limitation of v refin 1.5v the maximum output volt- age is limited to 2.78 x 1.5v = 4.17v in bypass mode. shutdown mode to put the pa step-down converter in shutdown mode, connect pa_en to gnd or disconnect pa_en (nc =>logic-low). during shutdown mode, the control circuitry, internal switching mosfet, and synchronous rectifier are turned off and lx becomes high impedance. for normal operation, connect pa_en to in1a/b or logic-high. to place ldo1 or ldo2 in shutdown mode, connect en1 or en 2 to gnd or disconnect en1 or en2 (nc => logic-low). the outputs of the ldos are pulled to ground through an internal 100 resistor during shutdown. when the pa step- down and ldos are all in shutdown, the as1339 enters a very low power state, where the input current drops to 0.8 a (typ). note: all enable pins (pa_en, en1 and en2) have an internal 110k pull-down resistance. soft-start the internal soft-start circuitry of the pa step-down converter limits inrush current at startup, reducing transients on the input source. soft-start is favorable for supplies with high output impedance such as li+ and alkaline cells. the dc-dc can start-up with full output load of 7.5 . analog refin control the pa step-down converter uses refin to set the output voltage, which enables the converter to operate in applica- tions requiring dynamic voltage control. the output voltage is limited to an upper level of 3.85v, when operating in pwm mode. in bypass mode the output voltage is limited to v in . notes: 1. v out = 2.5 x v refin 2. if refin is left floating the output voltage of the step-down converter can assume any value between 0.6v and v in . thermal overload protection to prevent the as1339 from short-term misuse and ov erload conditions the chip includes a thermal overload protection. to block the normal operation mode the device is turning off the pfet and the nfet in pwm and bypass mode as soon as the junction temperature exceeds 140c. to resume the normal operation the temperature has to drop below 130c. note: continuing operation in thermal overload conditions may damage the device and is considered bad practice. ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 18 - 25 as1339 datasheet - application information 9 application information the as1339 is designed to supply power amplifiers for rf applications. the output power of the pa can directly be controlled via the output voltage of the as1339. figure 50 shows a typical application. figure 50. typical application diagram capacitor selection fo r step-down converter input capacitor to reduce the current peaks drawn from the battery or power source and to reduce the switching noise in the device an input capacitor is highly recommended. at the switching frequency the impedance of the capacitor should be very low. it?s recommended to use a x5r or x7r dielectric multilayer ceramic capacitor due to their small size, low esr and small temperature coefficients. for most applications a 4.7f capacitor is sufficient. to decrease the interfering noise and to lower the input ripple the capacitor value can be set higher (e.g. 10f). output capacitor to ensure a stable loop regulation and a small output voltage ripple a low impedance capacitor should be used. it?s recommended to use a x5r or x7r dielectric multilayer ceramic capacitor due to their small size, low esr and small temperature coefficients. for most applications a 4.7f capacitor is sufficient. to achieve a better load-transient perfor- mance and to decrease the output ripple the capacitor value can be set higher (e.g. 10f). table 6. recommended capacitors for the step-down converter name part number c voltage type size manufacturer c in1 , c out grm21br60j106ke01 10f 6.3v x5r 0805 murata www.murata.com grm21br61c475ka88 4.7f 16v x5r 0805 c0603c475k8pac7867 4.7f 10v x5r 0603 kemet www.kemet.com bias in pa1 bias in pa2 baseband processor gpio gpio gpio dac + pa_en en1 en2 test in2 refin in1b in1a li+ battery ldo2 ldo1 agnd nc pgnd lx pab paa 2.2h c out c ldo1 not connected c ldo2 rf in rf out rf in rf out c in1 c in2 as1339 ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 19 - 25 as1339 datasheet - application information capacitor selection for ldo?s input capacitor the capacitor for the ldo input should have at least a value of the sum of the output capacitors of ldo1 and ldo2. with a larger input capacitance and lower esr a better noise rejection and line transient response can be achieved. output capacitor for the ldo outputs the capacitor value depends on the needed load current. for a stable operation with rated maxi- mum load currents a minimum output capacitor of 1f is recommended. at light loads of 10ma or less a 0.1f capac- itor is sufficient. with larger output capacitance a redu ced output noise, improved load-transient response, better stability and power-supply rejection can be achieved. inductor selection for most applications the value of the external inductor should be in the range of 1.5h to 4.7h as the inductor value has a direct effect on the ripple current. the selected inductor must be rated for its dc resistance and saturation cur- rent. the inductor ripple current ( i l ) decreases with higher inductance and increases with higher v in to v out . in equation (eq 3) the maximum inductor current in pwm mode under static load conditions is calculated. the satura- tion current of the inductor should be rated higher than the maximum inductor current as calculated with equation (eq 4) . this is recommended because the inductor current will rise above the calculated value during heavy load tran- sients. the inductor current ripple i l (see eq 3) is defined by the slope of the current (di / dt) (see eq 1) multiplied by the pfet on-time t on (see eq 2) . figure 51. ripple current diagram table 7. recommended capacitors for the ldo?s name part number c voltage type size manufacturer c in2 , c ldo1 , c ldo2 c0402c104k4rac 100nf 16v x7r 0402 kemet www.kemet.com grm155r61a105ke15 1f 10v x5r 0402 murata www.murata.com t on i l i l t i outmax i lmax di dt 1 / f (eq 1) di dt ---- - v in v out ? l ---------------------------- = (eq 2) t on dutycycle 1 f -- - dutycycle v out v in ------------- = = ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 20 - 25 as1339 datasheet - application information f .... switching frequency (2.0mhz typical) l .... inductor value i lmax .... maximum inductor current i l .... peak to peak inductor ripple current i outmax .... applied load current accepting larger values of ripple current allows the use of low inductance values, but results in higher output voltage ripple, greater core losses, and lower output current capability. the total losses of the coil have a strong impact on the efficiency of the dc/dc conversion and consist of both the losses in the dc resistance and the following frequency- dependent components: 1. the losses in the core material (magnetic hyst eresis loss, especially at high switching frequencies) 2. additional losses in the conductor from the skin effect (current displacement at high frequencies) 3. magnetic field losses of the neighboring windings (proximity effect) 4. radiation losses note: for highest efficiency, a low dc-resistance inductor is recommended. table 8. recommended inductors part number l dcr current rating dimensions (l/w/t) manufacturer mlp2520s1r5s 1.5h 80m 1.5a 2.5x2.0x1.2mm tdk www.tdk.com mlp2520s2r2s 2.2h 110m 1.2a 2.5x2.0x1.2mm mlp2520s3r3s 3.3h 110m 1.0a 2.5x2.0x1.2mm epl2014-222mlc 2.2h 120m 0.98a 2.2x2.0x1.4mm coilcraft www.coilcraft.com epl2014-332mlc 3.3h 152m 0.8a 2.2x2.0x1.4mm epl2014-472mlc 4.7h 231m 0.65a 2.2x2.0x1.4mm xpl2010-222ml 2.2h 156m 1.2a 2.0x1.9x1.0mm xpl2010-332ml 3.3h 207m 0.925a 2.0x1.9x1.0mm (eq 3) i l v out v in v out ? () v in fl ----------------------------------------------------- - = (eq 4) i lmax i outmax i l 2 -------- + = ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 21 - 25 as1339 datasheet - application information example the following system should be designed: - a supply with a lithium-ion battery = 4.5v -v out = 3.0v - i outmax = 500ma for the first step v ref is calculated as shown in equation (eq 5) . due to equation (eq 6) : v in = 3.23v if v in is falling below 3.23v the device is going into bypass mode (see bypass mode on page 17) . hence a 2.2h coil is used, i l can be calculated with equation (eq 3) : i l = 227ma with this result i max can be calculated with equation (eq 4) : i max = 614ma. the saturation current of the coil should be chosen slightly higher than i max because heavy load transients could increase the peak current. for a short period of time (~50s) the peak inductor current can rise up to a value of approx- imately 1.1a (p-channel mosfet peak current limit). in this case a coil with a rated saturation current of ~800ma can be chosen. figure 52. efficiency comparison of different inductors; v in = 3.9v, v out = 1.0v figure 53. efficiency comparison of different inductors; v in = 3.9v, v out = 1.5v 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) . mlp2520s1r5s mlp2520s2r2s mlp2520s3r3s epl2014-222 epl2014-332 epl2014-472 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 output current (ma) efficiency (%) . mlp2520s1r5s mlp2520s2r2s mlp2520s3r3s epl2014-222 epl2014-332 epl2014-472 (eq 5) v ref v out 25 , ------------- 12 v , == (eq 6) v in 269 , v ref ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 22 - 25 as1339 datasheet - application information layout considerations please carefully observe that large peak currents of up to 1.1a and high switching frequencies will make the pcb lay- out a very important part of the system performance and comp liance. a proper pc b design will minimize electro mag- netic interference (emi) as well as voltage gradients in the ground plane, which both can result in application instabilities. please closely follow the guidelines as mentioned below. - keep the power traces as short and wide as possible (in1a, in1b, in2, lx, paa, pab, pgnd) - place all capacitors as close as possible to the pins of the device - avoid voltage gradients in the ground plane please note the following pcb layout considerations shown in figure 54 : - the negative terminals of cout and cin1/cin2 are kept as close as possible to each other. it is recommended to connect these terminals directly to pgnd at a star point. - the current path between pins in1a/in1b (c3/c4) and pin pgnd (a4) via cin1 is routed very short - the current path between pins pab/paa (d3/d4) and pin pgnd (a4) via cout is routed very short - the connection between lx (b4) and pins pab/paa (d3/d4) via the coil (l) is routed very short - to keep the cross-coupling between the ldos and dc/dc minimized, in regard to supply ripple and noise induc- tion, the in1 and in2 path are separated. both power inputs should be connected at a star point directly at the main supply - to prevent voltage gradients between agnd (a2) and pg nd (a4), these pins are connected via a short, low ohmic, trace to each other. figure 54. layout for space limited applications ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 23 - 25 as1339 datasheet - package drawings and markings 10 package drawings and markings the devices are available in a 16-pin wlp (2x2mm) package. figure 55. 16-pin wlp (2x2mm) package 201520 201520 257.520 257.520 ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 24 - 25 as1339 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 9 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.a ustriamicrosystems.com/distributor table 9. ordering information ordering code marking description delivery form package AS1339-BWLT as1339 650ma rf step-down dc-dc for pa, with two ldos tape and reel 16-pin wlp (2x2mm) ams ag technical content still valid
www.austriamicrosystems.com/dc-dc_step-down/as1339 revision 1.05 25 - 25 as1339 datasheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaet ten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used without the prio r written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environ mental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specif ically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact ams ag technical content still valid

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