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june 2016 docid15676 rev 6 1 / 27 this is information on a product in full production. www.st.com ld39100 1 a, low quiescent current, low - noise voltage regulator datasheet - production data features ? industrial & automotive grade (aec - q100) ? input voltage from 1.5 to 5.5 v ? ultra low - dropout voltage (200 mv typ. at 1 a load) ? very low quiescent current (20 a typ. at no load, 200 a typ. at 1 a load, 1 a max. in off mode) ? very low - noise with no bypass capacitor (30 v rms at v out = 0.8 v) ? output voltage tolerance: 2.0% @ 25 c ? 1 a guaranteed output current ? wide range of output voltages available on request: 0.8 v to 4.5 v with 100 mv step and adjustable from 0.8 v ? logic - controlled electronic shutdown ? stable with ceramic capacitors c ou t = 1 f ? internal current and thermal limit ? dfn6 (3x3 mm) package ? temperature range: - 40 c to 125 c applications ? printers ? game consoles ? computer ? consumer applications ? a utomotive post regulation description the ld39100 provides 1 a maximum current with an input voltage range from 1.5 v to 5.5 v and a typical dropout voltage of 200 mv. the device is stable with ceramic capacitors on the input and output. the ultra low drop voltage, low quiescent current and low - noise features make it suitable for low power battery - powered applications. power supply rejection is 70 db at low frequency and starts to roll off at 10 khz. enable logic control function puts the ld39100 in shutdown mode, allowing a total current consumption lower than 1 a. the device also includes short - circuit constant current limiting and thermal protection. ld39100 is available also i n aec - q100 qualified version, in the dfn6 (3x3 mm) with wettable flank package. d f n 6 ( 3x 3 mm )
contents ld39100 2 / 27 docid15676 rev 6 contents 1 circuit schematics ................................ ................................ ........... 3 2 pin configuration ................................ ................................ ............. 4 3 maximum ratings ................................ ................................ ............. 5 4 electrical characteristics ................................ ................................ 6 5 typical performance characteristics ................................ ........... 10 6 application information ................................ ................................ 15 6.1 power dissipation ................................ ................................ ............ 16 6.2 enable function ................................ ................................ ............... 17 6.3 power good function ................................ ................................ ....... 17 7 package information ................................ ................................ ..... 18 7.1 dfn6 (3x3 mm) package infor mation ................................ ............. 19 7.2 dfn6 (3x3 mm) package information (automotive - grade) .............. 21 7.3 dfn6 (3x3 mm) packing information ................................ ............... 23 8 ordering information ................................ ................................ ..... 25 9 revision history ................................ ................................ ............ 26
ld39100 circuit schematics docid15676 rev 6 3 / 27 1 circuit schematics figure 1 : ld39100 schematic diagram (adjustable version) figure 2 : ld39100 schematic diagram (fixed version) c u r r e n t l i m i t t h e r m a l p r o t e c t i o n o u t g n d op am p i n p o w e r - g o od s i g n a l p g in t e r n a l e n a b l e i n n c e n b a n dg a p r e f ere n c e r 1 r 2 c u r r e n t l i m i t t h e r m a l p r o t e c t i o n o u t g n d op am p i n p o w e r - g o od s i g n a l p g in t e r n a l e n a b l e i n i n n c e n b a n dg a p r e f ere n c e r 1 r 2 gipd010920151333m t c u r r e n t l i m i t t h e r m a l p r o t e c t i o n o u t g n d op am p i n p o w e r - g o od s i g n a l p g in t e r n a l e n a b l e i n ad j e n b a n dg a p r e f ere n c e c u r r e n t l i m i t t h e r m a l p r o t e c t i o n o u t g n d op am p i n p o w e r - g o od s i g n a l p g in t e r n a l e n a b l e i n i n ad j e n b a n dg a p r e f ere n c e gipd010920151332m t
pin configuration ld39100 4 / 27 docid15676 rev 6 2 pin configuration figure 3 : pin connection (top view) table 1: pin description symbol pin function ld39100 (adjustable version) ld39100 (fixed version) en 1 1 enable pin logic input: low = shutdown, high = active gnd 2 2 common ground pg 3 3 power good v out 4 4 output voltage adj 5 - adjust pin v in 6 6 ldo input voltage nc - 5 not connected gnd exposed pad exposed pad has to be connected to gnd l d 3 91 0 0 (f i xe d ve r s i on ) en g n d pg v i n n c v o u t en g n d pg v i n ad j v ou t ld 3 91 0 0 ( a dju s t a b l e v e rsi o n ) 1 2 3 4 5 6 1 2 3 4 5 6 gipd010920151334m t
ld39100 maximum ratings docid15676 rev 6 5 / 27 3 maximum ratings table 2: absolute maximum ratings symbol parameter value unit v in dc input voltage - 0.3 to 7 v v out dc output voltage - 0.3 to v in + 0.3 (7 v max.) v en enable pin - 0.3 to v in + 0.3 (7 v max.) v pg power good pin - 0.3 to 7 v adj adjust pin 4 v i out output current internally limited p d power dissipation internally limited t stg storage temperature range - 65 to 150 c t op operating junction temperature range - 40 to 125 c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. all values are referred to gnd. table 3: thermal data symbol parameter value unit r thja thermal resistance junction - ambient 55 c/w r thjc thermal resistance junction - case 10 c/w table 4: esd performance symbol parameter test conditions value unit esd esd protection voltage hbm 4 kv mm 0.4 kv
electrical characteristics ld39100 6 / 27 docid15676 rev 6 4 electrical characteristics t j = 25 c, v in = 1.8 v, c in = c out = 1 f, i out = 100 ma, v en = v in , unless otherwise specified. table 5: ld39100 electrical characteristics (adjustable version) symbol parameter test conditions min. typ. max. unit v in operating input voltage 1.5 5.5 v v adj v adj accuracy i out = 10 ma t j = 25 c 784 800 816 mv i out = 10 ma - 40 c < t j < 125 c 776 800 824 i adj adjust pin current 1 a ?v out static line regulation v out + 1 v v in 5.5 v i out = 100 ma 0.01 %/v ?v out transient line regulation (1) ?v in = 500 mv i out = 100 ma t r = 5 s 10 mvpp ?v in = 500 mv i out = 100 ma t f = 5 s 10 ?v out static load regulation i out = 10 ma to 1 a 0.002 %/ma ?v out transient load regulation (1) i out = 10 ma to 1 a t r = 5 s 40 mvpp i out = 1 a to 10 ma t f = 5 s 40 v drop dropout voltage (2) i out = 1 a v o fixed to 1.5 v - 40 c < t j < 125 c 200 400 mv e n output noise voltage 10 hz to 100 khz i out = 100 ma v out = 0.8 v 30 v rms svr supply voltage rejection v o = 0.8 v v in = 1.8 v+/ - v ripple v ripple = 0.25 v frequency = 1 khz i out = 10 ma 70 db v in = 1.8 v+/ - v ripple v ripple = 0.25 v frequency = 10 khz i out = 100 ma 65
ld39100 electrical characteristics docid15676 rev 6 7 / 27 symbol parameter test conditions min. typ. max. unit i q quiescent current i out = 0 ma 20 a i out = 0 ma - 40 c < t j < 125 c 50 i out = 0 to 1 a 200 i out = 0 to 1 a - 40 c < t j < 125 c 300 v in input current in off mode: v en = gnd (3) 0.001 1 pg power good output threshold rising edge 0.92* v out v falling edge 0.8* v out power good output voltage low isink = 6 ma open drain output 0.4 v i sc short - circuit current r l = 0 1.5 a v en enable input logic low v in = 1.5 v to 5.5 v - 40 c < t j < 125 c 0.4 v enable input logic high 0.9 v i en enable pin input current v en = v in 0.1 100 na t on turn - on time (4) 30 s t shdn thermal shutdown 160 c hysteresis 20 c out output capacitor capacitance (see section 5: "typical performance characteristics" ) 1 f notes: (1) all transient values are guaranteed by design, not tested in production. (2) dropout voltage is the input - to - output voltage difference at which the output voltage is 100 mv below its nominal value . this specification does not apply to output voltages below 1.5 v. (3) pg pin floating. (4) turn - on time is time measured between the enable input just exceeding v en high value and the output voltage just reaching 95% of its nominal value.
electrical characteristics ld39100 8 / 27 docid15676 rev 6 t j = 25 c, v in = v out(nom) + 1 v, c in = c out = 1 f, i out = 100 ma, v en = v in , unless otherwise specified. table 6: ld39100 electrical characteristics (fixed version) symbol parameter test conditions min. typ. max. unit v i operating input voltage 1.5 5.5 v v out v out accuracy v out >1.5 v, i out = 10 ma t j = 25 c - 2.0 2.0 % v out > 1.5 v, i out = 10 ma - 40 c < t j < 125 c - 3.0 3.0 v out 1.5 v i out = 10 ma 20 mv v out 1.5 v i out = 10 ma - 40 c < t j < 125 c 30 ?v out static line regulation v out + 1 v v in 5.5 v i out = 100 ma 0.01 %/v ?v out transient line regulation (1) ?v in = 500 mv i out = 100 ma t r = 5 s 10 mvpp ?v in = 500 mv i out = 100 ma t f = 5 s 10 ?v out static load regulation i out = 10 ma to 1 a 0.002 %/ma ?v out transient load regulation (1) i out = 10 ma to 1 a t r = 5 s 40 mvpp i out = 1 a to 10 ma t f = 5 s 40 v drop dropout voltage (2) i out = 1 a v out > 1.5 v - 40 c < t j < 125 c 200 400 mv e n output noise voltage 10 hz to 100 khz i out = 100 ma v out = 2.5 v 85 v rms svr supply voltage rejection v out = 1.5 v v in = v out(nom) +0.5 v+/ - v ripple v ripple = 0.1 v frequency = 1 khz i out = 10 ma 65 db v in = v out(nom) +0.5 v+/ - v ripple v ripple = 0.1 v frequency = 10 khz i out = 100 ma 62
ld39100 electrical characteristics docid15676 rev 6 9 / 27 symbol parameter test conditions min. typ. max. unit i q quiescent current i out = 0 ma 20 a i out = 0 ma - 40 c < t j < 125 c 50 i out = 0 to 1 a 200 i out = 0 to 1 a - 40 c < t j < 125 c 300 v in input current in off mode: (3) v en = gnd 0.001 1 pg power good output threshold rising edge 0.92* v out v falling edge 0.8* v out power good output voltage low isink = 6 ma open drain output 0.4 v i sc short - circuit current r l = 0 1.5 a v en enable input logic low v in = 1.5 v to 5.5 v - 40 c < t j < 125 c 0.4 v enable input logic high 0.9 v i en enable pin input current v en = v in 0.1 100 na t on turn - on time (4) 30 s t shdn thermal shutdown 160 c hysteresis 20 c out output capacitor capacitance (see section 5: "typical performance characteristics" ) 1 f notes: (1) all transient values are guaranteed by design, not tested in production. (2) dropout voltage is the input - to - output voltage difference at which the output voltage is 100 mv below its nominal value. this specification does not apply to output voltages below 1.5 v. (3) pg pin floating. (4) turn - on time is t ime measured between the enable input just exceeding v en high value and the output voltage just reaching 95% of its nominal value.
typical performance characteristics ld39100 10 / 27 docid15676 rev 6 5 typical performance characteristics c in = c out = 1 f figure 4 : v adj accuracy figure 5 : v out accuracy figure 6 : dropout voltage vs. temperature (v out = 2.5 v) figure 7 : dropout voltage vs. temperature (v out = 1.5 v) figure 8 : dropout voltage vs. output current figure 9 : short - circuit current vs. drop voltage
ld39100 typical performance characteristics docid15676 rev 6 11 / 27 figure 10 : output voltage vs. input voltage (v out = 0.8 v) figure 11 : output voltage vs. input voltage (v out = 2.5 v) figure 12 : qui escent current vs. temperature figure 13 : v in input current in off mode vs. temperature figure 14 : load regulation figure 15 : line regulation v out = 0.8 v gipd02092015 1 106m t 0 0. 2 0. 4 0. 6 0. 8 1 1. 2 0 0. 5 1 1. 5 2 2 . 5 3 3. 5 4 4. 5 5 5 . 5 6 v in [v ] v ou t [v ] 1 25 c 8 5 c 5 5 c 2 5 c 0 c - 2 5 c - 4 0 c v i n f r o m 0 t o 5 . 5 v , v e n t o v i n , v o u t = 0 . 8 v , i o u t = 1 a 1 25 c 8 5 c 5 5 c 2 5 c 0 c - 2 5 c - 4 0 c v i n f r o m 0 t o 5 . 5 v , v e n t o v i n , v o u t = 0 . 8 v , i o u t = 1 a gipd02092015 1 108m t 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 -5 0 - 2 5 0 2 5 5 0 7 5 10 0 1 2 5 15 0 t [ c] i q [ a] n o l o a d i o u t = 1 a v i n = 1 . 8 v , v e n t o v i n , v o ut = 2 . 5 v n o l o a d i o u t = 1 a v i n = 1 . 8 v , v e n t o v i n , v o ut = 2 . 5 v gipd02092015 1 107m t 0 0 . 5 1 1 . 5 2 2 . 5 3 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 4 4 . 5 5 5 . 5 6 v i n [v ] v ou t [v ] 125c 85c 55c 25c 0c -25c -40c v i n from 0 to 5 v , v en to v i n , v o u t = 2 . 5 v , i o u t = 1 a v i n [v ] 125c 85c 55c 25c 0c -25c -40c v i n from 0 to 5 v , v en to v i n , v o u t = 2 . 5 v , i o u t = 1 a gipd02092015 111 1m t - 0 . 04 - 0 . 03 - 0 . 02 - 0 . 01 0 0.0 1 0.0 2 0.0 3 0.0 4 - 5 0 - 2 5 0 2 5 5 0 7 5 1 0 0 12 5 15 0 t [ c ] v i n = f r o m 1 . 8 v t o 5 . 5 v , i o u t = 1 0 0 m a , v e n = v i n , v o u t = 0 . 8 v l i n e [% /v ] v i n = f r o m 1 . 8 v t o 5 . 5 v , i o u t = 1 0 0 m a , v e n = v i n , v o u t = 0 . 8 v gipd02092015 1 109m t 0 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 -5 0 -2 5 0 2 5 5 0 7 5 10 0 1 2 5 15 0 t [ c ] i q [ a ] v i n = 3 . 5 v , v e n t o g nd , v o u t = 2 . 5 v v i n = 3 . 5 v , v e n t o g nd , v o u t = 2 . 5 v gipd02092015 11 10m t - 0 . 01 5 - 0 . 0 1 - 0 . 00 5 0 0 . 00 5 0 . 0 1 0 . 01 5 - 5 0 - 2 5 0 2 5 5 0 7 5 10 0 1 2 5 1 5 0 t [ c ] l o a d [ % /m a ] v in = 3 . 5 v , i o u t = f r o m 10 m a t o 1 a , v e n = v in , v o ut = 2 . 5 v v in = 3 . 5 v , i o u t = f r o m 10 m a t o 1 a , v e n = v in , v o ut = 2 . 5 v
typ ical performance characteristics ld39100 12 / 27 docid15676 rev 6 figure 16 : line regulation v out = 2.5 v figure 17 : supply voltage rejection vs. temperature (v out = 0.8 v) figure 18 : supply voltage rejection vs. temperature (v out = 2.5 v) figure 19 : supply voltage rejection vs. frequency (v out = 0.8 v) figure 20 : supply voltage rejection vs. frequency (v out = 2.5 v) figure 21 : output noise voltage vs. frequency
ld39100 typical performance characteristics docid15676 rev 6 13 / 27 figure 22 : enable voltage vs. temperature figure 23 : load transient (i out = from 10 ma to 1 a) figure 24 : load transient (v out = 0.8 v) figure 25 : load transient (v out = 2.5 v) figure 26 : load transient (i out = from 100 ma to 1 a) figure 27 : line regulation transient
typical performance characteristics ld39100 14 / 27 docid15676 rev 6 figure 28 : start - up transient figure 29 : enable transient figure 30 : esr required for stability with ceramic capacitors (v out = 0.8 v) figure 31 : esr required for stability with ceramic capacitors (v out = 2.5 v)
ld39100 application information docid15676 rev 6 15 / 27 6 application information the ld39100 is an ultra low - dropout linear regulator. it provides up to 1 a with a low 200 mv dropout. the input voltage range is from 1. 5 v to 5.5 v. the device is available in fixed and adjustable output versions. the regulator is equipped with internal protection circuitry, such as short - circuit current limiting and thermal protection. the regulator is stable with ceramic capacitors on t he input and the output. recommended values of the input and output ceramic capacitors are from 1 f to 22 f with 1 f typical. the input capacitor has to be connected within 1 cm from v in terminal. the output capacitor has also to be connected within 1 c m from output pin. there isnt any upper limit to the value of the input capacitor. figure 32: "typical application circuit for fixed output version" and figure 33: "typical application circ uit for adjustable version" illustrate the typical application schematics: figure 32 : typical application circuit for fixed output version figure 33 : typical application circuit for adjustable version
application information ld39100 16 / 27 docid15676 rev 6 regarding the adjustable version, the output voltage can be adjusted from 0.8 v up to the input voltage, minus the voltage drop across the pass element (dropout voltage), by connecting a resistor divider between adj pin and the output, thus allowing remo te voltage sensing. the resistor divider should be selected as follows: equation 1 resistors should be used with values in the range from 10 k to 50 k. lower values can also be suitable, but they increase current consumption. 6.1 power dissipation an internal thermal feedback loop disables the output voltage if the die temperature rises to approximately 160 c. this feature protects the device from excessive temperature a nd allows the user to push the limits of the power handling capability of a given circuit board without the risk of damaging the device. a good pc board layout should be used to maximize power dissipation. the thermal path for the heat generated by the dev ice is from the die to the copper lead frame, through the package leads and exposed pad, to the pc board copper. the pc board copper acts as a heatsink. the footprint copper pads should be as wide as possible to spread and dissipate the heat to the surroun ding ambient. feed - through vias to the inner or backside copper layers are also useful to improve the overall thermal performance of the device. the device power dissipation depends on the input voltage, output voltage and output current, and is given by: equation 2 junction temperature of the device is: equation 3 where: t j_max is the maximum junction of the die,125 c t a is the ambient temperature r thja is the thermal resistance junction - to - ambient v o u t = v a d j ( 1 + r 1 / r 2 ) w i t h v a d j = 0 . 8 v ( t y p .) p d = ( v i n - v o u t ) i o u t t j _ max = t a + r t h ja x p d
ld39100 application information docid15676 rev 6 17 / 27 figure 34 : power dissipation vs. ambient temperature 6.2 enable function the ld39100 features the enable function. when en voltage is higher than 0.9 v, the device is on, and if it is lower than 0.4 v, the device is off. in shutdown mode, consumption is lower than 1 a. en pin has not an internal pull - up, so it cannot be left floating if it is not used. 6.3 power good function some applications require a flag showing that the output voltage is in the correct range. power good threshold depends on the adjust voltage. when it is higher than 0.92*v adj , power good (pg) pin goes to high impedance. if it is below 0.80*v adj pg pin goes to low impedance. if the device works well, power good pin is at high impedance. if the output voltage is fixed using an external or internal resistor divider, power good threshold is 0.92*v out . if the device is disabled (en pin low) the pg signal is set to high impedance.this is done intentionally to avoid pull down current by the pg pin in disabled mode. power good function requires an external pull - up resistor, which has to be connected between pg pin and v in or v out . pg pin typical current capa bility is up to 6 ma. a pull - up resistor for pg should be in the range from 100 k to 1 m. if power good function is not used, pg pin has to remain floating. 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 11 0 13 0 t a [ c ] p d [ w ] 0 0 . 5 1 1 . 5 2 2 . 5 3 3 . 5 - 5 0 - 3 0 - 1 0 1 0 3 0 5 0 7 0 9 0 11 0 13 0 t a [ c ] p d [ w ] gipd040920151415m t
package information ld39100 18 / 27 docid15676 rev 6 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
ld39100 package information docid15676 rev 6 19 / 27 7.1 dfn6 (3x3 mm) package information figure 35 : dfn6 (3x3 mm) package outline
package information ld39100 20 / 27 docid15676 rev 6 table 7: dfn6 (3x3 mm) mechani cal data dim. mm min. typ. max. a 0.80 1 a1 0 0.02 0.05 a3 0.20 b 0.23 0.45 d 2.90 3 3.10 d2 2.23 2.50 e 2.90 3 3.10 e2 1.50 1.75 e 0.95 l 0.30 0.40 0.50 figure 36 : dfn6 (3x3 mm) recommended footprint
ld39100 package information docid15676 rev 6 21 / 27 7.2 dfn6 (3x3 mm) package information (automotive - grade) figure 37 : dfn6 (3x3 mm) automotive - grade package outline
package information ld39100 22 / 27 docid15676 rev 6 table 8: dfn6 (3x3 mm) automotive - grade mechanical data dim. mm min. typ. max. a 0.80 0.85 0.90 a1 0.0 0.05 b 0.20 0.25 0.30 d 2.95 3.00 3.05 d2 2.30 2.40 2.50 e 0.95 e 2.95 3.00 3.05 e2 1.50 1.60 1.70 l 0.30 0.40 0.50 figure 38 : dfn6 (3x3 mm) automotive - grade recommended footprint
ld39100 package information docid15676 rev 6 23 / 27 7.3 dfn6 (3x3 mm) packing information figure 39 : dfn6 (3x3 mm) tape outline
packag e information ld39100 24 / 27 docid15676 rev 6 figure 40 : dfn6 (3x3 mm) reel outline table 9: dfn6 (3x3 mm) tape and reel mechanical data dim. mm min. typ. max. a0 3.20 3.30 3.40 b0 3.20 3.30 3.40 k0 1 1.10 1.20
ld39100 ordering information docid15676 rev 6 25 / 27 8 ordering information table 10: order code order code output voltage industrial grade automotive grade (1) ld39100pur ld39100pury adj. from 0.8 v ld39100pu12r ld39100pu12ry 1.2 v LD39100PU18R LD39100PU18Ry 1.8 v ld39100pu25r ld39100pu25ry 2.5 v ld39100pu30r 3.0 v ld39100pu33r ld39100pu33ry 3.3 v notes: (1) according to aec - q 100 level 1.
revision history ld39100 26 / 27 docid15676 rev 6 9 revision history table 11: document revision history date revision changes 29 - jul - 2009 1 initial release. 16 - apr - 2010 2 modified figure 8 on page 9. 11 - oct - 2011 3 document status promoted from preliminary data to datasheet. 24 - apr - 2014 4 part numbers ld39100xx, ld39100xx12 and ld39100xx25 changed to ld39100. updated table 1: device summary. updated the description in cover page section 1: circuit schematics, section 2: pin configuration, section 4: electrical characteristics, section 5: typical performance characteristics, figure 32: typical application circuit for fixed output version, section 7: package mechanical data. deleted previous section 8: different output voltage versions of the ld39100xx available on request. added section 8: packaging mechanical data. minor text changes. 01 - sep - 2015 5 updated figure 32: typical application circuit for fixed output version. minor text changes. 20 - jun - 2016 6 updated features in c over page. removed table 1: device summary. updated section 6.2: "enable function" . added section 8: "ordering information" and section 7.1: "dfn6 (3x3 mm) package information" . minor text changes.
ld39100 docid15676 rev 6 27 / 27 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics C all rights reserved

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