DS282 june 24, 2009 www.xilinx.com 1 product specification ? 2009 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designated brands included herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. introduction the chipscope? opb iba core is a specialized bus analyzer core designed to debug embedded systems containing the ibm coreconnect on-chip peripheral bus (opb). the chipscope opb iba core in edk is based on tcl script that generates a hdl wrapper to the opb iba and calls the chipscope core generator to generate the netlist base d on user parameters. features ? a protocol violation monitor ? multiple trigger units for trigger and data capture ? each trigger unit can be enabled and configured independently ? the trigger units for the opb iba are: ? opb control signals ? opb address units ? opb data unit (combined) ? opb read/write data units ? opb protocol violation unit ? opb master units (based on no. of masters) ? opb slave units (based on no. of slaves) ? generic trigger/data unit with selectable width for more information about the atc2 core, refer to the chipscope pro software and cores user guide . chipscope opb iba (bus analyzer) (v. 1.01a) DS282 june 24, 2009 product specification logicore ip facts core specifics supported device family (1) 1. including the variants of these fpga device families. spartan?-3e, automotive spartan-3e, spartan-3, automotive spartan-3, spartan-3a, automotive spartan-3a, spartan-3a dsp, automotive spartan-3a dsp, virtex-4 resources used (2) 2. these estimates assume virtex-4 device family with one 8-bit wide bank. i/o luts ffs block rams 8 122 185 0 special features n/a provided with core documentation product specification design file formats vhdl/edif constraints file n/a ver ification n/a instantiation template n/a reference designs /application notes none additional items signal description file (.cdc) design tool requirements xilinx? implementation tools ise? 11.2 verification chipscope? pro 11.2 simulation not supported in simulation synthesis netlist is pre-synthesized by xst support provided by xilinx, inc.
2 www.xilinx.com DS282 june 24, 2009 product specification functional description the chipscope opb iba core is a specialized bus an alyzer core designed to debug embedded systems containing the ibm coreconnect on -chip peripheral bus (opb). the modules and interconnects are shown in figure 1 .the data path of the atc2 core consists of: chipscope opb iba i/o signals the i/o signals for the chipscope opb iba are listed and described in table 1 . figure top x-ref 1 figure 1: chipscope opb iba block diagram table 1: chipscope opb iba i/o signals signal name match unit interface i/o description chipscope_icon_control n/a n/a i[35:0] icon control signals iba_trig_in generic n/a i generic trigger inputs iba_trig_out generic n/a o iba trigger output opb_clk control n/a i opb clock opb_rst control mon_opb i opb reset sys_rst control n/a i system reset debug_sys_rst control mon_opb i debug system reset wdt_rst control mon_opb i watch dog reset opb_be control mon_opb i opb byte enable opb_buslock control mon_opb i opb bus lock opb_errack control mon_opb i opb error acknowledge opb_mgrant control mon_opb i opb master grant opb_pendreq control mon_opb i opb pending request opb_retry control mon_opb i opb retry opb_rnw control mon_opb i opb read / not write opb_select control m on_opb i opb select opb_seqaddr control mon_opb i opb sequential address opb_timeout control mon_opb i opb timeout chip s cope icon icon_control clk opb mon_op b chip s cope opb_iba i ba _trig_in i ba _trig_o u t d s 2 8 2_01_092506
DS282 june 24, 2009 www.xilinx.com 3 product specification chipscope opb iba parameters table 2 describes the features that can be parameterize d to create a chipscope opb iba that is uniquely tailored for a specific system and that will provid e optimal performance. for a detailed description of the opb iba core, see the chipscope pro software and cores user guide in the chipscope installation. the chipscope opb iba peripheral supports multiple trigger units that connect to the opb control bus, address bus, data bus, individual slave or ma ster buses, a generic trigger input, and a protocol violation unit. each trigger units can be enabled and parametrized independently. in the following table, c__unit, refers to any one of these un its and the parameters asso ciated wit it. the table also lists all the trigger units and the pa rameter names used to enable each unit. opb_toutsup control mon_opb i opb timeout suppress opb_xferack control mon_opb i opb transfer acknowledge opb_abus addr mon_opb i opb address bus opb_dbus data mon_opb i opb data bus opb_rddbus rddata mon_opb i opb read data bus opb_wrdbus wrdata mon_op b i opb write data bus m_be master mon_opb i master byte enable m_buslock master mon_opb i master bus lock m_request master mon_opb i master request m_rnw master mon_opb i master read / not write m_select master mon_opb i master select m_seqaddr master mon_opb i master sequential address sl_errack slave mon_opb i master error acknowledge sl_retry slave mon_opb i slave retry sl_toutsup slave mon_opb i slave timeout suppress sl_xferack slave mon_opb i slave transfer acknowledge table 1: chipscope opb iba i/o signals (cont?d) signal name match unit in terface i/o description
4 www.xilinx.com DS282 june 24, 2009 product specification table 2: chipscope opb iba parameters feature / description parameter name allowable values default value vhdl type number of data samples captured for every trigger match c_num_data_samples integer (512, 1024, 2048, 4096, 8192, 16384) 512 integer enable the trigger out signal iba_trig_out which will be asserted when iba gets triggered c_enable_trigger_out integer 1 = enable trigger out 0 = disable trigger out 0 integer target family c_family xilinx fpga families virtex2 strings disable rpm placement information in netlist c_disable_rpm integer 1 = rpm disable 0 = rpm enabled in netlist 0 integer disable srl16 usage c_ disable_srl16s integer 1 = disable 0 = enable 0 integer trigger on rising or falling edge of clock c_rising_clock_edge integer 1 = rising 0 = falling 1 integer enable trigger sequencer in the ila c_enable_trigger_ sequencer integer 1 = enable 0 = disable 1 integer maximum number of sequencer levels c_max_sequencer_ levels integer (1-16) 16 integer enable storage qualification for ila c_enable_storage_ qualification integer (1 = enable 0 = disable 1 integer number of match units enabled for unit ex: opb control signals c__units ex: c_control_units integer (0-16) 0 = disable unit 1-16 = number of match units 0 integer counter width for match unit ex: opb control signals match unit c__unit_ counter_width ex: c_control_unit_ counter_width integer (0-32) 0 - disable match counter 1-32 - match counter width (refer to the chipscope user guide) 0 integer match tyoe for match unit ex: opb control signals match unit c__unit_match_ type ex: c_control_unit_ match_type "basic", "basic with edges", "extended", "extended with edges", "range", "range with edges" (refer to the chipscope user guide) "basic" string opb control unit c_control_ units integer (0-16) 1 integer opb address unit c_addr_units integer (0-16) 1 integer
DS282 june 24, 2009 www.xilinx.com 5 product specification allowable parameter combinations the parameter c_generic_trigger_in_width is valid only when the generic trigger input signal (not opb-bus related) is enabled on the chipscope opb iba by specifying the c_generic_trgger_units to be 1 or higher. parameters c__unit_counter_width and c__unit_match_type are valid only when the corresponding trigger unit is enab led by setting c__units to be 1 or higher. the master and slave trigger units that ca n be enabled using c_master_units and c_slave_units is determined by the number of master or slave opb pe ripherals in the user?s processor design. refers to the position of a peripheral on the op b bus (this is usually the same as the order in the user?s mhs design). for more information, refer the chipscope pro software and cores user guide , in the chipscope installa- tion. parameter - port dependencies design implementation design tools the chipscope opb iba design consists mainly of a tcl script. when the edk platgen tool is run, this tcl script gets called and the script internally ca lls the chipscope pro core generator tool in command line mode and provides it an argu ments file (.arg) to generate the chipscope opb iba netlist. the tcl script also generates a hdl wrapper to match the iba ports based on the core parameters. opb data unit (combined) c_data_units integer (0-16) 1 integer opb protocol violation unit c_pv_units integer (0-16) 0 integer generic trigger unit c_generic_ trigger_units integer (0-16) 0 integer generic trigger input width c_generic_trigger_ in_width integer 0 integer opb write data unit c_wrdata_units integer (0-16) 0 integer opb read data unit c_rddata_units integer (0-16) 0 integer opb master (0-16) unit c_master_units integer (0-16) 0 integer opb slave (0-16) unit c_slave_units integer (0-16) 0 integer table 3: chipscope opb iba parameter - port dependencies port name parameter dependency description iba_trig_in c_generic_trigger_units c_generic_trigger_in_width the generic trigger input port and its width is determined by these two iba_trig_out c_enable_trigger_out the trig_out port is enabled when this parameter is set to 1 table 2: chipscope opb iba parameters (cont?d) feature / description parameter name allowable values default value vhdl type
6 www.xilinx.com DS282 june 24, 2009 product specification xst is the synthesis tool used for synthesizing the wrapper hdl generated for the chipscope opb iba. the edif netlist outputs from xst and chipsc ope core generator are then input to the xilinx foundation tool suite for actual device implementation. target technology the intended target technology is all xilinx fpgas. device utilization and performance benchmarks the device utilization varies widely based on the parameter combinations set by the user. restrictions maximum number of signals that can be mo nitored with a single iba is 256 signals. references [1] more information on the chipscope pro software and cores is available in the software and cores user guide , located at http://www.xilinx.com/support/documenta- tion/sw_manuals/chipscope_ pro_sw_cores_10_1_ug029.pdf . [2] information about hardware debugging using chipscope pro in edk is available in the platform studio 11.1 online help, located at http://www.xilinx.com/itp/xilinx11/help/pl atform_studio/platform_studio_start.htm . [3] information about hardware debugging using chipscope pro in system generator for dsp is avail- able in the xilinx system generator for dsp user guide , located at http://www.xilinx.com/support/sw_manuals/sysgen_ug.pdf . support xilinx provides technical support for this logicore product when used as described in the product documentation. xilinx cannot guaran tee timing, functionality, or supp ort of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . ordering information the opb iba core is provided under the signonce ip site license and can be generated using the xilinx core generator system 11.2 or higher. the core ge nerator system is shippe d with xilinx ise foun- dation series development software.
DS282 june 24, 2009 www.xilinx.com 7 product specification revision history notice of disclaimer xilinx is providing this product documentation, hereinafte r ?information,? to you ?as is? with no warranty of any kind, express or implied. xilinx make s no representation that the informat ion, or any particular implementation thereof, is free from any claims of infringement. you ar e responsible for obtaining any rights you may require for any implementation based on the info rmation. all specifications are subj ect to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, including but not limited to any warranties or representati ons that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose. except as stated herein, none of the information may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanic al, photocopying, recording, or otherwi se, without the prior written consent of xilinx. date version revision 01/16/2004 1.0 release 6.1i (initial xilinx release). 08/30/2004 1.1 release 6.3i. 04/02/2005 2.0 release 7.1i, service pack 1 changes. 10/31/2005 3.0 release 8.1i. 09/25/2006 4.0 release 9.1i. 04/21/2008 5.0 release 10.1. 04/07/2009 6.0 release 11.1. 06/24/2009 6.1 release 11.2.
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