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? semiconductor components industries, llc, 2016 september, 2016 ? rev. p0 1 publication order number: n84c161/d n84c161, n84c162 product preview supervisory circuits with i 2 c serial cmos eeprom, precision reset controller and watchdog timer (16k) description the n84c161/2 is a complete memory and supervisory solution for microcontroller?based systems. a serial eeprom memory (16k) with hardware memory write protection, a system power supervisor with brown out protection and a watchdog timer are integrated together in low power cmos technology. memory interface is via an i 2 c bus. the 1.6?second watchdog circuit returns a system to a known good state if a software or hardware glitch halts or ?hangs? the system. the n84c161 watchdog monitors the sda line, making an additional pc board trace unnecessary. the lower cost n84c162 does not have a watchdog timer. the power supply monitor and reset circuit protects memory and system controllers during power up/down and against brownout conditions. five reset threshold voltages support 5 v, 3.3 v and 3 v systems. if power supply voltages are out of tolerance reset signals become active, preventing the system microcontroller, asic or peripherals from operating. reset signals become inactive typically 200 ms after the supply voltage exceeds the reset threshold level. with both active high and low reset signals, interface to microcontrollers and other ics is simple. in addition, a reset pin can be used as a debounced input for pushbutton manual reset capability. the n84c161/2 memory features a 16?byte page. in addition, hardware data protection is provided by a write protect pin wp and by a v cc sense circuit that prevents writes to memory whenever v cc falls below the reset threshold or until v cc reaches the reset threshold during power up. these devices are available in a green soic?8 package. features ? watchdog monitors sda signal (n84c161) ? 400 khz i 2 c bus compatible ? 2.7 v to 6 v operation ? low power cmos technology ? 16?byte page write buffer ? built?in inadvertent write protection ? v cc lock out ? write protection pin, wp ? active high or low reset ? precision power supply voltage monitor ? 5 v, 3.3 v and 3 v systems ? five threshold voltage options ? 1,000,000 program/erase cycles ? manual reset ? 100 year data retention ? 8?pin soic ? commercial and industrial temperature ranges ? these devices are pb?free, halogen free/bfr free and are rohs compliant this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. ordering information www. onsemi.com soic?8 case 751bd for ordering information details, see page 11. 1 2 3 4 8 7 6 5 dc reset wp gnd v cc reset scl sda n84c161 n84c162 pin configuration pin functions pin name function dc do not connect reset active low reset i/o wp write protect gnd ground sda serial data/address scl clock input reset active high reset i/o v cc power supply
n84c161, n84c162 www. onsemi.com 2 table 1. reset threshold option part dash number minimum thresh- old maximum thresh- old ?45 4.50 4.75 ?42 4.25 4.50 ?30 3.00 3.15 ?28 2.85 3.00 ?25 2.55 2.70 block diagram 16k d out ack senseamps shift registers control logic wordaddress buffers start/stop logic eeprom v cc external load column decoders xdec data in storage highvoltage/ timing control gnd wp sda reset controller precision vcc monitor state counters slave address comparators scl reset?reset watchdog only fo r n84c161
n84c161, n84c162 www. onsemi.com 3 specifications table 2. absolute maximum ratings parameters ratings units temperature under bias ?55 to +125 c storage temperature ?65 to +150 c voltage on any pin with respect to ground (note 1) ?2.0 to v cc + 2.0 v v cc with respect to ground ?2.0 to 7.0 v package power dissipation capability (t a = 25 c) 1.0 w lead soldering temperature (10 sec) 300 c output short circuit current (note 2) 100 ma stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 1. the minimum dc input voltage is ?0.5 v. during transitions, inputs may undershoot to ?2.0 v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc +0.5 v, which may overshoot to v cc +2.0 v for periods of less than 20 ns. 2. output shorted for no more than one second. no more than one output shorted at a time. table 3. reliability characteristics symbol parameter reference test method min max units n end (note 3) endurance mil?std?883, test method 1033 1,000,000 cycles/byte t dr (note 3) data retention mil?std?883, test method 1008 100 years v zap (note 3) esd susceptibility mil?std?883, test method 3015 2000 volts i lth (notes 3 & 4) latch?up jedec standard 17 100 ma 3. this parameter is tested initially and after a design or process change that affects the parameter. 4. latch?up protection is provided for stresses up to 100 ma on address and data pins from ?1 v to v cc +1 v. table 4. d.c. operating characteristics v cc = 2.7 v to 6 v, unless otherwise specified. symbol parameter test conditions min typ max units i cc:r read power supply current f scl = 400 khz 0.5 ma i cc:w write power supply current write cycle 1 ma i sb standby current v cc = 3.3 v 40 a v cc = 5 v 50 a i li input leakage current v in = gnd or v cc 2 a i lo output leakage current v in = gnd or v cc 10 a v il input low voltage ?1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (sda) i ol = 3 ma, v cc = 3.0 v 0.4 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. table 5. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5 v symbol test test conditions max units c i/o (note 3) input/output capacitance (sda) v i/o = 0 v 8 pf c in (note 3) input capacitance (scl) v in = 0 v 6 pf
n84c161, n84c162 www. onsemi.com 4 table 6. ac characteristics v cc = 2.7 v to 6.0 v unless otherwise specified. output load is ttl gate and 100 pf. symbol parameter min max min max units f scl clock frequency 100 400 khz t 1 (note 1) noise suppression time constant at scl, sda inputs 200 200 ns t aa scl low to sda data out and ack out 3.5 1 s t buf (note 1) time the bus must be free before a new transmission can start 4.7 1.2 s t hd; sta start condition hold time 4 0.6 s t low clock low period 4.7 1.2 s t high clock high period 4 0.6 s t su; sta start condition setup time (for a repeated start condition) 4.7 0.6 s t hd; dat data in hold time 0 0 ns t su; dat data in setup time 50 50 ns t r (note 1) sda and scl rise time 1 0.3 s t f (note 1) sda and scl fall time 300 300 ns t su; sto stop condition setup time 4 0.6 s t dh data out hold time 100 100 ns 1. this parameter is tested initially and after a design or process change that affects the parameter. table 7. write cycle limits symbol parameter min typ max units t wr write cycle time 10 ms * the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cyc le. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave add ress. table 8. reset circuit characteristics symbol parameter min typ max units t glitch v cc glitch reject pulse width 100 ns v rt reset threshold hysteresis 15 mv v olrs reset output low voltage (i olrs = 1 ma) 0.4 v v ohrs reset output high voltage v cc ? 0.75 v v th reset threshold (v cc = 5 v), (n84c161/2?45) 4.50 4.75 v reset threshold (v cc = 5 v), (n84c161/2?42) 4.25 4.50 reset threshold (v cc = 3.3 v), (n84c161/2?30) 3.00 3.15 reset threshold (v cc = 3.3 v), (n84c161/2?28) 2.85 3.00 reset threshold (v cc = 3 v), (n84c161/2?25) 2.55 2.70 t purst power?up reset timeout 130 270 ms t wp watchdog period 1.6 s t rpd v th to reset output delay 5 s v rvalid reset output valid 1 v
n84c161, n84c162 www. onsemi.com 5 pin description wp : write protect if the pin is tied to v cc the entire memory array becomes write protected (read only). when the pin is tied to gnd or left floating normal read/write operations are allowed to the device. reset/reset : reset i/o these are open drain pins and can be used as reset trigger inputs. by forcing a reset condition on the pins the device will initiate and maintain a reset condition. the reset pin must be connected through a pulldown resistor, and the reset pin must be connected through a pull?up resistor. sda : serial data address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire?ored with other open drain or open collector outputs. if there is no transition on the sda for more than 1.6 seconds, the watchdog timer times out. scl : serial clock serial clock input. device operation reset controller description the n84c161/2 precision reset controller ensures correct system operation during brownout and power up/down conditions. it is configured with open drain reset outputs. during power?up, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200 ms (t purst ) after reaching v th . after the t purst timeout interval, the device will cease to drive the reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/down resistors. during power?down, the reset outputs will be active when v cc falls below v th . the reset outputs will be valid so long as v cc is > 1.0 v (v rvalid ). the reset pins are i/os; therefore, the n84c161/2 can act as a signal conditioning circuit for an externally applied manual reset. the inputs are edge triggered; that is, the reset input in the n84c161/2 will initiate a reset timeout after detecting a low to high transition and the reset input will initiate a reset timeout after detecting a high to low transition. watchdog timer the watchdog timer provides an independent protection for microcontrollers. during a system failure, the n84c161 will respond with a reset signal after a time?out interval of 1.6 seconds for a lack of activity. the n84c161 is designed with the watchdog timer feature on the sda input. if the microcontroller does not toggle the sda input pin within 1.6 seconds, the watchdog timer times out. this will generate a reset condition on reset outputs. the watchdog timer is cleared by any transition on sda. as long as reset signal is asserted, the watchdog timer will not count and will stay cleared. the n84c162 does not have a watchdog. figure 1. reset output timing glitch t v cc purst t purst t rpd t rvalid v v th reset reset rpd t
n84c161, n84c162 www. onsemi.com 6 hardware data protection the n84c161/2 is designed with the following hardware data protection features to provide a high degree of data integrity. 1. the n84c161/2 features a wp pin. when the wp pin is tied high the entire memory array becomes write protected (read only). 2. the v cc sense provides write protection when v cc falls below the reset threshold value (v th ). the v cc lock out inhibits writes to the serial eeprom whenever v cc falls below (power down) v th or until v cc reaches the reset threshold (power up) v th . any attempt to access the internal eeprom is not recognized and an ack will not be sent on the sda line when reset or reset is active. reset threshold voltage the n84c161/2 is offered with five reset threshold voltage ranges. they are 4.50 4.75 v, 4.25 4.50 v, 3.00 3.15 v, 2.85 3.00 v and 2.55 2.70 v. figure 2. bus timing t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 3. write cycle timing t wr stop condition start condition address ack 8th bit byte n scl sda figure 4. start/stop timing start bit a sd stop bit scl
n84c161, n84c162 www. onsemi.com 7 fuctional description the n84c161/2 supports the i 2 c bus data transmission protocol. this inter?integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: 1. data transfer may be initiated only when the bus is not busy. 2. during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the n84c161/2 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8?bit slave address are fixed as 1010. the next three bits (figure 6) define memory addressing. for the n84c161/2 the three bits define higher order bits. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the n84c161/2 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the n84c161/2 then performs a read or write operation depending on the r/w bit. figure 5. acknowledge timing acknowledge 1 rt sta scl from master 8 data output from transmitter data output from receiver 9 figure 6. slave address bits 1 0 1 0 a10 a9 a8 r/w note: a8, a9 and a10 correspond to the address of the memory array address word. n84c161/2 acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the n84c161/2 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8?bit byte. when the n84c161/2 begins a read mode it transmits 8 bits of data, releases the sda line and monitors the line for an acknowledge. once it receives this acknowledge, the n84c161/2 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition.
n84c161, n84c162 www. onsemi.com 8 write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends a 8?bit address that is to be written into the address pointers of the n84c161/2. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the n84c161/2 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to non?volatile memory. while the cycle is in progress, the device will not respond to any request from the master device. page write the n84c161/2 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been transmitted, the n84c161/2 will respond with an acknowledge and internally increment the lower order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes before sending the stop condition, the address counter ?wraps around,? and previously transmitted data will be overwritten. when all 16 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the n84c161/2 in a single write cycle. figure 7. byte write timing byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t figure 8. page write timing bus activity: master sda line data n+15 byte address (n) a c k a c k data?n a c k s t o p s a c k data n+1 a c k s t a r t p slave address acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write operation, the n84c161/2 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the n84c161/2 is still busy with the write operation, no ack will be returned. if a write operation has completed, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent memory array programming. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the n84c161/2 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device?s failure to send an acknowledge after the first byte of data is received.
n84c161, n84c162 www. onsemi.com 9 read operations the read operation for the n84c161/2 is initiated in the same manner as the write operation with one exception, that r/w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. immediate/current address read the n84c161/2 address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n+1. for all devices, n=e=2047. the counter will wrap around to zero and continue to clock out valid data for the 16k devices. after the n84c161/2 receives its slave address information (with the r/w bit set to one), it issues an acknowledge, then transmits the 8?bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. figure 9. immediate address read timing scl sda8th bit stop no ack data out 8 slave address s a c k data n o a c k s t o p p bus activity: master sda line s t a r t 9 selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a ?dummy? write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after the n84c161/2 acknowledges, the master device sends the start condition and the slave address again, this time with the r/w bit set to one. the n84c161/2 then responds with its acknowledge and sends the 8?bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the n84c161/2 sends the inital 8?bit byte requested, the master will responds with an acknowledge which tells the device it requires more data. the n84c161/2 will continue to output an 8?bit byte for each acknowledge, thus sending the stop condition. the data being transmitted from the n84c161/2 is outputted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the n84c161/2 address bits so that the entire memory array can be read during one operation. if more than e (where e=2047 fo r the n84c161/2) bytes are read out, the counter will ?wrap around? and continue to clock out data bytes. manual reset operation the n84c161/2 reset or reset pin can also be used as a manual reset input. only the ?active? edge of the manual reset input is internally sensed. the positive edge is sensed if reset is used as a manual reset input and the negative edge is sensed if reset is used as a manual reset input. an internal counter starts a 200 ms count. during this time, the complementary reset output will be kept in the active state. if the manual reset input is forced active for more than 200 ms, the complementary reset output will switch back to the non active state after the 200 ms expired, regardless for how long the manual reset input is forced active. the embedded eeprom is disabled as long as a reset condition is maintained on any reset pin. if the external forced reset/reset is longer than internal controlled time?out period, t purst , the memory will not respond with an acknowledge for any access as long as the manual reset input is active.
n84c161, n84c162 www. onsemi.com 10 figure 10. selective read timing slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t figure 11. sequential read timing bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address ordering information orderable part numbers ? n84c161/2 series (see notes 1 ? 4) device reset threshold voltage package?pins shipping n84c161wd45tg 4.50 v ? 4.75 v soic?8 3000 tape & reel n84c161wd42tg 4.25 v ? 4.50 v n84c161wd30tg 3.00 v ? 3.15 v n84c161wd28tg 2.85 v ? 3.00 v n84c161wd25tg 2.55 v ? 2.70 v n84c162wd45tg 4.50 v ? 4.75 v soic?8 n84c162wd42tg 4.25 v ? 4.50 v N84C162WD30TG 3.00 v ? 3.15 v n84c162wd28tg 2.85 v ? 3.00 v n84c162wd25tg 2.55 v ? 2.70 v 1. all packages are rohs?compliant (lead?free, halogen?free). 2. the standard lead finish is nipdau. 3. for additional package and temperatur e options, please contact your nearest on semiconductor sales office. 4. for detailed information and a breakdown of device nomenclature and numbering systems, please see the on semiconducto r device nomencla ture document, tnd310/d, available at www.onsemi.com
n84c161, n84c162 www. onsemi.com 11 soic 8, 150 mils case 751bd?01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35 on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 n84c161/d on semiconductor is licensed by the philips corporation to utilize the i 2 c bus protocol. literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative ?

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