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nuc029 may 1 8, 201 5 page 1 of 99 rev 1 . 02 nuc029 series datasheet arm ? cortex ? - m 32 - bit microcontroller numicro? family nuc029 series datasheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. a ll data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation. www.nuvoton.com
nuc029 may 1 8, 201 5 page 2 of 99 rev 1 . 02 nuc029 series datasheet table of contents list of figures ................................ ................................ ................................ ..... 6 list of tables ................................ ................................ ................................ ....... 7 1 general desc ription ................................ ................................ ..................... 8 2 features ................................ ................................ ................................ ............ 9 3 abbreviations ................................ ................................ ................................ 13 4 parts information li st and pin configura tion ................................ 14 numicro ? nuc029 series selection guide ................................ ................. 14 4.1 pin configuration ................................ ................................ ................. 16 4.2 numicro ? nuc029 pin diagram ................................ ................................ .... 16 4.2.1 pin description ................................ ................................ .................... 19 4.3 numicro ? nuc029 pin description ................................ ................................ 19 4.3.1 5 functional descripti on ................................ ................................ ............. 26 arm? cortex ? - m0 core ................................ ................................ ........ 26 5.1 system manager ................................ ................................ ................. 28 5.2 overview ................................ ................................ ................................ 28 5.2.1 system reset ................................ ................................ .......................... 28 5.2.2 system power distribution ................................ ................................ ........... 29 5.2.3 system memory map ................................ ................................ ................. 30 5.2.4 whole system memory mapping ................................ ................................ .... 33 5.2.5 system timer (systick) ................................ ................................ .............. 35 5.2.6 nested vectored interrupt controller (nvic) ................................ ...................... 35 5.2.7 clock controller of numicro ? nuc029xan ................................ .................. 40 5.3 overview ................................ ................................ ................................ 40 5.3.1 system clock and systick clock ................................ ................................ ... 43 5.3.2 power - down mode clock ................................ ................................ ............. 44 5.3.3 frequency divider output ................................ ................................ ............ 45 5.3.4 clock controller of numicro ? nuc029fae ................................ ................. 46 5.4 overview ................................ ................................ ................................ 46 5.4.1 system clock and systick clock ................................ ................................ ... 47 5.4.2 isp clock source selection ................................ ................................ .......... 48 5.4.3 module clock source selection ................................ ................................ ..... 48 5.4.4 power - down mode clock ................................ ................................ ............. 49 5.4.5 flash memory controller (fmc) ................................ ............................... 50 5.5 overview ................................ ................................ ................................ 50 5.5.1
nuc029 may 1 8, 201 5 page 3 of 99 rev 1 . 02 nuc029 series datasheet features ................................ ................................ ................................ . 50 5.5.2 external bus interface (ebi) (NUC029LAN only) ................................ ........... 51 5.6 overview ................................ ................................ ................................ 51 5.6.1 features ................................ ................................ ................................ . 51 5.6.2 general purpose i/o (gpio) ................................ ................................ ... 52 5.7 overview ................................ ................................ ................................ 52 5.7.1 features ................................ ................................ ................................ . 52 5.7.2 timer controller (timer) ................................ ................................ ....... 53 5.8 overview ................................ ................................ ................................ 53 5.8.1 features ................................ ................................ ................................ . 53 5.8.2 pwm generator and capture timer (pwm) (nuc029xan only) ........................ 54 5.9 overview ................................ ................................ ................................ 54 5.9.1 features ................................ ................................ ................................ . 55 5.9.2 enhanced pwm generator (nuc029fae only) ................................ ............ 56 5.10 overview ................................ ................................ ................................ 56 5.10.1 features ................................ ................................ ................................ . 56 5.10.2 watchdog timer (wdt) ................................ ................................ ......... 58 5.11 overview ................................ ................................ ................................ 58 5.11.1 features ................................ ................................ ................................ . 58 5.11.2 window watchdog timer (wwdt) (nuc029xan only) ................................ ... 59 5.12 overview ................................ ................................ ................................ 59 5.12.1 features ................................ ................................ ................................ . 59 5.12.2 uart interface controller (uart) ................................ ............................ 60 5.13 overview ................................ ................................ ................................ 60 5.13.1 features ................................ ................................ ................................ . 60 5.13.2 i 2 c serial interface controller (i 2 c) ................................ ............................ 61 5.14 overview ................................ ................................ ................................ 61 5.14.1 features ................................ ................................ ................................ . 61 5.14.2 serial peripheral interface (spi) ................................ ............................... 62 5.15 overview ................................ ................................ ................................ 62 5.15.1 features ................................ ................................ ................................ . 62 5.15.2 analog - to - digital converter (adc) ................................ ............................ 63 5.16 overview ................................ ................................ ................................ 63 5.16.1 features ................................ ................................ ................................ . 63 5.16.2 analog comparator (acmp) ................................ ................................ .... 65 5.17
nuc029 may 1 8, 201 5 page 4 of 99 rev 1 . 02 nuc029 series datasheet overview ................................ ................................ ................................ 65 5.17.1 features ................................ ................................ ................................ . 65 5.17.2 hardware divider (hdiv) (nuc029xan only) ................................ ............... 66 5.18 overview ................................ ................................ ................................ 66 5.18.1 features ................................ ................................ ................................ . 66 5.18.2 6 applicatio n circuit ................................ ................................ ...................... 67 7 nuc029xan electrical characteristics ................................ .............. 68 absolute maximum ratings ................................ ................................ ..... 68 7.1 dc electrical characteristics ................................ ................................ ... 69 7.2 ac electrical characteristics ................................ ................................ ... 73 7.3 external input clock ................................ ................................ ................... 73 7.3.1 external 4~24 mhz high speed crystal (hxt) ................................ ................... 73 7.3.2 internal 22.1184 mhz high speed rc oscillator (hirc) ................................ ....... 74 7.3.3 internal 10 khz low speed rc oscillator (l irc) ................................ ................ 74 7.3.4 analog characteristics ................................ ................................ ........... 75 7.4 12 - bit sar adc specification ................................ ................................ ....... 75 7.4.1 ldo and power management specification ................................ ...................... 76 7.4.2 low voltage reset specification ................................ ................................ .... 77 7.4.3 brown - out detector specification ................................ ................................ ... 77 7.4.4 power - on reset specification ................................ ................................ ....... 77 7.4.5 temperature sensor specification ................................ ................................ .. 79 7.4.6 comparator specification ................................ ................................ ............ 79 7.4.7 flash dc electrical characteristics ................................ ............................ 80 7.5 8 nuc029fae electrical characteristics ................................ .............. 81 absolute maximum ratings ................................ ................................ ..... 81 8.1 dc electrical characteristics ................................ ................................ ... 82 8.2 ac electrical characteristics ................................ ................................ ... 86 8.3 external input clock ................................ ................................ ................... 86 8.3.1 external 4~24 mhz high speed crystal (hxt) ................................ ................... 86 8.3.2 internal 22.1184 mhz high speed rc oscillator (hirc) ................................ ....... 87 8.3.3 internal 10 khz low speed rc oscillator (lirc) ................................ ................ 88 8.3.4 analog characteristics ................................ ................................ ........... 89 8.4 10 - bit sar adc specification ................................ ................................ ....... 89 8. 4.1 ldo and power management specification ................................ ...................... 90 8.4.2 low voltage reset specification ................................ ................................ .... 91 8.4.3
nuc029 may 1 8, 201 5 page 5 of 99 rev 1 . 02 nuc029 series datasheet brown - out detector specification ................................ ................................ ... 91 8.4.4 power - on reset specification ................................ ................................ ....... 91 8.4.5 comparator specification ................................ ................................ ............ 93 8.4.6 flash dc electrical characteristics ................................ ............................ 94 8.5 9 package dimensions ................................ ................................ .................... 95 48 - pin lqfp (7x7x1.4 mm footprint 2.0 mm) ................................ ................ 95 9.1 33 - pin qfn (4x4x0.75 mm footprint 1.0 mm) ................................ ................ 96 9.2 20 - pin tssop (6.5x4.4x1.2 mm footprint 2.0 mm) ................................ ......... 97 9.3 10 revision history ................................ ................................ ............................ 98
nuc029 may 1 8, 201 5 page 6 of 99 rev 1 . 02 nuc029 series datasheet list of f igures figure 4 - 1 numicro ? nuc029 series selection code ................................ ................................ .. 15 figure 4 - 2 numicro ? NUC029LAN lqfp 48 - pin diagram ................................ ........................... 16 figure 4 - 3 numicro ? nuc029tan qfn 33 - pin diagram ................................ ............................. 17 figure 4 - 4 numicro ? nuc029fae tssop 20 - pin diagram ................................ ......................... 18 figure 5 - 1 functional controller diagram ................................ ................................ ...................... 26 figure 5 - 2 numicro ? nuc029xan power distribution diagram ................................ ................... 29 figure 5 - 3 numicro ? nuc029fae power distribution diagram ................................ ................... 30 figure 5 - 4 numicro ? nuc029xan whole system memory mapping ................................ ........... 33 figure 5 - 5 numicro ? nuc029fae whole syst em memory mapping ................................ .......... 34 figure 5 - 6 numicro ? nuc029xan clock generator block diagram ................................ ............ 40 figure 5 - 7 numicro ? nuc029xan clock source controller overview (1/2) ................................ 41 figure 5 - 8 numicro ? nuc029xan clock source controller overview (2/2) ................................ 42 figure 5 - 9 numicro ? nuc029xan system clock block diagram ................................ ................ 43 figure 5 - 10 numicro ? nuc029xan systick clock control block diagram ................................ . 43 figure 5 - 11 numicro ? nuc029xan clock source of frequency divider ................................ ..... 45 figure 5 - 12 numicro ? nuc029xan frequency divider block diagram ................................ ....... 45 figure 5 - 13 numicro ? nuc029fae clock generator block diagram ................................ .......... 46 figure 5 - 14 numicro ? nuc029fae system clock block diagram ................................ .............. 47 figure 5 - 15 numicro ? nuc029fae systick clock control block diagram ................................ . 47 figure 5 - 16 numicro ? nuc029fae ahb clock source for hclk ................................ ............... 48 figure 5 - 17 numicro ? nuc029fae peripherals clock source selection for pclk .................... 49 figure 7 - 1 nuc029xan typical crystal application circuit ................................ .......................... 74 figure 7 - 2 nuc029xan power - up ramp condition ................................ ................................ ...... 78 figure 8 - 1 nuc029fae typical crystal application circuit ................................ .......................... 87 figure 8 - 2 nuc 029xan power - up ramp condition ................................ ................................ ...... 92
nuc029 may 1 8, 201 5 page 7 of 99 rev 1 . 02 nuc029 series datasheet list of t ables table 1 - 1 numicro tm nuc029 series difference list ................................ ................................ ...... 8 table 3 - 1 list of abbreviations ................................ ................................ ................................ ....... 13 table 4 - 1 numicro tm nuc029 series selection guide ................................ ................................ .. 14 table 5 - 1 numicro ? nuc029xan address space assignments for on - chip controllers ............ 31 table 5 - 2 numicro ? nuc029fae address space assignments for on - chip controllers ........... 32 table 5 - 3 exception model ................................ ................................ ................................ ............ 36 table 5 - 4 numicro ? nuc029xan system interrupt map ................................ ............................. 37 table 5 - 5 numicro ? nuc029fae system interrupt map ................................ ............................. 38 table 5 - 6 vector table format ................................ ................................ ................................ ...... 39 table 5 - 7 numicro ? nuc029fae peripheral clock source selection t able ............................... 49
nuc029 may 1 8, 201 5 page 8 of 99 rev 1 . 02 nuc029 series datasheet 1 general description the numicro ? nuc029 series 32 - bit microcontroller is embedded with arm ? cortex ? - m0 core for industrial control and applications which need rich communication interfaces or require high performance, high integration , and low cost . the cortex ? - m0 is the newest arm ? embedded processor with 32 - bit performance at a cost equivalent to the trad itional 8 - bit microcontroller. the numicro? nuc029 series includes the re part numbers: NUC029LAN, nuc029tan and nuc029fae. the NUC029LAN/nuc029tan can run up to 50 mhz and operate at 2.5v ~ 5.5v, - 40 ~ 8 5 , and the nuc029fa e can run up to 24 mhz and operate at 2.5v ~ 5.5v, - 40 ~ 10 5 . therefore, the nuc029 series can afford to support a variety of industrial control and applications which need high cpu performance. the NUC029LAN/nuc029tan offers 64 k/ 32 k bytes flash, 4 kbyte s data flash, 4 kbyte s flas h for the isp, and 4 kbyte s sram. the nuc029fa e offers 16 kbytes flash, size configurable data flash (shared with program flash) , 2 kbyte s flash for the isp, and 2 k - byte s sram. many system level peripheral functions, such as i/o port, ebi (external bus interface), timer, uart, spi, i 2 c, pwm, adc, wdt ( watchdog timer ) , wwdt ( window watchdog timer ) , analog comparator and brown - out detector, have been incorporated into the nuc029 series in order to reduce component count, board space and system cost. these useful functions make the nuc029 series powerful for a wide range of applications. additionally, the numicro? nuc029 series is equipped with isp (in - system programming) and icp (in - circuit programming) functions, and iap (in - application programming), which allow the user to update the program memory without removing the chip from the actual end product. item nuc029l a n / nuc029t an nuc029fa e core up to 50 mhz up to 24 mhz o perat ing t emp . - 40 ~ + 85 - 40 ~ + 105 h ardware d ivider - clock control supports pll as clock source - - supports e xternal 32.768 kh z crystal oscillator as clock source window wdt - pwm pwm generator and capture timer enhanced pwm generator adc 12 - bit sar adc with 760 ksps ( supports single, burst, single - cycle, and continuous scan mode ) 1 0 - bit sar adc with 300 ksps (o nly support s single mode ) ebi - b uilt - in t emp .s ensor - table 1 - 1 numicro tm nuc029 series difference list
nuc029 may 1 8, 201 5 page 9 of 99 rev 1 . 02 nuc029 series datasheet 2 features ? arm ? cortex ? - m0 core C r uns up to 50 mhz C one 24 - bit system timer C supports low power sleep mode C a single - cycle 32 - bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4 - levels of priority C supports serial wire debug (swd) interface and two watchpoints/ four breakpoints C provides hardware d ivider and supports signed 32 - bit dividend, 16 - bit divisor operation (nuc029xan only) ? o perating voltage ranges from 2.5 v to 5.5 v ? memory C 16/32/64 kb flash for program memory (aprom) C up to 4 kb flash for loader (ldrom) C up to 4 kb sram for internal scratch - p ad ram (sram) C 4 kb flash for data memory (data flash) (nuc029xan only) C configurable data flash (nuc029fae only) ? clock control C programmable system clock source C 22.1184 mhz internal oscillator ? dynamically calibrating the hirc osc to 22.1184 mhz 3 % from - 40 to 105 by external 32.768 khz crystal oscillator (lxt) (nuc029fae only) C 4~24 mhz external crystal input C 10 khz low - power oscillator for watchdog timer and wake - up in sleep mode C pll allows cpu operation up to the maximum 50 mhz ( nuc029xan only ) C 32.768 khz external crystal input (lxt) for power - down wake - up and system operation clock (nuc029fae only) ? gpio C up to 40 general - purpose i/o (gpio) pins for lqfp - 48 package C four i/o modes: ? quasi - bidirection al ? push - p ull output ? open - d rain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interrupt source with edge/level setting C supports high driver and high sink i/o mode C configurable i/o mode after por ? timer C up to f our sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter C independent clock source for each timer C provides up to four timer counting modes: one - shot, periodic, toggle and continuous counting C 24 - bit up counter value is readable through tdr (timer data register) C supports event countin g function to count the input event from external counter pin C 24 - bit capture value is readable through tcap (timer capture data register) C supports external capture pin for interval measurement ? supports external capture pin to reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generate d C supports internal capture triggered while internal acmp output signal transition
nuc029 may 1 8, 201 5 page 10 of 99 rev 1 . 02 nuc029 series datasheet (nuc029xan only) C supports inter - timer trigger mode (nuc029xan only) C supports internal signal (cpo0, cpo1) for interval measurement (nuc029fae only) ? w dt ( watchdog timer ) C multiple clock sources C supports wake - up from power - down or sleep mode C interrupt or reset selectable on watchdog time - out C t ime - out reset delay period can be selected to 3/18/130/1026 * wdt_clk ( nuc029xan only ) ? w wdt ( window watchdog timer ) ( nuc029 x a n only ) C 6 - bit down counter with 11 - bit pre - scale for wide range window selected ? pwm generator and capture timer ( nuc029 x a n only ) C up to four built - in 16 - bit pwm generators, providing eight pwm outputs or four complementary paired pwm outputs C individual clock source, clock divider, 8 - bit pre - scalar and dead - zone generator for each pwm generator C pwm interrupt synchronized to pwm period C 16 - bit digital capture tim ers with rising/falling capture inputs C supports capture interrupt C internal 10 khz to pwm clock source C polar inverse function C center - aligned type function C timer duty interrupt enable function C two kinds of pwm interrupt period type selection C two kinds of pw m interrupt duty type selection C period/duty trigger adc function C pwm timer synchronous start function ? enhanced pwm generator ( nuc029 f a e only ) C independent 16 - bit pwm duty control units with maximum three outputs C supports group/synchronous/independent/ compl ementary modes C supports one - shot or auto - reload mode C supports edge - aligned and center - aligned type C programmable dead - zone insertion between complementary channels C each output has independent polarity setting control C hardware fault brake protections C supports duty, period, and fault break interrupts C supports duty/period trigger adc conversion C timer comparing matching event trigger pwm to do phase change C supports comparator event trigger pwm to force pwm output low for current period C provides interrupt accumulation function ? uart C up to two sets of uart devices C programmable baud - rate generator C buffered receiver and transmitter, each with 16 bytes fifo C optional flow control function (cts and rts) C supports irda(sir) function C supports rs - 485 function C support s lin function ( nuc029xan only ) ? spi C up to two sets of spi devices C supports master/slave mode
nuc029 may 1 8, 201 5 page 11 of 99 rev 1 . 02 nuc029 series datasheet C full - duplex synchronous serial data transfer C provides 3 wire function C variable length of transfer data from 8 to 32 bits C msb or lsb first data transfer C rx latching data can be either at rising edge or at falling edge of serial clock C tx sending data can be either at rising edge or at falling edge of serial clock C supports byte suspend mode in 32 - bit transmission C 4 - level depth fifo buffer C pll clock source ( nuc029xan only ) ? i 2 c C up to two sets of i 2 c modules C supports master/slave mode C bi - directional data transfer between masters and slaves C multi - master bus (no central master) C arbitration between simultaneously transmitting masters without corruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate con trol C supports 7 - bit addressing mode C supports multiple address recognition (four slave address es with mask option) C supports power - down wake - up function C support s fifo function ( nuc029 f a e only ) ? adc C 12 - bit sar adc with 760 ksps for nuc029xan, and 10 - bit sar adc with 30 0 k sps for nuc029fae C up to eight single - end analog input channels ? or four differential analog input channels (nuc029xan only) C four operation modes ( nuc029fae only support single mode ) ? single mode: a/d conversion is performed one time on a specified channel ? burst mode: a/d converter samples and converts the specified single channel and sequentially stores the result in fifo ? single - cycle scan mode: a/d conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel ? continuous scan mode: a/d converter continuously performs single - cycle scan mode until software stops a/d conversion C an a/d conversion can be started by: ? software write 1 to adst bit ? extern al pin (stadc) ? pwm trigger with optional start delay period C each conversion result is held in data register with valid and overrun indicators C e ach channel has individual data register ( nuc029xan only) C conversion result can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting C i nternal temperature sensor output ( nuc029xan only) ? analog comparator C up to four sets of comparator analog modules C external input or internal band - gap voltage selectable at negative node C interrupt when compared results change C power - down wake - up
nuc029 may 1 8, 201 5 page 12 of 99 rev 1 . 02 nuc029 series datasheet ? ebi (external bus interface) for external memory - mapped device access ( nuc029 l a n only ) C accessible space: 64 kb in 8 - bit mode or 128 kb in 16 - bit mode C sup ports 8 - bit or 16 - bit data width C supports byte - write in 16 - bit data width ? isp ( in - system programming) and icp ( in - circuit programming) ? iap ( in - application programming) ? one built - in t emperature sensor with 1 resolutio n (nuc029x an only ) ? bod ( brown - o ut detector) C with 4 levels: 4. 4 v/3.7v/2.7v/2.2v C supports brown - out interrupt and reset option ? 96 - bit unique id (uid) ? lvr (low voltage reset) C threshold voltage level: 2.0v ? operating temperature: C nuc029la n /nuc029ta n: - 40 ~ 8 5 C nuc029fae: - 40 ~ 10 5 ? reliability: eft > 4 kv, esd hbm pass 4 kv ? packages: C all green package (rohs) C 48 - pin lqfp, 33 - pin qfn , 20 - pin tssop
nuc029 may 1 8, 201 5 page 13 of 99 rev 1 . 02 nuc029 series datasheet 3 abbreviations acronym description acmp analog comparator controller adc analog - to - digi t al converter apb advanced peripheral bus ahb a dvanced h igh - p erformance b us bod brown - out detection ebi external bus interface fifo first in, first out fmc flash memory controller gpio general - purpose input/output hclk the clock of a dvanced h igh - p erformance b us hirc 22.1184 mhz i nternal h igh s peed rc o scillator hxt 4~24 mhz e xternal h igh s peed c rystal o scillator iap in application programming icp in circuit programming isp in system programming ldo low dropout regulator lin local interconnect network lirc 10 khz internal low speed rc oscillator (lirc) lxt 32.768 khz external low speed crystal oscillator nvic nested vectored interrupt controller pclk the clock of advanced peripheral bus pll phase - locked loop pwm pulse width modulation spi serial peripheral interface sps samples per second tmr timer controller uart universal asynchronous receiver/transmitter ucid unique customer id usb universal serial bus wdt watchdog timer wwdt window watchdog timer table 3 - 1 list of abbreviations
nuc029 may 1 8, 201 5 page 14 of 99 rev 1 . 02 nuc029 series datasheet 4 parts information list and pin configuration numicro ? part n umber aprom ( kb ) ram ( kb ) data flash ( kb ) isp rom ( kb ) i / o timer (3 2 - b it ) connectivity pwm (1 6 - b it ) adc (1 2 - b it ) adc (1 0 - b it ) comparator wdt wwdt ebi pll 3 2 . 7 68 k hz crystal oscillator isp / icp / iap package operating temperature range ( ) uart spi i 2 c nuc 029lan 64 4 4 4 40 4 2 2 2 8 8 - 4 - lqfp48 - 40 to +85 nuc 0 29tan 32 4 4 4 24 4 2 1 2 5 5 - 3* - - qfn33 - 40 to +85 nuc 0 29fae 1 6 2 config. 2 17 2 1 1 1 3 - 4 2** - - - tssop20 - 40 to +105 tabl e 4 - 1 numicro tm nuc029 series selection guide note: *: acmp3 only has positive and negative input. **: acmp0 only has positive and negative input, and acmp1 only has positive input.
nuc029 may 1 8, 201 5 page 15 of 99 rev 1 . 02 nuc029 series datasheet figure 4 - 1 numicro ? nuc 029 series s election c ode n u c 0 2 9 x x x a r m c o r t e x m 0 l : l q f p 4 8 t : q f n 3 3 n : - 4 0 ~ + 8 5 e : - 4 0 ~ + 1 0 5 x x x c p u c o r e r e s e r v e d p a r t n u m b e r t e m p e r a t u r e p a c k a g e f : t s s o p 2 0
nuc029 may 1 8, 201 5 page 16 of 99 rev 1 . 02 nuc029 series datasheet pin configuration 4.2 numicro ? 4.2.1.1 numicro ? nuc 029lan lqfp 48 pin figure 4 - 2 numicro ? nuc 029lan lqfp 48 - pin diagram 2 4 4 1 4 3 6 5 8 7 1 0 9 1 1 4 8 4 2 4 1 4 0 3 9 3 8 3 7 3 2 3 3 3 0 3 1 2 8 2 9 2 6 2 7 2 5 1 3 1 4 1 5 1 6 1 8 1 9 2 0 2 1 2 2 1 2 1 7 2 3 2 4 3 4 3 5 3 6 4 6 4 7 4 3 4 5 p w m 3 , p 4 . 3 p 4 . 0 , p w m 0 , t 2 e x l q f p - 4 8 p i n p w m 2 , p 4 . 2 a c m p 2 _ n , m i s o _ 0 , a i n 6 , p 1 . 6 a c m p 0 _ p , m o s i _ 0 , a i n 5 , p 1 . 5 n r s t a c m p 2 _ p , s p i c l k 0 , a i n 7 , p 1 . 7 a v s s a c m p 1 _ n , r x d , p 3 . 0 a c m p 1 _ p , t x d , p 3 . 1 s d a 0 , t 0 , p 3 . 4 c k o , s c l 0 , t 1 , p 3 . 5 t 0 e x , s t a d c , n i n t 0 , p 3 . 2 t 1 e x , m c l k , n i n t 1 , p 3 . 3 x t a l 2 x t a l 1 v s s p 2 . 1 , a d 9 , p w m 1 l d o _ c a p p 2 . 2 , a d 1 0 , p w m 2 p 2 . 3 , a d 1 1 , p w m 3 p 2 . 4 , a d 1 2 , p w m 4 , s c l 1 p 2 . 0 , a d 8 , p w m 0 p 3 . 7 , n r d p 3 . 6 , n w r , c k o , a c m p 0 _ o p 4 . 5 , a l e , s d a 1 p 0 . 7 , a d 7 , s p i c l k 1 p 4 . 6 , i c e _ c l k p 0 . 6 , a d 6 , m i s o _ 1 p 0 . 5 , a d 5 , m o s i _ 1 p 0 . 4 , a d 4 , s p i s s 1 p 2 . 5 , a d 1 3 , p w m 5 , s d a 1 p 2 . 6 , a d 1 4 , p w m 6 , a c m p 1 _ o p 2 . 7 , a d 1 5 , p w m 7 p 4 . 7 , i c e _ d a t p 4 . 1 , p w m 1 , t 3 e x t x d 1 , a i n 3 , p 1 . 3 r x d 1 , a i n 2 , p 1 . 2 a c m p 0 _ n , s p i s s 0 , a i n 4 , p 1 . 4 a c m p 3 _ p , t x d 1 , c t s 1 , a d 0 , p 0 . 0 a v d d a c m p 3 _ n , r x d 1 , r t s 1 , a d 1 , p 0 . 1 t x d , c t s 0 , a d 2 , p 0 . 2 r x d , r t s 0 , a d 3 , p 0 . 3 v d d p 4 . 4 , n c s , s c l 1 n w r h , t 3 , a i n 1 , p 1 . 1 n w r l , t 2 , a i n 0 , p 1 . 0
nuc029 may 1 8, 201 5 page 17 of 99 rev 1 . 02 nuc029 series datasheet 4.2.1.2 numicro ? nuc 029tan qfn 33 pin figure 4 - 3 numicro ? nuc 029tan qfn 33 - pin diagram a c m p 0 _ p , a i n 5 , p 1 . 5 a v s s a c m p 1 _ n , r x d , p 3 . 0 a c m p 1 _ p , t x d , p 3 . 1 s d a 0 , t 0 , p 3 . 4 c k o , s c l 0 , t 1 , p 3 . 5 x t a l 2 x t a l 1 v s s l d o _ c a p p 2 . 2 , p w m 2 p 2 . 3 , p w m 3 p 2 . 4 , p w m 4 , s c l 1 p 3 . 6 , c k o , a c m p 0 _ o p 0 . 7 , s p i c l k 1 p 4 . 6 , i c e _ c l k p 0 . 6 , m i s o _ 1 p 0 . 5 , m o s i _ 1 p 0 . 4 , s p i s s 1 p 2 . 5 , p w m 5 , s d a 1 p 2 . 6 , p w m 6 , a c m p 1 _ o p 4 . 7 , i c e _ d a t t x d 1 , a i n 3 , p 1 . 3 r x d 1 , a i n 2 , p 1 . 2 a c m p 0 _ n , a i n 4 , p 1 . 4 a i n 0 , t 2 , p 1 . 0 a c m p 3 _ p , t x d 1 , c t s 1 , p 0 . 0 a v d d a c m p 3 _ n , r x d 1 , r t s 1 , p 0 . 1 v d d 3 3 v s s 3 2 2 4 q f n - 3 3 p i n 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 0 9 1 1 1 2 1 3 1 4 1 5 1 6 7 8 n r s t t 0 e x , s t a d c , n i n t 0 , p 3 . 2 1 2 3 4 5 6
nuc029 may 1 8, 201 5 page 18 of 99 rev 1 . 02 nuc029 series datasheet 4.2.1.3 numicro ? nuc 029fae tssop 20 pin figure 4 - 4 numicro ? nuc 029fae tssop 20 - pin diagram 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 2 3 4 5 6 7 8 9 1 0 a c m p 0 _ p , r x d , a i n 2 , p 1 . 2 a c m p 0 _ p , t x d , a i n 3 , p 1 . 3 a c m p 0 _ n , a i n 4 , p 1 . 4 a c m p 0 _ p , a i n 5 , p 1 . 5 n r s t a c m p 1 _ p , t 0 e x , s t a d c , n i n t 0 , p 3 . 2 a c m p 1 _ p , s d a 0 , t 0 , p 3 . 4 a c m p 1 _ p , s c l 0 , t 1 , p 3 . 5 x t a l 2 , p 5 . 1 x t a l 1 , p 5 . 0 v d d p 0 . 4 , s p i s s 0 , p w m 5 p 0 . 5 , m o s i _ 0 p 0 . 6 , m i s o _ 0 p 0 . 7 , s p i c l k 0 p 4 . 7 , i c e _ d a t p 4 . 6 , i c e _ c l k p 2 . 5 , p w m 3 p 2 . 4 , p w m 2 v s s t s s o p - 2 0 p i n
nuc029 may 1 8, 201 5 page 19 of 99 rev 1 . 02 nuc029 series datasheet pin description 4.3 numicro ? pin no . pin name pin type description lqfp 48 - pin q f n 33 - pin 1 1 p 1. 5 i/o general purpose digital i/o pin. ain5 ai adc5 analog input. acmp0_p ai comparator0 positive input pin . mosi_0 i/o spi 0 miso (master out , slave in ) pin. 2 p 1.6 i/o general purpose digital i/o pin. ain6 ai adc6 analog input. miso_0 i/o spi 0 miso (master in, slave out) pin. acmp2_n ai comparator 2 negative input pin . 3 p1 .7 i/o general purpose digital i/o pin. ain7 ai adc7 analog input. spiclk0 i/o spi 0 serial clock pin . acmp2_p ai comparator 2 positive input pin . 4 2 nrst i (st) external reset input: active low, with an internal pull - up. set this pin low reset chip to initial state. 5 3 p 3.0 i/o general purpose digital i/o pin. rxd [2] i data receiver input pin for uart0. a c m p 1_ n ai comparator 1 negative input pin . 6 4 av ss a p ground pin for analog circuit. 7 5 p3.1 i/o general purpose digital i/o pin. txd [2] o data transmitter output pin for uart 0 . acmp1_p ai comparator 1 positive input pin 8 6 p3.2 i/o general purpose digital i/o pin. nint0 i external interrupt0 input pin. stadc i adc external trigger input. t0ex i timer0 external capture/reset trigger input pin. 9 p 3.3 i/o general purpose digital i/o pin. nint1 i external interrupt 1 input pin. mclk o ebi external clock output pin . tiex i timer1 external capture/reset trigger input pin. 10 7 p 3.4 i/o general purpose digital i/o pin.
nuc029 may 1 8, 201 5 page 20 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description lqfp 48 - pin q f n 33 - pin t0 i/o timer0 external event counter input pin sda0 i/ o i2c0 data input/output pin. 11 8 p 3.5 i/o general purpose digital i/o pin. t1 i/o timer1 external event counter input pin. scl0 i/o i 2 c0 clock i/o pin. cko [2] o frequency divider output pin. 12 p 4.3 i/o general purpose digital i/o pin. pwm3 [2] i/o pwm3 output/capture input. 13 9 p 3.6 i/o general purpose digital i/o pin. cko [2] o frequency divider output pin. acmp0_o o analog comparator0 output pin. nwr o ebi write enable output pin . 14 p 3.7 i/o general purpose digital i/o pin. nrd o ebi read enable output pin . 15 10 xtal2 o external 4~24 mhz (high speed) crystal output pin. 16 11 xtal1 i (st) external 4~24 mhz (high speed) crystal input pin. 17 12 v ss p ground pin for digital circuit. 33 18 13 ldo_cap p ldo output pin. 19 p 2.0 i/o general purpose digital i/o pin. ad8 i/o ebi address/data bus bit8 pwm0 [2] i /o pwm0 output/capture input. 20 p 2.1 i/o general purpose digital i/o pin. ad9 i/o ebi address/data bus bit 9 pwm1 [2] i/ o pwm 1 output/capture input. 21 14 p2.2 i/o general purpose digital i/o pin. pwm2 [2] i/ o pwm 2 output/capture input. ad10 i/o ebi address/data bus bit 10. 22 15 p2.3 i/o general purpose digital i/o pin. pwm3 [2] i/ o pwm 3 output/capture input. ad11 i/o ebi address/data bus bit 11. 23 16 p2.4 i/o general purpose digital i/o pin.
nuc029 may 1 8, 201 5 page 21 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description lqfp 48 - pin q f n 33 - pin pwm4 i/ o pwm 4 output/capture input. scl1 [2] i/o i 2 c1 clock i/o pin. ad12 i/o ebi address/data bus bit 12. 24 p4.0 i/o general purpose digital i/o pin. pwm0 [2] i/ o pwm 0 output/capture input. t2ex i timer2 external capture/reset trigger input pin. 25 17 p2.5 i/o general purpose digital i/o pin. pwm5 i/ o pwm 5 output/capture input. sda1 [2] i/ o i2c 1 data input/output pin. ad13 i/o ebi address/data bus bit 13. 26 18 p 2.6 i/o general purpose digital i/o pin. pwm6 i/ o pwm 6 output/capture input. acmp1_o o analog comparator1 output pin. ad14 i/o ebi address/data bus bit 14. 27 p 2.7 i/o general purpose digital i/o pin. ad15 i/o ebi address/data bus bit 15. pwm7 i/ o pwm 7 output/capture input. 28 p 4.4 i/o general purpose digital i/o pin. ncs o ebi chip select enable output pin . scl1 [2] i/o i 2 c1 clock i/o pin. 29 p 4.5 i/o general purpose digital i/o pin. ale o ebi address latch enable output pin . sda1 [2] i/ o i2c 1 data input/output pin. 30 19 p 4.6 i/o general purpose digital i/o pin. ice_clk i serial wired debugger clock pin . 31 20 p 4.7 i/o general purpose digital i/o pin. ice_dat i/o serial wired debugger data pin . 32 21 p 0.7 i/o general purpose digital i/o pin. spiclk1 i/o spi 1 serial clock pin . ad7 i/o ebi address/data bus bit 7. 33 22 p 0.6 i/o general purpose digital i/o pin. miso_1 i/o spi 1 miso (master in, slave out) pin.
nuc029 may 1 8, 201 5 page 22 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description lqfp 48 - pin q f n 33 - pin ad6 i/o ebi address/data bus bit 6. 34 23 p 0.5 i/o general purpose digital i/o pin. mosi_1 i/o spi 1 miso (master out , slave in ) pin. ad5 i/o ebi address/data bus bit 5. 35 24 p 0.4 i/o general purpose digital i/o pin. spiss1 i/o spi1 slave select pin. ad4 i/o ebi address/data bus bit 4. 36 p 4.1 i/o general purpose digital i/o pin. pwm1 [2] i/ o pwm 1 output/capture input. t3ex i timer3 external capture/reset trigger input pin. 37 p 0.3 i/o general purpose digital i/o pin. ad3 i/o ebi address/data bus bit 3. rts0 o request to send output pin for uart 0. rxd [2] i data receiver input pin for uart0. 38 p 0.2 i/o general purpose digital i/o pin. ad2 i/o ebi address/data bus bit 2. cts0 i clear to send input pin for uart 0 . txd [2] o data transmitter output pin for uart 0 . 39 25 p 0.1 i/o general purpose digital i/o pin. rts1 o request to send output pin for uart 1. rxd1 [2] i data receiver input pin for uart 1 . a c m p 3 _ n ai comparator 3 negative input pin . ad1 i/o ebi address/data bus bit 1. 40 26 p 0.0 i/o general purpose digital i/o pin. cts1 i clear to send input pin for uart 1 . txd1 [2] o data transmitter output pin for uart 1 . acmp3_p ai comparator 3 positive input pin . ad0 i/o ebi address/data bus bit 0. 41 27 v dd p power supply for i/o ports and ldo source for internal pll and digital circuit. 42 28 av dd ap power supply for internal analog circuit. 43 29 p 1.0 i/o general purpose digital i/o pin.
nuc029 may 1 8, 201 5 page 23 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description lqfp 48 - pin q f n 33 - pin ain0 ai adc0 analog input. t2 i/o timer2 external event counter input pin. nwrl o ebi low byte write enable output pin . 44 p 1.1 i/o general purpose digital i/o pin. ain1 ai adc1 analog input. t3 i/o timer3 external event counter input pin. nwrh o ebi high byte write enable output pin . 45 30 p 1.2 i/o general purpose digital i/o pin. ain2 ai adc2 analog input. rxd1 [2] i data receiver input pin for uart 1 . 46 31 p 1.3 i/o general purpose digital i/o pin. ain3 ai adc3 analog input. txd1 [2] o data transmitter output pin for uart 1 . 47 32 p 1.4 i/o general purpose digital i/o pin. ain4 ai adc4 analog input. acmp0_n ai comparator 0 negative input pin . spiss0 i/o spi0 slave select pin. 48 p 4.2 i/o general purpose digital i/o pin. pwm 2 [2] i/o pwm 2 output /capture input. note 1 : pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power ; st = schmitt trigger note 2 : the pwm0 ~ pwm3, rxd, txd, rxd1, txd1, scl1, sda1 and cko can be assigned to different pins. however, a pin function can only be assigned to a pin at the same time, i.e. software cannot assign rxd to p0.3 and p3.0 at the same time.
nuc029 may 1 8, 201 5 page 24 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description tssop 20 - pin 1 p 1.2 i/o general purpose digital i/o pin. ain2 ai adc2 analog input. rxd i data receiver input pin for uart0. acmp0_p ai comparator0 positive input pin . 2 p 1.3 i/o general purpose digital i/o pin. ain3 ai adc3 analog input. txd o data transmitter output pin for uart 0 . acmp0_p ai comparator0 positive input pin . 3 p1 .4 i/o general purpose digital i/o pin. ain4 ai adc4 analog input. acmp0_n ai comparator0 negative input pin . 4 p 1.5 i/o general purpose digital i/o pin. ain5 ai adc5 analog input. acmp0_p ai comparator0 positive input pin . av ss a p ground pin for analog circuit. 5 nrst i (st) external reset input: active low, with an internal pull - up. set this pin low reset chip to initial state. 6 p3.2 i/o general purpose digital i/o pin. nint0 i external interrupt0 input pin. stadc i adc external trigger input. t0ex i timer0 external capture/reset trigger input pin. acmp1_p ai comparator 1 positive input pin 7 p 3.4 i/o general purpose digital i/o pin. t0 i/o timer0 external event counter input pin sda0 i/ o i2c0 data input/output pin. acmp1_p ai comparator 1 positive input pin 8 p 3.5 i/o general purpose digital i/o pin. t1 i/o timer1 external event counter input pin. scl0 i/o i 2 c0 clock i/o pin. acmp1_p ai comparator 1 positive input pin 9 p 5.1 i/o general purpose digital i/o pin. xtal2 o external 4~24 mhz (high speed) crystal output pin. 10 p 5.0 i/o general purpose digital i/o pin.
nuc029 may 1 8, 201 5 page 25 of 99 rev 1 . 02 nuc029 series datasheet pin no . pin name pin type description tssop 20 - pin xtal1 i (st) external 4~24 mhz (high speed) crystal input pin. 11 v ss p ground pin for digital circuit. 12 p 2.4 i/o general purpose digital i/o pin. pwm2 i /o pwm0 output. 13 p 2.5 i/o general purpose digital i/o pin. pwm3 i/ o pwm 3 output. 14 p 4.6 i/o general purpose digital i/o pin. ice_clk i serial wired debugger clock pin . 15 p 4.7 i/o general purpose digital i/o pin. ice_dat i/o serial wired debugger data pin . 16 p 0.7 i/o general purpose digital i/o pin. spiclk0 i/o spi 0 serial clock pin . 17 p 0.6 i/o general purpose digital i/o pin. miso_0 i/o spi 0 miso (master in, slave out) pin. 18 p 0.5 i/o general purpose digital i/o pin. mosi_0 i/o spi 0 miso (master out , slave in ) pin. 19 p 0.4 i/o general purpose digital i/o pin. spiss0 i/o spi1 slave select pin. pwm5 i/ o pwm 5 output. 20 v dd p power supply for i/o ports and ldo source for internal pll and digital circuit. note 1 : pin type i = digital input, o = digital output; ai = analog input; p = power pin; ap = analog power ; st = schmitt trigger
nuc029 may 1 8, 201 5 page 26 of 99 rev 1 . 02 nuc029 series datasheet 5 functional descripti on arm? cortex ? - m0 core 5.1 the cortex ? - m0 processor is a configurable, multistage, 32 - bit risc processor , which has an amba ahb - lite interface and includes an nvic component. it also has optional hardware debug functionality. the processor can execute thumb code and is compatible with other cortex ? - m profile processor. the profile supports two modes - thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entere d on reset, and can be entered as a result of an exception return. figure 5 - 1 shows the functional controller of processor. figure 5 - 1 functional controller diagram the implemented device provides the following components and features : ? a low gate count processor: - armv6 - m thumb ? instruction set - thumb - 2 technology - armv6 - m compliant 24 - bit systick timer - a 32 - bit hardware multiplier - s ystem interface support ed with little - endian data accesses - a bility to have deterministic, fixed - latency, interrupt handling - load/store - multiples and multicycle - multiplies that can be abandoned and restarted to facilitate rapid interrupt handling - c application binary interface compliant exception model. th is is the armv6 - m, c application binary interface (c - abi) compliant exception model that enables the use of pure c functions as interrupt handlers - low p ower s leep mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or the return f rom interrupt sleep - on - exit feature ? nvic: c o r t e x t m - m 0 p r o c e s s o r c o r e n e s t e d v e c t o r e d i n t e r r u p t c o n t r o l l e r ( n v i c ) b r e a k p o i n t a n d w a t c h p o i n t u n i t d e b u g g e r i n t e r f a c e b u s m a t r i x d e b u g a c c e s s p o r t ( d a p ) d e b u g c o r t e x t m - m 0 p r o c e s s o r c o r t e x t m - m 0 c o m p o n e n t s w a k e u p i n t e r r u p t c o n t r o l l e r ( w i c ) i n t e r r u p t s s e r i a l w i r e o r j t a g d e b u g p o r t a h b - l i t e i n t e r f a c e
nuc029 may 1 8, 201 5 page 27 of 99 rev 1 . 02 nuc029 series datasheet - 32 external interrupt inputs, each with four levels of priority - dedicated non - m askable interrupt (nmi) input - support s for both level - sensitive and pulse - sensitive interrupt lines - supports wake - up interrupt controll er (wic) and , providing u ltra - low p ower s leep mode ? debug support - four hardware breakpoints - two watchpoints - program counter sampling register (pcsr) for non - intrusive code profiling - single step and vector catch capabilities ? bus interfaces: - single 32 - bit amb a - 3 ahb - lite system interface that provides simple integration to all system peripherals and memory - single 32 - bit slave port that supports the dap (debug access port)
nuc029 may 1 8, 201 5 page 28 of 99 rev 1 . 02 nuc029 series datasheet system manager 5.2 overview 5.2.1 system management includes the following sections: ? system resets ? system power architecture ? system memory map ? system management registers for part number id, chip reset and on - chip controllers reset , multi - functional pin control ? system timer (systick) ? nested vectored interrupt controller (nvic) ? system control reg isters system reset 5.2.2 the system reset can be issued by one of the following listed events. for these reset event flags can be read by rstsrc register. ? hardware reset C power - o n reset (por) C l ow level on the reset pin (nrst) C watchdog time - out reset (wdt) C low vo ltage reset (lvr) C brown - out detector reset (bod) ? software reset C mc u reset - sysresetreq(aircr[2]) C cortex ? - m0 core one - shot reset - cpu_rst(iprstc1[1]) C chip one - shot reset - chip_rst(iprstc 1 [0 ]) note: isp c on.bs keeps the original value after mcureset and cpu reset.
nuc029 may 1 8, 201 5 page 29 of 99 rev 1 . 02 nuc029 series datasheet system power distribution 5.2.3 in this chip, the power distribution is divided into three segments. ? analog power from av dd and av ss provides the power for analog components operation. av dd must be equal to v dd to avoid leakage current. ? digital power from v dd and v ss supplies the power to the i/o pins and internal regulator which provides a fixed 1.8 v power for digital operation. ? build - in a capacitor for internal voltage regulator . (nuc029fae only) the output of internal voltage regulator , ldo _c ap , require s an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level with the digital power (v dd ). figure 5 - 2 shows the numicro ? nuc0 29 xan power distribution and figure 5 - 3 shows the numicro ? nuc0 29fae power distribution . figure 5 - 2 numicro ? nuc0 29 xan power distribution diagram 5 v t o 1 . 8 v l d o p l l 1 2 - b i t s a r - a d c b r o w n o u t d e t e c t o r p o r 5 0 p o r 1 8 l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r t e m p e r a t u r e s e n s o r f l a s h d i g i t a l l o g i c 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z a n d 1 0 k h z o s c i l l a t o r a v d d a v s s v d d v s s l d o _ c a p 1 u f i o c e l l g p i o p i n s n u m i c r o t m n u c 0 2 9 x a n p o w e r d i s t r i b u t i o n
nuc029 may 1 8, 201 5 page 30 of 99 rev 1 . 02 nuc029 series datasheet figure 5 - 3 numicro ? nuc0 29fae power distribution diagram system memory map 5.2.4 the numicro ? nuc 0 29 s eries provides 4g - byte addressing space. the memory locations assigned to each on - chip controllers are shown in the following table. the detailed register definition, addressing space, and programming detailed will be described in the following sections for each on - chip peripheral. the numicro ? nuc 0 29 s eries only supports little - endian data format. address space token controllers flash and sram memory space 0x0000_0000 C 0x000 0 _ffff flash_ba flash memory space ( 64 kb) 0x2000_0000 C 0x2000_ 0 fff sram_ba sram memory space ( 4 kb) ebi space (0x6000_0000 ~ 0x6001_ffff) (NUC029LAN only) 0x 6 000_0000 C 0x 6 00 1 _ ff ff ebi_ba external memory space (128 kb ) ahb controllers space (0x5000_0000 ~ 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 5 v t o 1 . 8 v l d o 1 0 - b i t s a r - a d c b r o w n o u t d e t e c t o r p o r 1 8 l o w v o l t a g e r e s e t a n a l o g c o m p a r a t o r f l a s h d i g i t a l l o g i c 1 . 8 v i n t e r n a l 2 2 . 1 1 8 4 m h z a n d 1 0 k h z o s c i l l a t o r v d d v s s i o c e l l g p i o p i n s n u m i c r o t m n u c 0 2 9 f a e p o w e r d i s t r i b u t i o n 5 0 0 p f
nuc029 may 1 8, 201 5 page 31 of 99 rev 1 . 02 nuc029 series datasheet 0x5000_0200 C 0x5000_02ff clk_ba clock control registers 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gpio_ba gpio (p0 ~ p4) control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers 0x500 1 _ 0 000 C 0x500 1 _ 03 ff ebi_ctl_ba ebi control registers (NUC029LAN o nly) 0x500 1 _ 4 000 C 0x500 1 _ 7f ff hdiv_ba hardware divider register (nuc029xan o nly) apb controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 C 0x4000_ 40 ff wdt_ba watchdog timer control registers 0x4000_4 1 00 C 0x4000_7fff wwdt_ba window watchdog timer control registers (nuc029 xan o nly) 0x4001_0000 C 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 C 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 C 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 C 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm0/1/2/3 control registers 0x4005_0000 C 0x4005_3fff uart0_ba uart0 control registers 0x400d_0000 C 0x400d_3fff acmp 01 _ba analog comparator 0/ analog comparator 1 control registers 0x400e_0000 C 0x400e_ffff adc_ba analog - digital - converter (adc) control registers 0x4011_0000 C 0x4011_3fff tmr23_ba timer2/timer3 control registers 0x4012_0000 C 0x4012_3fff i2c1_ba i 2 c1 interface control registers (nuc029 xan o nly) 0x4014_0000 C 0x4014_3fff pwmb_ba pwm4/5/6/7 control registers 0x4015_0000 C 0x4015_3fff uart1_ba uart1 control registers 0x401 d _0000 C 0x401 d _3fff acmp23 _ba analog comparator 2/ analog comparator 3 control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff s yst _ba system timer control registers 0xe000_e100 C 0xe000_ecff nvic _ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f sc b _ba system control registers table 5 - 1 numicro ? nuc029xan address space assignments for on - chip controllers address space token controllers flash and sram memory space 0x0000_0000 C 0x000 0 _ 3 fff flash_ba flash memory space ( 16 kb) 0x2000_0000 C 0x2000_ 0 fff sram_ba sram memory space ( 2 kb) ahb controllers space (0x5000_0000 ~ 0x501f_ffff) 0x5000_0000 C 0x5000_01ff gcr_ba system global control registers 0x5000_0200 C 0x5000_02ff clk_ba clock control registers
nuc029 may 1 8, 201 5 page 32 of 99 rev 1 . 02 nuc029 series datasheet 0x5000_0300 C 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 C 0x5000_7fff gp_ba gpio (p0 ~ p5) control registers 0x5000_c000 C 0x5000_ffff fmc_ba flash memory control registers apb controllers space (0x4000_0000 ~ 0x40 1 f_ffff) 0x4000_4000 C 0x4000_ 7f ff wdt_ba watchdog timer control registers 0x4001_0000 C 0x4001_3fff tmr_ba timer0/timer1 control registers 0x4002_0000 C 0x4002_3fff i2c_ba i 2 c interface control registers 0x4003_0000 C 0x4003_3fff spi_ba spi with master/slave function control registers 0x4004_0000 C 0x4004_3fff pwma_ba pwm control registers 0x4005_0000 C 0x4005_3fff uart_ba uart control registers 0x400d_0000 C 0x400d_3fff acm p _ba analog comparator control registers 0x400e_0000 C 0x400e_ 3 fff adc_ba analog - digital - converter (adc) control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 C 0xe000_e0ff s cs _ba system timer control registers 0xe000_e100 C 0xe000_ecff s cs _ba external interrupt controller control registers 0xe000_ed00 C 0xe000_ed8f sc b _ba system control registers table 5 - 2 numicro ? nuc029fae address space assignments for on - chip controllers
nuc029 may 1 8, 201 5 page 33 of 99 rev 1 . 02 nuc029 series datasheet whole system memory mapping 5.2.5 figure 5 - 4 numicro ? nuc029xan whole system memory mapping 4 gb 0xffff_ffff | system control 0xe000_f000 system control block 0xe000_ed00 scb_ba 0xe000_efff external interrupt controller 0xe000_e100 nvic_ba 0xe000_e000 system timer control 0xe000_e010 syst_ba 0xe000_dfff system control space 0xe000_e000 scs_ba | 0x6002_0000 0x6001_ffff 0x6000_0000 0x5fff_ffff | 0x5020_0000 ahb peripherals 0x501f_ffff hardw are divider control 0x5001_4000 hdiv_ba 0x5000_0000 ebi control 0x5001_0000 ebi_ctl_ba 0x4fff_ffff fmc 0x5000_c000 flash_ba gpio control 0x5000_4000 gpio_ba interrupt multiplexer control 0x5000_0300 int_ba 0x4020_0000 clock control 0x5000_0200 clk_ba 0x401f_ffff system global control 0x5000_0000 gcr_ba 1 gb 0x4000_0000 0x3fff_ffff apb peripherals acmpb control 0x401d_0000 acmp23_ba uart1 control 0x4015_0000 uart1_ba 0x2000_1000 pwm4/5/6/7 control 0x4014_0000 pwmb_ba 0x2000_0fff i2c1 control 0x4012_0000 i2c1_ba timer2/timer3 control 0x4011_0000 tmr23_ba adc control 0x400e_0000 adc_ba acmpa control 0x400d_0000 acmp01_ba 0.5 gb 0x2000_0000 uart0 control 0x4005_0000 uart0_ba 0x1fff_ffff pwm0/1/2/3 control 0x4004_0000 pwma_ba spi1 control 0x4003_4000 spi1_ba spi0 control 0x4003_0000 spi0_ba 0x0001_0000 i2c control 0x4002_0000 i2c0_ba 64 kb on-chip flash (NUC029LAN) 0x0000_ffff timer0/timer1 control 0x4001_0000 tmr01_ba 0x0000_7fff wdt control 0x4000_4100 wwdt_ba 0 gb 0x0000_0000 wwdt control 0x4000_4000 wdt_ba | | apb reserved reserved | | 4 kb sram 32 kb on-chip flash (nuc029tan) reserved ebi reserved ahb reserved | system control reserved
nuc029 may 1 8, 201 5 page 34 of 99 rev 1 . 02 nuc029 series datasheet figure 5 - 5 numicro ? nuc029fae whole system memory mapping system control 4 gb 0xffff_ffff system c ontrol 0xe000_ed00 sc s_ba | external interrupt c ontrol 0xe000_e100 sc s_ba 0xe000_f000 system timer c ontrol 0xe000_e010 sc s_ba 0xe000_efff 0xe000_e000 0xe000_e00f | 0x6002_0000 0x6001_ffff 0x6000_0000 0x5fff_ffff | 0x5020_0000 ahb peripherals 0x501f_ffff fmc 0x5000_c 000 fmc _ba 0x5000_0000 gpio c ontrol 0x5000_4000 gp_ba 0x4fff_ffff interrupt multiplexer c ontrol 0x5000_0300 int_ba c lock c ontrol 0x5000_0200 c lk_ba system global c ontrol 0x5000_0000 gc r_ba 0x4020_0000 0x401f_ffff 1 gb 0x4000_0000 0x3fff_ffff apb peripherals adc c ontrol 0x400e_0000 adc _ba ac mp c ontrol 0x400d_0000 c mp_ba uart c ontrol 0x4005_0000 uart_ba 0x2000_0800 pwm c ontrol 0x4004_0000 pwm_ba 0x2000_07ff spi c ontrol 0x4003_0000 spi_ba 0.5 gb 0x2000_0000 i2c c ontrol 0x4002_0000 i2c _ba 0x1fff_ffff timer0/timer1 c ontrol 0x4001_0000 tmr_ba wdt c ontrol 0x4000_4000 wdt_ba 0x0000_4000 0x0000_3fff 0 gb 0x0000_0000 2 kb sram reserved reserved reserved reserved apb reserved ahb reserved 16 kb on-chip flash (nuc 029fae) | | | | system c ontrol reserved
nuc029 may 1 8, 201 5 page 35 of 99 rev 1 . 02 nuc029 series datasheet system timer (systick) 5.2.6 the cortex ? - m0 includes an integrated system timer, systick , which provides a simple, 24 - bit clear - on - write, decrementing, wrap - on - zero counter with a flexible control mechanism. the counter can be used as a real time operating system (rtos) tick timer or as a simple counter. when system timer is enabled, it will count d own from the value in the systick current value register (syst_cvr) to 0 , and reload (wrap) to the value in the systick reload value register (syst_rvr) on the next clock cycle, then decrement on subsequent clocks. when the counter transitions to 0 , the countflag status bit is set. the countflag bit clears on reads. the syst_cvr value is unknown on reset. software should write to the register to clear it to 0 before enabling the feature. this ensures the timer will count from the syst_rvr value rather tha n an arbitrary value when it is enabled. if the syst_rvr is 0 , the timer will be maintained with a current value of 0 after it is reloaded with this value. this mechanism can be used to disable the feature independently from the timer enable bit. for more detailed information, please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual. nested vectored interrupt controller (nvic) 5.2.7 the cortex ? - m0 provides an interrupt controller as an integral part of the ex ception mode, named as nested vectored interrupt controller (nvic) , which is closely coupled to the processor core and provides following features: ? nested and vectored interrupt support ? automatic processor state saving and restoration ? reduced and determi nistic interrupt latency the nvic prioritizes and handles all supported exceptions. all exceptions are handled in handler mode. this nvic architecture supports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most o f the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will compare the priority of the new interrupt to the current running ones priority. if the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. when a n interrupt is accepted, the starting address of the interrupt service routine (isr) is fetched from a vector table in memory. there is no need to determine which interrupt is accepte d and branch to the starting address of the correlated isr by software. while the starting address is fetched, nvic will also automatically save processor state including the registers pc, psr, lr, r0~r3, r12 to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume the normal execution. thus it will take less and deterministic time to process the interrupt request. the nvic supports tail chaining which handles back - to - back interrupts efficiently without th e overhead of states saving and restoration and therefore reduces delay time in switching to pending isr at the end of current isr. the nvic also supports late arrival which improves the efficiency of concurrent isrs. when a higher priority interrupt req uest occurs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penalty. thus it advances the real - time capability. for more detailed information , please refer to the arm ? cortex ? - m0 technical reference manual and arm ? v6 - m architecture reference manual.
nuc029 may 1 8, 201 5 page 36 of 99 rev 1 . 02 nuc029 series datasheet 5.2.7.1 exception model and system interrupt map the following table lists the exception model supported by numicro ? nuc 029 s eries . software can set f our levels of priority on some of these exceptions as well as on all interrupts. the highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. the default priority of all the user - configurable interrupts is 0. note t hat priority 0 is treated as the fourth priority on the system, after three system exceptions reset, nmi and hard fault. exception name vector number priority reset 1 - 3 nmi 2 - 2 hard fault 3 - 1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5 - 3 exception model
nuc029 may 1 8, 201 5 page 37 of 99 rev 1 . 02 nuc029 series datasheet vector number interrupt number ( bit in interrupt registers ) interrupt name source module interrupt description power - d own wake - u p 1 ~ 15 - - - system exceptions - 16 0 bod_ int brown - out brown - out low voltage detected interrupt yes 17 1 wdt_int wdt watchdog timer interrupt yes 18 2 eint0 gpio external signal interrupt from p 3.2 pin yes 19 3 eint1 gpio external signal interrupt from p 3 . 3 pin yes 20 4 p 0/1 _int gpio external signal interrupt from p0 [7:0]/ p1 [7:0] yes 21 5 p 2/3/4 _int gpio external signal interrupt from p2 [7:0]/p3[7:0]/p 4 [7:0], except p3.2 and p3.3 yes 22 6 pwm a _int pwm 0~3 pwm 0, pwm 1, pwm 2 and pwm3 interrupt no 23 7 pwmb _int pwm 4~7 pwm 4, pwm 5, pwm 6 and pwm7 interrupt no 24 8 tmr0_int tmr0 timer 0 interrupt yes 25 9 tmr1_int tmr1 timer 1 interrupt yes 26 10 tmr 2 _int tmr 2 timer 2 interrupt yes 27 11 tmr 3 _int tmr 3 timer 3 interrupt yes 28 12 uart 0 _int uart 0 uart 0 interrupt yes 29 13 uart 1 _int uart 1 uart 1 interrupt yes 30 14 spi0_int spi 0 spi 0 interrupt no 31 15 spi 1 _int spi 1 spi 1 interrupt no 32 ~ 33 16 ~ 17 - - reserved - 34 18 i2c 0 _int i 2 c0 i 2 c 0 interrupt yes 35 19 i2c 1 _int i 2 c 1 i 2 c 1 interrupt yes 36 ~ 40 20 ~ 24 - - reserved - 4 1 2 5 acmp01 _int acmp0/1 analog comparator0 or comparator1 interrupt yes 4 2 2 6 acmp23 _int acmp2/3 analog comparator2 or comparator3 interrupt yes 43 27 - - reserved - 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from power - down state yes 45 29 adc_int adc adc interrupt no 46 ~ 47 30 ~ 31 - - reserved - table 5 - 4 numicro ? nuc029xan system interrupt map
nuc029 may 1 8, 201 5 page 38 of 99 rev 1 . 02 nuc029 series datasheet vector number interrupt number ( bit in interrupt registers ) interrupt name source module interrupt description power - d own wake - u p 1 ~ 15 - - - system exceptions - 16 0 bod_ int brown - out brown - out low voltage detected interrupt yes 17 1 wdt_int wdt watchdog timer interrupt yes 18 2 eint0 gpio external signal interrupt from p 3.2 pin yes 19 3 - - reserved - 20 4 p 0/1 _int gpio external signal interrupt from p0[7:0]/p1[7:0] yes 21 5 p 2/3/4 _int gpio external signal interrupt from p2[7:0]/p3[7:0]/p4[7:0], except p3.2 yes 22 6 pwm_int pwm pwm interrupt no 23 7 brake _int pwm pwm interrupt no 24 8 tmr0_int tmr0 timer0 interrupt yes 25 9 tmr1_int tmr1 timer1 interrupt yes 26 ~ 27 10 ~ 11 - - reserved - 28 12 uart_int uart uart interrupt yes 29 13 - - reserved - 30 14 spi_int spi spi interrupt no 31 15 - - reserved - 32 16 gp5_int gpio external signal interrupt from p5 yes 33 17 hirc_trim_ int hirc hirc trim interrupt no 34 18 i2c_int i 2 c i 2 c interrupt yes 3 5 ~ 40 19 ~ 24 - - reserved - 4 1 2 5 acmp _int acmp analog comparator interrupt yes 42 ~ 43 26 ~ 27 - - reserved - 44 28 pwrwu_int clkc clock controller interrupt for chip wake - up from power - down state yes 45 29 adc_int adc adc interrupt no 46 ~ 47 30 ~ 31 - - reserved - table 5 - 5 numicro ? nuc029fae system interrupt map
nuc029 may 1 8, 201 5 page 39 of 99 rev 1 . 02 nuc029 series datasheet 5.2.7.2 vector table when an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (isr) from a vector table in memory. for armv6 - m, the vector table base address is fixed at 0x00000000. the vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handl ers. the vector number on previous page defines the order of entries in the vector table associated with exception handler entry as illustrated in previous section. vector table word offset description 0 sp_main C the main stack pointer vector number exception entry pointer using that vector number table 5 - 6 vector table format 5.2.7.3 operation description nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set - enable or inte rrupt clear - enable register bit - field. the registers use a write - 1 - to - enable and write - 1 - to - clear policy, both registers reading back the current enabled state of the corresponding interrupts. when an interrupt is disabled, interrupt assertion will cause t he interrupt to become pending, however, the interrupt will not activate. if an interrupt is active when it is disabled, it remains in its active state until cleared by reset or an exception return. clearing the enable bit prevents new activations of the a ssociated interrupt. nvic interrupts can be pended/un - pended using a complementary pair of registers to those used to enable/disable the interrupts, named the set - pending register and clear - pending register respectively. the registers use a write - 1 - to - enab le and write - 1 - to - clear policy, both registers reading back the current pended state of the corresponding interrupts. the clear - pending register has no effect on the execution status of an active interrupt. nvic interrupts are prioritized by updating an 8 - bit field within a 32 - bit register (each register supporting four interrupts). the general registers associated with the nvic are all accessible from a block of memory in the system control space and will be described in next section.
nuc029 may 1 8, 201 5 page 40 of 99 rev 1 . 02 nuc029 series datasheet clock controller of numicro ? overview 5.3.1 the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clo ck source selection and clock divider. the chip enters power - down mode when cortex ? - m0 core executes the wfi instruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . after that, chip enter s power - down mode and wait for wake - up interrupt source triggered to leave power - down mode. in the power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal oscillator (hxt) and 22.1184 mhz internal high speed rc oscillator (hirc) to reduce the ove rall system power consumption. the following figures show the clock generator and the overview of the clock source control. the clock generator consists of 4 clock sources as listed below: ? 4~24 mhz external high speed crystal oscillator (hxt) ? p rogrammable pll output clock frequency (pll source can be selected from external 4~24 mhz external high speed crystal oscillator (hxt) or 22.1184 mhz internal high speed rc oscillator (hirc)) (pll fout ) ? 22.1184 mhz i nternal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc) note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 6 numicro ? nuc029xan clock g enerator b lock d iagram x t a l 2 4 ~ 2 4 m h z h x t x t l 1 2 m _ e n ( p w r c o n [ 0 ] ) x t a l 1 2 2 . 1 1 8 4 m h z h i r c o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 0 1 p l l p l l _ s r c ( p l l c o n [ 1 9 ] ) p l l f o u t 1 0 k h z l i r c o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) h x t h i r c l i r c l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r
nuc029 may 1 8, 201 5 page 41 of 99 rev 1 . 02 nuc029 series datasheet note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 7 numicro ? nuc029xan clock source controller overview (1/2) a d c u a r t 0 - 2 a c m p 0 a c m p 1 i 2 c 0 c p u f m c e b i 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t r e s e r v e d h x t l i r c h i r c 0 0 0 c l k s e l 0 [ 2 : 0 ] 1 / ( h c l k _ n + 1 ) p c l k c p u c l k h c l k 1 1 0 1 0 0 p l l f o u t h x t h c l k c l k s e l 1 [ 3 : 2 ] h i r c 1 / ( a d c _ n + 1 ) 1 / ( u a r t _ n + 1 ) 1 1 0 1 0 0 p l l f o u t h x t h i r c c l k s e l 1 [ 2 5 : 2 4 ] h i r c 1 0 1 0 s p i 0 c l k s e l 1 [ 4 : 5 ] h c l k p l l f o u t b o d l i r c h d i v s p i 1 l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r i 2 c 1 a c m p 2 a c m p 3
nuc029 may 1 8, 201 5 page 42 of 99 rev 1 . 02 nuc029 series datasheet note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 8 numicro ? nuc029xan clock source controller overview (2/2) 1 1 1 0 1 1 0 1 0 0 0 1 h x t r e s e r v e d h x t h c l k h i r c 0 0 0 1 / 2 1 / 2 1 / 2 c l k s e l 0 [ 5 : 3 ] 1 0 s y s t i c k t m r 3 f d i v p w m 0 - 1 w d t p w m 2 - 3 p w m 4 - 5 p w m 6 - 7 t m r 0 t m r 1 t m r 2 s y s t _ c s r [ 2 ] c p u c l k 1 1 1 0 0 1 0 0 h c l k h x t h i r c r e s e r v e d c l k s e l 2 [ 7 : 2 ] c l k s e l 1 [ 3 1 : 2 8 ] l i r c 1 1 1 0 c l k s e l 1 [ 1 : 0 ] h c l k 1 / 2 0 4 8 0 1 r e s e r v e d 0 1 1 0 1 0 0 0 0 h c l k h x t t 0 ~ t 3 c l k s e l 1 [ 2 2 : 2 0 ] c l k s e l 1 [ 1 8 : 1 6 ] c l k s e l 1 [ 1 4 : 1 2 ] c l k s e l 1 [ 1 0 : 8 ] l i r c h i r c 1 0 1 1 1 1 w w d t 1 1 1 0 c l k s e l 2 [ 1 7 : 1 6 ] l i r c h c l k / 2 0 4 8 l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r
nuc029 may 1 8, 201 5 page 43 of 99 rev 1 . 02 nuc029 series datasheet system clock and systick clock 5.3.2 the system clock has 4 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_s (clksel0[2:0]). the block diagram is show n in figure 5 - 9 . note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 9 numicro ? nuc029xan system clock block diagram the clock source of systick in cortex ? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 4 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3]). the block diagram is show n in figure 5 - 10 . note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 10 numicro ? nuc029xan systick clock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 p l l f o u t r e s e r v e d 4 ~ 2 4 m h z h x t 1 0 k h z l i r c h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z h i r c 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2
nuc029 may 1 8, 201 5 page 44 of 99 rev 1 . 02 nuc029 series datasheet power - down mode clock 5.3.3 when chip enters power - down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock s are still active in power - down mode. the clocks still kep t active are list ed below: ? clock generator - 10 khz i nternal low speed rc oscillator clock (lirc) ? peripherals clock ( w hen 10 khz inte r tnal low speed rc oscillator is adopted as clock source)
nuc029 may 1 8, 201 5 page 45 of 99 rev 1 . 02 nuc029 series datasheet frequency divider output 5.3.4 this device is equipped with a power - of - 2 frequency divider which is composed by16 chained divide - by - 2 shift registers. one of the 16 shift register outputs selected by a sixteen to one multiplexer is re flected to c ko pin. therefore there are 16 options of power - of - 2 divided clocks with the frequency from f in /2 1 to f in /2 16 where f in is input clock frequency to the clock divider. the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4 - bit value in fsel (frqdiv[3:0]). when writ ing 1 to divider_en (frqdiv [4]), the chained counter starts to count. when writ ing 0 to divider_en (frqdiv[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 11 numicro ? nuc029xan clock source of frequency divider figure 5 - 12 numicro ? nuc029xan frequency divider block diagram 1 1 1 0 0 1 0 0 h c l k 1 0 k h z l i r c 4 ~ 2 4 m h z h x t 2 2 . 1 1 8 4 m h z h i r c f r q d i v _ s ( c l k s e l 2 [ 3 : 2 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) f r q d i v _ c l k l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 : : 1 6 t o 1 m u x 1 / 2 1 / 2 2 1 / 2 3 1 / 2 1 5 1 / 2 1 6 . . . f s e l ( f r q d i v [ 3 : 0 ] ) c k o 1 6 c h a i n e d d i v i d e - b y - 2 c o u n t e r d i v i d e r _ e n ( f r q d i v [ 4 ] ) e n a b l e d i v i d e - b y - 2 c o u n t e r f r q d i v _ c l k
nuc029 may 1 8, 201 5 page 46 of 99 rev 1 . 02 nuc029 series datasheet clock controller of numicro ? overview 5.4.1 the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also implements the power control function with the individually clock on/off control, clock source selection and clock di vider. the chip enters power - down mode when cortex ? - m0 core executes the wfi instruction only if the pwr_down_en (pwrcon[7]) bit and pd_wait_cpu (pwrcon[8]) bit are both set to 1 . after that, chip enter s power - down mode and wait for wake - up interrupt sourc e triggered to leave power - down mode. in the power - down mode, the clock controller turns off the 4~24 mhz external high speed crystal oscillator (hxt) and 22.1184 mhz internal high speed rc oscillator (hirc) to reduce the overall system power consumption. t he following figures show the clock generator and the overview of the clock source control. the clock generator consists of 3 clock sources as listed below: ? 4~24 mhz external high speed crystal oscillator (hxt) or 32 .768 k hz external low speed crystal oscillator (lxt) ? 22.1184 mhz i nternal high speed rc oscillator (hirc) ? 10 khz internal low speed rc oscillator (lirc) note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and s table. figure 5 - 13 numicro ? nuc029fae clock g enerator b lock d iagram x t a l 2 4 ~ 2 4 m h z h x t o r 3 2 . 7 6 8 k h z l x t x t l c l k _ e n ( p w r c o n [ 1 : 0 ] ) x t a l 1 2 2 . 1 1 8 4 m h z h i r c o s c 2 2 m _ e n ( p w r c o n [ 2 ] ) 1 0 k h z l i r c o s c 1 0 k _ e n ( p w r c o n [ 3 ] ) h x t o r l x t h i r c l i r c l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r l x t = 3 2 . 7 6 8 k h z e x t e r n a l l o w s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r
nuc029 may 1 8, 201 5 page 47 of 99 rev 1 . 02 nuc029 series datasheet system clock and systick clock 5.4.2 the system clock has 3 clock sources which were generated from clock generator block. the clock source switch depends on the register hclk_s (clksel0[2:0]). the block diagram is show n in figure 5 - 14 . note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 14 numicro ? nuc029fae system clock block diagram the clock source of systick in cortex ? - m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the systick clock (stclk) has 4 clock sources. the clock source switch depends on the setting of the register stclk_s (clksel0[5:3]). the block diagram is show n in figure 5 - 15 . note: before clock switching, both the pre - selected and newly selected clock sources must be turned on and stable. figure 5 - 15 numicro ? nuc029fae systick clock control block diagram 1 1 1 0 1 1 0 1 0 0 0 1 4 ~ 2 4 m h z 3 2 . 7 6 8 k h z 4 ~ 2 4 m h z h c l k s t c l k _ s ( c l k s e l 0 [ 5 : 3 ] ) s t c l k 2 2 . 1 1 8 4 m h z 0 0 0 1 / 2 1 / 2 1 / 2 1 1 1 0 1 1 0 1 0 0 0 1 r e s e r v e d r e s e r v e d 4 ~ 2 4 m h z h x t o r 3 2 . 7 6 8 k h z l x t 1 0 k h z l i r c h c l k _ s ( c l k s e l 0 [ 2 : 0 ] ) 2 2 . 1 1 8 4 m h z h i r c 0 0 0 1 / ( h c l k _ n + 1 ) h c l k _ n ( c l k d i v [ 3 : 0 ] ) c p u i n p o w e r d o w n m o d e c p u a h b a p b c p u c l k h c l k p c l k l e g e n d : h x t = 4 ~ 2 4 m h z e x t e r n a l h i g h s p e e d c r y s t a l o s c i l l a t o r h i r c = 2 2 . 1 1 8 4 m h z i n t e r n a l h i g h s p e e d r c o s c i l l a t o r l i r c = 1 0 k h z i n t e r n a l l o w s p e e d r c o s c i l l a t o r
nuc029 may 1 8, 201 5 page 48 of 99 rev 1 . 02 nuc029 series datasheet isp clock source select ion 5.4.3 the clock source of isp is from ahb clock (hclk). please refer to the register ahbclk. figure 5 - 16 numicro ? nuc029fae ahb clock source for hclk module clock source select ion 5.4.4 the peripheral clock ha s different clock source switch setting s depend ing on different peripheral s . i s p _ e n ( a h b c l k [ 2 ] ) h c l k i s p ( i n s y s t e m p r o g r a m m e r ) w d t _ e n ( a p b c l k [ 0 ] ) p c l k w a t c h d o g t i m e r t i m e r 1 t i m e r 0 t m r 0 _ e n ( a p b c l k [ 2 ] ) t m r 1 _ e n ( a p b c l k [ 3 ] ) f d i v _ e n ( a p b c l k [ 6 ] ) i 2 c _ e n ( a p b c l k [ 8 ] ) s p i _ e n ( a p b c l k [ 1 2 ] ) u a r t _ e n ( a p b c l k [ 1 6 ] ) p w m 0 1 _ e n ( a p b c l k [ 2 0 ] ) p w m 2 3 _ e n ( a p b c l k [ 2 1 ] ) p w m 4 5 _ e n ( a p b c l k [ 2 2 ] ) c m p _ e n ( a p b c l k [ 3 0 ] ) a d c _ e n ( a p b c l k [ 2 8 ] ) f r e q u e n c y d i v i d e r i 2 c s p i u a r t p w m 0 1 p w m 2 3 p w m 4 5 a c m p a d c
nuc029 may 1 8, 201 5 page 49 of 99 rev 1 . 02 nuc029 series datasheet figure 5 - 17 numicro ? nuc029fae peripherals clock source select ion for pclk ext . clk ( hxt o r lxt ) hirc lirc pclk wdt yes no yes yes timer0 yes yes yes yes timer1 yes yes yes yes i 2 c no no no yes spi no no no yes uart yes yes no no pwm no no no yes adc yes yes no yes acmp no no no yes table 5 - 7 numicro ? nuc029fae peripheral clock source select ion t able power - down mode clock 5.4.5 when chip enters power - down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. some clock sources and peripherals clock s are still active in power - down mode. the clocks still kep t active are list ed below: ? clock generator - 10 khz i nternal low speed rc oscillator clock (lirc) ? 32.768 k hz e xternal low speed crystal oscillator (lxt) clock (if pd_32k = 1 and xtlclk_en[1:0] = 10 ) ? peripheral s clock (when 10 khz low speed oscillator is adopted as clock source) - watchdog clock - timer 0/1 clock
nuc029 may 1 8, 201 5 page 50 of 99 rev 1 . 02 nuc029 series datasheet f lash m emory c ontroller (fmc) 5.5 overview 5.5.1 the numicro ? nuc 029 s eries has 64 / 32 / 16 k bytes on - chip embedded flash for application program memory (aprom) that can be updated through isp procedure. the i n - system - programming (isp) function enables user to update program memory when chip is soldered on pcb. after chip is power ed on, cortex ? - m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. t he numicro ? nuc 029 s eries also provides addit ional data flash for user to store some application dependent data before chip power off . t he nuc029xan provide s additional 4 kbytes data flash , and nuc029fae provides data flash that is shared with aprom and its start address is configurable and defined by user in c onfig 1 . features 5.5.2 ? run s up to 50 mhz with zero wait cycle for continuous address read access ? 64 / 32 / 16 kb application program memory (aprom) ? up to 4 kb i n - s ystem - p rogramming (isp) loader program memory (ldrom) ? fixed 4kb data flash for nuc029xan ? configurable data flash size and programmable data flash start address for nuc029fae ? all embedded flash memory supports 512 bytes page erase ? support s in - application - programming (iap) to switch code between aprom and ldrom without reset ? in - system - program min g (isp) to update on - chip flash
nuc029 may 1 8, 201 5 page 51 of 99 rev 1 . 02 nuc029 series datasheet external bus interface ( ebi ) (NUC029LAN only) 5.6 overview 5.6.1 the numicro ? nuc 029lan has an external bus interface (ebi) to access external device. to save the connections between external device and this chip, ebi support address bus and data bus multiplex mode. also, address latch enable (ale) signal is used to differentiate the address and data cycle. features 5.6.2 ? s upports external devices with maximum 64 kb size (8 - bit data width) / 128 kb (16 - bit data width) ? supports variab le external bus base clock (mclk) which based on hclk ? s upports 8 - bit or 16 - bit data width ? s upports v ariable data access time (tacc), address latch enable time (tale) and address hold time (tahd) ? s upports a ddress bus and data bus multiplex mode to save the address pins ? s upports c onfigurable idle cycle for different access condition: write command finish (w2x), read - to - read (r2r) ? supports zero address hold time with read/write operation and write buffer for write operation to enhance read/write performance
nuc029 may 1 8, 201 5 page 52 of 99 rev 1 . 02 nuc029 series datasheet general purpose i/o (gpio) 5.7 overview 5.7.1 the numicro ? nuc 029 series has up to 40 general purpose i/o pins to be shared with other function pins depend ing on the chip configuration. these 40 pins are arranged in 6 ports named as p0 , p1 , p2 , p3, p4 and p5 . each p ort has the maximum of 8 pins. each o f the 40 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configur ed by software individually as i nput, push - pull output , o pen - drain output or q uasi - bidirectional mode. each i/o pin has a very weak individual pull - up resistor which is about 110~300 k ? for v dd is from 5.0 v to 2.5 v. features 5.7.2 ? four i/o modes: - quasi - bidirection al - push - pull output - open - drain output - input only with high impendence ? ttl/schmitt trigger input selectable by px_type[15:0] in px_mfp[23:16] ? i/o pin configured as interrupt source with edge/level setting ? configurable default i/o mode of all pins after reset by cioini( c onfig [10] ) setting - for nuc029xan : ? if cioini is 0, all gpio pins in input tri - state mode after chip reset ? if cioini is 1, all gpio pins in quasi - bidirectional mode after chip reset (default) after reset, the i/o mode of all pins are stay i n quasi - bidirectional mode and each port data register px_dout[7:0] resets to 0x000_00ff. - for nuc029fae : ? if cioini is 0, all gpio pins in quasi - bidirectional mode after chip reset ? if cioini is 1, all gpio pins in input tri - state mode after chip reset (default) ? i/o pin internal pull - up resistor enabled only in quasi - bidirectional i/o mode ? enabling the pin interrupt function will also enable the pin wake - up function .
nuc029 may 1 8, 201 5 page 53 of 99 rev 1 . 02 nuc029 series datasheet timer controller (t i m e r) 5.8 overview 5.8.1 the timer controller includes up to 4 sets 32 - bit timers, timer0 ~ timer3, allow ing user to easily implement a timer control for applications. the timer can perform functions , such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins . featu res 5.8.2 ? up to 4 sets of 32 - bit timers with 24 - bit up counter and one 8 - bit prescale counter ? independent clock source for each timer ? provides four timer counting modes: one - shot, periodic, toggle and continuous counting ? time - out period = (period of timer clock input) * (8 - bit prescale counter + 1) * (24 - bit tcmp) ? maximum counting cycle time = (1 / t mhz) * (2 8 ) * (2 24 ), t is the period of timer clock ? 24 - bit up count er value is readable through tdr (timer data register) ? support s event counting function to count t he event from external counter pin (t0~t3) ? 24 - bit capture value is readable through t cap (timer capture data register) ? support s external pin capture (t0ex~t3ex) for interval measurement ? support s external pin capture (t0ex~t3ex) for reset 24 - bit up counter ? supports chip wake - up from idle/power - down mode if a timer interrupt signal is generated ? supports internal capture triggered while internal acmp output signal transition (nuc029xan only) ? supports inter - timer trigger mode (nuc029xan only) ? suppor ts internal signal (cpo0, cpo1 ) for interval measurement (nuc029fae only)
nuc029 may 1 8, 201 5 page 54 of 99 rev 1 . 02 nuc029 series datasheet pwm generator and capture timer (pwm) (nuc029xan only) 5.9 overview 5.9.1 the numicro ? nuc 029xan has 2 sets of pwm group support ing a total of 4 sets of pwm g enerators that can be configured as 8 independent pwm outputs, pwm0~pwm7, or as 4 complementary pwm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) with 4 programmable d ead - zone generators. each pwm g enerator has one 8 - bit prescaler, one clock divider w ith 5 divided frequencies (1, 1/2, 1/4, 1/8, 1/16), two pwm timers including two clock selectors, two 16 - bit pwm counters for pwm period control, two 16 - bit comparators for pwm duty control and one d ead - zone generator. the 4 sets of pwm g enerators provide 8 independent pwm interrupt flags set by hardware when the corresponding pwm period down counter reaches 0 . each pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform continuously. when dzen01 ( pcr [4]) is set, pwm0 and pwm1 perform complementary pwm paired function; the paired pwm period, duty and d ead - time are determined by pwm0 timer and dead - zone generator 0. similarly, the complementary pwm pairs of (pwm2, pwm3), (pwm4, pwm5) and (pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 timers and dead - zone generator 2, 4 and 6, respectively. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers , the updated value will be load into the 16 - bit down counter/ comparator at the time down count er reaching 0 . the double buffering feature avoids glitch at pwm outputs. when the 16 - bit period down counter reaches 0 , the interrupt request is generated. if pwm - timer is set as auto - reload mode, when the down counter reaches 0 , it is reloaded with pwm c ounter register (cnrx) automatically then start s decreasing, repeatedly. if the pwm - timer is set as one - shot mode, the down counter will stop and generate one interrupt request when it reaches 0 . the value of pwm counter comparator is used for pulse high w idth modulation. the counter control logic changes the output to high level when down - counter value matches the value of compare register. the alternate feature of the pwm - timer is digital input capture function. if capture function is enabled the pwm outp ut pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the capture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm - timer before enable capture feature. after capture feature is e nabled, the capture always latched pwm - counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm - counter to capture falling latch register (cflr) when input channel has a falling transition. capture channel 0 interrupt is programmable by setting crl_ie0 ( ccr0[1] ) (rising latch interrupt enable) and cfl_ie0 ( ccr0[2] ) (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting crl_ie1 ( ccr0[17] ) and cfl_ie1 ( ccr0[18] ) . and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each group, whenever capture issues interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this mom ent. the maximum captured frequency that pwm can capture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at least three steps, including : read piir to get interrupt source and read crlrx/cflrx(x=0~3) to get c apture value and finally write 1 to clear piir to 0 . if interrupt latency will take time t0 to finish, the capture signal mustnt transition during this interval (t0). in this case, the maximum capture frequency will be 1/t0.
nuc029 may 1 8, 201 5 page 55 of 99 rev 1 . 02 nuc029 series datasheet features 5.9.2 5.9.2.1 pwm f unction: ? up to 2 pwm group s (pwma/pwmb) to support 8 pwm channels or 4 complementary pwm paired channels ? each pwm group has two pwm generators with e ach pwm generator support ing one 8 - bit prescaler, one clock divider, two pwm - timers, one d ead - zone generator and two pwm ou tputs. ? up to 16 - bit resolution ? one - shot or auto - reload mode ? edge - aligned type or c enter - aligned type option ? pwm trigger adc start - to - conversion 5.9.2.2 capture function: ? timing control logic shared with pwm generators ? support s 8 capture input channels shared with 8 pwm output channels ? each channel supports one rising latch register (crlr x ), one falling latch register (cflr x ) and capture interrupt flag (capifx)
nuc029 may 1 8, 201 5 page 56 of 99 rev 1 . 02 nuc029 series datasheet enhanced pwm generator ( nuc029fae only ) 5.10 overview 5.10.1 the numicro ? nuc 029fae has built one pwm unit which is specially designed for motor driving control applications. the pwm unit supports six pwm generators which can be configured as three independent pwm outputs, pwm 2, pwm3 and pwm5, or as three complementary pwm pairs, ( pwm0, pwm1), (pwm2, pwm3) and (pwm4, pwm5) with three programmable dead - zone generators. every complementary pwm pairs share one 8 - bit prescaler. there are six clock dividers providing five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. eac h pwm output has independent 16 - bit counter for pwm period control, and 16 - bit comparators for pwm duty control. the six pwm generators provide twelve independent pwm interrupt flags which are set by hardware when the corresponding pwm period counter compa rison matched period and duty. each pwm interrupt source with its corresponding enable bit can request pwm interrupt. the pwm generators can be configured as one - shot mode to produce only one pwm cycle signal or auto - reload mode to output pwm waveform cont inuously. to prevent pwm driving output pin with unsteady waveform, the 16 - bit period down counter and 16 - bit comparator are implemented with double buffer. when user writes data to counter/comparator buffer registers, the updated value will be loaded into the 16 - bit down counter/ comparator at the end of current period. the double buffering feature avoids glitch at pwm outputs. besides pwm, motor controlling also need timer, acmp and adc to work together. in order to control motor more precisely, we provid e some registers that not only configure pwm but also timer, adc and acmp, by doing so, it can save more cpu time and control motor with ease especially in bldc . features 5.10.2 the pwm unit supports the following features: ? independ ent 1 6 - bit pwm duty control uni ts with maximum six port pins: - three independent pwm outputs C pwm2, pwm3 and pwm5 - three complementary pwm pairs, with each pin in a pair mutually complement to each other and capable of programmable dead - zone insertion C (pwm0, pwm1), (pwm2, pwm3) and (pwm 4, pwm5) ? group control bit C pwm2 and pwm4 are synchronized with pwm0, pwm3 and pwm5 are synchronized with pwm1 ? one - shot (only support edge alignment mode) or auto - reload mode pwm ? up to 16 - bit resolutio n ? support s edge - aligned and center - aligned mode ? programmable dead - zone insertion between complementary paired p wms ? each pin of pwm0 to pwm5 has independent polarity setting control ? hardware fault brake protection s
nuc029 may 1 8, 201 5 page 57 of 99 rev 1 . 02 nuc029 series datasheet - two interrupt source types: ? s ynchronously requested at pwm frequency when down counter com parison matched (edge - and center - aligned mode) or underflow (edge - aligned mode) ? r equested when external fault brake asserted ? bkp0: e int0 or cpo1 ? the pwm signals before polarity control stage are defined in the view of positive logic. the pwm ports is acti ve high or active low are controlled by polarity control register ? support s independently rising cmr matching (in c enter - aligned mode), cnr matching (in c enter - aligned mode), falling cmr matching, period matching to trigger adc conversion ? t imer comparing m atching event trigger pwm to do phase change in bldc application ? support s acmp output event trigger pwm to force pwm output at most one period low, this feature is usually for step motor control ? p rovide s interrupt accumulation function
nuc029 may 1 8, 201 5 page 58 of 99 rev 1 . 02 nuc029 series datasheet watchdog timer (wdt) 5.11 overview 5.11.1 the purpose of watchdog timer is to perform a system reset when system runs into an unknown state. this prevents system from hanging for an infinite period of time. besides, this watchdog timer supports the function to wake - up system from idle/power - down mode. features 5.11.2 ? 18 - bit free running up counter for watchdog t imer time - out interval . ? selectable time - out interval (2 4 ~ 2 18 ) wdt_clk cycle and the time - out interval period is 104 ms ~ 26.3168 s if wdt_clk = 10 khz. ? system kept in reset stat e for a period of (1 / wdt_clk) * 63 ? supports watchdog t imer reset delay period (nuc029xan only) - s electable it includes (1026 130 18 or 3) * wdt_clk reset delay period ? supports to force watchdog t imer enabled after chip powered on or reset while cwdten (c onfig 0[31] w atchdog e nable) bit is set to 0 (nuc029xan only) ? supports watchdog timer time - out wake - up function only if wdt clock source is selected as 10 khz
nuc029 may 1 8, 201 5 page 59 of 99 rev 1 . 02 nuc029 series datasheet window watchdog timer (wwdt) (nuc029xan only) 5.12 overview 5.12.1 the numicro ? nuc 029xan supports the window watchdog timer (wwdt). wwdt is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. features 5.12.2 ? 6 - bit dow n counter value wwdtcval (wwdtval[5:0]) and 6 - bit compare window value wincmp (wwdtcr[21:16]) to make the wwdt time - out window period flexible ? s upports 4 - bit value to programmable maximum 11 - bit prescale counter period of wwdt counter
nuc029 may 1 8, 201 5 page 60 of 99 rev 1 . 02 nuc029 series datasheet uart interface controller (uart) 5.13 overview 5.13.1 the numicro ? nuc 029 series provides up to 2 channels of universal asynchronous receiver/transmitters (uart). uart controller perform s normal speed uart , and support s flow control function. the uart controller performs a serial - to - parallel conversion on data received from the peripheral, and a parallel - to - serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function and rs - 485 function mode. the nuc 0 29xan also supports lin master/slave function mode. each uart controller channel supports six types of interrupts . nuc029xan has seventh interrupt, lin receiver break field detected interrupt (lin_rx_break_int) . features 5.13.2 ? full duplex, asynchronous communic ations ? separate s receive / transmit 16/16 bytes entry fifo for data payloads ? support s hardware auto flow control/flow control function (cts, rts) and programmable rts flow control trigger level ? programmable receiver buffer trigger level ? support s programmab le baud - rate generator for each channel individually ? support s cts wake - up function ? support s 8 - bit receiver buffer time - out detection function ? programmable transmitting data delay time between the last stop and the next start bit by setting dly ( ua_tor [ 15: 8 ] ) register ? support s break error, frame error, parity error and receive / transmit buffer overflow detect function ? fully programmable serial - interface characteristics - progra mmable data bit length , 5 - , 6 - , 7 - , 8 - bit character - progra mmable parity bit, even, odd, no parity or stick parity bit generation and detection - programmable stop bit length , 1, 1.5, or 2 stop bit generation ? supports irda sir function mode - support s 3 - /16 - bit duration for normal mode ? supports rs - 485 function mode. - suppo rt s rs - 485 9 - bit mo de - supports hardware or software enable to control rs - 485 transmission direct ion by programming rts pin ? supports lin function mode (nuc029xan only) - support s lin master/slave mode - suppo rt s programmable break generation function for transmitter - suppo rt s break detect function for receiver
nuc029 may 1 8, 201 5 page 61 of 99 rev 1 . 02 nuc029 series datasheet i 2 c serial interface controller (i 2 c) 5.14 overview 5.14.1 i 2 c is a two - wire, bi - directional serial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi - master bus includ ing collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. features 5.14.2 the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the i 2 c bus include: ? supports up to two i 2 c serial interface controller ? master/slave mode ? bidirectional data transfer between masters and slaves ? multi - master bus (no central master) ? arbitration between simultaneously transmitting masters without corruption of serial data on the bus ? serial clock synchronization allow devices with different bit rates to communicate via one serial bus ? serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer ? built - in a 14 - bit time - out counter requesting the i 2 c interrupt if the i 2 c bus hangs up and timer - out counter overflows. ? programmable clocks allow for versatile rate control ? supports 7 - bit addressing mode ? supports multiple address recognition ( four slave address wit h mask option) ? supports power - down wake - up function ? support fifo function (nuc029fae only)
nuc029 may 1 8, 201 5 page 62 of 99 rev 1 . 02 nuc029 series datasheet serial peripheral interface (spi) 5.15 overview 5.15.1 the serial peripheral interface (spi) is a synchronous serial data communication protocol that operates in full duplex mode. devices communicate in m aster/ slave mode with the 4 - wire bi - direction interface. the numicro ? nuc 029 series contains up to 2 sets of spi controller s performing a serial - to - parallel conversion on data received from a peripheral device, and a parallel - to - serial conversion on data transmitted to a peripheral device. each set of spi controller can be configured as a master or a slave device . features 5.15.2 ? up to 2 sets of spi controller s ? support s m aster or slave mode operation ? configurable bit length of a transaction word from 8 to 32 bit s ? provide s separate 4 - layer depth transmit and receive fifo buffers ? support s msb first or lsb first transfer sequence ? support s the b yte r eorder function ? support s b yte or w ord s uspend mode ? support s slave 3 - wire mode ? supports pll clock source (nuc029xan only)
nuc029 may 1 8, 201 5 page 63 of 99 rev 1 . 02 nuc029 series datasheet analog - to - digital converter (adc) 5.16 overview 5.16.1 the numicro ? nuc 029xan contains one 12 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels , and the numicro ? nuc 029fae contains one 1 0 - bit successive approximation analog - to - digital converters (sar a/d converter) with 8 input channels. the a/d converter of nuc 029xan supports four operation modes: s ingle, burst, s ingle - cycle s can and c ontinuous s can mode , and t he a/d converter of nuc 029xan only supports single mode . the a/d converter can be started by software, pwm trigger and external stadc pin . features 5.16.2 ? a nalog input voltage range: 0~ av dd ? 12 - bit resolution and 10 - bit accuracy is guaranteed (nuc029xan only) ? 10 - bit resolution and 8 - bit accuracy is guaranteed (nuc029fae only) ? up to 8 s ingle - end analog input channels - o r 4 differential analog input channels (nuc029xan only) ? up to 760 k sps sample rate for nuc029xan ? 300 ksps (v dd 4.5v - 5.5v) and 200 ksps (v dd 2.5v - 5.5v) conversion rate for nuc029fae ? four operating modes ( nuc029fae only supports single mode ) - single mode: a/d conversion is performed one time on a specified channel - burst mode: a/d converter samples and converts the specified single channel and sequentially stores the result in fifo. - single - cycle s can mode: a/d conversion is performed one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel - continuous s can mode: a/d converter continuously performs single - cy cle scan mode until software stops a/d conversion ? an a/d conversion can be started by: - writing 1 to adst bit (adcr[11]) through software - pwm trigger with optional start delay period - external pin stadc ? each c onversion result is held in data register with va lid and overrun indicators ? each channel has individual data regiter (nuc029xan only) ? the c onversion result can be compared with specify value and user can select whether to generate an interrupt when conversion result matches the compare register setting ? c hannel 7 supports 3 input sources: - external analog voltage - internal band - gap voltage
nuc029 may 1 8, 201 5 page 64 of 99 rev 1 . 02 nuc029 series datasheet - internal temperature sensor output (nuc029xan only)
nuc029 may 1 8, 201 5 page 65 of 99 rev 1 . 02 nuc029 series datasheet analog comparator ( a cmp) 5.17 overview 5.17.1 the numicro ? nuc 029 s eries contains up to four sets of comparators which can be used in a number of different configurations. the comparator output is logic 1 when positive input voltage is greater than negative input voltage ; otherwise the output is logic 0 . each comparator can be configured to generate interrupt request when the comparator output value changes. features 5.17.2 ? up to four sets of comparator analog modules ? analog input voltage range: 0~ v dd ? supports hysteresis function ? o ptional internal reference voltage source for each comparator negative input ? two interrupt vectors for the four analog comparators ? external input or i nternal band - gap voltage selectable at negative node ? interrupt when compared results change ? power - down wake - up
nuc029 may 1 8, 201 5 page 66 of 99 rev 1 . 02 nuc029 series datasheet hard w are divider (hdiv) (nuc029xan only) 5.18 overview 5.18.1 the numicro ? nuc 029xan has t he hardware divider (hdiv) . hdiv is useful to the high performance application. the hardware divider is a signed, integer divider with both quotient and remainder outputs. features 5.18.2 ? signed (twos complement) integer calculation ? 32 - bit dividend with 16 - bit divisor calculation capacity ? 32 - bit quotient and 32 - bit remainder outputs (16 - bit remainder with sign extends to 32 - bit) ? divided by zero warning flag ? 6 hclk clocks taken for one cycle calculation ? write divisor to trigger calculation ? waiting for calculation ready a utomatically when reading quotient and remainder
nuc029 may 1 8, 201 5 page 67 of 99 rev 1 . 02 nuc029 series datasheet 6 application circuit a v s s a v d d a v c c d v c c v s s v d d 4 ~ 2 4 m h z c r y s t a l 0 . 1 u f f b f b 2 0 p 2 0 p d v c c 1 0 u f / 2 5 v 1 0 k p o w e r c r y s t a l r e s e t c i r c u i t n r s t x t a l 2 l d o _ c a p n u c 0 2 9 l a n l q f p 4 8 v d d v s s n r s t i c e _ c l k i c e _ d a t s w d i n t e r f a c e 1 u f v d d v s s i 2 c d e v i c e c l k d i o s d a 0 s c l 0 4 . 7 k v d d v s s s p i d e v i c e c s c l k m i s o s p i s s 0 m o s i s p i c l k 0 m i s o _ 0 m o s i _ 0 l d o r s 2 3 2 t r a n s c e i v e r r o u t t i n r i n t o u t p c c o m p o r t a d d r [ 1 5 : 0 ] n c e n o e d a t a [ 1 5 : 0 ] n w e 6 4 k x 1 6 - b i t s r a m l a t c h e n d q n l b n u b e b i x t a l 1 0 . 1 u f d v c c 4 . 7 k d v c c d v c c n o t e : f o r t h e s p i d e v i c e , t h e n u c 0 2 9 x a n c h i p s u p p l y v o l t a g e m u s t b e e q u a l t o s p i d e v i c e w o r k i n g v o l t a g e . f o r e x a m p l e , w h e n t h e s p i f l a s h w o r k i n g v o l t a g e i s 3 . 3 v , t h e n u c 0 2 9 x a n c h i p s u p p l y v o l t a g e m u s t a l s o b e 3 . 3 v . u a r t a l e n c s n r d n w r n w r l n w r h [ 1 ] a d [ 1 5 : 0 ] r x d t x d
nuc029 may 1 8, 201 5 page 68 of 99 rev 1 . 02 nuc029 series datasheet 7 nuc029xan electrical characteristics absolute maximum ratings 7.1 symbol parameter min. max unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 + 85 ? c storage temperature t st - 55 +150 ? c maximum current into v dd i dd - 120 ma maximum current out of v ss i ss - 120 ma maximum current sunk by a i/o pin i io - 35 ma maximum current sourced by a i/o pin - 35 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
nuc029 may 1 8, 201 5 page 69 of 99 rev 1 . 02 nuc029 series datasheet dc electrical characteristics 7.2 (v dd - v ss = 5.5 v, t a = 25 ? c) parameter sym. specification test conditions min. typ. max. unit operation v oltage v dd 2.5 - 5.5 v v dd = 2.5v ~ 5.5v up to 50 mhz power ground v ss av ss - 0.3 - - v - ldo output voltage v ldo 1.62 1.8 1.98 v v dd > 2. 5 v band - gap voltage v bg 1.16 1.20 1.24 v v dd = 2 .5 v ~ 5.5 v , t a = 25 ? dd = 2 .5 v ~ 5.5 v , t a = - 40 ? ? dd and av dd v dd - av dd - 0.3 0 0.3 v - operating current normal run mode hclk = 50 mhz while(1){} excuted from flash i dd1 - 21 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x v v i dd2 - 15 - ma 5.5v 12 mhz x v x i dd3 - 20 - ma 3.3v 12 mhz x v v i dd4 - 13 - ma 3.3v 12 mhz x v x operating current normal run mode hclk = 22.184 mhz while(1){} excuted from flash i dd 5 - 6.6 - ma v dd hxt hirc pll all digital modules 5.5v x v x v i dd 6 - 3.7 - ma 5.5v x v x x i dd 7 - 6.4 - ma 3.3v x v x v i dd 8 - 3.6 - ma 3.3v x v x x operating current normal run mode hclk = 12 mhz while(1){} excuted from flash i dd 9 - 5.4 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x x v i dd 10 - 3.6 - ma 5.5v 12 mhz x x x i dd 11 - 4.0 - ma 3.3v 12 mhz x x v i dd 12 - 2.3 - ma 3.3v 12 mhz x x x operating current normal run mode hclk = 4 mhz while(1){} excuted from flash i dd 13 - 3.3 - ma v dd hxt hirc pll all digital modules 5.5v 4 mhz x x v i dd 14 - 2.5 - ma 5.5v 4 mhz x x x i dd1 5 - 2.0 - ma 3.3v 4 mhz x x v i dd1 6 - 1.3 - ma 3.3v 4 mhz x x x
nuc029 may 1 8, 201 5 page 70 of 99 rev 1 . 02 nuc029 series datasheet parameter sym. specification test conditions min. typ. max. unit operating current normal run mode hclk = 10 khz while(1){} excuted from flash i dd17 - 110 - ? a v dd hxt hirc lirc pll all digital modules 5.5v x x v x v [4] i dd18 - 105 - ? a 5.5v x x v x x i dd19 - 92 - ? a 3.3v x x v x v [4] i dd20 - 90 - ? a 3.3v x x v x x operating current idle mode hclk = 50 mhz i idle1 - 17 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x v v i idle2 - 10 - ma 5.5v 12 mhz x v x i idle3 - 15 - ma 3.3v 12 mhz x v v i idle4 - 8 - ma 3.3v 12 mhz x v x operating current idle mode hclk= 22.1184 mhz i idle 5 - 4.5 - ma v dd hxt hirc pll all digital modules 5.5v x v x v i idle 6 - 1.6 - ma 5.5v x v x x i idle 7 - 4.4 - ma 3.3v x v x v i idle 8 - 1.6 - ma 3.3v x v x x operating current idle mode hclk = 12 mhz i idle 9 - 4.1 - ma v dd hxt hirc pll all digital modules 5.5v 12 mhz x x v i idle 10 - 2.4 - ma 5.5v 12 mhz x x x i idle 11 - 2.8 - ma 3.3v 12 mhz x x v i idle 12 - 1.2 - ma 3.3v 12 mhz x x x operating current idle mode hclk = 4 mhz i idle 13 - 2.9 - ma v dd hxt hirc pll all digital modules 5.5v 4 mhz x x v i idle1 4 - 2.1 - ma 5.5v 4 mhz x x x i idle1 5 - 1.6 - ma 3.3v 4 mhz x x v i idle1 6 - 0.9 - ma 3.3v 4 mhz x x x operating current idle mode hclk = 10 k hz i idle 17 - 106 - ? a v dd hxt hirc lirc pll all digital modules 5.5v x x v x v [4] i idle1 8 - 104 - ? a 5.5v x x v x x i idle1 9 - 90 - ? a 3.3v x x v x v [4] i idle 20 - 89 - ? a 3.3v x x v x x standby current i pwd1 - 10 - ? a v dd = 5.5v, all oscillators and analog blocks turned off
nuc029 may 1 8, 201 5 page 71 of 99 rev 1 . 02 nuc029 series datasheet parameter sym. specification test conditions min. typ. max. unit power - down mode (deep sleep mode) i pwd 2 - 8 - ? a v dd = 3. 3 v, all oscillators and analog blocks turned off logic 0 input current p 0/1/2/3/4 (quasi - bidirectional mode) i il - - 65 - 75 ? a v dd = 5.5v, v in = 0v logic 1 to 0 transition current p 0/1/2/3/4 (quasi - bidirectional mode) i tl [3] - - 690 - 750 ? a v dd = 5.5v, v in = 2.0v input leakage current p 0/1/2/3/4 i lk - 1 - + 1 ? a v dd = 5.5v, 0 nuc029 may 1 8, 201 5 page 72 of 99 rev 1 . 02 nuc029 series datasheet parameter sym. specification test conditions min. typ. max. unit i sk1 3 5 8 - ma v dd = 2.5v, v s = 0.45v note 1 : nrst pin is a schmitt trigger input. note 2 : xtal1 is a cmos input. note 3 : pins of p 0 , p 1 , p 2 , p 3 and p 4 can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd = 5.5 v, t he transition current reaches its maximum value when v in approximates to 2 v. note 4 : only enable modules which support 10 khz lirc clock source.
nuc029 may 1 8, 201 5 page 73 of 99 rev 1 . 02 nuc029 series datasheet ac electrical characteristics 7.3 external input clock 7.3.1 note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time - 1 0 - - n s t clcx clock low time - 1 0 - - n s t clch clock rise time - 2 - 1 5 ns t chcl clock fall time - 2 - 1 5 n s external 4~24 mhz high speed crystal (hxt) 7.3.2 symbol parameter condition min. typ. max. unit v hxt operation voltage v dd - 2. 5 - 5.5 v t a temperature - - 40 - 85 i hxt operating c urrent 12 mhz at v dd = 5v - 2 - ma 12 mhz at v dd = 3.3v - 0.8 - ma f hxt c lock f requency - 4 - 24 mhz 7.3.2.1 typical crystal application circuits crystal c1 c2 4 mhz ~ 24 mhz 10~20pf 10~20pf t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d
nuc029 may 1 8, 201 5 page 74 of 99 rev 1 . 02 nuc029 series datasheet figure 7 - 1 nuc029xan typical crystal application circuit internal 22.1184 mhz high speed rc oscillator (hirc) 7.3.3 symbol parameter condition min. typ. max. unit v hrc [1] operation voltage v dd - 1.62 1.8 1.98 v f hrc center frequency - - 22.1184 - mhz calibrated internal oscillator frequency t a = 25 , v dd = 5 v - 1 - +1 % t a = - 40 ~ 85 , v dd = 2.5 v ~ 5.5 v - 3 - +3 % i hrc operation current t a = 25 , v dd = 5 v - 800 - ua note: o peration voltage comes from internal ldo. internal 10 khz low speed rc oscillator (lirc) 7.3.4 symbol parameter condition min. typ. max. unit v lrc operation voltage v dd - 2.5 - 5.5 v f lrc center frequency - - 10 - k hz calibrated internal oscillator frequency t a = 25 , v dd = 2.5 v ~ 5.5 v - 10 - +10 % t a = - 40 ~ 85 , v dd = 2.5 v ~ 5.5 v - 40 - +40 % x t a l 1 c 1 c 2 x t a l 2 4 ~ 2 4 m h z c r y s t a l v s s v s s
nuc029 may 1 8, 201 5 page 75 of 99 rev 1 . 02 nuc029 series datasheet analog characteristics 7.4 12 - bit sar adc specification 7.4.1 symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error - 1 - 1~4 lsb inl integral nonlinearity error - 2 4 lsb e o offset error - 2 4 lsb e g gain error (transfer gain) - - 2 - 4 lsb e a absolute error - 3 4 lsb - monotonic guaranteed f adc adc clock frequency (av dd = 4.5v ~ 5.5v) - - 16 mhz adc clock frequency (av dd = 2.5v ~ 5.5v) - - 8 mhz f s sample rate ( f adc /t conv ) (av dd = 4.5v ~ 5.5v) - - 800 k sps sample rate ( f adc /t conv ) (av dd = 2.5v ~ 5.5v) - - 400 k sps t acq acquisition time (sample stage) 7 1/ f adc t conv total conversion time 20 1/ f adc av dd supply voltage 2.5 - 5.5 v i dda supply current (avg.) ( av dd = 5v ) - 2.9 - ma v in analog input voltage 0 - av dd v c in input capacitance - 3.2 - pf r in input load - 6 - k
nuc029 may 1 8, 201 5 page 76 of 99 rev 1 . 02 nuc029 series datasheet note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. ldo and power management specification 7.4.2 symbol parameter condition min. typ. max. unit v dd input voltage v dd - 2. 5 5.5 v v ldo output voltage - 1.62 1.8 1.98 v t a operating temperature - - 40 25 85 c ldo capacitor r esr = 1 ? - 1 - ? f note 1: it is recommended that a 0.1 uf bypass capacitor is connected between v dd and the closest v ss pin of the device. note 2: to ensure power stability, a 1 ? f or higher capacitor must be connected between ldo_cap pin and the closest v ss pin of the device. 1 2 3 4 5 6 4 0 9 5 4 0 9 4 7 4 0 9 3 4 0 9 2 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 4 0 9 5 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b
nuc029 may 1 8, 201 5 page 77 of 99 rev 1 . 02 nuc029 series datasheet low voltage reset specification 7.4.3 symbol parameter condition min. typ. max. unit av dd input voltage av dd - 0 - 5.5 v t a operating temperature - - 40 25 85 i lvr capacitor av dd = 5.5 v - 1 5 ? f v lvr threshold voltage t a = 25 1.90 2.00 2.20 v t a = - 40 2.00 2.10 2.40 v t a = 85 1.70 1.90 2.10 v brown - out detector specification 7.4.4 symbol parameter condition min. typ. max. unit av dd input voltage av dd - 0 - 5.5 v t a operating temperature - - 40 25 85 i bod quiescent current av dd = 5.5 v - - 1 40 a v bod brown - out v oltage (falling edge) bod_vl [1:0]=11 4. 2 4. 38 4. 55 v bod_vl [1:0]=10 3. 5 3. 68 3. 85 v bod_vl [1:0]=01 2. 5 2. 68 2.8 5 v bod_vl [1:0]=00 2. 0 2. 18 2. 35 v v bod brown - out v oltage (rising edge) bod_vl [1:0]=11 4. 3 4. 52 4. 75 v bod_vl [1:0]=10 3. 5 3. 8 4 . 05 v bod_vl [1:0]=01 2. 5 2. 77 3 . 05 v bod_vl [1:0]=00 2. 0 2. 25 2. 55 v power - on reset specification 7.4.5 symbol parameter condition min. typ. max. unit t a operating temperature - - 40 25 85 v por reset v oltage v+ - 2 - v v por v dd start voltage to ensure power - on reset - - - 100 mv rr vdd v dd raising rate to ensure power - on reset - 0.025 - - v/ms t por minimum time for v dd stays at v por to ensure power - on reset - 0.5 - - ms
nuc029 may 1 8, 201 5 page 78 of 99 rev 1 . 02 nuc029 series datasheet figure 7 - 2 nuc029xan power - up ramp condition t p o r r r v d d v p o r v d d t i m e
nuc029 may 1 8, 201 5 page 79 of 99 rev 1 . 02 nuc029 series datasheet temperature sensor specification 7.4.6 symbol parameter condition min. typ. max. unit v temp [1] operating voltage - 1.62 1.8 1.98 v t a operating temperature - - 40 25 85 i temp current c onsumption - - 16 - a - gain - - 1.65 - 1.75 - 1.85 mv/ - offset voltage t a = 0 714 724 734 mv note 1 : o peration voltage comes from internal ldo. note 2 : the temperature sensor formula for the output voltage (vtemp) is as below equation. vtemp (mv) = gain (mv/ ) x temperature ( ) + offset (mv) comparator specification 7.4.7 symbol parameter condition min. typ. max. unit v cmp operation voltage a v dd - 2.5 - 5.5 v t a operation temperature - - 40 25 85 i cmp operation c urrent a v dd = 5 v - 50 100 a v off input o ffset v oltage - - 10 20 m v v sw output s wing - 0.1 - a v dd - 0.1 v v com input c ommon m ode r ange - 0.1 - a v dd - 0.1 v - dc g ain - 40 70 - db t pgd propagation d elay v com = 1.2 v, v diff = 0.1 v - 200 - ns v hys hysteresis - - 2 0 3 0 m v t stb stable t ime - - - 1 s
nuc029 may 1 8, 201 5 page 80 of 99 rev 1 . 02 nuc029 series datasheet flash dc electrical characteristics 7.5 symbol parameter condition min. typ. max. unit v fla [1] operation voltage - 1.62 1.8 1.98 v t ret data retention t a = 25 10 - - year t erase page erase time - - 3 - ms t prog program time - - 40 - s i dd1 read current - - 0.25 - v i dd2 program current - - 7 - ma i dd3 erase current - - 20 - ma note 1 : o peration voltage comes from internal ldo. note 2 : this table is guaranteed by design, not test in production.
nuc029 may 1 8, 201 5 page 81 of 99 rev 1 . 02 nuc029 series datasheet 8 nuc029fae electrical characteristics absolute maximum ratings 8.1 symbol parameter min. max unit dc power supply v dd ? v ss - 0.3 +7.0 v input voltage v in v ss - 0.3 v dd +0.3 v oscillator frequency 1/t clcl 4 24 mhz operating temperature t a - 40 + 105 ? c storage temperature t st - 55 +150 ? c maximum current into v dd i dd - 120 ma maximum current out of v ss i ss - 120 ma maximum current sunk by a i/o pin i io - 35 ma maximum current sourced by a i/o pin - 35 ma maximum current sunk by total i/o pins - 100 ma maximum current sourced by total i/o pins - 100 ma note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lif e and reliability of the device.
nuc029 may 1 8, 201 5 page 82 of 99 rev 1 . 02 nuc029 series datasheet dc electrical characteristics 8.2 (v dd - v ss = 5.5 v, t a = 25 ? c) parameter sym. specification test conditions min. typ. max. unit operation v oltage v dd 2.5 - 5.5 v v dd = 2.5v ~ 5.5v up to 24 mhz power ground v ss av ss - 0.3 - - v - ldo output voltage v ldo 1.62 1.8 1.98 v v dd bg 1.22 1.25 1.28 v v dd = 2 .5 v ~ 5.5 v , t a = 25 ? dd = 2 .5 v ~ 5.5 v , t a = - 40 ? ? dd and av dd v dd - av dd - 0.3 0 0.3 v - operating current normal run mode hclk = 24 mhz while(1){} excuted from flash i dd1 - 9.2 - ma v dd hxt hirc all digital modules 5.5v 24 mhz x v i dd2 - 7.0 - ma 5.5v 24 mhz x x i dd3 - 7.1 - ma 3.3v 24 mhz x v i dd4 - 5.0 - ma 3.3v 24 mhz x x operating current normal run mode hclk = 22.184 mhz while(1){} excuted from flash i dd 5 - 6.1 - ma v dd hxt hirc all digital modules 5.5v x v v i dd 6 - 3.9 - ma 5.5v x v x i dd 7 - 6.0 - ma 3.3v x v v i dd 8 - 3.9 - ma 3.3v x v x operating current normal run mode hclk = 12 mhz while(1){} excuted from flash i dd 9 - 5.5 - ma v dd hxt hirc all digital modules 5.5v 12 mhz x v i dd 10 - 4.3 - ma 5.5v 12 mhz x x i dd 11 - 3.9 - ma 3.3v 12 mhz x v i dd 12 - 2.8 - ma 3.3v 12 mhz x x operating current normal run mode hclk = 4 mhz while(1){} excuted from flash i dd 13 - 3.2 - ma v dd hxt hirc all digital modules 5.5v 4 mhz x v i dd 14 - 2.8 - ma 5.5v 4 mhz x x i dd1 5 - 1.8 - ma 3.3v 4 mhz x v i dd1 6 - 1.4 - ma 3.3v 4 mhz x x
nuc029 may 1 8, 201 5 page 83 of 99 rev 1 . 02 nuc029 series datasheet parameter sym. specification test conditions min. typ. max. unit operating current normal run mode hclk = 10 khz while(1){} excuted from flash i dd17 - 225 - ? a v dd hxt hirc lirc all digital modules 5.5v x x v v [4] i dd18 - 225 - ? a 5.5v x x v x i dd19 - 200 - ? a 3.3v x x v v [4] i dd20 - 200 - ? a 3.3v x x v x operating current idle mode hclk = 24 mhz i idle1 - 7.1 - ma v dd hxt hirc all digital modules 5.5v 24 mhz x v i idle2 - 4.9 - ma 5.5v 24mhz x x i idle3 - 5.1 - ma 3.3v 24 mhz x v i idle4 - 2.9 - ma 3.3v 24 mhz x x operating current idle mode hclk= 22.1184 mhz i idle 5 - 4.1 - ma v dd hxt hirc all digital modules 5.5v x v v i idle 6 - 2.0 - ma 5.5v x v x i idle 7 - 4.1 - ma 3.3v x v v i idle 8 - 1.9 - ma 3.3v x v x operating current idle mode hclk = 12 mhz i idle 9 - 4.4 - ma v dd hxt hirc all digital modules 5.5v 12 mhz x v i idle 10 - 3.3 - ma 5.5v 12 mhz x x i idle 11 - 2.9 - ma 3.3v 12 mhz x v i idle 12 - 1.8 - ma 3.3v 12 mhz x x operating current idle mode hclk = 4 mhz i idle 13 - 2.9 - ma v dd hxt hirc all digital modules 5.5v 4 mhz x v i idle1 4 - 2.5 - ma 5.5v 4 mhz x x i idle1 5 - 1.5 - ma 3.3v 4 mhz x v i idle1 6 - 1.1 - ma 3.3v 4 mhz x x operating current idle mode hclk = 10 k hz i idle 17 - 225 - ? a v dd hxt hirc lirc all digital modules 5.5v x x v v [4] i idle1 8 - 225 - ? a 5.5v x x v x i idle1 9 - 200 - ? a 3.3v x x v v [4] i idle 20 - 200 - ? a 3.3v x x v x standby current i pwd1 - 10 - ? a v dd = 5.5v, all oscillators and analog blocks turned off
nuc029 may 1 8, 201 5 page 84 of 99 rev 1 . 02 nuc029 series datasheet parameter sym. specification test conditions min. typ. max. unit power - down mode (deep sleep mode) i pwd 2 - 9 - ? a v dd = 3. 3 v, all oscillators and analog blocks turned off logic 0 input current p 0/1/2/3/4 (quasi - bidirectional mode) i il - - 70 - 75 ? a v dd = 5.5v, v in = 0v logic 1 to 0 transition current p 0/1/2/3/4 (quasi - bidirectional mode) i tl [3] - - 690 - 750 ? a v dd = 5.5v, v in = 2.0v input leakage current p 0/1/2/3/4 i lk - 1 - + 1 ? a v dd = 5.5v, 0 nuc029 may 1 8, 201 5 page 85 of 99 rev 1 . 02 nuc029 series datasheet note 3 : pins of p 0 , p 1 , p 2 , p 3 and p 4 can source a transition current when they are being externally driven from 1 to 0. in the condition of v dd = 5.5 v, t he transition current reaches its maximum value when v in approximates to 2 v. note 4 : only enable modules which support 10 khz lirc clock source.
nuc029 may 1 8, 201 5 page 86 of 99 rev 1 . 02 nuc029 series datasheet ac electrical characteristics 8.3 external input clock 8.3.1 note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time - 1 0 - - n s t clcx clock low time - 1 0 - - n s t clch clock rise time - 2 - 1 5 ns t chcl clock fall time - 2 - 1 5 n s external 4~24 mhz high speed crystal (hxt) 8.3.2 symbol parameter condition min. typ. max. unit v hxt operation voltage v dd - 2. 5 - 5.5 v t a temperature - - 40 - 105 i hxt operating c urrent 12 mhz at v dd = 5v - 2.5 - ma 12 mhz at v dd = 3.3v - 1.0 - ma f hxt c lock f requency - 4 - 24 mhz 8.3.2.1 typical crystal application circuits crystal c1 c2 4 mhz ~ 24 mhz 10~20pf 10~20pf t c h c x 9 0 % 1 0 % t c l c h t c h c l t c l c x t c l c l 0 . 3 v d d 0 . 7 v d d
nuc029 may 1 8, 201 5 page 87 of 99 rev 1 . 02 nuc029 series datasheet figure 8 - 1 nuc029fae typical crystal application circuit internal 22.1184 mhz high speed rc oscillator (hirc) 8.3.3 symbol parameter condition min. typ. max. unit v hrc [1] operation voltage v dd - 1.62 1.8 1.98 v f hrc center frequency - - 22.1184 - mhz calibrated internal oscillator frequency t a = 25 , v dd = 5 v - 1 - +1 % t a = - 40 ~ 105 , v dd = 2.5 v ~ 5.5 v - 3 - +3 % i hrc operation current t a = 25 , v dd = 5 v - 700 - ua note : o peration voltage comes from internal ldo. x t a l 1 c 1 c 2 x t a l 2 4 ~ 2 4 m h z c r y s t a l v s s v s s
nuc029 may 1 8, 201 5 page 88 of 99 rev 1 . 02 nuc029 series datasheet internal 10 khz low speed rc oscillator (lirc) 8.3.4 symbol parameter condition min. typ. max. unit v lrc operation voltage v dd - 2.5 - 5.5 v f lrc center frequency - - 10 - k hz calibrated internal oscillator frequency t a = 25 , v dd = 2.5 v ~ 5.5 v - 10 - +10 % t a = - 40 ~ 105 , v dd = 2.5 v ~ 5.5 v - 40 - +40 % -1.00 -0.80 -0.60 -0.40 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 -40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100 110 deviation percentage % ta hirc oscillator accuracy vs. temperature max min
nuc029 may 1 8, 201 5 page 89 of 99 rev 1 . 02 nuc029 series datasheet analog characteristics 8.4 10 - bit sar adc specification 8.4.1 symbol parameter min. typ. max. unit - resolution - - 1 0 bit dnl differential nonlinearity error - - 1~1.5 - 1~2.5 lsb inl integral nonlinearity error - 1 2 lsb e o offset error - 1 2 lsb e g gain error (transfer gain) - - 1 - 3 lsb e a absolute error - 3 4 lsb - monotonic guaranteed f adc adc clock frequency (av dd = 4.5v ~ 5.5v) - - 4.2 mhz adc clock frequency (av dd = 2.5v ~ 5.5v) - - 2.8 mhz f s sample rate ( f adc /t conv ) (av dd = 4.5v ~ 5.5v) - - 300 k sps sample rate ( f adc /t conv ) (av dd = 2.5v ~ 5.5v) - - 200 k sps t acq acquisition time (sample stage) n+1 [2] 1/ f adc t conv total conversion time n+14 [2] 1/ f adc av dd supply voltage 2.5 - 5.5 v i dda supply current (avg.) ( av dd = 5.5v ) - 600 - a v in analog input voltage 0 - av dd v c in input capacitance - 3.2 - pf r in input load - 6 - k note 1 : adc voltage reference is same with av dd . note 2 : n is sampling counter, n=0, 1, 2, 4, 8, 16, 32, 4, 128, 256, 1024 .
nuc029 may 1 8, 201 5 page 90 of 99 rev 1 . 02 nuc029 series datasheet note: the inl is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. a calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. ldo and power management specification 8.4.2 symbol parameter condition min. typ. max. unit v dd input voltage v dd - 2. 5 5.5 v v ldo output voltage - 1.62 1.8 1.98 v t a operating temperature - - 40 25 105 note: it is recommended that a 0.1 uf bypass capacitor is connected between v dd and the closest v ss pin of the device. 1 2 3 4 5 6 1 0 2 3 1 0 2 2 7 1 0 2 1 1 0 2 0 i d e a l t r a n s f e r c u r v e a c t u a l t r a n s f e r c u r v e o f f s e t e r r o r e o a n a l o g i n p u t v o l t a g e ( l s b ) 1 0 2 3 a d c o u t p u t c o d e o f f s e t e r r o r e o g a i n e r r o r e g e f ( f u l l s c a l e e r r o r ) = e o + e g d n l 1 l s b
nuc029 may 1 8, 201 5 page 91 of 99 rev 1 . 02 nuc029 series datasheet low voltage reset specification 8.4.3 symbol parameter condition min. typ. max. unit av dd input voltage av dd - 2.5 - 5.5 v t a operating temperature - - 40 25 105 i lvr capacitor av dd = 5.5 v - 1 5 ? f v lvr threshold voltage t a = 25 1.90 2.00 2.10 v t a = - 40 1.70 1.90 2.05 v t a = 105 2.00 2.20 2.45 v brown - out detector specification 8.4.4 symbol parameter condition min. typ. max. unit av dd input voltage av dd - 2. 5 - 5.5 v t a operating temperature - - 40 25 105 i bod quiescent current av dd = 5.5 v - - 1 40 a v bod brown - out v oltage (falling edge) bod_vl [1:0]=11 4. 2 4. 38 4. 55 v bod_vl [1:0]=10 3. 5 3. 68 3. 85 v bod_vl [1:0]=01 2. 5 2. 68 2.8 5 v bod_vl [1:0]=00 2. 0 2. 18 2. 35 v v bod brown - out v oltage (rising edge) bod_vl [1:0]=11 4. 3 4. 52 4. 75 v bod_vl [1:0]=10 3. 5 3. 8 4 . 05 v bod_vl [1:0]=01 2. 5 2. 77 3 . 05 v bod_vl [1:0]=00 2. 0 2. 25 2. 55 v power - on reset specification 8.4.5 symbol parameter condition min. typ. max. unit t a operating temperature - - 40 25 85 v por reset v oltage v+ 1.6 2 2.4 v v por v dd start voltage to ensure power - on reset - - - 100 mv rr vdd v dd raising rate to ensure power - on reset - 0.025 - - v/ms t por minimum time for v dd stays at v por to ensure power - on reset - 0.5 - - ms
nuc029 may 1 8, 201 5 page 92 of 99 rev 1 . 02 nuc029 series datasheet figure 8 - 2 nuc029xan power - up ramp condition t p o r r r v d d v p o r v d d t i m e
nuc029 may 1 8, 201 5 page 93 of 99 rev 1 . 02 nuc029 series datasheet comparator specification 8.4.6 symbol parameter condition min. typ. max. unit v cmp operation voltage a v dd - 2.5 - 5.5 v t a operation temperature - - 40 25 105 i cmp operation c urrent a v dd = 5 v - 40 80 a v off input o ffset v oltage - - 10 20 m v v sw output s wing - 0.1 - a v dd - 0.1 v v com input c ommon m ode r ange - 0.1 - a v dd - 0.1 v - dc g ain - 40 70 - db t pgd propagation d elay v com = 1.2 v, v diff = 0.1 v - 200 - ns v hys hysteresis v com = 1.2 v - 3 0 6 0 m v t stb stable t ime - - - 1 s
nuc029 may 1 8, 201 5 page 94 of 99 rev 1 . 02 nuc029 series datasheet flash dc electrical characteristics 8.5 symbol parameter condition min. typ. max. unit v fla [1] operation voltage - 1.62 1.8 1.98 v n endur endurance - 20,000 - - cycles [2] t ret data retention t a = 25 10 - - year t erase page erase time - - 3 - ms t prog program time - - 40 - s i dd1 read current - - 0.25 - v i dd2 program current - - 7 - ma i dd3 erase current - - 20 - ma note 1 : o peration voltage comes from internal ldo. note 2 : number of program/erase cycles. note 3 : this table is guaranteed by design, not test in production.
nuc029 may 1 8, 201 5 page 95 of 99 rev 1 . 02 nuc029 series datasheet 9 package dimensions 48 - pin lqfp ( 7 x 7 x1.4 mm footprint 2.0 mm) 9.1 1 12 48 h h ? controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13
nuc029 may 1 8, 201 5 page 96 of 99 rev 1 . 02 nuc029 series datasheet 33 - pin qf n ( 4 x 4 x 0.75 mm footprint 1 .0 mm) 9.2
nuc029 may 1 8, 201 5 page 97 of 99 rev 1 . 02 nuc029 series datasheet 20 - pin tssop ( 6.5 x 4.4 x1. 2 mm footprint 2.0 mm) 9.3
nuc029 may 1 8, 201 5 page 98 of 99 rev 1 . 02 nuc029 series datasheet 10 revision history date rev ision description 2014.05 . 19 1.00 1. preliminary version. 2014.08.26 1.01 1. modified figure 4 - 1 numicro ? nuc 029 series s election c ode . 2015.05.18 1.0 2 1. changed the order of chapter 5 functional description . 2. fixe d typos and obscure description . 3. added chapter 5.2.5 whole system memory mapping . 4. fixed the description about frequency divider output of nuc029xan series in chapter 5.3.4 . 5. added clock switching note in chapter 5.3 and 5.4 . 6. removed description about acmp output inverse function available on nuc029xan series. 7. modified nuc029x dn lvr and bod specification . 8. updated 33 - pin qfn (4x4) package dimension in chapter 9.2 .
nuc029 may 1 8, 201 5 page 99 of 99 rev 1 . 02 nuc029 series datasheet important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. such applications are deemed, insecure usage. insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. all insecure usage shall be made at customers risk, and in the event that third parties lay claims to nuvoton as a result of customers insecure usage, custome r shall indemnify the damages and liabilities thus incurred by nuvoton.

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