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ams datasheet page 1 [v1-02] 2016-feb-08 document feedback tcs3472 color light-to-digital converter with ir filter the tcs3472 device provides a digital return of red, green, blue (rgb), and clear light sensing values. an ir blocking filter, integrated on-chip and localized to the color sensing photodiodes, minimizes the ir spectral component of the incoming light and allows color measurements to be made accurately. the high sensitivity, wide dynamic range, and ir blocking filter make the tcs3472 an ideal color sensor solution for use under varying lighting conditions and through attenuating materials. the tcs3472 color sensor has a wide range of applications including rgb led backlight control, solid-state lighting, health/fitness products, industrial process controls and medical diagnostic equipment. in addition, the ir blocking filter enables the tcs3472 to perform ambient light sensing (als). ambient light sensing is widely used in display-based products such as cell phones, notebooks, and tvs to sense the lighting environment and enable automatic display brightness for optimal viewing and power savings. the tcs3472, itself, can enter a lower-power wait state between light sensing measurements to further reduce the average power consumption. ordering information and content guide appear at end of datasheet. key benefits & features the benefits and features of tc s3472, color light-to-digital converter with ir filter are listed below: figure 1: added value of using tcs3472 benefits features ? enables accurate color and light sensing measurements under varying lighting conditions by minimizing ir and uv spectral component effects ? red, green, blue (rgb), and clear light ? sensing with ir blocking filter ? programmable analog gain and integration time ? 3,800,000:1 dynamic range ? very high sensitivity - ideally suited for operation behind dark glass ? programmable interrupt pin enables level-style interrupts when pre-set values are exceeded, thus reducing companion micro-processor overhead ? maskable interrupt ? programmable upper and lower thresholds with persistence filter general description
page 2 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? general description applications the applications of tcs3472 include: ? rgb led backlight control ? light color temperature measurement ? ambient light sensing for display backlight control ? fluid and gas analysis ? product color verification and sorting end products and market segments ? tvs, mobile handsets, tablet s, computers, and monitors ? consumer and commercial printing ? medical and health fitness ? solid state lighting ( ssl) and digital signage ? industrial automation ? enabling a low-power wait-state between rgbc measurements to reduce average power consumption ? power management ? low power - 2.5 a sleep state ? 65 a wait state with programmable wait state time from 2.4ms to > 7 seconds ? digital interfaces are less susceptible to noise ? i2c fast mode compatible interface ? data rates up to 400 kbit/s ? input voltage levels compatible with v dd or 1.8 v bus ? backward compatibility enables interchangeability and re-usability in systems ? register set and pin compatible with the tcs3x71 series ? reduces pcb space requirements while simplifying designs ? small 2mm x 2.4mm dual flat no-lead ? fn package benefits features
ams datasheet page 3 [v1-02] 2016-feb-08 document feedback tcs3472 ? general description block diagram the functional blocks of this device are shown below: figure 2: functional block diagram
page 4 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? detailed description the tcs3472 light-to-digital converter contains a 3 4 photodiode array, four analog-to-digital converters (adc) that integrate the photodiode current, data registers, a state machine, and an i2c interface. the 3 4 photodiode array is composed of red-filtered, green-filtered, blue-filtered, and clear (unfiltered) photodiodes. in addition, the photodiodes are coated with an ir-blocking filter. the four integrating adcs simultaneously convert the amplified photodiode currents to a 16-bit digital value. upon comple tion of a conversion cycle, the results are transferred to the data registers, which are double-buffered to ensure the in tegrity of the data. all of the internal timing, as well as the low-power wait state, is controlled by the state machine. communication of the tcs3472 data is accomplished over a fast, up to 400 khz, two-wire i2c serial bus. the industry standard i2c bus facilitates easy, direct connection to microcontrollers and embedded processors. in addition to the i2c bus, the tcs3472 provides a separate interrupt signal output. when interrupts are enabled, and user-defined thresholds are exceeded, the active-low interrupt is asserted and remains asserted until it is cleared by the controller. this interrupt feature simplifies and improves the efficiency of the system software by eliminating the need to poll the tcs3472. the user can define the upper and lower interrupt thresholds and apply an interrupt persistence filter. the interrupt persistence filter allows the user to define the number of consecutive out-of-threshold events necessary before generating an interrup t. the interrupt output is open-drain, so it can be wire-ored with other devices. detailed description
ams datasheet page 5 [v1-02] 2016-feb-08 document feedback tcs3472 ? pin assignment t he tcs3472 pin assignment is described below. figure 3: pin diagram figure 4: pin description package fn dual flat no-lead (top view): package drawing is not to scale. pin number pin name pin type description 1 v dd supply voltage 2 scl input i2c serial clock input terminal C clock signal for i2c serial data 3 gnd power supply ground. all voltages are referenced to gnd 4 nc output no connect - do not connect 5 int output interrupt - open drain (active low). 6 sda input/output i2c serial data i/o terminal - serial data i/o for i2c. pin assignment v dd 1 scl 2 gnd 3 6 sda 5 int 4 nc
page 6 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. figure 5: absolute maximum ratings over operating free-air temperature range (unless otherwise noted) parameter min max units comments supply voltage, v dd 3.8 v all voltages are with respect to gnd input terminal voltage - 0.5 3.8 v output terminal voltage - 0.5 3.8 v output terminal current - 1 20 ma storage temperature range, t strg - 40 85 oc esd tolerance, human body model 2000 v absolute maximum ratings
ams datasheet page 7 [v1-02] 2016-feb-08 document feedback tcs3472 ? electrical characteristics all limits are guaranteed. the parameters with min and max values are guaranteed with production tests or sqc (statistical quality control) methods. figure 6: recommended operating conditions figure 7: operating characteristics, v dd = 3 v, t a = 25 o c (unless otherwise noted) symbol parameter conditions min typ max units v dd supply voltage tcs34721 and tcs34725 (i2c v bus = v dd ) 2.7 3 3.6 v tcs34723 and TCS34727 (i2c v bus = 1.8 v) 2.7 3 3.3 t a operating free - air temperature -30 70 oc symbol parameter conditions min typ max units i dd supply current active 235 330 a wait state 65 sleep state - no i2c activity 2.5 10 v ol int sda output low voltage 3 ma sink current 0 0.4 v 6 ma sink current 0 0.6 i leak leakage current, sda, scl, int pins -5 5 a leakage current, ldr pin -5 5 v ih scl sda input high voltage tcs34721 and tcs34725 0.7 v dd v tcs34723 and TCS34727 1.25 v il scl sda input low voltage tcs34721 and tcs34725 0.3 v dd v tcs34723 and TCS34727 0.54 electrical characteristics
page 8 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? electrical characteristics figure 8: optical characteristics, v dd =3 v, t a = 25 o c, again = 16, atime = 0xf6 (unless otherwise noted) (1) notes: 1. the percentage shown represents the ra tio of the respective red, green, or blue channel value to the clear channel value. 2. the 465 nm input irradiance is supplied by an ingan light-em itting diode with the following characteristics: dominant wavele ngth d = 465 nm, spectral halfwidth ?? = 22 nm. 3. the 525 nm input irradiance is supplied by an ingan light-em itting diode with the following characteristics: dominant wavele ngth d = 525 nm, spectral halfwidth ?? = 35 nm. 4. the 615 nm input irradiance is supplied by a alingap light-em itting diode with the following characteristics: dominant wavel ength d = 615 nm, spectral halfwidth ?? = 15 nm. parameter test conditions red channel green channel blue channel clear channel unit min max min max min max min typ max r e irradiance responsivity d = 465 nm (2) 0% 15% 10% 42% 65% 88% 11.0 13.8 16.6 counts /w /cm 2 d = 525 nm (3) 4% 25% 60% 85% 10% 45% 13.2 16.6 20.0 d = 615 nm (4) 80% 110% 0% 14% 5% 24% 15.6 19.5 23.4
ams datasheet page 9 [v1-02] 2016-feb-08 document feedback tcs3472 ? electrical characteristics figure 9: rgbc characteristics, v dd = 3 v, t a = 25 o c, again = 16, aen = 1 (unless otherwise noted) note(s): 1. parameter ensured by design and is not tested. figure 10: wait characteristics, v dd = 3 v, t a = 25 o c, wen = 1 (unless otherwise noted) note(s): 1. parameter ensured by design and is not tested. parameter conditions min typ max units dark adc count value ee = 0, again = 60, atime = 0xd6 (100 ms) 0 1 5 counts adc integration time step size atime = 0xff 2.27 2.4 2.56 ms adc number of integration steps (1) 1 256 steps adc counts per step (1) 0 1024 counts adc count value (1) atime = 0xc0 (153.6 ms) 0 65535 counts gain scaling, relative to 1x gain setting 4x 3.8 4 4.2 x 16x 15 16 16.8 60x 58 60 63 parameter conditions channel min typ max units wait step size wtime = 0xff 2.27 2.4 2.56 ms wait number of integration steps (1) 1256steps
page 10 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? timing characteristics the timing characteristics of tcs3472 are given below. figure 11: ac electrical characteristics, v dd = 3 v, t a = 25oc (unless otherwise noted) note(s): 1. specified by design and characterization; not production tested. timing diagram figure 12: parameter measurement information parameter description min typ max units f (scl) clock frequency (i2c only) 0 400 khz t (buf) bus free time between star t and stop condition 1.3 s t (hdsta) hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 s t (susta) repeated start condition setup time 0.6 s t (susto) stop condition setup time 0.6 s t (hddat) data hold time 0 0.9 s t (sudat) data setup time 100 ns t (low) scl clock low period 1.3 s t (high) scl clock high period 0.6 s t f clock/data fall time 300 ns t r clock/data rise time 300 ns c i input pin capacitance 10 pf timing characteristics
ams datasheet page 11 [v1-02] 2016-feb-08 document feedback tcs3472 ? typical operating characteristics figure 13: photodiode spectral responsivity rgbc figure 14: normalized responsivity vs. angular displacement typical operating characteristics - wavelength - nm relative responsivity normalized responsivity - angular displacement - o
page 12 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? typical operating characteristics figure 15: normalized i dd vs. v dd and temperature figure 16: responsivity temperature coefficient v dd C v i dd normalized @ 3v, 25oc temperature coefficient - ppm/oc - wavelength - nm
ams datasheet page 13 [v1-02] 2016-feb-08 document feedback tcs3472 ? principles of operation system states an internal state machine provides system control of the rgbc and power management features of the device. at power up, an internal power-on-reset initia lizes the device and puts it in a low-power sleep state. when a start condition is detected on the i2c bus, the device transitions to the idle state where it checks the enable register (0x00) pon bit. if pon is disabled, the device will return to the sleep state to save power. otherwise, the device will remain in the idle state until the rgbc function is enabled (aen). once enabled, the device will execute the wait and rgbc states in sequence as indicated in figure 16 . upon completion and return to idle, the device will automatically begin a new wait-rgbc cycle as long as pon and aen remain enabled. figure 17: simplified state diagram principles of operation
page 14 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? principles of operation rgbc operation the rgbc engine contains rgbc gain control (again) and four integrating analog-to-digital converters (adc) for the rgbc photodiodes. the rgbc integrat ion time (atime) impacts both the resolution and the sensit ivity of the rgbc reading. integration of all four channels occurs simultaneously and upon completion of the conversion cycl e, the results are transferred t o t h e c o l o r d a t a r e g i s t e r s . t h i s d a t a i s a l s o r e f e r r e d t o a s c h a n n e l count. the transfers are double-buffered to ensure that invalid data is not read during the transfer. after the transfer, the device automatically moves to the next state in accordance with the configured state machine. figure 18: rgbc operation note(s): 1. in this document, the nomenclature uses the bit field name in italics followed by the regist er address and bit number to all ow the user to easily identify the register and bi t that controls the function. for example, the power on (pon) is in register 0x00, b it 0. this is represented as pon (r0x00:b0) .
ams datasheet page 15 [v1-02] 2016-feb-08 document feedback tcs3472 ? principles of operation the registers for programming the integration and wait times are a 2s compliment values. the actual time can be calculated as follows: atime = 256 ? integration time / 2.4 ms inversely, the time can be calculated from the register value as follows: integration time = 2.4 ms (256 ? atime) for example, if a 100-ms integration time is needed, the device needs to be programmed to: 256 ? (100 / 2.4) = 256 ? 42 = 214 = 0xd6 conversely, the programmed value of 0xc0 would correspond to: (256 ? 0xc0) 2.4 = 64 2.4 = 154 ms. interrupts the interrupt feature simplifies and improves system efficiency by eliminating the need to poll the sensor for light intensity values outside of a user-defin ed range. while the interrupt function is always enabled and its status is available in the status register (0x13), the output of the interrupt state can be enabled using the rgbc interrupt enable (aien) field in the enable register (0x00). two 16-bit interrupt threshold re gisters allow the user to set limits below and above a desired light level. an interrupt can be generated when the clear data (cdata) is less than the clear interrupt low threshold (ailtx) or is greater than the clear interrupt high threshold (aihtx). it is important to note that the thresholds are evaluated in sequence, first the low threshold, then the high threshold. as a result, if the low threshold is set above the high threshold, the high threshold is ignored and only the low threshold is evaluated.
page 16 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? principles of operation to further control when an interrupt occurs, the device provides a persistence filter. the persiste nce filter allows the user to specify the number of cons ecutive out-of-range clear occurrences before an interrupt is generated. the persistence filter register (0x0c) allows the user to set the clear persistence filter (apers) value. see the persistence filter register for details on the persistence filter value. once the persistence filter generates an interrupt, it will continue until a special function interrupt clear command is received (see command register). figure 19: programmable interrupt
ams datasheet page 17 [v1-02] 2016-feb-08 document feedback tcs3472 ? principles of operation system timing the system state machine shown in figure 17 provides an overview of the states and state transitions that provide system control of the device. this section highlights the programmable features, which affect the state machine cycle time, and provides details to determine system level timing. when the power management feature is enabled (wen), the state machine will transition to the wait state. the wait time is determined by wlong, which extends normal operation by 12 when asserted, and wtime. the formula to determine the wait time is given in the box associated with the wait state in figure 20 . when the rgbc feature is enabled (aen), the state machine will transition through the rgbc init and rgbc adc states. the rgbc init state takes 2.4 ms, while the rgbc adc time is dependent on the integration time (atime). the formula to determine rgbc adc time is given in the associated box in figure 20 . if an interrupt is generate d as a result of the rgbc cycle, it will be asserted at the end of the rgbc adc. figure 20: detailed state diagram notes: 1. there is a 2.4 ms warm-up delay if pon is enabled. if pon is not enabled, the devi ce will return to the sleep state as shown . 2. pon, wen, and aen are fields in the enable register (0x00).
page 18 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? principles of operation power management power consumption can be managed with the wait state, because the wait state typically consumes only 65 a of i dd current. an example of the power management feature is given below. with the assumptions provided in the example, average i dd is estimated to be 152 a. figure 21: power management average i dd current = ((43.2 0.065) + (43.2 0.235) + (2.40 0.235)) / 89 152 a keeping with the same programmed values as the example, figure 22 shows how the average i dd current is affected by the wait state time, which is determined by wen, wtime, and wlong. note that the worst-case current occurs when the wait state is not enabled. figure 22: average i dd current system state machine state programmable parameter programmed value duration typical current wait wtime 0xee 43.2 ms 0.065 ma wlong 0 rgbc init 2.40 ms 0.235 ma rgbc adc atime 0xee 43.2 ms 0.235 ma wen wtime wlong wait state average i dd current 0 n/a n/a 0 ms 291 a 1 0xff 0 2.40 ms 280 a 1 0xee 0 43.2 ms 152 a 1 0x00 0 614 ms 82 a 10x00 1 7.37 s 67 a
ams datasheet page 19 [v1-02] 2016-feb-08 document feedback tcs3472 ? i2c protocol interface and control are accomplished through an i2c serial compatible interface (standard or fast mode) to a set of registers that provide access to device cont rol functions and output data. the devices support the 7-bit i2c addressing protocol. the i2c standard provides for three types of bus transaction: read, write, and a combined protocol ( figure 23 ). during a write operation, the first byte written is a command byte followed by data. in a combined protocol, the first byte written is the command byte followed by reading a series of bytes. if a read command is issued, the register address from the previous command will be used for data access. likewise, if the msb of the command is not set, the device will write a series of bytes at the address stored in the last valid command with a register address. the command byte contains either control information or a 5-bit register address. the control commands can also be used to clear interrupts. the i2c bus protocol was develo ped by philips (now nxp). for a complete description of the i2c protocol, please review the nxp i2c design specification at www.i2c-bus.org/references/. figure 23: i2c protocols i2c protocol repeated start condition write (0) continuation of protocol master - to - slave slave - to - master sr w acknowledge (0) not acknowledged (1) stop condition read (1) start condition a n p r s
page 20 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? register description the tcs3472 is controlled and mo nitored by data registers and a command register accessed th rough the serial interface. these registers provide for a variety of control functions and can be read to determine results of the adc conversions. the register set is summarized in figure 24 . figure 24: register set the mechanics of accessing a spec ific register depends on the specific protocol used. see the section on i2c protocols on the previous pages. in general, the command register is written first to specify the specific c ontrol-status-data register for subsequent read/write operations. address register name r/w register function reset value ?? command w specifies register address 0x00 0x00 enable r/w enables states and interrupts 0x00 0x01 atime r/w rgbc time 0xff 0x03 wtime r/w wait time 0xff 0x04 ailtl r/w clear interrupt low threshold low byte 0x00 0x05 ailth r/w clear interrupt low threshold high byte 0x00 0x06 aihtl r/w clear interrupt high threshold low byte 0x00 0x07 aihth r/w clear interrupt high threshold high byte 0x00 0x0c pers r/w interrupt persistence filter 0x00 0x0d config r/w configuration 0x00 0x0f control r/w control 0x00 0x12 id r device id id 0x13 status r device status 0x00 0x14 cdatal r clear data low byte 0x00 0x15 cdatah r clear data high byte 0x00 0x16 rdatal r red data low byte 0x00 0x17 rdatah r red data high byte 0x00 0x18 gdatal r green data low byte 0x00 0x19 gdatah r green data high byte 0x00 0x1a bdatal r blue data low byte 0x00 0x1b bdatah r blue data high byte 0x00 register description
ams datasheet page 21 [v1-02] 2016-feb-08 document feedback tcs3472 ? register description command register the command register specifie s the address of the target register for future write and read operations. figure 25: command register 7654321 0 cmd type addr/sf fields bits description cmd 7 select command register. must write as 1 when addressing command register. type 6:5 selects type of transaction to fo llow in subsequent data transfers: field value transaction type 00 repeated byte protocol transaction 01 auto-increment protocol transaction 10 reserved do not use 11 special function see description below byte protocol will repeatedly read the same register with each data access. block protocol will provide auto-increment function to read successive bytes. addr/sf 4:0 address field/special function field. depe nding on the transaction type, see above, this field either specifies a special fu nction command or selects the specific control-status-data register for subsequent read and write transactions. the field values listed below only apply to special function commands: field value read value 00110 clear channel interrupt clear other reserved do not write the clear channel interrupt clear special function clears any pe nding interrupt and is self-clearing.
page 22 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? register description enable register (0x00) the enable register is used primarily to power the tcs3472 device on and off, and enable functions and interrupts as shown below. figure 26: enable register notes: 1. see power management section for more information. 2. a minimum interval of 2.4 ms must pass after pon is asserted before an rgbc can be initiated. 765 4 321 0 reserved aien wen reserved aen pon fields bits description reserved 7:5 reserved. write as 0. aien 4 rgbc interrupt enable. when assert ed, permits rgbc interrupts to be generated. wen 3 wait enable. this bit activates the wait feature. writing a 1 activates the wait timer. writing a 0 disables the wait timer. reserved 2 reserved. write as 0. aen 1 rgbc enable. this bit actives the two-channel adc. writing a 1 activates the rgbc. writing a 0 disables the rgbc. pon (1) , (2) 0 power on. this bit activates the internal oscillator to permit the timers and adc channels to operate. writing a 1 activates the oscillator. writing a 0 disables the oscillator.
ams datasheet page 23 [v1-02] 2016-feb-08 document feedback tcs3472 ? register description rgbc timing register (0x01) the rgbc timing register controls the internal integration time of the rgbc clear and ir channel adcs in 2.4-ms increments. max rgbc count = (256 ? atime) 1024 up to a maximum of 65535. figure 27: rgbc timing register wait time register (0x03) wait time is set 2.4 ms incr ements unless the wlong bit is asserted, in which case the wait times are 12 longer. wtime is programmed as a 2s complement number. figure 28: wait time register fields bits description atime 7:0 value integ_cycles time max count 0xff 1 2.4 ms 1024 0xf6 10 24 ms 10240 0xd5 42 101 ms 43008 0xc0 64 154 ms 65535 0x00 256 700 ms 65535 fields bits description wtime 7:0 register value wait time time (wlong= 0) time (wlong= 1) 0xff 1 2.4 ms 0.029 sec 0xab 85 204 ms 2.45 sec 0x00 256 614 ms 7.4 sec
page 24 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? register description rgbc interrupt threshold registers (0x04 ? 0x07) the rgbc interrupt threshold registers provides the values to be used as the high and low trigger points for the comparison function for interrupt generation . if the value generated by the clear channel crosses below the lower threshold specified, or above the higher threshold, an interrupt is asserted on the interrupt pin. figure 29: rgbc interrupt threshold registers persistence register (0x0c) the persistence register controls the filtering interrupt capabilities of the device. configurable filtering is provided to allow interrupts to be generated after each integration cycle or if the integration has produced a result that is outside of the values specified by the threshol d register for some specified amount of time. figure 30: persistence register register address bits description ailtl 0x04 7:0 rgbc clear channel low threshold lower byte ailth 0x05 7:0 rgbc clear channel low threshold upper byte aihtl 0x06 7:0 rgbc clear channel high threshold lower byte aihth 0x07 7:0 rgbc clear channel high threshold upper byte 76543210 reserved apers field bits description ppers 7:4 reserved
ams datasheet page 25 [v1-02] 2016-feb-08 document feedback tcs3472 ? register description configuration register (0x0d) the configuration register sets the wait long time. figure 31: configuration register apers 3:0 interrupt persistence. controls rate of interrupt to the host processor. field value meaning interrupt persistence function 0000 every every rgbc cycle generates an interrupt 0001 1 1 clear channel value outside of threshold range 0010 2 2 clear channel consecutive values out of range 0011 3 3 clear channel consecutive values out of range 0100 5 5 clear channel consecutive values out of range 0101 10 10 clear channel consecutive values out of range 0110 15 15 clear channel consecutive values out of range 0111 20 20 clear channel consecutive values out of range 1000 25 25 clear channel consecutive values out of range 1001 30 30 clear channel consecutive values out of range 1010 35 35 clear channel consecutive values out of range 1011 40 40 clear channel consecutive values out of range 1100 45 45 clear channel consecutive values out of range 1101 50 50 clear channel consecutive values out of range 1110 55 55 clear channel consecutive values out of range 1111 60 60 clear channel consecutive values out of range 765 4 321 0 reserved wlong reserved fields bits description reserved 7:2 reserved. write as 0. wlong 1 wait long. when asserted, the wait cycles are increased by a factor 12 from that programmed in the wtime register. reserved 0 reserved. write as 0. field bits description
page 26 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? register description control register (0x0f) the control register provides eight bits of miscellaneous control to the analog block. these bits typically control functions such as gain setti ngs and/or diode selection. figure 32: control register 765 4 321 0 reserved again fields bits description reserved 7:2 reserved. write as 0. again 1:0 rgbc gain control. field value rgbc gain value 00 1x gain 01 4x gain 10 16x gain 11 60x gain
ams datasheet page 27 [v1-02] 2016-feb-08 document feedback tcs3472 ? register description id register (0x12) the id register provides the value for the part number. the id register is a read-only register. figure 33: id register status register (0x13) the status register provides the internal status of the device. this register is read only. figure 34: status register 76543210 id field bits description id 7:0 part number identification 0x44 = tcs34721 and tcs34725 0x4d = tcs34723 and TCS34727 7654321 0 reserved aint reserved avalid field bits description reserved 7:5 reserved. aint 4 rgbc clear ch annel interrupt. reserved 3:1 reserved. avalid 0 rgbc valid. indicates that the rgbc channels have completed an integration cycle.
page 28 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? register description rgbc channel data registers (0x14 C 0x1b) clear, red, green, and blue data is stored as 16-bit values. to ensure the data is read correctly, a two-byte read i2c transaction should be used with a read word protocol bit set in the command register. with this operation, when the lower byte register is read, the upper eight bits are stored into a shadow register, which is read by a subsequent read to the upper byte. the upper register will read the correct value even if additional adc integration cycles end betw een the reading of the lower and upper registers. figure 35: rgbc channel data registers register address bits description cdata 0x14 7:0 clear data low byte cdatah 0x15 7:0 clear data high byte rdata 0x16 7:0 red data low byte rdatah 0x17 7:0 red data high byte gdata 0x18 7:0 green data low byte gdatah 0x19 7:0 green data high byte bdata 0x1a 7:0 blue data low byte bdatah 0x1b 7:0 blue data high byte
ams datasheet page 29 [v1-02] 2016-feb-08 document feedback tcs3472 ? application information: hardware pcb pad layout suggested pcb pad layout guidelines for the dual flat no-lead (fn) surface mount package are shown in figure 36 . figure 36: suggested fn package pcb layout notes: 1. all linear dimensions are in micrometers. 2. this drawing is subject to change without notice. application information: hardware pads can be extended further if hand soldering is needed
page 30 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? package drawings & markings figure 37: package fn C dual flat no-lead packaging configuration notes: 1. all linear dimensions are in micrometers. dime nsion tolerance is 20 m unless otherwise noted. 2. the die is centered within the package within a tolerance of 3 mils. 3. package top surface is molded with an electrically noncondu ctive clear plastic compound having an index of refraction of 1. 55. 4. contact finish is copper alloy a194 with pre-plated nipdau lead finish. 5. this package contains no lead (pb). 6. this drawing is subjec t to change without notice. package drawings & markings green rohs
ams datasheet page 31 [v1-02] 2016-feb-08 document feedback tcs3472 ? mechanical data figure 38: carrier tape and reel information notes: 1. all linear dimensions are in millimeters. dimension tolerance is 0.10 mm unless otherwise noted. 2. the dimensions on this drawing are fo r illustrative purposes only. dimensions of an actual carrier may vary slightly. 3. symbols on drawing a 0 , b 0 , and k 0 are defined in ansi eia standard 481-b 2001. 4. each reel is 178 millimeters in diameter and contains 3500 parts. 5. ams packaging tape and reel conform to the requiremen ts of eia standard 481-b. 6. in accordance with eia standard, device pin 1 is located next to sprocket holes in the tape. 7. this drawing is subjec t to change without notice. mechanical data
page 32 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? soldering & storage information soldering information the fn package has been tested and has demonstrated an ability to be reflow soldered to a pcb substrate. the process, equipment, and materials used in these test are detailed below. the solder reflow profile describes the expected maximum heat exposure of components during the solder reflow process of product on a pcb. temperature is measured on top of component. the components should be limited to a maximum of three passes through this solder reflow profile. figure 39: solder reflow profile figure 40: solder reflow profile graph note(s): 1. not to scale C for reference only. parameter reference device average temperature gradient in preheating 2.5 oc/s soak time t soak 2 to 3 minutes time above 217 oc (t 1 )t 1 max 60 s time above 230 oc (t 2 )t 2 max 50 s time above t peak - 10 oc (t 3 )t 3 max 10 s peak temperature in reflow t peak 260 oc temperature gradient in cooling max -5 oc/s soldering & storage information (s)
ams datasheet page 33 [v1-02] 2016-feb-08 document feedback tcs3472 ? soldering & storage information storage information moisture sensitivity optical characteristics of the device can be adversely affected during the soldering process by the release and vaporization of moisture that has been previous ly absorbed into the package. to ensure the package contains the smallest amount of absorbed moisture possible, each device is dry-baked prior to being packed for shipping. devices are packed in a sealed aluminized envelope called a moisture barrier bag with silica gel to protect them from ambient moisture during shipping, handling, and storage before use. the moisture barrier bags should be stored under the following conditions: ? temperature range < 40c ? relative humidity < 90% ? total time - no longer than 12 months from the date code on the aluminized envelope if unopened. rebaking of the reel will be required if the devices have been stored unopened for more than 12 months and the humidity indicator card shows the parts to be out of the allowable moisture region. opened reels should be used within 168 hours if exposed to the following conditions: ? temperature range < 30c ? relative humidity < 60% if rebaking is required, it should be done at 50c for 12 hours. the fn package has been assigned a moisture sensitivity level of msl 3.
page 34 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? ordering & contact information figure 41: ordering information note(s): 1. contact ams for availability. buy our products or get free samples online at: www.ams.com/icdirect technical support is available at: www.ams.com/technical-support provide feedback about this document at: www.ams.com/document-feedback for further information and requests, e-mail us at: ams_sales@ams.com for sales offices, distributors and representatives, please visit: www.ams.com/contact headquarters ams ag tobelbaderstrasse 30 8141 premstaetten austria, europe tel: +43 (0) 3136 500 0 website: www.ams.com device address package-leads interface description ordering number tcs34721 (1) 0x39 fn?6 i2c v bus = v dd interface tcs34721fn tcs34723 (1) 0x39 fn?6 i2c v bus = 1.8 v interface tcs34723fn tcs34725 0x29 fn?6 i2c v bus = v dd interface tcs34725fn TCS34727 0x29 fn?6 i2c v bus = 1.8 v interface TCS34727fn ordering & contact information
ams datasheet page 35 [v1-02] 2016-feb-08 document feedback tcs3472 ? rohs compliant & ams green statement rohs: the term rohs compliant means that ams ag products fully comply with current rohs directives. our semiconductor products do not contain any chemicals for all 6 substance categories, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, rohs compliant products are suitable for use in specif ied lead-free processes. ams green (rohs compliant and no sb/br): ams green defines that in addition to rohs compliance, our products are free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material). important information: the information provided in this statement represents ams ag knowledge and belief as of the date that it is provided. ams ag bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are unde rway to better integrate information from third parties. ams ag has taken and continues to take reasonable steps to prov ide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ams ag and ams ag suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. rohs compliant & ams green statement
page 36 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? copyrights & disclaimer copyright ams ag, tobelbader st rasse 30, 8141 premstaetten, austria-europe. trademarks registered. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used with out the prior written consent of the copyright owner. devices sold by ams ag are covered by the warranty and patent indemnification provisions appe aring in its general terms of trade. ams ag makes no warranty, express, statutory, implied, or by description regarding th e information set forth herein. ams ag reserves the right to ch ange specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliability applications , such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by ams ag for each application. this product is provided by ams ag as is and any express or implied wa rranties, including, but not limited to the implied warranties of merchantability and fitness for a particular purpose are disclaimed. ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any th ird party shall arise or flow out of ams ag rendering of technical or other services. copyrights & disclaimer
ams datasheet page 37 [v1-02] 2016-feb-08 document feedback tcs3472 ? document status document status product status definition product preview pre-development information in this datasheet is based on product ideas in the planning phase of development. all specifications are design goals without any warranty and are subject to change without notice preliminary datasheet pre-production information in this datasheet is based on products in the design, validation or qualific ation phase of development. the performance and parameters shown in this document are preliminary without any warranty and are subject to change without notice datasheet production information in this datashee t is based on products in ramp-up to full production or full production which conform to specifications in accordance with the terms of ams ag standard warranty as given in the general terms of trade datasheet (discontinued) discontinued information in this datasheet is based on products which conform to specifications in accordance with the terms of ams ag standard warranty as given in the general terms of trade, but these products have been superseded and should not be used for new designs document status
page 38 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? revision information note(s): 1. page and figure numbers for the previous version may diff er from page and figure numbers in the current revision. 2. correction of typographical er rors is not explicitly mentioned. changes from v1.0 (2013-apr) to current revision 1-02 (2016-feb-08) page v1.0 (2013-apr) to 1-01 (2016-feb-03) content was updated to the latest ams design updated figure 25 21 1-01 (2016-feb-03) to 1-02 (2016-feb-08) updated figure 33 27 updated notes under figure 36 29 revision information
ams datasheet page 39 [v1-02] 2016-feb-08 document feedback tcs3472 ? content guide 1 general description 1 key benefits & features 2 applications 2 end products and market segments 3 block diagram 4 detailed description 5 pin assignment 6absolute maximum ratings 7 electrical characteristics 10 timing characteristics 10 timing diagram 11 typical operating characteristics 13 principles of operation 13 system states 14 rgbc operation 15 interrupts 17 system timing 18 power management 19 i2c protocol 20 register description 21 command register 22 enable register (0x00) 23 rgbc timing register (0x01) 23 wait time register (0x03) 24 rgbc interrupt threshold registers (0x04 ? 0x07) 24 persistence register (0x0c) 25 configuration register (0x0d) 26 control register (0x0f) 27 id register (0x12) 27 status register (0x13) 28 rgbc channel data registers (0x14 C 0x1b) 29 application information: hardware 29 pcb pad layout 30 package drawings & markings 31 mechanical data 32 soldering & storage information 32 soldering information 33 storage information 33 moisture sensitivity content guide
page 40 ams datasheet document feedback [v1-02] 2016-feb-08 tcs3472 ? content guide 34 ordering information 35 rohs compliant & ams green statement 36 copyrights & disclaimer 37 document status 38 revision information

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