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31214hk 20140227-s00001/201813hk no.a2172-1/30 http://onsemi.com semiconductor components industries, llc, 2014 march, 2014 LC89091JA 1. overview the LC89091JA is a digital audio interface receiver that de modulates signals according to the data transfer format between digital audio devices via iec60958, iec61937 and jeita cpr-1205. it supports demodulation sampling frequencies of up to 192khz. the LC89091JA adjusts to using in various systems in cluding av receivers, digital tvs and dvd recorders. 2. features ? s/pdif demodulation process according to iec60958, ie c61937 and jeita cpr-1205 ? outputs master clock: 512fs, 256fs and 128fs (with output frequency automatic adjustment function) ? audio data output interface: 24-bit i 2 s and msb first left justified ? i 2 c microcontroller interface (with addr ess automatic increment function) ? built-in power-on reset circuit ? supply voltages: 3.0 to 3.6v ? package: ssop16 (lea d-free and halogen-free) ? operation guarantee temperature: ? 30 to 70c applicaitons ? consumer audio ? digital audio interface end products ? av receiver ? home theater-in-a-box ? mini compo ? sound bar ? headphone amplifier cmos lsi digital audio interface receiver * i 2 c bus is a trademark of philips corporation. orderin g numbe r : ena2172a ssop16(225mil) ordering information see detailed ordering and shipping informa tion on page 30 of this data sheet.
LC89091JA no.a2172-2/30 3. package dimensions unit : mm ssop16 (225mil) case 565am issue a xxxxxxxxxx ymddd xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. soldering footprint* note: the measurements are not to guarantee but for reference only. (unit: mm) *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 1.0 5.80 0.32 0.65
LC89091JA no.a2172-3/30 4. pin assignment figure 4.1: LC89091JA pin assignment 5. pin functions table 5.1: pin functions no name i/o function 1 scl i microcontroller interface i 2 c: clock input pin 2 sda i microcontroller interface i 2 c: data input pin o microcontroller interface i 2 c: data output pin 3 err o pll lock error and data error flag output pin (initial output) output data mute signal output pin 4 gpo o channel status bit-1 (pcm or non-pcm flag) output pin (initial output) input s/pdif (rxin or mpio) through output pin general purpose output pin 5 rxin i 3.3v tolerance ttl-compatible s/pdif input pin 6 mpio o channel status emphasis flag output pin (initial output) i 3.3v tolerance ttl-compatible s/pdif input pin 7 lpf o pll: loop filter connection output pin 8 gnd digital gnd 9 mcko o master clock output pin (512fs, 256fs, and 128fs) 10 bcko o bit clock output pin (64fs) 11 lrcko o lr clock output pin (fs) 12 datao o serial audio data output pin (i 2 s and left justified) 13 xin i crystal resonator connection or external clock input pin (24.576mhz) 14 xout o crystal resonator connection output pin 15 sdin i serial audio data input pin 16 vdd digital power supply (3.3v) *pin.2 and pin 6 configure an open-drain output. *pin.2 needs a pull-up resistor when using microcontroller interface. *pin.6 needs a pull-up resistor when set to the output. scl 1 2 314 15 16 sda err vdd sdin xout 413 gpo xin 512 rxin datao 611 mpio lrcko 710 lpf bcko 89 gnd mcko
LC89091JA no.a2172-4/30 6. block diagram figure 6.1: LC89091JA block diagram default: ?l? emphasis pcm / non-pcm micom i/f cbit demodulation & lock detect data selecto r 15 3err sdin clock selecto r input selecto r 6 7 mpio lpf 11 lrcko 9mcko 4 gpo oscillation a mplifie r 13 xin 14 xout 2 sd a 1 scl 5 rxin 12 datao 10 bcko clock divide r power on reset pll
LC89091JA no.a2172-5/30 7. electrical characteristics 7.1 absolute maximum ratings table 7.1: absolute maximum ratings at gnd=0v parameter symbol conditions ratings unit maximum supply voltage v dd max 7.1.1 -0.3 to 4.6 v input voltage v in 7.1.2 -0.3 to v dd max+0.3 (max.4.6vp-p) v output voltage v out 7.1.3 -0.3 to v dd max+0.3 (max.4.6vp-p) v storage ambient temperature tstg -55 to 125 ? c operating ambient temperature topr -30 to 70 ? c maximum input/output current i in , i out 7.1.4 ? 20 ma 7.1.1: v dd pin 7.1.2: scl, sda, rxin, mpio, xin and sdin pins 7.1.3: sda, err, gpo, mpio, mcko, bcko, lrcko, datao and xout pins 7.1.4: per input/output pin 7.2 allowable operating range table 7.2: recommended operating conditions at gnd=0v parameter symbol conditions min typ max unit supply voltage v dd 7.2.1 3.0 3.3 3.6 v input voltage range v in 7.2.2 0 3.6 v output load capacitance c l1 7.2.3 20 pf output load capacitance c l2 7.2.4 30 pf operating temperature vopr -30 25 70 ? c 7.2.1: v dd pin 7.2.2: scl, sda, rxin, mpio, xin and sdin pins 7.2.3: mcko pin 7.2.4: output pins expect mcko pin 7.3 dc characteristics table 7.3: dc characteristics at ta=-30 to 70 ? c, v dd =3.0 to 3.6v, gnd=0v parameter symbol conditions min max unit input, high v ih 7-3-1 0.7 v dd v input, low v il 0.2v dd v input, high v ih 7.3.2 2.0 v input, low v il 0.8 v output, high v oh 7.3.3 v dd -0.8 v output, low v ol 0.4 v v dd supply current i dd1 7.3.4 20 ma v dd supply current i dd2 7.3.5 2 ? a 7.3.1: cmos-compatible: xin pin (while external clock inputs) 7.3.2: ttl-compatible: scl, sda, rxin, mpio and sdin pins 7.3.3: i oh =-4ma, i ol =4ma: err, mcko, bcko, lrcko, datao and xout output pins i oh =-2ma, i ol =2ma: sda and mpio output pins 7.3.4: input fs: 96khz, mcko: 512fs output status 7.3.5: "pdmode=1" stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
LC89091JA no.a2172-6/30 7.4 ac characteristics table 7.4: ac characteristics at ta=-30 to 70 ? c, v dd =3.0 to 3.6v, gnd=0v parameter symbol min typ max unit vdd rise slope t vdd - - 100 ms rxin and mpio input receive frequency f rfs 28 - 195 khz rxin and mpio input duty factor f rxduy 40 50 60 % xin clock input frequency f xf - 24.576 - mhz mcko clock output frequency f mck 4 - 50 mhz mcko clock output duty factor f xmckduy 40 - 60 % mcko-bcko output delay t mbo -10 - 10 ns bcko-lrcko output delay t blo -10 - 10 ns bcko-datao output delay t bdo -10 - 10 ns lrcko-datao output delay t ldo -10 - 10 ns figure 7.1: ac characteristics mcko bcko datao lrcko rxin, mpio t rxduy t rxduy t ldo t blo t mckduy t mc kduy t mbo t bdo t mbo input output output output output
LC89091JA no.a2172-7/30 7.5 i 2 c microcontroller interface ac characteristics table 7.5: ac characteristics at ta=-30 to 70 ? c, v dd =3.0 to 3.6v, gnd=0v parameter symbol min max unit rstb input pulse width (l) t rstdw - 400 khz scl input frequency f scl 600 - ns scl input pulse width (l) t scldw 1300 - ns scl input pulse width (h) t scluw 600 - ns start (repeated) setup t csbuw 600 - ns sda hold t sdahold 0 900 ns sda setup t sdasetup 100 - ns scl-sda rise time t sclsdard 20+0.1cb 300 ns scl-sda fall time t sclsdafd 20+0.1cb 300 ns stop setup t stopsetup 600 - ns bus open t busopen 1300 - ns spike pulse width t spkpw 0 50 ns c b = total capacitance of one bus line in pf. figure 7.2: i 2 c microcontroller interf ace ac characteristics sda scl t starthold t scldw t sclsdard t sdahold t sdasetup t sclsdafd t startsetup t starthold t scluw t spkpw t stopsetup t busopen t sclsdafd t sclsdard start repeated start stop start product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
LC89091JA no.a2172-8/30 8. system settings 8.1 power-on reset ? the LC89091JA features a built-in power-on reset circuit, and constantly monitors the power supply status. figure 8.1: power-on reset timing table 8.1: output port state i mmediately after power-on reset pin no. port name output state pin no. port name output state 3 err h output 10 bcko xin/4 input clock output (6.144mhz) 4 gpo l output (non-pcm flag) 11 lrck o xin/256 input clock output (96khz) 6 mpio hi-z output (emphasis flag) 12 datao sdin input data output 9 mcko xin input clock output (24. 576mhz) 14 xout xi n invert output 8.2 register reset and power-down mode ? the sysrst register resets circuits other than register. ? during reset period, register setting state hold and can also change. ? although a system is reset by sysrst register, the osc illation amplifier operates, and the clock is output to mcko, bcko and lrcko pins. but, datao pin outputs "l" without relation to the setup. ? the system is set power-down mode by pdmode register. ? during power-down mode period, register setting state hold and can also change. ? in power-down mode, the circuits exp ect a power-on reset and a microcontrolle r interface will be set to stop condition all the circuit operations, and the clock is not output. vdd internal reset 1/2vdd <100ms reset state >150 ? >1 ?
LC89091JA no.a2172-9/30 8.3 oscillation amplifier pin settings (xin, xout) ? the LC89091JA has a built-in oscillation amplifier, and co nnects a quartz resonator, f eedback resistor and load capacitance to xin and xout to configure an oscillation circuit. the figure below shows the connection diagram. ? when connecting a quartz resonator, use one with a fundamental wave, and be aware that the load capacitance depends on the quartz resonato r characteristics, so thorough i nvestigation should be made. ? if the built-in oscillation amplifier is not used and an oscillation module is used as the clock source instead, connect the output of an external clock supply source to xin. at this time, it is not necessary to connect a feedback resistor between xin and xout. ? always supply 24.576mhz clock to xin. ? xin clock is output to mcko, bcko and lrcko while pll is locked. (a) xin and xout quartz resonator connection diagram (b) xin external clock input diagram figure 8.2: xin and xout external circuit connection diagram 8.4 loop filter pin setting (lpf) ? the LC89091JA has a built-in vco (voltage controlled oscillator) that synchronizes with sampling frequencies from 32khz to 192khz and with the data with a transfer rate from 4mhz to 25mhz. ? the pll is locked at 512fs. ? lpf is a pin for the pll loop filter. connect the resistor and capacitors shown in the right figure, as close to the pin as possible. figure 8.3: lpf external circuit connection diagram 1m ? 1p to 33pf 150 to 2.2k ? xin xout 13 14 24.576mhz open xin xout 13 14 0.022 ? f pgnd lpf 2 1 100 ? 0. 1 ? f
LC89091JA no.a2172-10/30 8.5 clocks 8.5.1 master clock ? the clock source is selected betw een the following two master clocks. 1) pll source: 512fs 2) xin source: 24.576mhz 8.5.2 pll source master clock ? the pll synchronizes with the input s/pdif and outputs 512fs clock. ? the pll clock is controlled by pllacc, plldiv[1:0] and prsel[1:0] register settings. ? normally, "pllacc=0" is set and pll clock is output fo r each input sampling frequency band. at this setting, output clock frequency fluctuation by varying the sampling frequency is kept to a narrow band, such as 512fs output when fs=32khz to 48khz, 256fs output when fs=64khz to 96khz, and 128fs output when fs=128khz to 192khz. ? when "pllacc=0" is set, the pll cloc k is set with the plldiv[1:0] register ? when "pllacc=0" is set, during the pll is locked, switc hing is not performed even when the plldiv[1:0] register setting is changed. these registers switching are executed when the pll is in unlocked status. this setting becomes valid after the pll is locked again. ? to set an output clock that does not depend on the s/pdif input sampling frequency, "pllacc=1" is set. at this setting, the clock frequency is always multiplied by a constant and output, such as output at 256fs for all sampling frequencies from 32khz to 192khz. ? when "pllacc=1" is set, the pll cloc k is set with the prsel[1:0] register. ? when "pllacc=1" is set, prsel[1:0] register can be changed even pll lock state. ? the change to "pllacc=1" from "pllacc=0" is possible even pll lock state. but, the setting change to "pllacc=0" from "pllacc=1" becomes valid after the pll is locked again. ? the pll output clock setting flow is shown below. figure 8.4: pll output clock flow diagram s/pdif input 512fs lock detection fs calculation fs= 32k,44.1k,48k fs= 64k,88.2k,96k fs= 128k,176.4k,192k yes no yes no yes no ? pllacc? lock unlock pll output 256fs 0 1 pll fi xation output ? prsel =00?: 256fs ? prsel =01?: 512fs ? prsel =10?: 128fs pll output free- run pll output 128fs pll output 512fs pll output 256fs ? plldiv? pll output 512fs pll output 256fs ? pll d i v? 01 or 11 00 or 10 10 or 11 00 or 01
LC89091JA no.a2172-11/30 ? the pll clock output frequencies are shown below. ? when "pllacc=1" and "prsel[1:0]=01" (512fs) are set, 128khz, 176.4khz and 192khz s/pdif reception results in a pll output frequency that exceeds 50mhz, so direct output to mcko is not guaranteed. table 8.2: pll clock output frequencies (bold settings are initial values.) s/pdif fs (khz) pll clock output frequencies (mhz) "pllacc=0" (fixed multiple outputs for each input fs band) "pllacc=1" (fixed multiple outputs of input fs) "plldiv=00" "plldiv=01" "plldiv =10" "plldiv=11" "prsel=00" (256fs) "prsel=01" (512fs) "prsel=10" (128fs) 32 16.38 8.19 16.38 8.19 8.19 16.38 4.09 44.1 22.57 11.28 22.57 11.28 11.28 22.57 5.64 48 24.57 12.28 24.57 12.28 12.28 24.57 6.14 64 16.38 16.38 32.76 32.76 16.38 32.76 8.19 88.2 22.57 22.57 45.15 45.15 22.57 45.15 11.28 96 24.57 24.57 49.15 49.15 24.57 49.15 12.28 128 16.38 16.38 16.38 16.38 32. 76 65.54 * 16.38 176.4 22.57 22.57 22.57 22.57 45. 15 90.32 * 22.57 192 24.57 24.57 24.57 24.57 49. 15 98.30 * 24.57 *: direct output to the mc ko pin is not guaranteed. 8.5.3 xin source master clock (xin, xout) ? supply xin with clocks all the time to be used in the following applications. 1) clock source when the pll is unlocked 2) pll lock-in support 3) calculation of the s/pdif input data sampling frequency ? 24.576mhz clock always has to supply to xin. ? normally, the oscillation amplifier automatically stops while the pll is locked, but operation that always operates regardless of the pll status can also be se t. this is set with the ampopr register. the ampopr register must be set before s/pdif input, or the setting must be completed while the pll is unlocked. ? for fixing a system clock to a xin clock, pll is changed into an unlocking state. the admode register always sets pll as an unlocking state. ? the output clock frequency at the time of xin source is set up with the xoutck register. table 8.3: list of output clock frequencies output pin name when pll is unlocked, xin source clock (xin input clock) when pll is locked, pll source clock (internal vco clock) 24.576 mhz 512fs master clock mcko 24.576 mhz 512fs 256fs 128fs bit clock bcko 6.144 mhz 3.072 mhz 64fs l/r clock lrcko 96 khz 48 khz fs
LC89091JA no.a2172-12/30 8.5.4 output clock switching (mcko, bcko, lrcko) ? the clock source of pll clock or xin clock is switched automatically according to the pll locked or unlocked status. ? the output clock switches 2.7ms after the change of pll status. figure 8.5: timing chart of output clock switching 8.5.5 calculation of digital input data sampling frequency ? the input data sampling frequency is calculated using the xin clock. ? in the "ampopr=0" mode (initial value) where the oscilla tion amplifier automatically stops according to the lock status of the pll, the input data sampling frequency is calculated during the err error period and completed when the oscillation amplifier stops with holding the value. th erefore, the value remains unchanged until the pll becomes unlocked. ? if the oscillation amplifier is in a continuous operatio n mode ("ampopr=1"), calculation is repeated constantly. even if sampling changes within the pll capture range for input data whose channel status sampling information does not change, the calculation results that follow the input data can be read. ? the calculation results can be readout with the microcontroller interface. pll status err (a) : loc k -in stage unlock lock ?? ?? ?? (b) : unlock stage xin clock pll clock mcko bcko lrcko err ?? ?? xin clock pll clock pll status lock unlock ?? 2.7ms errwt registe r 2.7ms mcko bcko lrcko
LC89091JA no.a2172-13/30 8.6 data 8.6.1 reception range of s/pdif input ? the input data reception range is 32khz to 192khz. 8.6.2 s/pdif input/output pins (rxin, mpio, gpo) ? two digital input pins and one through output pin are provided. ? rxin and mpio are ttl input level pins with 3.3v-tolerance voltage. ? mpsel register needs to be set up, using mpio as s/pdif input. ? the demodulation data is selected with dinsel register. ? all the s/pdif input pins ca n receive 32khz to 192khz data. ? gpo is input selector output pin, and output the s/pdif through data. ? the demodulated data and the through output data can be selected separately. ? the gpo pin output data is selected with gposel[1:0] and thrsel register. ? when mpio is no-load at an output setup, don't choose mpio by dinsel or thrsel register. ? in order to stop demodulation processing and to switch to oscillation amplifier operation, the s/pdif input to rxin and mpio is stopped, or pll is always set as an unlocking state by admode register. figure 8.6: s/pdif input circuit example 8.6.3 output data format (datao) ? the datao output data format is set with daform register. ? the initial value of the output format is i 2 s. the data is output synchronized with bckin falling edge. figure 8.7: datao pin data output timing mpio lc89091j a rxin optical 0 to 100 ? gpo 0 to 100 ? optical l -ch r-ch msb lsb msb lsb 24bit 24bit lrcko bcko datao l -ch r-ch msb lsb msb msb lsb 24bit 24bit lrcko bcko datao [ daform=0 ] : i 2 s data output [ daform=1 ] : msb first left-justified data output
LC89091JA no.a2172-14/30 8.6.4 serial audio data input format (sdin) ? the LC89091JA is provided with a serial data input pin of sdin. ? the format of the serial audio data input to sdin and the demodulation data output format must be identical. ? the sdin data to be input must be sync hronization with the bcko and lrcko clocks. ? the data input from the sdin pin is through-output to the datao pin. data format conversion cannot be performed. ? normally, sdin input data is output to datao pin when pll is unlocked. but, with the admode register setting, the sdin input data is output to datao regardle ss of the locked/unlocked status of the pll. ? the sdin pin must be connected to gnd when it is not used. figure 8.8: sdin pin data input timing msb lsb msb lsb sdin msb lsb msb msb lsb sdin l-ch r-ch msb lsb msb lsb 24bit 24bit lrcko bcko datao l-ch r-ch msb lsb msb msb lsb 24bit 24bit lrcko bcko datao [ daform=0 ] : i 2 s data input [ daform=1 ] : msb first left-justified data input
LC89091JA no.a2172-15/30 8.6.5 output data switching (sdin, datao) ? datao outputs demodulation data when the pll is locked, and outputs sdin input data when the pll is unlocked. this output is automatically switched according to the pll locked/unlocked status. ? when sdin input data is selected, sdin in put data must synchronize with clock source. ? datao output switches via a mute period. ? it adjusts by errwt register during the mute period at the time of pll lock-in process. ? it adjusts by datwt register during the mute period at the time of pll unlock process ? with the datmut setting, the datao output data can be also muted forcibly. ? npmode register can be muted the datao output data, when non-pcm data is received. non-pcm data applies to the state of the channel status bit 1. figure 8.9: timing chart of datao output data switching pll status err (a) : loc k -in stage unlock lock ~~ ? ~~ ~~ (b) : unlock stage sdin data muted demodulation data datao err ~~ ? ~~ ? sdin data muted demodulation data datao pll status lock unlock ~~ ? errwt register datwt registe r ~~ ? errsel=0 ~~ ? errsel=0 err err errsel=1 errsel=1
LC89091JA no.a2172-16/30 8.7 error output processing (err) ? the err output can be selected the following outputs by the errsel register. 8.7.1 lock error and data error output ("errsel=0") ? the err pin outputs an error flag when pll lock error or data error occurs. ? the err is output synchronizing with lrcko and can be readout with the microcontroller interface. 8.7.1.1 pll lock error ? the pll gets unlocked for input data that lost bi-phase modulation regularity, or input data for which preambles b, m and w cannot be detected. ? however, even if preambles b, m and w are detected if the timing does not conform to the iec60958, the pll get unlocked and processed. for example, period of preamble b is not every192 frames. ? the err outputs "h" when the pll lock error occurs. ? the err outputs "l" when the data demodulation returns normal and "h" is held for somewhere between 3m to 36ms. ? this holding time is set with the errwt register. table 8.4: err release maintenance period after a pll locks s/pdif input sampling frequency (khz) err release maintenance period after a pll locks (ms) "errwt=0" "errwt=1" 32 18 36 44.1 13 26 48 12 24 88.2 6.5 13 96 6 12 176.4 3.3 6.5 192 3 6 8.7.1.2 input data parity error ? an odd number of errors among parity bits in input data and input parity errors are detected. ? the err outputs "h" when an input parity error occurs. ? when an input parity error occurs, output data is replaced to the data of one frame ago. however, when having received non-pcm data, data does no t replace. in this case, data including an error is output. 8.7.1.3 other errors ? even if err turns to "l", the channel status bits of 24 to 27 (sampling frequency information) are always fetched and the data of the previous block is compared with the cu rrent data. moreover, the input data sampling frequency is calculated from the fs clock extracted from the input data, an d the fs calculated value is compared in the same way as described above. if any difference is detected in these data, err is instantly made "h" and the same processing as for pll lock errors is carried out. in this case, the clock source is switched to xi n and processing is restarted at lock status identification processing. ? in order to support sources with a variable fs (for example, a cd player with a variable pitch function), any change in fs made after err is reset is not reflected on e rr unless such change exceeds the pll capture range. 8.7.2 datao data mute signal output ("errsel=1") ? this mode outputs the state of the audio data outputted from the datao pin. (see ?figure 8.9?) ? a mute processing setup at the time of non-pcm audio data reception ("npmode =1")) is also reflected. table 8.5: datao output state signal output err output datao output conditions l muted h outputted
LC89091JA no.a2172-17/30 8.8 general purpose output (gpo) ? the gpo output can be selected the following outputs by the gposel[1:0] register. 8.8.1 channel status bit 1 output ("gposel[1:0]=00") ? the initial mode outputs bit 1 of the channel status that indicates whether the input bi-phase data is pcm audio data. it is immediately output upon detection of err even during an error output period. table 8.6: channel status bit 1 output gpo output gpo output conditions l audio sample word represents linear pcm samples (bit1=l) h audio sample word used for other purposes (bit 1=h) 8.8.2 s/pdif through-output ("gposel[1:0]=01") ? the data selected by the s/pdif input selector (dinsel register) is output. the output data is selected with the thrsel register. table 8.7: output of s/pdif data gpo output gpo output conditions rxin or mpio input data "gposel[1:0]=01" 8.8.3 microcontroller register output ("gposel[1:0]=10 or 11") ? this mode outputs a serial data that is set by the microcontroller interface. it can be used as a control signal of peripheral circuitry. table 8.8: microcontroller register output gpo output gpo output conditions l "gposel[1:0]=10" h "gposel[1:0]=11" figure 8.10: gposel [1:0] register example of use mpio LC89091JA rxin gpo in 0 in 1 out 157 etc in 0 in 1 out 157 etc hcu04 hcu04
LC89091JA no.a2172-18/30 8.9 multi purpose input/output (mpio) ? mpio can be selected the following input/output by the mpsel register. ? mpio needs a pull-up resistor when set to the output. ? when not using mpio, it uses no connecting (open state). however, don't choose mpio by dinsel or thrsel register. 8.9.1 pre-emphasis flag output ("mpsel=0") ? the initial mode outputs pre-emphasis of the channel status that indicates whether there is 50/15 ? s emphasis parameter for consumer. ? mpio becomes a hi-z output when an emphasis signal is not detected. for this reason, it connects with a pull-up resistor. the example of use is shown below table 8.9: pre-emphasis flag output mpio output mpio output conditions hi-z (h**) no pre-emphasis l 50/15 ? s pre-emphasis **: when mpio connects w ith a pull-up resistor figure 8.11: mpio output example of use (pre-emphasis output) 8.9.1 s/pdif data input ("mpsel=1") ? mpio can be used as s/pdif input terminal by "mpsel=1". ? mpio immediately after power-on is set as an output state. for this reason, be fore input all the s/pdif signals, mpio is set as an input state by mpsel regi ster. if s/pdif signal input (rxin input) before mpsel register setup and pre- emphasis flag is detected, mpio output will short-circuit with peripheral circu itry. therefore, before s/pdif signal input, mpio setup must be complete. LC89091JA mpio dac de - emphasis
LC89091JA no.a2172-19/30 9. microcontroller interface ? the LC89091JA is controlled via i 2 c (fast-mode, 400khz). 9.1 terminal setup (scl, sda) ? the pull-up resistor is connected to scl and sda pins. the resistor should take current and timing into consideration enough. ? if the clock line will not be hi-z state, the pull-up resistor of scl may delete. ? when not using microcontroller, scl and sda make gnd connec tion. in this case, initial value of register is set up. 9.2 data transfer ? i 2 c slave transceiver interface is based on ver2.1 (hs mode un-corresponding). ? at first, input start condition and slave-address, an acknowledge generates, write operation and read operation (input register-address and control-data) is executed. after the command execution, input stop condition. ? sda line state must be constant while scl is "h". state change on sda line is restricted while scl line is "l". if sda data changes while scl line is "h", it will be recognized as start condition or stop condition. figure 9.1: data transfer on i 2 c bus 9.3 start and stop condition ? the start condition is generated by the transition of "h" to "l" on sda line while scl line is "h". ? the stop condition is generated by the transition of "l" to "h" on sda lin e while scl line is "h". figure 9.2: start and stop condition 9.4 acknowledge ? after receiving bits (1 byte) of data, sda line is released, LC89091JA will stabili ze sda line in "l" state. this operation is called "acknowledgement". ? the LC89091JA generates an acknowledgement upon receipt of start condition and slave-address. furthermore, for a write instruction, an acknowledgement is generated whenever receipt of each byte is completed. for a read instruction, succeeded by generation of an acknowledgement, the LC89091JA releases the sda line after outputting data at the designated address, and it monitors the sda line condition. when the microcontroller generates an acknowledgement without sending stop condition, the LC89091JA outputs data at the next address location. when no acknowledgement is generated, the LC89091JA ends data output (not acknowledged). sda scl data line stable: data valid change of data allowed sda scl start condition stop condition s p
LC89091JA no.a2172-20/30 9.5 slave-address ? the slave-address inputs after the start condition. ? the slave-address is configured with th e upper 7-bits. data of the upper 5-bits is device code that is input "00100". the next 2-bits are device address that is input "10". ? when the r/w bit is "1", the read instruction is executed , and when it is "0", the write instruction is executed. figure 9.3: slave-address configuration 9.6 register-address ? after transmitting 1 byte of data containing slave-address, register-address is set up from next byte. figure 9.4: register-address configuration 9.7 control data ? the control data inputs after register-address transmission. ? the control data (d7 to d0) is configured with msb first. figure 9.5: control data configuration 0 010 0 1* 0 *r/w device code device address slave address 0 0 000 a2 a1 a0 register address d7 d6 d5 d4 d3 d2 d1 d 0 control data
LC89091JA no.a2172-21/30 9.8 write operation ? when the r/w bit is "0", the write instruction is executed. ? after start condition input, slave-address (r/w=0 ) and register-address are input one by one. ? after an acknowledge is generated, the write data is taken in by scl ? in front of an acknowledge clock pulse. ? when the slave-address is differ, an acknowledge is not generated, sda line will be in an open state. in this case, it has to input from start conditions (s). figure 9.6: i 2 c data write timing chart (byte write) ? after receipt of 8 bits (1 byte) data , when data (1 byte) transmits further without sending stop conditions after an acknowledge generation, the register-address counter is incremented by one and data is stored in the next address. ? if an address value becomes 08h address, address counter will "rolls over" to 00h address and data is stored from 00h and the previous data will be overwritten. figure 9.7: i 2 c data write timing chart (page write) p s sda slave address register address (n) 0 0 1 0 0 ack 0 0 ack ack ack ack ack data (n) data (n+1) data (n+2) data (n+x) 1 0 a0 a1 a3 0 0 0 r/w d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 a2 scl sda 1 0 0 0 a 3 a 1 a 0 d6 d 5 d4 d3 d 2 d1 d0 d 7 s p start condition slave address ack register address (n) ack control data (n) ack stop condition 0 0 0 0 1 0 0 0 r/w a 2
LC89091JA no.a2172-22/30 9.9 read operation ? when the r/w bit is "1", the read instruction is executed. ? after start condition input, slave-address (r/w=0 ) and register-address are input one by one. ? after an acknowledge is generated, start condition (sr) and sl ave-address (r/w=1) input again. and, after an acknowledge is generated, the data of the register-address specified is output. ? if the microcontroller does not generate an acknowledge but generate the stop condition, the LC89091JA discontinues transmission. figure 9.8: i 2 c data read timing chart (random read) ? if a microcontroller returns an acknowledge after 8 bits (1 byte) data output, the data (1 byte) of the next address will be read continuously. ? if an address value becomes 08h address, the next address will be read from 00h data one by one. ? if a microcontroller does not generate an acknowledge but generate the stop condition, the LC89091JA discontinues transmission. figure 9.9: i 2 c data read timing chart (sequential read) scl sda 1 0 0 0 0 s p start condition slave address ack register address ack stop condition 0 0 0 1 0 0 0 r/w a3 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 sr 1 0 00100 1 slave address ack control data r/w ack a2 sr sda s slave address r/w register address 0 0 1 0 0 ack 0 0 ack ack ack ack p ack data (n) data (n+1) data (n+x) 00100 slave address r/w 1 0 0 a3 a2 a1 a0 10 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 0
LC89091JA no.a2172-23/30 9.10 registers 9.10.1 register map table 9.1: register map setting item r/w adr d7 d6 d5 d4 d3 d2 d1 d0 system r/w 00h "0" mpsel datwt errw t admode ampopr pdmode sysrst clock r/w 01h "0" "0" xoutck prsel1 prsel0 plldiv1 plldiv0 pllacc data r/w 02h npmode errsel gposel1 g posel0 datmut thrsel dinsel daform fs calculation r 03h 0 0 0 errf lg fsc3 fsc2 fsc1 fsc0 channel status r 04h cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 r 05h cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 r 06h cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 r 07h cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 r 08h cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 ? "0" is a reserved bit. always must be set to "0".
LC89091JA no.a2172-24/30 9.10.2 details of registers address: 00h; system setting 00h d7 d6 d5 d4 d3 d2 d1 d0 register name "0" mpsel datwt errw t admode ampopr pdmode sysrst initial value 0 0 0 0 0 0 0 0 setting r r/w r/w r/w r/w r/w r/w r/w sysrst system reset 0: don?t reset (initial value) 1: reset all circuits other than registers pdmode power down mode setting 0: normal operation (initial value) 1: power down mode (clock operation stop) ampopr oscillation amplifier operation setting 0: automatic stopping of oscillation amplifier while pll is locked (initial value) 1: permanent continuous operation admode s/pdif reception refusal mode setting 0: normal operation (initial value) 1: always pll unlock state errwt err wait time setting after pll is locked 0: error is canceled after 3 occurrences of preamble b are counted (initial value) 1: error is canceled after 6 occu rrences of preamble b are counted datwt datao wait time setti ng after pll is unlocked 0: mute is canceled after about 5.4 ms (initial value) 1: mute is canceled after about 342ms mpsel mpio pin input/output setting 0: pre-emphasis flag output (initial value) 1: s/pdif input
LC89091JA no.a2172-25/30 address: 01h; clock setting 01h d7 d6 d5 d4 d3 d2 d1 d0 register name "0" "0" xoutck pr sel1 prsel0 plldiv1 plldiv0 pllacc initial value 0 0 0 0 0 0 0 0 setting r r r/w r/w r/w r/w r/w r/w pllacc pll clock lock frequency setting 0: automatic control (initial value) 1: manual setting plldiv[1:0] pll lock time mcko output setting when pllacc is set to "0" 00: 512fs output: when receiving 32kh z, 44.1khz, 48kh z (initial value) 256fs output: when receiving 64khz, 88.2 khz, 96khz 128fs output: when receiving 128khz, 176.4khz, 192khz 01: 256fs output: when receivi ng 32khz, 44 .1khz, 48khz 256fs output: when receiving 64khz, 88.2 khz, 96khz 128fs output: when receiving 128khz, 176.4khz, 192khz 10: 512fs output: when receivi ng 32khz, 44 .1khz, 48khz 512fs output: when receiving 64khz, 88.2 khz, 96khz 128fs output: when receiving 128khz, 176.4khz, 192khz 11: 256fs output: when receivi ng 32khz, 44 .1khz, 48khz 512fs output: when receiving 64khz, 88.2 khz, 96khz 128fs output: when receiving 128khz, 176.4khz, 192khz prsel[1:0] pll lock time mcko output setting when pllacc is set to "1" 00: 256fs output (initial value) 01: 512fs output 10: 128fs output 11: reserved xoutck xin clock output setting when pll is unlocked 0: mcko=24.576mhz, bcko=6.144mhz, lrcko=96khz (initial value) 1: mcko=24.576mhz, bcko=3.072mhz, lrcko=48khz
LC89091JA no.a2172-26/30 address: 02h; data setting 02h d7 d6 d5 d4 d3 d2 d1 d0 register name npmode err sel gposel1 gposel0 datmut thrsel dinsel daform initial value 0 0 0 0 0 0 0 0 setting r/w r/w r/w r/w r/w r/w r/w r/w daform audio data output format setting 0: i 2 s data output (initial value) 1: 24-bit msb first, left-justified data output dinsel data demodulation input setting 0: rxin (initial value) 1: mpio (when "mpsel=1") thrsel gpo output data setting when "gposel[1:0]=01" 0: rxin (initial value) 1: mpio (when "mpsel=1") datmut datao pin output setting 0: output sdin data while pll is unlocked (initial value) 1: mute, "l" output gposel[1:0] gpo output data setting 00: channel status bit 1 output (initial value) 01: input s/pdif through output 10: "l" output 11: "h" output errsel err pin output setting 0: pll lock error or tr ansfer data parity error output (initial value) 1: datao data mute signal output npmode datao pin output setting when s/pdif non-pcm data is received 0: output (initial value) 1: mute, "l" output ? when mpio is no-load at an output setup, don't choose mpio by dinsel or thrsel register. ? datao is muted when non-pcm data is detected at "npm ode=1". but, due to it is not a data error, err output pll lock state ("l" output).
LC89091JA no.a2172-27/30 address: 03h; input fs calculation value 03h d7 d6 d5 d4 d3 d2 d1 d0 register name 0 0 0 errflg fsc3 fsc2 fsc1 fsc0 setting r r r r r r r r fsc[3:0] input data fs calculation result read 0000: 44.1khz 0001: out of range 0010: 48khz 0011: 32khz 0100: - 0101: - 0110: - 0111: - 1000: 88.2khz 1001: - 1010: 96khz 1011: 64khz 1100: 176.4khz 1101: 128khz 1110: 192khz 1111: - errflg err pin output read (it can be read when "errsel=1") 0: no transfer error while pll is locked 1: transfer error exists or pll is unlocked
LC89091JA no.a2172-28/30 address: 04h to 08h; channel status information (read only) address d7 d6 d5 d4 d3 d2 d1 d0 04h cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 05h cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 06h cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 07h cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 08h cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 table 9.2: channel status register contents adr reg cs bit description adr reg cs bit description 04h cs0 bit0 application 07h cs24 bit24 sampling frequency cs1 bit1 control cs25 bit25 cs2 bit2 cs26 bit26 cs3 bit3 cs27 bit27 cs4 bit4 cs28 bit32 clock accuracy cs5 bit5 cs29 bit33 cs6 bit6 not defined cs30 bit30 not defined cs7 bit7 cs31 bit31 05h cs8 bit8 category code 08h cs32 bit32 bit width cs9 bit9 cs33 bit33 cs10 bit10 cs34 bit34 cs11 bit11 cs35 bit35 cs12 bit12 cs36 bit36 original sampling frequency cs13 bit13 cs37 bit37 cs14 bit14 cs38 bit38 cs15 bit15 cs39 bit39 06h cs16 bit16 source number cs17 bit17 cs18 bit18 cs19 bit19 cs20 bit20 channel number cs21 bit21 cs22 bit22 cs23 bit23 ? for details, check the iec60958 specifications
LC89091JA no.a2172-29/30 10. application circuit example (1) example of microcontroller interface is not used (2) example of microcontroller interface is used element symbol recommended parameter application remarks c0 0.01 ? f to 0.1 ? f power supply de-coupling ceramic capacitor r0 1m ? oscillation amplifier feedback r1 150 ? to 2.2k ? oscillation amplifier current limit c1 1pf to 33pf quarts resonator load ceramic capacitor with np0 characteristics r2 0 ? to 100 ? damping resistor r3 10k ? to 100k ? pull-up resistor r4 100 ? pll loop filter see 8.4 c2 0.1 ? f pll loop filter see 8.4 c3 0.022 ? f pll loop filter see 8.4 figure 10.1: LC89091JA application circuit example a nalog data input / output ssop-16 (225mil) c0 r0 r1 c1 c1 c3 r4 c2 24.576mhz r2 r2 r2 to audio codec r3 to dsp (emphasis flag) (non-pcm flag) (pll error flag) digital data input mcko 9 bcko 10 lrcko 11 datao 12 8 gnd 7 lpf 6mpio 5rxin LC89091JA xin 13 xout 14 sdin 15 vdd 16 4 gpo 3 er r 2 sd a 1 scl a udio codec dsp s/pdif input controlle r r2 r3 c3 r4 c2 mcko 9 bcko 10 lrcko 11 datao 12 8 gnd 7 lpf 6 m pio 5 rxin LC89091JA xin 13 xout 14 sdin 15 vdd 16 4 gpo 3 err 2 sd a 1 scl a udio codec dsp a nalog data input / output ssop- 16 (225mil ) c0 r0 r1 c1 c1 24.576mhz r2 r2 s/pdif output
LC89091JA no.a2172-30/30 ordering information device package shipping (qty / packing) LC89091JA-ah ssop16(225mil) (pb-free / halogen free) 2000 / tape & reel LC89091JA-h ssop16(225mil) (pb-free / halogen free) 90 / fan-fold ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona linjuryor death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale i n any manner.

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