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| this is information on a product in full production. may 2016 docid028798 rev 2 1/149 STM32L432KB stm3l432kc ultra-low-power arm ? cortex ? -m4 32-bit mcu+fpu, 100dmips, up to 256kb flash, 64kb sram, usb fs, analog, audio datasheet - production data features ? ultra-low-power with flexpowercontrol ? 1.71 v to 3.6 v power supply ? -40 c to 85/105/125 c temperature range ? 8 na shutdown mode (2 wakeup pins) ? 28 na standby mode (2 wakeup pins) ? 280 na standby mode with rtc ? 1.0 a stop 2 mode, 1.28 a stop 2 with rtc ? 84 a/mhz run mode ? batch acquisition mode (bam) ? 4 s wakeup from stop mode ? brown out reset (bor) in all modes except shutdown ? interconnect matrix ? core: arm ? 32-bit cortex ? -m4 cpu with fpu, adaptive real-time accelerator (art accelerator?) allowing 0- wait-state execution from flash memory, frequency up to 80 mhz, mpu, 100dmips/1.25dmips/mhz (dhrystone 2.1), and dsp instructions ? performance benchmark ? 1.25 dmips/mhz (drystone 2.1) ? 273.55 coremark ? (3.42 coremark/mhz @ 80 mhz) ? energy benchmark ? 176.7 ulpbench ? score ? clock sources ? 32 khz crystal oscillator for rtc (lse) ? internal 16 mhz factory-trimmed rc (1%) ? internal low-power 32 khz rc (5%) ? internal multispeed 100 khz to 48 mhz oscillator, auto-trimmed by lse (better than 0.25 % accuracy) ? internal 48 mhz wi th clock recovery ? 2 plls for system clock, usb, audio, adc ? rtc with hw calendar, alarms and calibration ? up to 3 capacitive sensing channels ? 11x timers: 1x 16-bit advanced motor-control, 1x 32-bit and 2x 16-bit general purpose, 2x 16- bit basic, 2x low-power 16-bit timers (available in stop mode), 2x watchdogs, systick timer ? up to 26 fast i/os, most 5 v-tolerant ? memories ? up to 256 kb single bank flash, proprietary code readout protection ? 64 kb of sram including 16 kb with hardware parity check ? quad spi memory interface ? rich analog peripherals (independent supply) ? 1 12-bit adc 5 msps, up to 16-bit with hardware oversampling, 200 a/msps ? 2x 12-bit dac, low-power sample and hold ? 1x operational amplifier with built-in pga ? 2x ultra-low-power comparators ? 13x communication interfaces ? usb 2.0 full-speed crystal less solution with lpm and bcd ? 1x sai (serial audio interface) ?2x i2c fm+(1 mbi t/s), smbus/pmbus ? 3x usarts (iso 7816, lin, irda, modem) ? 2x spis (3x spis with the quad spi) ? can (2.0b active) ? swpmi single wire pr otocol master i/f ? irtim (infrared interface) ? 14-channel dma controller ? true random number generator ? crc calculation unit, 96-bit unique id ? development support: serial wire debug (swd), jtag, embedded trace macrocell? ufqfpn32 (5x5) www.st.com
contents STM32L432KB stm3l432kc 2/149 docid028798 rev 2 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 arm ? cortex ? -m4 core with fpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 adaptive real-time memory accelerator (art accelerator?) . . . . . . . . . 13 3.3 memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.5 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.7 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.8 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 16 3.9 power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.9.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.4 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.9.5 reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.10 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.11 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.13 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.14 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.14.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 29 3.14.2 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . 29 3.15 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.15.2 internal voltage reference (vrefint) . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.16 digital to analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.17 comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.18 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 docid028798 rev 2 3/149 STM32L432KB stm3l432kc contents 5 3.19 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.20 random number generator (rng) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.21.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.21.2 general-purpose timers (tim2, tim15, ti m16) . . . . . . . . . . . . . . . . . . . 35 3.21.3 basic timers (tim6 and tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.21.4 low-power timer (lptim1 and lptim2) . . . . . . . . . . . . . . . . . . . . . . . . 35 3.21.5 infrared interface (irtim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21.6 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21.7 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.21.8 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.22 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 37 3.23 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.24 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 39 3.25 low-power universal asynchronous rece iver transmitter (lpuart) . . . . 40 3.26 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.27 serial audio interfaces (sai) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.28 single wire protocol master interface (swpmi) . . . . . . . . . . . . . . . . . . . . 42 3.29 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.30 universal serial bus (usb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.31 clock recovery system (crs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3.32 quad spi memory interface (quadspi) . . . . . . . . . . . . . . . . . . . . . . . . . 44 3.33 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.33.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.33.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 contents STM32L432KB stm3l432kc 4/149 docid028798 rev 2 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 63 6.3.3 embedded reset and power control bloc k characteristics . . . . . . . . . . . 63 6.3.4 embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.5 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.6 wakeup time from low-power modes and voltage scaling transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.3.7 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.8 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 6.3.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.3.10 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.11 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.12 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.3.13 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 6.3.14 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.3.15 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.3.16 analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.3.17 analog-to-digital converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 109 6.3.18 digital-to-analog converter characteristi cs . . . . . . . . . . . . . . . . . . . . . 122 6.3.19 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6.3.20 operational amplifiers characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 127 6.3.21 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.22 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 6.3.23 communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 131 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.1 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 7.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 7.2.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 docid028798 rev 2 5/149 STM32L432KB stm3l432kc contents 5 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 list of tables STM32L432KB stm3l432kc 6/149 docid028798 rev 2 list of tables table 1. stm32l432kx family device features and peripher al counts. . . . . . . . . . . . . . . . . . . . . . . 10 table 2. access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 14 table 3. functionalities depending on the working mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4. stm32l432xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 5. dma implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. internal voltage reference calibrati on values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. i2c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 10. stm32l432xx usart/lpuart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 11. sai implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 13. stm32l432xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 14. alternate function af0 to af7 (for af8 to af15 see table 15 ) . . . . . . . . . . . . . . . . . . . . . 50 table 15. alternate function af8 to af15 (for af0 to af7 see table 14 ) . . . . . . . . . . . . . . . . . . . . . 52 table 16. stm32l432xx memory map and peripheral register boundary addresses . . . . . . . . . . . . 55 table 17. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 18. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 19. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 20. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 21. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 22. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 23. embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 table 24. current consumption in run and lo w-power run modes, code with data processing running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . . 68 table 25. current consumption in run and low-power run modes, code with data processing running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 26. current consumption in run and lo w-power run modes, code with data processing running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 27. typical current consumption in run a nd low-power run modes, with different codes running from flash, art enable (cache on prefetch off) . . . . . . . . . . . . . . . . . . . . . . . 71 table 28. typical current consumption in run a nd low-power run modes, with different codes running from flash, art disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 29. typical current consumption in run a nd low-power run modes, with different codes running from sram1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 30. current consumption in sleep and low-power sleep modes, flash on . . . . . . . . . . . . . . 73 table 31. current consumption in low-power sleep modes, flash in power-down . . . . . . . . . . . . . . 74 table 32. current consumption in stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 33. current consumption in stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 34. current consumption in stop 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 35. current consumption in standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 36. current consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 37. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 38. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 39. regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 40. wakeup time using usart/lpuart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 41. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 42. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 docid028798 rev 2 7/149 STM32L432KB stm3l432kc list of tables 7 table 43. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 44. hsi16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 45. msi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 table 46. hsi48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 47. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 48. pll, pllsai1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 49. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 50. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 51. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 52. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 53. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0 table 54. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 55. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 56. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 57. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 58. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 59. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 60. analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 61. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 62. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 63. adc accuracy - limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 64. adc accuracy - limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 65. adc accuracy - limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 66. adc accuracy - limited test conditions 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 67. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 68. dac accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 69. comp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 table 70. opamp characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 table 71. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 72. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 table 73. iwdg min/max timeout period at 32 khz (lsi). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 74. wwdg min/max timeout value at 80 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 75. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 table 76. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 table 77. quad spi characteristics in sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 table 78. quadspi characteristics in ddr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 table 79. sai characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 table 80. usb electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 table 81. swpmi electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 table 82. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 table 83. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 table 84. stm32l432xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 table 85. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 list of figures STM32L432KB stm3l432kc 8/149 docid028798 rev 2 list of figures figure 1. stm32l432xx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 2. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4. stm32l432kx ufqfpn32 pinout (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 5. stm32l432xx memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 6. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 7. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 8. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 9. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 10. vrefint versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 11. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 12. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 13. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 14. hsi16 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 figure 15. typical current consumption versus msi frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 16. hsi48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 figure 17. i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 18. i/o ac characteristics definition (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 19. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 20. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 figure 21. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 22. 12-bit buffered / non-buffered dac. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 figure 23. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 figure 24. spi timing diagram - slave mode and cpha = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 figure 25. spi timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 35 figure 26. quad spi timing diagram - sdr mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 27. quad spi timing diagram - ddr mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 28. sai master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 29. sai slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 figure 30. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 figure 31. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 figure 32. ufqfpn32 marking (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 docid028798 rev 2 9/149 STM32L432KB stm3l432kc introduction 45 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the stm32l432xx microcontrollers. this document should be read in conjun ction with the stm32l4x2 reference manual (rm0393). the reference manual is available from the stmicroelectronics website www.st.com . for information on the arm ? cortex ? -m4 core, please refer to the cortex ? -m4 technical reference manual, available from the www.arm.com website. description STM32L432KB stm3l432kc 10/149 docid028798 rev 2 2 description the stm32l432xx devices are the ultra-low- power microcontrollers based on the high- performance arm ? cortex ? -m4 32-bit risc core operating at a frequency of up to 80 mhz. the cortex-m4 core features a floating point un it (fpu) single precision which supports all arm single-precision data-processing instructions and data types. it also implements a full set of dsp instructions and a memory protec tion unit (mpu) which enhances application security. the stm32l432xx devices embed high-speed memories (flash memory up to 256 kbyte, 64 kbyte of sram), a quad spi flash memories interface and an extensive range of enhanced i/os and peripherals connected to two apb buses, two ahb buses and a 32-bit multi-ahb bus matrix. the stm32l432xx devices embed several pr otection mechanisms for embedded flash memory and sram: readout protection, writ e protection, proprietary code readout protection and firewall. the devices offer a fast 12-bit adc (5 msps), two comparators, one operational amplifier, two dac channels, a low-power rtc, one gene ral-purpose 32-bit timer, one 16-bit pwm timer dedicated to motor control, four genera l-purpose 16-bit timers, and two 16-bit low- power timers. in addition, up to 3 capacitive sensing channels are available. they also feature standard and advanced communication interfaces. ? two i2cs ? two spis ? two usarts and one low-power uart. ? one sai (serial audio interfaces) ? one can ? one usb full-speed device crystal less ? one swpmi (single wire protocol master interface) the stm32l432xx operates in the -40 to +85 c (+105 c junction), -40 to +105 c (+125 c junction) and -40 to +125 c (+130 c junction) temperature ranges from a 1.71 to 3.6 v power supply. a comprehensive set of powe r-saving modes allows the design of low- power applications. some independent power supplies are supported: analog independent supply input for adc, dac, opamps and comparators . the stm32l432xx family offers a single 32-pin package. table 1. stm32l432kx family device features and peripheral counts peripheral stm32l432kx flash memory 256kb sram 64kb quad spi yes docid028798 rev 2 11/149 STM32L432KB stm3l432kc description 45 timers advanced control 1 (16-bit) general purpose 2 (16-bit) 1 (32-bit) basic 2 (16-bit) low -power 2 (16-bit) systick timer 1 watchdog timers (independent, window) 2 comm. interfaces spi 2 i 2 c2 usart lpuart 2 1 sai 1 can 1 usb fs yes (1) swpmi yes rtc yes tamper pins 1 random generator yes gpios wakeup pins 26 2 capacitive sensing number of channels 3 12-bit adcs number of channels 1 10 12-bit dac channels 2 analog comparator 2 operational amplifiers 1 max. cpu frequency 80 mhz operating voltage 1.71 to 3.6 v operating temperature ambient operating temperature: -40 to 85 c / - 40 to 105 c / -40 to 125 c junction temperature: -40 to 105 c / -40 to 125 c / -40 to 130 c packages ufqfpn32 1. there is no vddusb pin. v ddusb is connected internally at v dd . to be functional, v dd must be equal to 3.3 v (+/- 10%). table 1. stm32l432kx family device features and peripheral counts (continued) peripheral stm32l432kx description STM32L432KB stm3l432kc 12/149 docid028798 rev 2 figure 1. stm32l432xx block diagram note: af: alternate function on i/o pins. 0 6 y 9 ) o d v k x s w r . % 8 6 % ) 6 * 3 , 2 3 2 5 7 $ $ + % $ 3 % 3 $ > @ $ 3 % 0 + ] $ 3 % 0 + ] 2 8 7 , 7 ) : : ' * 2 6 & b , 1 2 6 & b 2 8 7 - 7 $ * 6 : $ 5 0 & r u w h [ 0 0 + ] ) 3 8 1 9 , & ( 7 0 0 3 8 ' 0 $ $ 5 7 $ & & ( / & $ & + ( 5 1 * # 9 ' ' $ % 2 5 6 x s s o \ v x s h u y l v l r q 3 9 ' 3 9 0 , q w u h v h w ; 7 $ / n + ] 0 $ 1 $ * 7 5 7 & ) & / . 6 w d q g e \ l q w h u i d f h , : ' * # 9 % $ 7 # 9 ' ' # 9 ' ' $ : 8 5 h v h w f o r f n f r q w u r o 3 & / . [ 9 r o w d j h u h j x o d w r u w r 9 9 ' ' 3 r z h u p d q d j h p h q w # 9 ' ' 5 7 & b 7 $ 0 3 [ % d f n x s u h j l v w h u $ + % e x v p d w u l [ ' $ & ' $ & 7 , 0 7 , 0 7 , 0 ' % 8 6 6 5 $ 0 . % $ 3 % 0 + ] p d [ 6 5 $ 0 . % , % 8 6 6 % 8 6 ' 0 $ 3 % > @ 3 % > @ 3 & > @ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 + 2 8 7 e e e f k d q q h o v ( 7 5 d v $ ) $ + % $ 3 % + & / . [ h [ w h u q d o d q d o r j l q s x w v 8 6 $ 5 7 0 % s v 7 h p s h u d w x u h v h q v r u # 9 ' ' $ 7 r x f k v h q v l q j f r q w u r o o h u * u r x s r i f k d q q h o v p d [ d v $ ) 5 & + 6 , 5 & / 6 , 3 / / 0 6 , 4 x d g 6 3 , p h p r u \ l q w h u i d f h ' > @ & / . & 6 # 9 ' ' 8 6 % & 2 0 3 , 1 3 , 1 0 2 8 7 & 2 0 3 , 1 3 , 1 0 2 8 7 # 9 ' ' $ ) , ) 2 3 + < $ + % 0 + ] & 5 & $ 3 % 0 + ] $ + % 0 + ] ) , 5 ( : $ / / # 9 ' ' ' 3 ' 0 9 ' ' w r 9 9 6 6 7 5 $ & ( & / . 7 5 $ & ( ' > @ 1 - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 ' 2 6 : ' - 7 ' 2 , 7 ) $ ' & 1 2 ( + 6 , / 3 7 , 0 , 1 2 8 7 ( 7 5 d v $ ) / 3 7 , 0 , 1 , 1 2 8 7 ( 7 5 d v $ ) 6 : 3 0 , , 2 5 ; 7 ; 6 8 6 3 ( 1 ' d v $ ) / 3 8 $ 5 7 5 ; 7 ; & 7 6 5 7 6 d v $ ) 9 2 8 7 9 , 1 0 9 , 1 3 2 s $ p s # 9 ' ' $ ) , ) 2 7 ; 5 ; d v $ ) e [ & $ 1 6 & / 6 ' $ 6 0 % $ d v $ ) , & 6 0 % 8 6 , & 6 0 % 8 6 6 & / 6 ' $ 6 0 % $ d v $ ) 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 3 , 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) v p f d u g , u ' $ & 5 6 & 5 6 b 6 < 1 & 9 ' ' $ 9 6 6 $ 9 ' ' 9 6 6 1 5 6 7 3 + > @ ( ; 7 , 7 : . 8 3 $ ) 7 , 0 3 : 0 f r p s o f k d q q h o v 7 , 0 b & + > @ 1 f k d q q h o v 7 , 0 b & + > @ ( 7 5 % . , 1 % . , 1 d v $ ) e 7 , 0 f k d q q h o v f r p s o f k d q q h o % . , 1 d v $ ) e 7 , 0 e f k d q q h o f r p s o f k d q q h o % . , 1 d v $ ) 8 6 $ 5 7 5 ; 7 ; & . & 7 6 5 7 6 d v $ ) v p f d u g , u ' $ 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 6 $ , 0 & / . b $ 6 ' b $ ) 6 b $ 6 & . b $ ( ; 7 & / . 0 & / . b % 6 ' b % ) 6 b % 6 & . b % d v $ ) docid028798 rev 2 13/149 STM32L432KB stm3l432kc functional overview 45 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu the arm ? cortex ? -m4 with fpu processor is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 with fpu 32-bit risc processor features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the stm32l432xx family is compatible with all arm tools and software. figure 1 shows the general block diagram of the stm32l432xx family devices. 3.2 adaptive real-time memory accelerator (art accelerator?) the art accelerator? is a memory accelerator which is optimized for stm32 industry- standard arm ? cortex ? -m4 processors. it balances the in herent performance advantage of the arm ? cortex ? -m4 over flash memory technologies, which normally requires the processor to wait for the flash memory at higher frequencies. to release the processor near 100 dmips performance at 80mhz, the accelerator implements an instruction prefetch queue and branch cache, which increases program execution speed from the 64-bit flash memory. based on coremark benchmark, the performance achieved thanks to the art accele rator is equivalent to 0 wait state program execution from flash memory at a cpu frequency up to 80 mhz. 3.3 memory protection unit the memory protection unit (mpu) is used to manage the cpu accesses to memory to prevent one task to accidentally corrupt the memory or resources used by any other active task. this memory area is organized into up to 8 protected areas that can in turn be divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the mpu is especially helpful for applications wh ere some critical or ce rtified code has to be protected against the misbehavior of other ta sks. it is usually managed by an rtos (real- time operating system). if a prog ram accesses a memory location that is prohibited by the mpu, the rtos can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. functional overview STM32L432KB stm3l432kc 14/149 docid028798 rev 2 3.4 embedded flash memory stm32l432xx devices feature up to 256 kbyte of embedded flash memory available for storing programs and data in single bank ar chitecture. the flash memory contains 128 pages of 2 kbyte. flexible protections can be configured thanks to option bytes: ? readout protection (rdp) to protect the wh ole memory. three levels are available: ? level 0: no readout protection ? level 1: memory readout protection: th e flash memory cannot be read from or written to if either debug features are co nnected, boot in ram or bootloader is selected ? level 2: chip readout protection: debug features (cortex-m4 jtag and serial wire), boot in ram and bootloader sele ction are disabled (jtag fuse). this selection is irreversible. ? write protection (wrp): the protected ar ea is protected against erasing and programming. two areas can be selected, with 2-kbyte granularity. ? proprietary code readout protection (pcro p): a part of the flash memory can be protected against read and write from third pa rties. the protected area is execute-only: it can only be reached by the stm32 cpu, as an instruction co de, while all other accesses (dma, debug and cpu data read, wr ite and erase) are strictly prohibited. the pcrop area granularity is 64-bit wi de. an additional option bit (pcrop_rdp) allows to select if the pcrop area is erased or not when the rdp protection is changed from level 1 to level 0. table 2. access status versus readout protection level and execution modes area protection level user execution debug, boot from ram or boot from system memory (loader) read write erase read write erase main memory 1 yes yes yes no no no 2 yes yes yes n/a n/a n/a system memory 1 yes no no yes no no 2 yes no no n/a n/a n/a option bytes 1 yes yes yes yes yes yes 2 yes no no n/a n/a n/a backup registers 1yesyesn/a (1) 1. erased when rdp change from level 1 to level 0. no no n/a (1) 2 yes yes n/a n/a n/a n/a sram2 1 yes yes yes (1) no no no (1) 2 yes yes yes n/a n/a n/a docid028798 rev 2 15/149 STM32L432KB stm3l432kc functional overview 45 the whole non-volatile memory embeds the error correction code (ecc) feature supporting: ? single error detection and correction ? double error detection. ? the address of the ecc fail can be read in the ecc register 3.5 embedded sram stm32l432xx devices feature 64 kbyte of embedded sram. this sram is split into two blocks: ? 48 kbyte mapped at address 0x2000 0000 (sram1) ? 16 kbyte located at address 0x1000 0000 with hardware parity check (sram2). this memory is also mapped at address 0x2000 c000, offering a contiguous address space with the sram1 (16 kbyte aliased by bit band) this block is accessed through the icode/dcode buses for maximum performance. these 16 kbyte sram can also be retained in standby mode. the sram2 can be write-protec ted with 1 kbyte granularity. the memory can be accessed in read/writ e at cpu clock speed with 0 wait states. 3.6 firewall the device embeds a firewall which protects code sensitive and secure data from any access performed by a code executed outside of the protected areas. each illegal access generates a reset which kills immediat ely the detected intrusion. the firewall main features are the following: ? three segments can be protected and de fined thanks to the firewall registers: ? code segment (located in flash or sram 1 if defined as ex ecutable protected area) ? non-volatile data segment (located in flash) ? volatile data segment (located in sram1) ? the start address and the length of each segments are configurable: ? code segment: up to 1024 kbyte with granularity of 256 bytes ? non-volatile data segment: up to 1024 kbyte with granularity of 256 bytes ? volatile data segment: up to 48 kbyte with a granularity of 64 bytes ? specific mechanism implemented to open th e firewall to get access to the protected areas (call gate entry sequence) ? volatile data segment can be shared or not with the non-protected code ? volatile data segment can be executed or not depending on the firewall configuration the flash readout protection must be set to le vel 2 in order to reach the expected level of protection. functional overview STM32L432KB stm3l432kc 16/149 docid028798 rev 2 3.7 boot modes at startup, boot0 pin or nswboot0 option bit, and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram boot0 value may come from the ph3-boot0 pin or from an option bit depending on the value of a user option bit to free the gpio pad if needed. a flash empty check mechanism is implemented to force the boot from system flash if the first flash memory location is not programmed and if the boot selection is configured to boot from main flash. the boot loader is located in system memory. it is used to reprogram the flash memory by using usart, i2c, spi and usb fs in de vice mode through dfu (device firmware upgrade). 3.8 cyclic redundancy che ck calculation unit (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 3.9 power supply management 3.9.1 power supply schemes ? v dd = 1.71 to 3.6 v: external power supply for i/os (v ddio1 ), the internal regulator and the system analog such as reset, power mana gement and internal clocks. it is provided externally through v dd pins. ? v dda = 1.62 v (adcs/comps) / 1.8 (dacs/opamp) to 3.6 v: external analog power supply for adcs, dacs, opamp, comparators and voltage reference buffer. the v dda voltage level is independent from the v dd voltage. note: when the functions supplied by v dda or v ddusb are not used, these supplies should preferably be shorted to v dd . note: if these supplies are tied to ground, the i/os supplied by these power supplies are not 5 v tolerant (refer to table 17: voltage characteristics ). note: v ddiox is the i/os general purpos e digital functions supply. v ddiox represents v ddio1 , with v ddio1 = v dd . docid028798 rev 2 17/149 STM32L432KB stm3l432kc functional overview 45 figure 2. power supply overview 3.9.2 power supply supervisor the device has an integrated ultra-low-power brown-out reset (bor) active in all modes except shutdown and ensuring proper operation after power-on and during power down. the device remains in reset mode when the monitored supply voltage v dd is below a specified threshold, without the need for an external reset circuit. the lowest bor level is 1.71 v at power on, and other higher thresholds can be selected through option bytes.the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and co mpares it to the vpvd threshold. an interrupt can be generated when v dd drops below the vpvd th reshold and/or when v dd is higher than the vpvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. in addition, the devices embed a peripher al voltage monitor which compares the independent supply voltage v dda with a fixed threshold in order to ensure that the peripheral is in its functional supply range. 0 6 y 9 9 ' ' $ g r p d l q % d f n x s g r p d l q [ ' $ f r q y h u w h u v [ $ ' f r q y h u w h u 6 w d q g e \ f l u f x l w u \ : d n h x s o r j l f , : ' * 9 r o w d j h u h j x o d w r u & r u h 6 5 $ 0 6 5 $ 0 ' l j l w d o s h u l s k h u d o v / r z y r o w d j h g h w h f w r u / 6 ( f u \ v w d o . r v f % . 3 u h j l v w h u v 5 & & % ' & 5 u h j l v w h u 5 7 & [ f r p s d u d w r u v [ r s h u d w l r q d o d p s o l i l h u , 2 u l q j 9 & 2 5 ( g r p d l q 7 h p s v h q v r u 5 h v h w e o r f n [ 3 / / + 6 , 0 6 , + 6 , ) o d v k p h p r u \ 9 ' ' , 2 9 ' ' $ 9 6 6 $ 9 ' ' g r p d l q 9 & 2 5 ( 9 6 6 9 ' ' functional overview STM32L432KB stm3l432kc 18/149 docid028798 rev 2 3.9.3 voltage regulator two embedded linear voltage regulators supply most of the digital circuitries: the main regulator (mr) and the low-power regulator (lpr). ? the mr is used in the run and sleep modes and in the stop 0 mode. ? the lpr is used in low-power run, low-power sleep, stop 1 and stop 2 modes. it is also used to supply the 16 kbyte sram2 in standby with ram2 retention. ? both regulators are in power-down in standby and shutdown modes: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. the ultralow-power stm32l432xx supports dynam ic voltage scaling to optimize its power consumption in run mode. the voltage from the main regulator that supplies the logic (vcore) can be adjusted according to the system?s maximum operating frequency. there are two power consumption ranges: ? range 1 with the cpu running at up to 80 mhz. ? range 2 with a maximum cpu frequency of 26 mhz. all peripheral clocks are also limited to 26 mhz. the vcore can be supplied by the low-power r egulator, the main regulator being switched off. the system is then in low-power run mode. ? low-power run mode with the cpu running at up to 2 mhz. peripherals with independent clock can be clocked by hsi16. 3.9.4 low-power modes the ultra-low-power stm32l432xx supports seven low-power modes to achieve the best compromise between low-power consumption, short startup time, available peripherals and available wakeup sources: by default, the microcontroller is in run mode af ter a system or a power reset. it is up to the user to select one of the low-power modes described below: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? low-power run mode this mode is achieved with vcore supplied by the low-power regu lator to minimize the regulator's operating current. the code ca n be executed from sram or from flash, docid028798 rev 2 19/149 STM32L432KB stm3l432kc functional overview 45 and the cpu frequency is limited to 2 mhz. the peripherals with independent clock can be clocked by hsi16. ? low-power sleep mode this mode is entered from the low-power run mode. only the cpu clock is stopped. when wakeup is triggered by an event or an interrupt, the system reverts to the low- power run mode. ? stop 0, stop 1 and stop 2 modes stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the vcore domain are stopped, the pll, the msi rc and the hsi16 rc are disabled. the lse or lsi is still running. the rtc can remain active (stop mode with rtc, stop mode without rtc). some peripherals with wakeup capability can enable the hsi16 rc during stop mode to detect their wakeup condition. three stop modes are available: stop 0, stop 1 and stop 2 modes. in stop 2 mode, most of the vcore domain is put in a lower leakage mode. stop 1 offers the largest number of active peripherals and wakeup sources, a smaller wakeup time but a higher consumption than stop 2. in stop 0 mode, the main regulator remains on, allowing a very fast wakeup time but with much higher consumption. the system clock when exiting from stop 0, stop1 or stop2 modes can be either msi up to 48 mhz or hsi16, depending on software configuration. ? standby mode the standby mode is used to achieve t he lowest power consumption with bor. the internal regulator is switched off so that the vcore domain is powered off. the pll, the msi rc and the hsi16 rc are also switched off. the rtc can remain active (standby mo de with rtc, standby mode without rtc). the brown-out reset (bor) always remains active in standby mode. the state of each i/o during standby mode can be selected by software: i/o with internal pull-up, internal pull-down or floating. after entering standby mode, sram1 and register contents are lost except for registers in the backup domain and standby circuitry. optionally, sram2 can be retained in functional overview STM32L432KB stm3l432kc 20/149 docid028798 rev 2 standby mode, supplied by the low-power regulator (standby with ram2 retention mode). the device exits standby mode when an external reset (nrst pin), an iwdg reset, wkup pin event (configurable rising or fallin g edge), or an rtc event occurs (alarm, periodic wakeup, timestamp, tamper) or a failure is detected on lse (css on lse). the system clock after wakeup is msi up to 8 mhz. ? shutdown mode the shutdown mode allows to achieve the lowest power consumption. the internal regulator is switched off so that the vc ore domain is powered off. the pll, the hsi16, the msi and the lsi osc illators are also switched off. the rtc can remain active (shutdown mode with rtc, shutdown mode without rtc). the bor is not available in shutdown mode . no power voltage monitoring is possible in this mode, therefore the switch to backup domain is not supported. sram1, sram2 and register contents are lost except for registers in the backup domain. the device exits shutdown mode when an external reset (nrst pin), a wkup pin event (configurable rising or falling edge), or an rtc ev ent occurs (alarm, periodic wakeup, timestamp, tamper). the system clock after wakeup is msi at 4 mhz. docid028798 rev 2 21/149 STM32L432KB stm3l432kc functional overview 45 table 3. functionalities depending on the working mode (1) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown - wakeup capability - wakeup capability - wakeup capability - wakeup capability cpu y - y - - -- -- -- - flash memory (up to 256 kb) o (2) o (2) o (2) o (2) - -- -- -- - sram1 (48 kb) y y (3) yy (3) y -y -- -- - sram2 (16 kb) y y (3) yy (3) y -y -o (4) -- - quad spi oooo- -- -- -- - backup registers y y y y y -y -y -y - brown-out reset (bor) yyyyy yy yy y- - programmable voltage detector (pvd) ooooo oo o- -- - peripheral voltage monitor (pvmx; x=1,3,4) ooooo oo o- -- - dma o o o o - -- -- -- - high speed internal (hsi16) oooo (5) - (5) -- -- - oscillator rc48 o o - - - -- -- -- - high speed external (hse) oooo- -- -- -- - low speed internal (lsi) ooooo -o -o -- - low speed external (lse) ooooo -o -o -o - multi-speed internal (msi) oooo- -- -- -- - clock security system (css) oooo- -- -- -- - clock security system on lse ooooo oo oo o- - rtc / auto wakeup o o o o o oo oo oo o number of rtc tamper pins 11111 o1 o1 o1 o usb fs o (8) o (8) --- o- -- -- - functional overview STM32L432KB stm3l432kc 22/149 docid028798 rev 2 usartx (x=1,2) o o o o o (6) o (6) - -- -- - low-power uart (lpuart) ooooo (6) o (6) o (6) o (6) - -- - i2cx (x=1) o o o o o (7) o (7) - -- -- - i2c3 ooooo (7) o (7) o (7) o (7) - -- - spix (x=1,3) o o o o - -- -- -- - can o o o o - -- -- -- - swpmi1 o o o o - o- -- -- - saix (x=1) o o o o - -- -- -- - adcx (x=1) o o o o - -- -- -- - dacx (x=1,2) o o o o o -- -- -- - opampx (x=1) o o o o o -- -- -- - compx (x=1,2) o o o o o oo o- -- - temperature sensor o o o o - -- -- -- - timers (timx) o o o o - -- -- -- - low-power timer 1 (lptim1) ooooo oo o- -- - low-power timer 2 (lptim2) ooooo o- -- -- - independent watchdog (iwdg) ooooo oo oo o- - window watchdog (wwdg) oooo- -- -- -- - systick timer o o o o - -- -- -- - touch sensing controller (tsc) oooo- -- -- -- - random number generator (rng) o (8) o (8) --- -- -- -- - crc calculation unit oooo- -- -- -- - gpios o o o o o oo o (9) 2 pins (10) (11) 2 pins (10) table 3. functionalities depending on the working mode (1) (continued) peripheral run sleep low- power run low- power sleep stop 0/1 stop 2 standby shutdown - wakeup capability - wakeup capability - wakeup capability - wakeup capability docid028798 rev 2 23/149 STM32L432KB stm3l432kc functional overview 45 3.9.5 reset mode in order to improve the consumption under reset, the i/os state under and after reset is ?analog state? (the i/o schmitt trigger is disabl e). in addition, the internal reset pull-up is deactivated when the reset source is internal. 3.10 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. depending on peripherals, these interconnecti ons can operate in run, sleep, low-power run and sleep, stop 0, stop 1 and stop 2 modes. 1. legend: y = yes (enable). o = optional (disable by default. can be enabled by software). - = not available. 2. the flash can be configured in power-down mode. by default, it is not in power-down mode. 3. the sram clock can be gated on or off. 4. sram2 content is preserved when the bit rrs is set in pwr_cr3 register. 5. some peripherals with wakeup from stop capability can request hsi16 to be enabled. in this case, hsi16 is woken up by the peripheral, and onl y feeds the peripheral which request ed it. hsi16 is automatically put off when the peripheral does not need it anymore. 6. uart and lpuart reception is functional in stop mode, and generates a wakeup interrupt on start, address match or received frame event. 7. i2c address detection is functional in stop mode, and generates a wakeup interrupt in case of address match. 8. voltage scaling range 1 only. 9. i/os can be configured with internal pul l-up, pull-down or floating in standby mode. 10. the i/os with wakeup from standby/shutdown capability are: pa0, pa2. 11. i/os can be configured with internal pull-up, pull-down or floating in shut down mode but the configuration is lost when exiting the shutdown mode. table 4. stm32l432xx peripherals interconnect matrix interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2 timx timx timers synchronization or chaining y y y y - - adcx dacx conversion triggers y y y y - - dma memory to memory transfer trigger y y y y - - compx comparator output blanking y y y y - - tim15/tim16 irtim infrared inte rface output generation y y y y - - functional overview STM32L432KB stm3l432kc 24/149 docid028798 rev 2 compx tim1 tim2 timer input channel, trigger, break from analog signals comparison yyyy - - lptimerx low-power timer triggered by analog signals comparison yyyyy y (1) adcx tim1 timer triggered by analog watchdog y y y y - - rtc tim16 timer input channel from rtc events y y y y - - lptimerx low-power timer triggered by rtc alarms or tampers yyyyy y (1) all clocks sources (internal and external) tim2 tim15, 16 clock source used as input channel for rc measurement and trimming yyyy - - usb tim2 timer triggered by usb sof y y - - - - css cpu (hard fault) ram (parity error) flash memory (ecc error) compx pvd tim1 tim15,16 timer break y y y y - - gpio timx external trigger y y y y - - lptimerx external trigger y y y y y y (1) adcx dacx conversion external trigger y y y y - - 1. lptim1 only. table 4. stm32l432xx peripherals interconnect matrix (continued) interconnect source interconnect destination interconnect action run sleep low-power run low-power sleep stop 0 / stop 1 stop 2 docid028798 rev 2 25/149 STM32L432KB stm3l432kc functional overview 45 3.11 clocks and startup the clock controller (see figure 3 ) distributes the clocks coming from different oscillators to the core and the peripherals. it also manages clock gating for low-power modes and ensures clock robust ness. it features: ? clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. ? system clock source: four different clock sources can be used to drive the master clock sysclk: ? high speed external clock (hse) can supply a pll. ? 16 mhz high-speed internal rc oscillator (h si16), trimmable by software, that can supply a pll ? multispeed internal rc oscillator (msi), tr immable by software, able to generate 12 frequencies from 100 khz to 48 mhz. when a 32.768 khz clock source is available in the system (lse), the msi fr equency can be automatically trimmed by hardware to reach better than 0.25% accuracy. in this mode the msi can feed the usb device. the msi can supply a pll. ? system pll which can be fed by hse, hsi16 or msi, with a maximum frequency at 80 mhz. ? rc48 with clock recovery system (hsi48) : internal rc48 mhz clock source can be used to drive the usb or the rng periphera ls. this clock can be output on the mco. ? auxiliary clock source: two ultralow-power clock sources that can be used to drive the real-time clock: ? 32.768 khz low-speed external crystal (lse), supporting four drive capability modes. the lse can also be configured in bypass mode for an external clock. ? 32 khz low-speed internal rc (lsi), also used to drive the independent watchdog. the lsi clock accura cy is 5% accuracy. ? peripheral clock sources: several peripherals (usb, rng, sai, usarts, i2cs, lptimers, adc, swpmi) have their own inde pendent clock whatever the system clock. two plls, each having three independent out puts allowing the highest flexibility, can generate independent clocks for the adc, the usb/rng and the sai. ? startup clock: after reset, the microcontroller restar ts by default with an internal 4 mhz clock (msi). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the master clock is automatically switched to hsi16 and a software interrupt is generated if enabled. lse failure can also be detected and generated an interrupt. ? clock-out capability: ? mco: microcontroller clock output: it outputs one of the internal clocks for external use by the application ? lsco: low speed clock output: it outputs lsi or lse in all low-power modes. functional overview STM32L432KB stm3l432kc 26/149 docid028798 rev 2 several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domains. the ma ximum frequency of the ahb and the apb domains is 80 mhz. docid028798 rev 2 27/149 STM32L432KB stm3l432kc functional overview 45 figure 3. clock tree 0 6 y 9 6 < 6 & / . 0 & 2 / 6 & 2 0 + ] f o r f n w r 8 6 % 5 1 * w r $ ' & w r , : ' * w r 5 7 & w r 3 : 5 + & / . w r $ + % e x v f r u h p h p r u \ d q g ' 0 $ ) & / . & r u w h [ i u h h u x q q l q j f o r f n w r & r u w h [ v \ v w h p w l p h u w r $ 3 % s h u l s k h u d o v w r $ 3 % s h u l s k h u d o v 3 & / . 3 & / . w r 6 $ , / 6 ( + 6 , 6 < 6 & / . w r 8 6 $ 5 7 [ ; w r / 3 8 $ 5 7 w r , & [ [ w r / 3 7 , 0 [ [ 6 $ , b ( ; 7 & / . w r 6 : 3 0 , w r 7 , 0 [ [ 2 6 & b 2 8 7 2 6 & b , 1 0 6 , + 6 , + 6 ( + 6 , / 6 , / 6 ( + 6 ( 6 < 6 & / . + 6 ( 0 6 , + 6 , 0 6 , 6 < 6 & / . > ^ k ^ ??x? l , l?? , w z ^ l u?uxx?? l ? w w z ^ l u?ueu?u ? }? ?? + 6 , 6 < 6 & / . / 6 , / 6 ( + 6 , + 6 , w ? w z ^ l u?ueu?u w r 7 , 0 [ [ ? }? ?? w r 8 6 $ 5 7 / 6 ( + 6 , 6 < 6 & / . l d d ^ / z l , t e? d , , ^ / z d , o}l ? ?}? & . b , 1 : >y>a > ^ / z ?? l , o}l ?}? }v??}o 3 / / 6 $ , & / . 3 / / 8 6 % & / . 3 / / & / . 3 / / 6 $ , & / . 3 / / 8 6 % & / . 3 / / $ ' & & / . + 6 , + 6 , + 6 , 5 & 0 + ] + 6 , & 5 6 3 / / 3 / / 6 $ , s k ) 9 & 2 l w l z l y l w l y l z s k ) 9 & 2 functional overview STM32L432KB stm3l432kc 28/149 docid028798 rev 2 3.12 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. fast i/o toggling can be achieved thanks to their mapping on the ahb2 bus. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.13 direct memory a ccess controller (dma) the device embeds 2 dmas. refer to table 5: dma implementation for the features implementation. direct memory access (dma) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. data can be quickly moved by dma without any cpu actions. this keeps cpu resources free for other operations. the two dma controllers have 14 channels in total, each dedicated to managing memory access requests from one or more peripherals. each has an arbiter for handling the priority between dma requests. the dma supports: ? 14 independently configurable channels (requests) ? each channel is connected to dedicated hardware dma requests, software trigger is also supported on each channel. this configuration is done by software. ? priorities between requests from channels of one dma are software programmable (4 levels consisting of very high, high, medi um, low) or hardware in case of equality (request 1 has priority over request 2, etc.) ? independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. source/destination addresses must be aligned on the data size. ? support for circular buffer management ? 3 event flags (dma half transfer, dma transfer complete and dma transfer error) logically ored together in a single interrupt request for each channel ? memory-to-memory transfer ? peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers ? access to flash, sram, apb and ahb pe ripherals as source and destination ? programmable number of data to be transferred: up to 65536. table 5. dma implementation dma features dma1 dma2 number of regular channels 7 7 docid028798 rev 2 29/149 STM32L432KB stm3l432kc functional overview 45 3.14 interrupts and events 3.14.1 nested vectored inte rrupt controller (nvic) the devices embed a nested vectored interrupt controller able to manage 16 priority levels, and handle up to 61 maskable interrupt channels plus the 16 interrupt lines of the cortex ? - m4. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14.2 extended interrupt/event controller (exti) the extended interrupt/event co ntroller consists of 34 edge det ector lines used to generate interrupt/event requests and wake-up the system from stop mode. each external line can be independently configur ed to select the trigger event (rising edge, fa lling edge, both) and can be masked independently a pending register main tains the status of the interrupt requests. the internal lines are connected to peripherals with wakeup fr om stop mode capability. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 26 gpios can be connected to the 16 external interrupt lines. functional overview STM32L432KB stm3l432kc 30/149 docid028798 rev 2 3.15 analog to digital converter (adc) the device embeds a successive approxima tion analog-to-digital converter with the following features: ? 12-bit native resolution , with built-in calibration ? 5.33 msps maximum conversion rate with full resolution ? down to 18.75 ns sampling time ? increased conversion rate for lower resolution (up to 8.88 msps for 6-bit resolution) ? up to 10 external channels. ? 4 internal channels: internal reference vo ltage, temperature sensor, dac1 and dac2 outputs. ? single-ended and differential mode inputs ? low-power design ? capable of low-current operation at lo w conversion rate (consumption decreases linearly with speed) ? dual clock domain architecture: adc speed independent from cpu frequency ? highly versatile digital interface ? single-shot or continuous/discontinuous sequencer-based scan mode: 2 groups of analog signals conversions can be programmed to differentiate background and high-priority real-time conversions ? adc supports multiple trigger inputs for synchronization with on-chip timers and external signals ? results stored into data register or in ram with dma controller support ? data pre-processing: left/right alignment and per channel offset compensation ? built-in oversampling unit for enhanced snr ? channel-wise programmable sampling time ? three analog watchdog for automatic voltage monitoring, generating interrupts and trigger for selected timers ? hardware assistant to prepare the context of the injected channels to allow fast context switching 3.15.1 temperature sensor the temperature sensor (ts) generates a voltage v ts that varies linearly with temperature. the temperature sensor is internally connec ted to the adc1_in17 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. docid028798 rev 2 31/149 STM32L432KB stm3l432kc functional overview 45 3.15.2 internal voltage reference (v refint ) the internal voltage reference (vrefint) provides a stable (bandgap) voltage output for the adc and comparators. vrefint is inte rnally connected to the adc1_in0 input channel. the precise voltage of vrefint is individually measured for each part by st during production test and stored in the system memory area. it is a ccessible in read-only mode. 3.16 digital to analog converter (dac) two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in inve rting configuration. this digital interface supp orts the following features: ? up to two dac output channels ? 8-bit or 12-bit output mode ? buffer offset calibration (factory and user trimming) ? left or right data alignment in 12-bit mode ? synchronized update capability ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simultaneous conversions ? dma capability for each channel ? external triggers for conversion ? sample and hold low-power mode, with internal or external capacitor the dac channels are triggered through the ti mer update outputs that are also connected to different dma channels. table 6. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75a8 - 0x1fff 75a9 ts_cal2 ts adc raw data acquired at a temperature of 130 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75ca - 0x1fff 75cb table 7. internal voltage reference calibration values calibration value name description memory address vrefint raw data acquired at a temperature of 30 c ( 5 c), v dda = v ref+ = 3.0 v ( 10 mv) 0x1fff 75aa - 0x1fff 75ab functional overview STM32L432KB stm3l432kc 32/149 docid028798 rev 2 3.17 comparators (comp) the stm32l432xx devices embed two rail-to-rail comparators with programmable reference voltage (internal or external), hyster esis and speed (low speed for low-power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output channels ? internal reference voltage or submultiple (1/4, 1/2, 3/4). all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. 3.18 operational amplifier (opamp) the stm32l432xx embeds one operational amplifier with external or internal follower routing and pga capability. the operational amplifier features: ? low input bias current ? low offset voltage ? low-power mode ? rail-to-rail input 3.19 touch sensing controller (tsc) the touch sensing controller provides a simple solution for adding capacitive sensing functionality to any a pplication. capacitive sensing technology is able to detect finger presence near an electrode which is protecte d from direct touch by a dielectric (glass, plastic, ...). the capacitive va riation introduced by the finger (or any conductive object) is measured using a proven implementation base d on a surface charge transfer acquisition principle. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. docid028798 rev 2 33/149 STM32L432KB stm3l432kc functional overview 45 the main features of the touch sensing controller are the following: ? proven and robust surface charge transfer acquisition principle ? supports up to 3 capacitive sensing channels ? up to 3 capacitive sensing channels can be acquired in parallel offering a very good response time ? spread spectrum feature to improve system robustness in noisy environments ? full hardware management of the charge transfer acquisition sequence ? programmable charge transfer frequency ? programmable sampling capacitor i/o pin ? programmable channel i/o pin ? programmable max count value to avoid long acquisition when a channel is faulty ? dedicated end of acquisiti on and max count er ror flags with inte rrupt capability ? one sampling capacitor for up to 3 capaciti ve sensing channels to reduce the system components ? compatible with proximity, touchkey, linear and rotary touch sensor implementation ? designed to operate with stmtouch touch sensing firmware library note: the number of capacitive sensing channels is dependent on the size of the packages and subject to i/ o availability. 3.20 random number generator (rng) all devices embed an rng that delivers 32-bi t random numbers generated by an integrated analog circuit. 3.21 timers and watchdogs the stm32l432xx includes one advanced control timers, up to five general-purpose timers, two basic timers, two low-power timers, two watchdog timers and a systick timer. the table below compares the features of the advanced control, general purpose and basic timers. table 8. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 yes 4 3 general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 functional overview STM32L432KB stm3l432kc 34/149 docid028798 rev 2 3.21.1 advanced-control timer (tim1) the advanced-control timer can each be se en as a three-phase pwm multiplexed on 6 channels. they have complementary pwm outputs with programmable inserted dead- times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose timx timers (described in section 3.21.2 ) using the same architecture, so the advanced-control timer can work together with the timx timers via the time r link feature for synchronization or event chaining. general- purpose tim16 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no table 8. timer feature comparison (continued) timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs docid028798 rev 2 35/149 STM32L432KB stm3l432kc functional overview 45 3.21.2 general-purpose timers (tim2, tim15, tim16) there are up to three synchronizable general-purpose timers embedded in the stm32l432xx (see table 8 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2 it is a full-featured general-purpose timer: tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler. this timer features 4 independent channels for input capture/output compare, pwm or one-pulse mode output. it can work with the other general-purpose timers via the timer link feature for synchronization or event chaining. the counter can be frozen in debug mode. it has independent dma request generation and support quadrature encoder. ? tim15 and 16 they are general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 has 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.21.3 basic timers (tim6 and tim7) the basic timers are mainly used for dac tri gger generation. they can also be used as generic 16-bit timebases. 3.21.4 low-power timer (lptim1 and lptim2) the devices embed two low-power timers. these timers have an independent clock and are running in stop mode if they are clocked by lse, lsi or an external cl ock. they are able to wakeup the system from stop mode. lptim1 is active in stop 0, stop 1 and stop 2 modes. lptim2 is active in stop 0 and stop 1 mode. functional overview STM32L432KB stm3l432kc 36/149 docid028798 rev 2 this low-power timer supports the following features: ? 16-bit up counter with 16-bit autoreload register ? 16-bit compare register ? configurable output: pulse, pwm ? continuous/ one shot mode ? selectable software/ hardware input trigger ? selectable clock source ? internal clock sources: l se, lsi, hsi16 or apb clock ? external clock source over lptim input (working even with no internal clock source running, used by pulse counter application). ? programmable digital glitch filter ? encoder mode (lptim1 only) 3.21.5 infrared interface (irtim) the stm32l432xx includes one infrared interfac e (irtim). it can be used with an infrared led to perform remote contro l functions. it uses tim15 an d tim16 output channels to generate output signal waveforms on ir_out pin. 3.21.6 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 32 khz internal rc (lsi) and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.21.7 system window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.21.8 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source docid028798 rev 2 37/149 STM32L432KB stm3l432kc functional overview 45 3.22 real-time clock (rtc ) and backup registers the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? automatic correction for 28, 29 (leap ye ar), 30, and 31 days of the month. ? two programmable alarms. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal inaccuracy. ? one anti-tamper detection pin with programmable filter. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. ? 17-bit auto-reload wakeup timer (wut) for periodic events with programmable resolution and period. the rtc and the 32 backup registers are supplied through a switch that takes power from the v dd supply. the backup registers are 32-bit registers used to store 128 bytes of user application data when vdd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby or shutdown mode. the rtc clock sources can be: ? a 32.768 khz external crystal (lse) ? an external resonator or oscillator (lse) ? the internal low power rc oscillator (l si, with typical frequency of 32 khz) ? the high-speed external clock (hse) divided by 32. the rtc is functional in all lo w-power modes when it is clocked by the lse. when clocked by the lsi, the rtc is functional in all low-power modes except shutdown mode. all rtc events (alarm, wakeup timer, timestamp or tamper) can generate an interrupt and wakeup the device from the low-power modes. functional overview STM32L432KB stm3l432kc 38/149 docid028798 rev 2 3.23 inter-integrated ci rcuit interface (i2c) the device embeds 2 i2c. refer to table 9: i2c implementation for the features implementation. the i 2 c bus interface handles communications bet ween the microcontroller and the serial i 2 c bus. it co ntrols all i 2 c bus-specific sequencing, protocol, arbitration and timing. the i2c peripheral supports: ? i 2 c-bus specification and user manual re v. 5 compatibility: ? slave and master modes , multimaster capability ? standard-mode (sm), with a bitrate up to 100 kbit/s ? fast-mode (fm), with a bitrate up to 400 kbit/s ? fast-mode plus (fm+), with a bitrate up to 1 mbit/s and 20 ma output drive i/os ? 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses ? programmable setup and hold times ? optional clock stretching ? system management bus (smbus) spec ification rev 2.0 compatibility: ? hardware pec (packet error checking) generation and verification with ack control ? address resolution protocol (arp) support ? smbus alert ? power system management protocol (pmbus tm ) specification rev 1.1 compatibility ? independent clock: a choice of independent clock sources allowing the i2c communication speed to be independent from the pclk reprogramming. refer to figure 3: clock tree . ? wakeup from stop mode on address match ? programmable analog and digital noise filters ? 1-byte buffer with dma capability table 9. i2c implementation i2c features (1) 1. x: supported i2c1 i2c3 standard-mode (up to 100 kbit/s) x x fast-mode (up to 400 kbit/s) x x fast-mode plus with 20ma output drive i/os (up to 1 mbit/s) x x programmable analog and digital noise filters x x smbus/pmbus hardware support x x independent clock x x wakeup from stop 0 / stop 1 mode on address match x x wakeup from stop 2 mode on address match - x docid028798 rev 2 39/149 STM32L432KB stm3l432kc functional overview 45 3.24 universal synchronous/asynch ronous receiver transmitter (usart) the stm32l432xx devices have two embedd ed universal synchronous receiver transmitters (usart1 and usart2). these interfaces provide asynchronous communication, irda sir endec support, multiprocessor communication mode, single-wire half-duplex communication mode and have lin master/slave capability. they pr ovide hardware m anagement of the cts and rts signals, and rs485 driver enable. they are able to communicate at speeds of up to 10mbit/s. usart1 and usart2 also provide smart card mode (iso 7816 compliant) and spi-like communication capability. all usart have a clock domain independent from the cpu clock, allowing the usartx (x=1,2) to wake up the mcu from stop mode using baudrates up to 200 kbaud. the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame all usart interfaces can be served by the dma controller. table 10. stm32l432xx usart/lpuart features usart modes/features (1) 1. x = supported. usart1 usart2 lpuart1 hardware flow control for modem x x x continuous communication using dma x x x multiprocessor communication x x x synchronous mode x x - smartcard mode x x - single-wire half-duplex communication x x x irda sir endec block x x - lin mode x x - dual clock domain x x x wakeup from stop 0 / stop 1 modes x x x wakeup from stop 2 mode - - x receiver timeout interrupt x x - modbus communication x x - auto baud rate detection x (4 modes) - driver enable x x x lpuart/usart data length 7, 8 and 9 bits functional overview STM32L432KB stm3l432kc 40/149 docid028798 rev 2 3.25 low-power universal asynchr onous receiver transmitter (lpuart) the device embeds one low-power uart. the lpuart supports asynchronous serial communication with minimum power consumption. it supports half duplex single wire communication and modem operations (c ts/rts). it allows multiprocessor communication. the lpuart has a clock domain independent from the cpu clock, and can wakeup the system from stop mode using baudrates up to 220 kbaud. the wake up events from stop mode are programmable and can be: ? start bit detection ? any received data frame ? a specific programmed data frame only a 32.768 khz clock (lse) is needed to allow lpuart communication up to 9600 baud. therefore, even in stop mode, the lpuart can wait for an incoming frame while having an extremely low energy consumption. higher speed clock can be used to reach higher baudrates. lpuart interface can be served by the dma controller. docid028798 rev 2 41/149 STM32L432KB stm3l432kc functional overview 45 3.26 serial peripheral interface (spi) two spi interfaces allow commun ication up to 40 mbits/s in master and up to 24 mbits/s slave modes, in half-duplex, full-duplex and simplex modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. the spi interfaces support nss pulse mode, ti mode and hardware crc calculation. all spi interfaces can be served by the dma controller. 3.27 serial audio interfaces (sai) the device embeds 1 sai. refer to table 11: sai implementation for the features implementation. the sai bus interface handles communications between the microcontroller and the serial audio protocol. the sai peripheral supports: ? two independent audio sub-blocks which can be transmitters or receivers with their respective fifo. ? 8-word integrated fifos for each audio sub-block. ? synchronous or asynchronous mode between the audio sub-blocks. ? master or slave configuration inde pendent for both audio sub-blocks. ? clock generator for each audio block to target independent audio frequency sampling when both audio sub-blocks are configured in master mode. ? data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit. ? peripheral with large configurability and flexib ility allowing to target as example the following audio protocol: i2s, lsb or msb-ju stified, pcm/dsp, td m, ac?97 and spdif out. ? up to 16 slots available with configurable size and with th e possibility to select which ones are active in the audio frame. ? number of bits by frame may be configurable. ? frame synchronization active level conf igurable (offset, bit length, level). ? first active bit position in the slot is configurable. ? lsb first or msb first for data transfer. ? mute mode. ? stereo/mono audio frame capability. ? communication clock strobing edge configurable (sck). ? error flags with associated interrupts if enabled respectively. ? overrun and underrun detection. ? anticipated frame synchronization signal detection in slave mode. ? late frame synchronization signal detection in slave mode. ? codec not ready for the ac?97 mode in reception. ? interruption sources when enabled: ?errors. ? fifo requests. ? dma interface with 2 dedicated channels to handle access to the dedicated integrated fifo of each sai audio sub-block. functional overview STM32L432KB stm3l432kc 42/149 docid028798 rev 2 3.28 single wire protocol master interface (swpmi) the single wire protocol master interface (swp mi) is the master interface corresponding to the contactless frontend (clf) defined in the et si ts 102 613 technical specification. the main features are: ? full-duplex communication mode ? automatic swp bus state management (active, suspend, resume) ? configurable bitrate up to 2 mbit/s ? automatic sof, eof and crc handling swpmi can be served by the dma controller. 3.29 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. the can peripheral supports: ? supports can protocol version 2.0 a, b active ? bit rates up to 1 mbit/s table 11. sai implementation sai features support (1) 1. x: supported i2s, lsb or msb-justifie d, pcm/dsp, tdm, ac?97 x mute mode x stereo/mono audio frame capability. x 16 slots x data size configurable: 8-, 10-, 16-, 20-, 24-, 32-bit x fifo size x (8 word) spdif x docid028798 rev 2 43/149 STM32L432KB stm3l432kc functional overview 45 ? transmission ? three transmit mailboxes ? configurable transmit priority ? reception ? two receive fifos with three stages ? 14 scalable filter banks ? identifier list feature ? configurable fifo overrun ? time-triggered communication option ? disable automatic retransmission mode ? 16-bit free running timer ? time stamp sent in last two data bytes ? management ? maskable interrupts ? software-efficient mailbox mapping at a unique address space 3.30 universal serial bus (usb) the stm32l432xx devices embed a full-speed usb device peripheral compliant with the usb specification version 2.0. the intern al usb phy supports usb fs signaling, embedded dp pull-up and also battery charging detection according to battery charging specification revision 1.2. the usb interface implements a full-speed (12 mbit/s) function interface with added support for usb 2.0 link power management. it has software- configurable endpoint setting with packet memory up-to 1 kb and suspend/resume support. it requires a precise 48 mhz clock which can be generated from the internal main pll or by the internal 48 mhz oscillator in automatic trimming mode. the synchronization for this oscillator can be taken from the usb data str eam itself (sof signa lization) which allows crystal less operation. 3.31 clock recover y system (crs) the stm32l432xx devices embed a special block which allows automatic trimming of the internal 48 mhz oscillator to guarantee its optima l accuracy over the whole device operational range. this automatic trimming is based on the external synchronization signal, which could be either derived fr om usb sof signalization, fr om lse oscillator, from an external signal on crs_sync pin or generated by user software. for faster lock-in during startup it is also possible to combine autom atic trimming with manual trimming action. functional overview STM32L432KB stm3l432kc 44/149 docid028798 rev 2 3.32 quad spi memory interface (quadspi) the quad spi is a specialized communication in terface targeting single, dual or quad spi flash memories. it can operate in any of the three following modes: ? indirect mode: all the operations are performed using the quadspi registers ? status polling mode: the exter nal flash status register is periodically read and an interrupt can be generated in case of flag setting ? memory-mapped mode: the external flash is memory mapped and is seen by the system as if it were an internal memory both throughput and capacity can be increased two-fold using dual-flash mode, where two quad spi flash memories are accessed simultaneously. the quad spi interface supports: ? three functional modes: indirect , status-polling, and memory-mapped ? sdr and ddr support ? fully programmable opcode for both indirect and memory mapped mode ? fully programmable frame format for both indirect and memory mapped mode ? each of the 5 following phases can be conf igured independently (enable, length, single/dual/quad communication) ? instruction phase ? address phase ? alternate bytes phase ? dummy cycles phase ? data phase ? integrated fifo for reception and transmission ? 8, 16, and 32-bit data accesses are allowed ? dma channel for indirect mode operations ? programmable masking for external flash flag management ? timeout management ? interrupt generation on fifo threshold, tim eout, status match, operation complete, and access error docid028798 rev 2 45/149 STM32L432KB stm3l432kc functional overview 45 3.33 development support 3.33.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. debug is performed using 2 pins only instead of 5 required by the jtag (jtag pins could be re-use as gpio with alternate function): the jtag tms and tck pins are shared with swdio and swclk, respectively, and a specific sequence on the tms pin is used to switch between jtag-dp and sw-dp. 3.33.2 embedded trace macrocell? the arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the stm32l432xx through a small number of etm pins to an external hardware trace port analyzer (tpa) device. real-time instruction and data flow activity be recorded and then formatted for display on the host computer th at runs the debugger software. tpa hardware is commercially available from common development tool vendors. the embedded trace macrocell operates wi th third party debugger software tools. pinouts and pin description STM32L432KB stm3l432kc 46/149 docid028798 rev 2 4 pinouts and pin description figure 4. stm32l432kx ufqfpn32 pinout (1) 1. the above figure shows the package top view. 0 6 y 9 8 ) 4 ) 3 1 9 ' ' 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 9 ' ' $ 9 5 ( ) 3 $ & . b , 1 3 $ 3 $ 3 $ 3 $ 3 $ 9 6 6 3 $ 3 $ 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 9 ' ' 9 6 6 3 + % 2 2 7 3 % 3 $ 3 % 3 % 3 % 3 % table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below th e pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o tt 3.6 v tolerant i/o rst bidirectional reset pin with embedded weak pull-up resistor option for tt or ft i/os _f (1) i/o, fm+ capable _u (2) i/o, with usb function supplied by v ddusb _a (3) i/o, with analog switch function supplied by v dda notes unless otherwise specified by a note, all i/os are set as analog inputs during and after reset. pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers 1. the related i/o structures in table 13 are: ft_f, ft_fa. 2. the related i/o structures in table 13 is: ft_u. 3. the related i/o structures in table 13 are: ft_a, ft_fa, tt_a. docid028798 rev 2 47/149 STM32L432KB stm3l432kc pinouts and pin description 57 table 13. stm32l432xx pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions ufqfpn32 alternate functions additional functions 2 pc14- osc32_i n (pc14) i/o ft (1) (2) eventout osc32_in 3 pc15- osc32_ out (pc15) i/o ft (1) (2) eventout osc32_out 4 nrst i/o rst - - - 5 vdda/vr ef+ s-- - - 6 pa0/ ck_in i/o ft_a - tim2_ch1, usart2_cts, comp1_out, sai1_extclk, tim2_etr, eventout opamp1_vinp, comp1_inm, adc1_in5, rtc_tamp2, wkup1, ck_in 7 pa1 i/o ft_a - tim2_ch2, i2c1_smba, spi1_sck, usart2_rts_de, tim15_ch1n, eventout opamp1_vinm, comp1_inp, adc1_in6 8 pa2 i/o ft_a - tim2_ch3, usart2_tx, lpuart1_tx, quadspi_bk1_ncs, comp2_out, tim15_ch1, eventout comp2_inm, adc1_in7, wkup4, lsco 9 pa3 i/o tt_a - tim2_ch4, usart2_rx, lpuart1_rx, quadspi_clk, sai1_mclk_a, tim15_ch2, eventout opamp1_vout, comp2_inp, adc1_in8 10 pa4 i/o tt_a - spi1_nss, spi3_nss, usart2_ck, sai1_fs_b, lptim2_out, eventout comp1_inm, comp2_inm, adc1_in9, dac1_out1 11 pa5 i/o tt_a - tim2_ch1, tim2_etr, spi1_sck, lptim2_etr, eventout comp1_inm, comp2_inm, adc1_in10, dac1_out2 12 pa6 i/o ft_a - tim1_bkin, spi1_miso, comp1_out, usart3_cts, lpuart1_cts, quadspi_bk1_io3, tim1_bkin_comp2, tim16_ch1, eventout adc1_in11 pinouts and pin description STM32L432KB stm3l432kc 48/149 docid028798 rev 2 13 pa7 i/o ft_fa - tim1_ch1n, i2c3_scl, spi1_mosi, quadspi_bk1_io2, comp2_out, eventout adc1_in12 14 pb0 i/o ft_a - tim1_ch2n, spi1_nss, usart3_ck, quadspi_bk1_io1, comp1_out, sai1_extclk, eventout adc1_in15 15 pb1 i/o ft_a - tim1_ch3n, usart3_rts_de, lpuart1_rts_de, quadspi_bk1_io0, lptim2_in1, eventout comp1_inm, adc1_in16 16 vss s - - - - 17 vdd s - - - - 18 pa8 i/o ft - mco, tim1_ch1, usart1_ck, swpmi1_io, sai1_sck_a, lptim2_out, eventout - 19 pa9 i/o ft_f - tim1_ch2, i2c1_scl, usart1_tx, sai1_fs_a, tim15_bkin, eventout - 20 pa10 i/o ft_f - tim1_ch3, i2c1_sda, usart1_rx, usb_crs_sync, sai1_sd_a, eventout - 21 pa11 i/o ft_u - tim1_ch4, tim1_bkin2, spi1_miso, comp1_out, usart1_cts, can1_rx, usb_dm, tim1_bkin2_comp1, eventout - 22 pa12 i/o ft_u - tim1_etr, spi1_mosi, usart1_rts_de, can1_tx, usb_dp, eventout - 23 pa13 (jtms- swdio) i/o ft (3) jtms-swdio, ir_out, usb_noe, swpmi1_tx, sai1_sd_b, eventout - table 13. stm32l432xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions ufqfpn32 alternate functions additional functions docid028798 rev 2 49/149 STM32L432KB stm3l432kc pinouts and pin description 57 24 pa14 (jtck- swclk) i/o ft (3) jtck-swclk, lptim1_out, i2c1_smba, swpmi1_rx, sai1_fs_b, eventout - 25 pa15 (jtdi) i/o ft (3) jtdi, tim2_ch1, tim2_etr, usart2_rx, spi1_nss, spi3_nss, usart3_rts_de, tsc_g3_io1, swpmi1_suspend, eventout - 26 pb3 (jtdo- trace swo) i/o ft_a (3) jtdo-traceswo, tim2_ch2, spi1_sck, spi3_sck, usart1_rts_de, sai1_sck_b, eventout comp2_inm 27 pb4 (njtrst) i/o ft_fa (3) njtrst, i2c3_sda, spi1_miso, spi3_miso, usart1_cts, tsc_g2_io1, sai1_mclk_b, eventout comp2_inp 28 pb5 i/o ft - lptim1_in1, i2c1_smba, spi1_mosi, spi3_mosi, usart1_ck, tsc_g2_io2, comp2_out, sai1_sd_b, tim16_bkin, eventout - 29 pb6 i/o ft_fa - lptim1_etr, i2c1_scl, usart1_tx, tsc_g2_io3, sai1_fs_b, tim16_ch1n, eventout comp2_inp 30 pb7 i/o ft_fa - lptim1_in2, i2c1_sda, usart1_rx, tsc_g2_io4, eventout comp2_inm, pvd_in 31 ph3/ boot0 i/o ft - eventout boot0 32 vss s - - - - 1vdds-- - - 1. pc14 and pc15 are supplied through the power switch. since the switch only si nks a limited amount of current (3 ma), the use of gpios pc14 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as curre nt sources (e.g. to drive an led). 2. after a backup domain power-up, pc14 and pc15 operat e as gpios. their f unction then depends on the content of the rtc registers which are not reset by the system reset. for details on how to manage these gpios, refer to the backup domain and rtc regist er descriptions in the rm0393 reference manual. 3. after reset, these pins are configured as jtag/s w debug alternate functions, and the internal pull-up on pa15, pa13, pb4 pins and the internal pull-down on pa14 pin are activated. table 13. stm32l432xx pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions ufqfpn32 alternate functions additional functions pinouts and pin description STM32L432KB stm3l432kc 50/149 docid028798 rev 2 table 14. alternate function af0 to af7 (for af8 to af15 see table 15 ) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ lptim1 tim1/tim2 usart2 i2c1/i2c2/i2c3 spi1/spi2 spi3 usart1/ usart2/ usart3 port a pa0-tim2_ch1-----usart2_cts pa1 - tim2_ch2 - - i2c1_smba spi1_sck - usart2_rts_ de pa2-tim2_ch3-----usart2_tx pa3-tim2_ch4-----usart2_rx pa4 - - - - - spi1_nss spi3_nss usart2_ck pa5 - tim2_ch1 tim2_etr - - spi1_sck - - pa6 - tim1_bkin - - - spi1_mi so comp1_out usart3_cts pa7 - tim1_ch1n - - i2c3_scl spi1_mosi - - pa8mcotim1_ch1-----usart1_ck pa9 - tim1_ch2 - - i2c1_scl - - usart1_tx pa10 - tim1_ch3 - - i2c1_sda - - usart1_rx pa11 - tim1_ch4 tim1_bkin2 - - spi 1_miso comp1_out usart1_cts pa12 - tim1_etr - - - spi1_mosi - usart1_rts_ de pa13jtms-swdioir_out------ pa14 jtck-swclk lptim1_out - - i2c1_smba - - - pa15 jtdi tim2_ch1 tim2_etr usart2_rx - spi1_nss spi3_nss usart3_rts_ de STM32L432KB stm3l432kc pinouts and pin description docid028798 rev 2 51/149 port b pb0 - tim1_ch2n - - - spi1_nss - usart3_ck pb1-tim1_ch3n----- usart3_rts_ de pb3 jtdo- traceswo tim2_ch2 - - - spi1_sck spi3_sck usart1_rts_ de pb4 njtrst - - - i2c3_sda spi1_miso spi3_miso usart1_cts pb5 - lptim1_in1 - - i2c1_smba spi1_mosi spi3_mosi usart1_ck pb6 - lptim1_etr - - i2c1_scl - - usart1_tx pb7 - lptim1_in2 - - i2c1_sda - - usart1_rx port c pc14-------- pc15-------- port hph3-------- table 14. alternate function af0 to af7 (for af8 to af15 see table 15 ) (continued) port af0 af1 af2 af3 af4 af5 af6 af7 sys_af tim1/tim2/ lptim1 tim1/tim2 usart2 i2c1/i2c2/i2c3 spi1/spi2 spi3 usart1/ usart2/ usart3 pinouts and pin description STM32L432KB stm3l432kc 52/149 docid028798 rev 2 table 15. alternate function af8 to af15 (for af0 to af7 see table 14 ) port af8 af9 af10 af11 af12 af13 af14 af15 lpuart1 can1/tsc usb/quadspi - comp1/ comp2/ swpmi1 sai1 tim2/tim15/ tim16/lptim2 eventout port a pa0 - - - - comp1_out sai1_extclk tim2_etr eventout pa1------tim15_ch1n eventout pa2 lpuart1_tx - quadspi_ bk1_ncs - comp2_out - tim15_ch1 eventout pa3 lpuart1_rx - quadspi_clk - - sai1_mclk_a tim15_ch2 eventout pa4-----sai1_fs_blptim2_out eventout pa5------lptim2_etr eventout pa6 lpuart1_cts - quadspi_ bk1_io3 - tim1_bkin_ comp2 - tim16_ch1 eventout pa7 - - quadspi_ bk1_io2 - comp2_out - - eventout pa8 - - - - swpmi1_io sai1_s ck_a lptim2_out eventout pa9-----sai1_fs_atim15_bkin eventout pa10 - - usb_crs_ sync - - sai1_sd_a - eventout pa11 - can1_rx usb_dm - tim1_bkin2_ comp1 - - eventout pa12 - can1_tx usb_dp - - - - eventout pa13 - - usb_noe - swpmi1_tx sai1_sd_b - eventout pa14 - - - - swpmi1_rx sai1_fs_b - eventout pa15 - tsc_g3_io1 - - swpmi1_ suspend - - eventout STM32L432KB stm3l432kc pinouts and pin description docid028798 rev 2 53/149 port b pb0 - - quadspi_ bk1_io1 - comp1_out sai1_extclk - eventout pb1 lpuart1_rts _de - quadspi_ bk1_io0 - - - lptim2_in1 eventout pb3-----sai1_sck_b- eventout pb4 - tsc_g2_io1 - - - sai1_mclk_b - eventout pb5 - tsc_g2_io2 - - comp2_out sai1_sd_b tim16_bkin eventout pb6 - tsc_g2_io3 - - - sai1_f s_b tim16_ch1n eventout pb7 - tsc_g2_io4 - - - - - eventout port c pc14------ - eventout pc15------ - eventout port hph3------ - eventout table 15. alternate function af8 to af15 (for af0 to af7 see table 14 ) (continued) port af8 af9 af10 af11 af12 af13 af14 af15 lpuart1 can1/tsc usb/quadspi - comp1/ comp2/ swpmi1 sai1 tim2/tim15/ tim16/lptim2 eventout memory mapping stm32 l432kb stm3l432kc 54/149 docid028798 rev 2 5 memory mapping figure 5. stm32l 432xx memory map 0 6 y 9 [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ ? 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 7 3 d u h d 6 \ v w h p p h p r u \ ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ & [ [ [ [ [ [ [ [ ) ) ) ) ) ) ) [ ) ) ) [ [ [ [ 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g [ [ 6 5 $ 0 4 8 $ ' 6 3 , u h j l v w h u v 2 s w l r q v % \ w h v [ ) ) ) [ ) ) ) [ ) ) ) [ ) ) ) 5 h v h u y h g 4 8 $ ' 6 3 , u h j l v w h u v [ % ) ) ) ) ) ) ) [ $ [ $ 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g [ ) ) ) ) ) ) ) [ 4 8 $ ' 6 3 , ) o d v k e d q n 6 5 $ 0 [ & [ $ docid028798 rev 2 55/149 STM32L432KB stm3l432kc memory mapping 57 table 16. stm32l432xx memory map and peripheral register boundary addresses (1) bus boundary address size(bytes) peripheral ahb2 0x5006 0800 - 0x5006 0bff 1 kb rng 0x5004 0400 - 0x5006 07ff 158 kb reserved 0x5004 0000 - 0x5004 03ff 1 kb adc 0x5000 0000 - 0x5003 ffff 16 kb reserved 0x4800 2000 - 0x4fff ffff ~127 mb reserved 0x4800 1c00 - 0x4800 1fff 1 kb gpioh 0x4800 0c00 - 0x4800 1bff 4 kb reserved 0x4800 0800 - 0x4800 0bff 1 kb gpioc 0x4800 0400 - 0x4800 07ff 1 kb gpiob 0x4800 0000 - 0x4800 03ff 1 kb gpioa - 0x4002 4400 - 0x47ff ffff ~127 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1 kb tsc 0x4002 3400 - 0x4002 3fff 1 kb reserved 0x4002 3000 - 0x4002 33ff 1 kb crc 0x4002 2400 - 0x4002 2fff 3 kb reserved 0x4002 2000 - 0x4002 23ff 1 kb flash registers 0x4002 1400 - 0x4002 1fff 3 kb reserved 0x4002 1000 - 0x4002 13ff 1 kb rcc 0x4002 0800 - 0x4002 0fff 2 kb reserved 0x4002 0400 - 0x4002 07ff 1 kb dma2 0x4002 0000 - 0x4002 03ff 1 kb dma1 apb2 0x4001 5800 - 0x4001 ffff 42 kb reserved 0x4001 5400 - 0x4000 57ff 1 kb sai1 0x4001 4800 - 0x4000 53ff 3 kb reserved 0x4001 4400 - 0x4001 47ff 1 kb tim16 0x4001 4000 - 0x4001 43ff 1 kb tim15 0x4001 3c00 - 0x4001 3fff 1 kb reserved 0x4001 3800 - 0x4001 3bff 1 kb usart1 0x4001 3400 - 0x4001 37ff 1 kb reserved 0x4001 3000 - 0x4001 33ff 1 kb spi1 0x4001 2c00 - 0x4001 2fff 1 kb tim1 0x4001 2000 - 0x4001 2bff 3 kb reserved memory mapping stm32 l432kb stm3l432kc 56/149 docid028798 rev 2 apb2 0x4001 1c00 - 0x4001 1fff 1 kb firewall 0x4001 0800- 0x4001 1bff 5 kb reserved 0x4001 0400 - 0x4001 07ff 1 kb exti 0x4001 0200 - 0x4001 03ff 1 kb comp 0x4001 0030 - 0x4001 01ff reserved 0x4001 0000 - 0x 4001 002f syscfg apb1 0x4000 9800 - 0x4000 ffff 26 kb reserved 0x4000 9400 - 0x4000 97ff 1 kb lptim2 0x4000 8c00 - 0x4000 93ff 2 kb reserved 0x4000 8800 - 0x4000 8bff 1 kb swpmi1 0x4000 8400 - 0x4000 87ff 1 kb reserved 0x4000 8000 - 0x4000 83ff 1 kb lpuart1 0x4000 7c00 - 0x4000 7fff 1 kb lptim1 0x4000 7800 - 0x4000 7bff 1 kb opamp 0x4000 7400 - 0x4000 77ff 1 kb dac 0x4000 7000 - 0x4000 73ff 1 kb pwr 0x4000 6c00 - 0x4000 6fff 1 kb usb sram 0x4000 6800 - 0x4000 6bff 1 kb usb fs 0x4000 6400 - 0x4000 67ff 1 kb can1 0x4000 6000 - 0x4000 63ff 1 kb crs 0x4000 5c00- 0x4000 5fff 1 kb i2c3 0x4000 5800 - 0x4000 5bff 1 kb reserved 0x4000 5400 - 0x4000 57ff 1 kb i2c1 0x4000 4800 - 0x4000 53ff 3 kb reserved 0x4000 4400 - 0x4000 47ff 1 kb usart2 0x4000 4000 - 0x4000 43ff 1 kb reserved 0x4000 3c00 - 0x4000 3fff 1 kb spi3 0x4000 3400 - 0x4000 3bff 2 kb reserved 0x4000 3000 - 0x4000 33ff 1 kb iwdg 0x4000 2c00 - 0x4000 2fff 1 kb wwdg 0x4000 2800 - 0x4000 2bff 1 kb rtc 0x4000 1800 - 0x4000 27ff 4 kb reserved 0x4000 1400 - 0x4000 17ff 1 kb tim7 table 16. stm32l432xx memory map and peripheral register boundary addresses bus boundary address size(bytes) peripheral docid028798 rev 2 57/149 STM32L432KB stm3l432kc memory mapping 57 apb1 0x4000 1000 - 0x4000 13ff 1 kb tim6 0x4000 0400- 0x4000 0fff 3 kb reserved 0x4000 0000 - 0x4000 03ff 1 kb tim2 1. the gray color is used for reserved boundary addresses. table 16. stm32l432xx memory map and peripheral register boundary addresses bus boundary address size(bytes) peripheral electrical characteristics STM32L432KB stm3l432kc 58/149 docid028798 rev 2 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean 3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = v dda = 3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean 2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 6 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 7 . figure 6. pin loading conditions figure 7. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid028798 rev 2 59/149 STM32L432KB stm3l432kc electrical characteristics 142 6.1.6 power supply scheme figure 8. power supply scheme caution: each power supply pair (v dd /v ss , v dda /v ssa etc.) must be decoupled with filtering ceramic capacitors as shown above. these capacitors must be placed as close as possible to, or below, the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 0 6 y 9 9 ' ' / h y h o v k l i w h u , 2 o r j l f < ?v o o}p] ~ w hu ]p]?o ? d u}?] ? l? ]?]??? ~ > ^ u z d u l? ? p]?? ?? / e k h d z po?}? * 3 , 2 v x?? t ?x s q [ q ) [ ? ) q [ 9 6 6 q [ 9 ' ' 9 & 2 5 ( 9 ' ' , 2 $ ' & v ' $ & v 2 3 $ 0 3 v & 2 0 3 v 9 5 ( ) 9 5 ( ) 9 ' ' $ v & ? ) 9 ' ' $ 9 6 6 $ 9 5 ( ) v & ? ) electrical characteristics STM32L432KB stm3l432kc 60/149 docid028798 rev 2 6.1.7 current consumption measurement figure 9. current consumption measurement scheme 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 17: voltage characteristics , table 18: current characteristics and table 19: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. 0 6 y 9 , ' ' b 8 6 % 9 ' ' 8 6 % , ' ' 9 ' ' , ' ' $ 9 ' ' $ table 17. voltage characteristics (1) symbol ratings min max unit v ddx - v ss external main supply voltage (including v dd , v dda , v ddusb ) -0.3 4.0 v v in (2) input voltage on ft_xxx pins v ss -0.3 min (v dd , v dda , v ddusb ) + 4.0 (3)(4) v input voltage on tt_xx pins v ss -0.3 4.0 input voltage on any other pins v ss -0.3 4.0 | ? v ddx | variations between different v ddx power pins of the same domain -50mv |v ssx -v ss | variations between all the different ground pins (5) -50mv 1. all main power (v dd , v dda , v ddusb ,) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. v in maximum must always be respected. refer to table 18: current characteristics for the maximum allowed injected current values. 3. this formula has to be applied only on the power supplies related to the io struct ure described in the pin definition table. docid028798 rev 2 61/149 STM32L432KB stm3l432kc electrical characteristics 142 4. to sustain a voltage higher than 4 v the internal pull-up/pull-down resistors must be disabled. 5. include vref- pin. table 18. current characteristics symbol ratings max unit iv dd total current into sum of all v dd power lines (source) (1) 140 ma iv ss total current out of sum of all v ss ground lines (sink) (1) 140 iv dd(pin) maximum current into each v dd power pin (source) (1) 100 iv ss(pin) maximum current out of each v ss ground pin (sink) (1) 100 i io(pin) output current sunk by any i/o and control pin except ft_f 20 output current sunk by any ft_f pin 20 output current sourced by any i/o and control pin 20 i io(pin) total output current sunk by sum of all i/os and control pins (2) 100 total output current sourced by sum of all i/os and control pins (2) 100 i inj(pin) (3) injected current on ft_xxx, tt_xx, rst and b pins, except pa4, pa5 -5/+0 (4) injected current on pa4, pa5 -5/0 |i inj(pin) | total injected current (sum of all i/os and control pins) (5) 25 1. all main power (v dd , v dda , v ddusb ) and ground (v ss , v ssa ) pins must always be connected to the external power supplies, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins. the total output current must not be sunk/sourced between two c onsecutive power supply pins referr ing to high pin count qfp packages. 3. positive injection (when v in > v ddiox ) is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer also to table 17: voltage characteristics for the maximum allowed input voltage values. 5. when several inputs are submitted to a current injection, the maximum | i inj(pin) | is the absolute sum of the negative injected currents (instantaneous values). table 19. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c electrical characteristics STM32L432KB stm3l432kc 62/149 docid028798 rev 2 6.3 operating conditions 6.3.1 general operating conditions table 20. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency - 0 80 mhz f pclk1 internal apb1 clock frequency - 0 80 f pclk2 internal apb2 clock frequency - 0 80 v dd standard operating voltage - 1.71 (1) 3.6 v v dda analog supply voltage adc or comp used 1.62 3.6 v dac or opamp used 1.8 adc, dac, opamp, comp not used 0 v ddusb usb supply voltage usb used 3.0 3.6 v usb not used 0 3.6 v in i/o input voltage tt_xx i/o -0.3 v ddiox +0.3 v all i/o except tt_xx -0.3 min(min(v dd , v dda , v ddusb )+3.6 v, 5.5 v) (2)(3) p d power dissipation at t a = 125 c for suffix 3 (4) ufqfpn32 - 128 mw p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (4) ufqfpn32 - 523 mw t a ambient temperature for the suffix 6 version maximum power dissipation ?40 85 c low-power dissipation (5) ?40 105 ambient temperature for the suffix 7 version maximum power dissipation ?40 105 low-power dissipation (5) ?40 125 ambient temperature for the suffix 3 version maximum power dissipation ?40 125 low-power dissipation (5) ?40 130 t j junction temperature range suffix 6 version ?40 105 c suffix 7 version ?40 125 suffix 3 version ?40 130 1. when reset is released func tionality is guaranteed down to v bor0 min. 2. this formula has to be applied only on t he power supplies related to the io struct ure described by the pin definition table. maximum i/o input voltage is the smallest value between min(v dd , v dda , v ddusb )+3.6 v and 5.5v. 3. for operation with voltage higher than min (v dd , v dda , v ddusb ) +0.3 v, the internal pull-up and pull-down resistors must be disabled. 4. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). docid028798 rev 2 63/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.2 operating conditions at power-up / power-down the parameters given in table 21 are derived from tests performed under the ambient temperature condition summarized in table 20 . 6.3.3 embedded reset and power control block characteristics the parameters given in table 22 are derived from tests performed under the ambient temperature conditions summarized in table 20: general operating conditions . 5. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see section 7.2: thermal characteristics ). table 21. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 10 t vdda v dda rise time rate - 0 v dda fall time rate 10 t vddusb v ddusb rise time rate - 0 v ddusb fall time rate 10 table 22. embedded reset and power control block characteristics symbol parameter conditions (1) min typ max unit t rsttempo (2) reset temporization after bor0 is detected v dd rising - 250 400 s v bor0 (2) brown-out reset threshold 0 rising edge 1.62 1.66 1.7 v falling edge 1.6 1.64 1.69 v bor1 brown-out reset threshold 1 rising edge 2.06 2.1 2.14 v falling edge 1.96 2 2.04 v bor2 brown-out reset threshold 2 rising edge 2.26 2.31 2.35 v falling edge 2.16 2.20 2.24 v bor3 brown-out reset threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v bor4 brown-out reset threshold 4 rising edge 2.85 2.90 2.95 v falling edge 2.76 2.81 2.86 v pvd0 programmable voltage detector threshold 0 rising edge 2.1 2.15 2.19 v falling edge 2 2.05 2.1 v pvd1 pvd threshold 1 rising edge 2.26 2.31 2.36 v falling edge 2.15 2.20 2.25 electrical characteristics STM32L432KB stm3l432kc 64/149 docid028798 rev 2 v pvd2 pvd threshold 2 rising edge 2.41 2.46 2.51 v falling edge 2.31 2.36 2.41 v pvd3 pvd threshold 3 rising edge 2.56 2.61 2.66 v falling edge 2.47 2.52 2.57 v pvd4 pvd threshold 4 rising edge 2.69 2.74 2.79 v falling edge 2.59 2.64 2.69 v pvd5 pvd threshold 5 rising edge 2.85 2.91 2.96 v falling edge 2.75 2.81 2.86 v pvd6 pvd threshold 6 rising edge 2.92 2.98 3.04 v falling edge 2.84 2.90 2.96 v hyst_borh0 hysteresis voltage of borh0 hysteresis in continuous mode -20- mv hysteresis in other mode -30- v hyst_bor_pvd hysteresis voltage of borh (except borh0) and pvd --100-mv i dd (bor_pvd) (2) bor (3) (except bor0) and pvd consumption from v dd --1.11.6a v pvm1 v ddusb peripheral voltage monitoring - 1.18 1.22 1.26 v v pvm3 v dda peripheral voltage monitoring rising edge 1.61 1.65 1.69 v falling edge 1.6 1.64 1.68 v pvm4 v dda peripheral voltage monitoring rising edge 1.78 1.82 1.86 v falling edge 1.77 1.81 1.85 v hyst_pvm3 pvm3 hysteresis - - 10 - mv v hyst_pvm4 pvm4 hysteresis - - 10 - mv i dd (pvm1) (2) pvm1 consumption from v dd --0.2-a i dd (pvm3/pvm4) (2) pvm3 and pvm4 consumption from v dd --2-a 1. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. 2. guaranteed by design. 3. bor0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current characteristics tables. table 22. embedded reset and power control block characteristics (continued) symbol parameter conditions (1) min typ max unit docid028798 rev 2 65/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.4 embedded voltage reference the parameters given in table 23 are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . table 23. embedded internal voltage reference symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +130 c 1.182 1.212 1.232 v t s_vrefint (1) adc sampling time when reading the internal reference voltage -4 (2) -- s t start_vrefint start time of reference voltage buffer when adc is enable --812 (2) s i dd (v refintbuf ) v refint buffer consumption from v dd when converted by adc - - 12.5 20 (2) a ? v refint internal reference voltage spread over the temperature range v dd = 3 v - 5 7.5 (2) mv t coeff temperature coefficient ?40c < t a < +130c - 30 50 (2) ppm/c a coeff long term stability 1000 hours, t = 25c - - tbd (2) ppm v ddcoeff voltage coefficient 3.0 v < v dd < 3.6 v - 250 1200 (2) ppm/v v refint_div1 1/4 reference voltage - 24 25 26 % v refint v refint_div2 1/2 reference voltage 49 50 51 v refint_div3 3/4 reference voltage 74 75 76 1. the shortest sampling time can be determined in the application by multiple iterations. 2. guaranteed by design. electrical characteristics STM32L432KB stm3l432kc 66/149 docid028798 rev 2 figure 10. v refint versus temperature 0 6 y 9 9 ? & 0 h d q 0 l q 0 d [ docid028798 rev 2 67/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.5 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 9: current consumption measurement scheme . typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input mode ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted with the minimum wait states number, depending on the f hclk frequency (refer to the table ?number of wait states according to cpu clock (hclk) frequency? available in the rm0393 reference manual). ? when the peripherals are enabled f pclk = f hclk the parameters given in table 24 to table 36 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . electrical characteristics STM32L432KB stm3l432kc 68/149 docid028798 rev 2 table 24. current consumption in run and low-power run modes, code with data processing running from flash, art enable (cache on prefetch off) symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.37 2.38 2.44 2.52 2.66 2.7 2.7 2.8 2.9 3.2 ma 16 mhz 1.5 1.52 1.57 1.64 1.79 1.7 1.7 1.8 2.0 2.3 8 mhz 0.81 0.82 0.87 0.94 1.08 0.9 0.9 1.0 1.2 1.5 4 mhz 0.46 0.47 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 2 mhz 0.29 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 1 mhz 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 100 khz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 range 1 80 mhz 8.53 8.56 8.64 8.74 8.92 9.5 9.6 9.7 9.9 10.3 72 mhz 7.7 7.73 7.8 7.9 8.08 8.6 8.6 8.7 8.9 9.3 64 mhz 6.86 6.9 6.97 7.06 7.23 7.7 7.7 7.8 8.0 8.3 48 mhz 5.13 5.16 5.23 5.32 5.49 5.8 5.8 6.0 6.1 6.5 32 mhz 3.46 3.48 3.55 3.64 3.8 3.9 4.0 4.1 4.2 4.6 24 mhz 2.63 2.64 2.71 2.79 2.96 3.0 3.0 3.1 3.3 3.6 16 mhz 1.8 1.81 1.87 1.96 2.12 2.0 2.1 2.2 2.3 2.7 i dd (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable 2 mhz 211 230 280 355 506 273.8 301.1 360.4 502.7 815.9 a 1 mhz 117 134 179 254 404 154.7 184.6 249.6 398.4 712.4 400 khz 58.5 70.4 116 189 338 80.2 111.5 179.7 330.8 643.4 100 khz 30 41.1 85.2 159 308 46.5 76.6 147.1 299.1 611.2 1. guaranteed by characterization re sults, unless otherwise specified. STM32L432KB stm3l432kc electrical characteristics docid028798 rev 2 69/149 table 25. current consumption in run and low-power run modes, code with data processing running from flash, art disable symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.66 2.68 2.73 2.81 2.96 3.0 3.1 3.2 3.3 3.6 ma 16 mhz 1.88 1.9 1.94 2.02 2.17 2.1 2.2 2.3 2.4 2.7 8 mhz 1.05 1.06 1.11 1.18 1.33 1.2 1.2 1.3 1.4 1.7 4 mhz 0.6 0.62 0.66 0.73 0.87 0.7 0.7 0.8 0.9 1.2 2 mhz 0.36 0.37 0.34 0.48 0.62 0.4 0.4 0.5 0.6 0.9 1 mhz 0.23 0.25 0.25 0.36 0.5 0.3 0.3 0.4 0.5 0.8 100 khz 0.12 0.14 0.17 0.25 0.39 0.1 0.2 0.2 0.4 0.7 range 1 80 mhz 8.56 8.61 8.69 8.79 8.97 9.6 9.7 9.8 10.0 10.3 72 mhz 7.74 7.79 7.86 7.96 8.14 8.7 8.7 8.8 9.0 9.4 64 mhz 7.63 7.68 7.75 7.85 8.04 8.6 8.6 8.7 8.9 9.3 48 mhz 6.36 6.4 6.48 6.58 6.76 7.2 7.3 7.4 7.6 7.9 32 mhz 4.56 4.6 4.66 4.76 4.93 5.2 5.2 5.3 5.5 5.8 24 mhz 3.45 3.48 3.54 3.64 3.8 3.9 4.0 4.1 4.2 4.6 16 mhz 2.48 2.51 2.56 2.65 2.82 2.8 2.9 3.0 3.1 3.5 i dd (lprun) supply current in low-power run f hclk = f msi all peripherals disable 2 mhz 310 317 364 440 593 375.3 400.9 456.7 595.3 909.6 a 1 mhz 157 173 226 296 448 204.8 234.2 298.2 445.8 758.9 400 khz 72.6 89 130 206 356 99.7 131.2 199.7 349.3 663.7 100 khz 32.3 46 89.7 164 314 52.4 82.1 153.3 301.2 616.9 1. guaranteed by characterization re sults, unless otherwise specified. electrical characteristics STM32L432KB stm3l432kc 70/149 docid028798 rev 2 table 26. current consumption in run and low-power run modes, code with data processing running from sram1 symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (run) supply current in run mode f hclk = f hse up to 48mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 2.42 2.43 2.49 2.56 2.71 2.7 2.7 2.8 3.0 3.3 ma 16 mhz 1.54 1.55 1.6 1.67 1.82 1.7 1.7 1.8 2.0 2.3 8 mhz 0.82 0.84 0.88 0.95 1.1 0.9 1.0 1.0 1.2 1.5 4 mhz 0.47 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 2 mhz 0.29 0.3 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 1 mhz 0.2 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 100 khz 0.12 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 range 1 80 mhz 8.63 8.68 8.74 8.84 9.01 9.5 9.6 9.7 9.9 10.2 72 mhz 7.79 7.83 7.9 7.99 8.17 8.6 8.6 8.8 8.9 9.3 64 mhz 6.95 6.99 7.05 7.15 7.32 7.7 7.7 7.9 8.0 8.4 48 mhz 5.19 5.22 5.29 5.38 5.55 5.8 5.8 5.9 6.1 6.5 32 mhz 3.51 3.53 3.6 3.68 3.85 3.9 4.0 4.1 4.2 4.6 24 mhz 2.66 2.68 2.74 2.83 2.99 3.0 3.0 3.1 3.3 3.6 16 mhz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.2 2.3 2.7 i dd (lprun) supply current in low-power run mode f hclk = f msi all peripherals disable flash in power-down 2 mhz 205 228 275 352 501 276.5 302.3 358.4 502.5 816.4 a 1 mhz 111 126 175 248 397 151.3 180.9 245.3 390.7 703.4 400 khz 49.2 62.7 108 181 330 73.3 104.0 170.8 321.0 632.4 100 khz 21.5 33.3 76.6 151 299 36.4 67.7 137.2 287.8 600.8 1. guaranteed by characterization re sults, unless otherwise specified. docid028798 rev 2 71/149 STM32L432KB stm3l432kc electrical characteristics 142 table 27. typical current consumption in run and low-power run modes, with different codes running from flash, art enable (cache on prefetch off) symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.37 ma 91 a/mhz coremark 2.69 103 dhrystone 2.1 2.74 105 fibonacci 2.58 99 while(1) 2.30 88 range 1 f hclk = 80 mhz reduced code (1) 8.53 ma 107 a/mhz coremark 9.68 121 dhrystone 2.1 9.76 122 fibonacci 9.27 116 while(1) 8.20 103 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 211 a 106 a/mhz coremark 251 126 dhrystone 2.1 269 135 fibonacci 230 115 while(1) 286 143 1. reduced code used for characterization results provided in table 24 , table 25 , table 26 . electrical characteristics STM32L432KB stm3l432kc 72/149 docid028798 rev 2 table 28. typical current consumption in run and low-power run modes, with different codes running from flash, art disable symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.66 ma 102 a/mhz coremark 2.44 94 dhrystone 2.1 2.46 95 fibonacci 2.27 87 while(1) 2.20 84.6 range 1 f hclk = 80 mhz reduced code (1) 8.56 ma 107 a/mhz coremark 8.00 100 dhrystone 2.1 7.98 100 fibonacci 7.41 93 while(1) 7.83 98 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 310 a 155 a/mhz coremark 342 171 dhrystone 2.1 324 162 fibonacci 324 162 while(1) 384 192 1. reduced code used for characterization results provided in table 24 , table 25 , table 26 . table 29. typical current consumption in run and low-power run modes, with different codes running from sram1 symbol parameter conditions typ unit typ unit - voltage scaling code 25 c 25 c i dd (run) supply current in run mode f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 f hclk = 26 mhz reduced code (1) 2.42 ma 93 a/mhz coremark 2.18 84 dhrystone 2.1 2.40 92 fibonacci 2.40 92 while(1) 2.29 88 range 1 f hclk = 80 mhz reduced code (1) 8.63 ma 108 a/mhz coremark 7.76 97 dhrystone 2.1 8.55 107 fibonacci 8.56 107 while(1) 8.12 102 i dd (lprun) supply current in low-power run f hclk = f msi = 2 mhz all peripherals disable reduced code (1) 205 a 103 a/mhz coremark 188 94 dhrystone 2.1 222 111 fibonacci 204 102 while(1) 211 106 1. reduced code used for characterization results provided in table 24 , table 25 , table 26 . STM32L432KB stm3l432kc electrical characteristics docid028798 rev 2 73/149 table 30. current consumption in sleep and low-power sleep modes, flash on symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (sleep) supply current in sleep mode, f hclk = f hse up to 48 mhz included, bypass mode pll on above 48 mhz all peripherals disable range 2 26 mhz 0.68 0.69 0.74 0.81 0.95 0.8 0.8 0.9 1.0 1.3 ma 16 mhz 0.46 0.48 0.52 0.59 0.73 0.5 0.6 0.6 0.8 1.1 8 mhz 0.29 0.30 0.34 0.41 0.55 0.3 0.4 0.4 0.6 0.9 4 mhz 0.20 0.21 0.25 0.32 0.46 0.2 0.3 0.3 0.5 0.8 2 mhz 0.16 0.17 0.21 0.28 0.42 0.2 0.2 0.3 0.4 0.7 1 mhz 0.13 0.15 0.19 0.26 0.40 0.1 0.2 0.3 0.4 0.7 100 khz 0.11 0.13 0.17 0.24 0.38 0.1 0.2 0.2 0.4 0.7 range 1 80 mhz 2.23 2.25 2.30 2.38 2.54 2.5 2.5 2.6 2.8 3.1 72 mhz 2.02 2.04 2.10 2.18 2.34 2.2 2.3 2.4 2.5 2.9 64 mhz 1.82 1.84 1.89 1.98 2.14 2.0 2.1 2.1 2.3 2.6 48 mhz 1.34 1.36 1.42 1.50 1.66 1.5 1.6 1.7 1.8 2.2 32 mhz 0.93 0.95 1.01 1.09 1.25 1.1 1.1 1.2 1.4 1.7 24 mhz 0.73 0.75 0.80 0.88 1.04 0.8 0.9 1.0 1.1 1.4 16 mhz 0.53 0.55 0.60 0.68 0.84 0.6 0.6 0.7 0.9 1.2 i dd (lpsleep) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 71.8 80.7 125 200 350 91.1 122.7 191.3 341.5 653.5 a 1 mhz 45.0 57.3 101 176 325 63.2 95.4 165.4 316.5 628.7 400 khz 27.0 40.7 84.6 158 308 43.9 75.8 147.2 297.6 609.2 100 khz 22.8 30.9 63.3 113.2 20 7.7 35.2 67.9 140.9 290.8 602.4 1. guaranteed by characterization re sults, unless otherwise specified. electrical characteristics STM32L432KB stm3l432kc 74/149 docid028798 rev 2 table 31. current consumption in low-pow er sleep modes, flash in power-down symbol parameter conditions typ max (1) unit - voltage scaling f hclk 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (lpsleep ) supply current in low-power sleep mode f hclk = f msi all peripherals disable 2 mhz 58.7 70.7 103.2 153.7 248.5 80 113 180 330 641 a 1 mhz 39.4 47.2 79.3 129.6 224.8 53 86 154 304 616 400 khz 20.8 30.8 62.1 112.5 207.8 35 67 137 286 597 100 khz 14.3 23.1 55.1 105.7 201.5 27 58 130 279 590 1. guaranteed by characterization re sults, unless otherwise specified. table 32. current consumption in stop 2 mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 2) supply current in stop 2 mode, rtc disabled - 1.8 v 1 2.54 8.74 19.8 43.4 2.0 5.6 21.1 50.8 116.0 a 2.4 v 1.02 2.59 8.89 20.2 44.3 2.1 5.8 21.6 52.3 119.6 3 v 1.06 2.67 9.11 20.7 45.5 2.1 5.9 22.2 53.7 123.2 3.6 v 1.23 2.88 9.56 21.6 47.3 2.3 6.1 23.0 55.8 127.9 i dd (stop 2 with rtc) supply current in stop 2 mode, rtc enabled rtc clocked by lsi 1.8 v 1.3 2.82 9.02 20.1 43.6 2.5 6.2 21.6 51.3 116.3 a 2.4 v 1.39 2.95 9.24 20.5 44.6 2.8 6.4 22.3 52.8 120.0 3 v 1.5 3.11 9.55 21.1 45.8 3.0 6.8 23.0 54.5 123.8 3.6 v 1.76 3.42 10.1 22.1 47.8 3.3 7.2 24.1 56.7 128.7 rtc clocked by lse bypassed at 32768 hz 1.8 v 1.36 2.9 9.1 20.1 43.7 - - - - - 2.4 v 1.48 3.09 9.44 20.8 45 - - - - - 3 v 1.83 3.67 10.4 22.3 47.3 - - - - - 3.6 v 3.58 6.17 13.9 26.6 53 - - - - - rtc clocked by lse quartz (2) in low drive mode 1.8 v 1.28 2.81 9.13 20.8 - - - - - - 2.4 v 1.39 2.93 9.34 21.3 - - - - - - 3 v 1.59 3.1 9.64 21.8 - - - - - - 3.6 v 1.86 3.45 10.2 22.8 - - - - - - STM32L432KB stm3l432kc electrical characteristics docid028798 rev 2 75/149 i dd (wakeup from stop2) supply current during wakeup from stop 2 mode wakeup clock is msi = 48 mhz, voltage range 1. see (3) . 3 v1.85--------- ma wakeup clock is msi = 4 mhz, voltage range 2. see (3) . 3 v1.52--------- wakeup clock is hsi16 = 16 mhz, voltage range 1. see (3) . 3 v1.54--------- 1. guaranteed based on test during charac terization, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 38: low-power mode wakeup timings . table 32. current consumption in stop 2 mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c electrical characteristics STM32L432KB stm3l432kc 76/149 docid028798 rev 2 table 33. current consumption in stop 1 mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 1) supply current in stop 1 mode, rtc disabled - 1.8 v 4.34 12.4 43.6 96.4 2 04 9.3 27.4 98.9 198.7 397.5 a 2.4 v 4.35 12.5 43.8 97 205 9.4 27.6 99.5 199.0 398.0 3 v 4.41 12.6 44.1 97.7 207 9.5 27.8 100.3 200.4 400.8 3.6 v 4.56 12.9 44.8 98.9 2 10 9.7 28.3 101.7 202.1 404.2 i dd (stop 1 with rtc) supply current in stop 1 mode, rtc enabled rtc clocked by lsi 1.8 v 4.63 12.7 43.9 96.8 2 05 9.9 28.0 99.5 198.9 397.8 a 2.4 v 4.78 12.8 44.2 97.4 206 10.1 28.3 100.3 199.5 399.0 3 v 4.93 13 44.6 98.1 207 10.4 28.7 101.2 200.9 401.9 3.6 v 5.05 13.4 45.3 99.5 210 10.8 29.4 102.8 202.5 405.0 rtc clocked by lse bypassed, at 32768 hz 1.8 v 4.7 12.8 44 96.9 205 - - - - - 2.4 v 4.95 13 44.4 97.6 206 - - - - - 3 v 5.33 13.6 45.4 99.1 209 - - - - - 3.6 v 6.91 16.1 48.8 103 216 - - - - - rtc clocked by lse quartz (2) in low drive mode 1.8 v 4.76 12.3 43.7 99.1 - - - - - - 2.4 v 4.95 12.4 43.8 99.3 - - - - - - 3 v 5.1 12.6 44.1 99.6 - - - - - - 3.6 v 5.65 13 44.8 101 - - - - - - i dd (wakeup from stop1) supply current during wakeup from stop 1 wakeup clock msi = 48 mhz, voltage range 1. see (3) . 3 v1.14--------- ma wakeup clock msi = 4 mhz, voltage range 2. see (3) . 3 v1.22--------- wakeup clock hsi16 = 16 mhz, voltage range 1. see (3) . 3 v1.20--------- 1. guaranteed based on test during charac terization, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 38: low-power mode wakeup timings . STM32L432KB stm3l432kc electrical characteristics docid028798 rev 2 77/149 table 34. current consumption in stop 0 symbol parameter conditions typ max (1) 1. guaranteed by characterization re sults, unless otherwise specified. unit v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (stop 0) supply current in stop 0 mode, rtc disabled 1.8 v 108 119 158 221 347 133 158 244 395 704 a 2.4 v 110 121 160 223 349 136 161 248 399 710 3 v 111 123 161 224 352 139 164 251 403 716 3.6 v 114 125 163 227 355 142 167 254 408 722 (2) 2. guaranteed by test in production. electrical characteristics STM32L432KB stm3l432kc 78/149 docid028798 rev 2 table 35. current consumption in standby mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (standby) supply current in standby mode (backup registers retained), rtc disabled no independent watchdog 1.8 v 27.7 144 758 2 072 5 425 119 425 2866 7524 20510 na 2.4 v 50.9 187 892 2 408 6 247 183 564 3383 8778 23768 3 v 90.2 253 1 090 2 884 7 409 225 681 3912 10071 26976 3.6 v 253 459 1 474 3 575 8 836 292 877 4638 11659 30758 with independent watchdog 1.8 v 216 - - - - - - - - - 2.4 v 342 - - - - - - - - - 3 v 416 - - - - - - - - - 3.6 v 551 - - - - - - - - - i dd (standby with rtc) supply current in standby mode (backup registers retained), rtc enabled rtc clocked by lsi, no independent watchdog 1.8 v 287 407 989 2 230 5 396 585 944 3344 7866 20504 na 2.4 v 386 526 1 201 2 638 6 274 811 1230 4007 9246 23824 3 v 513 679 1 478 3 167 7 414 1022 1521 4683 10671 27124 3.6 v 771 978 1 963 3 992 9 039 1284 1924 5577 12383 30954 (2) rtc clocked by lsi, with independent watchdog 1.8 v 342 - - - - - - - - - 2.4 v 521 - - - - - - - - - 3 v 655 - - - - - - - - - 3.6 v 865 - - - - - - - - - rtc clocked by lse bypassed at 32768hz 1.8 v 142 126 865 2 220 5 650 - - - - - na 2.4 v 249 219 1 090 2 660 6 600 - - - - - 3 v 404 364 1 410 3 260 7 850 - - - - - 3.6 v 742 670 2 000 4 230 9 700 - - - - - rtc clocked by lse quartz (3) in low drive mode 1.8 v 281 423 1 046 2 410 5 700 - - - - - 2.4 v 388 548 1 268 2 847 6 564 - - - - - 3 v 535 715 1 565 3 420 7 694 - - - - - 3.6 v 836 1 048 2 081 4 311 9 338 - - - - - STM32L432KB stm3l432kc electrical characteristics docid028798 rev 2 79/149 i dd (sram2) (4) supply current to be added in standby mode when sram2 is retained - 1.8 v 173 349 1 009 2 158 4 542 249 527 1604 3402 6908 na 2.4 v 174 345 1 015 2 163 4 535 271 589 1623 3438 6924 3 v 178 350 1 019 2 148 4 419 277 594 1628 3467 6935 3.6 v 184 352 1 033 2 208 4 610 293 611 1631 3480 6948 i dd (wakeup from standby) supply current during wakeup from standby mode wakeup clock is msi = 4 mhz. see (5) . 3 v1.23---------ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. guaranteed by test in production. 3. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 4. the supply current in standby with sram2 mode is: i dd (standby) + i dd (sram2). the supply current in standby with rtc with sram2 mode is: i dd (standby + rtc) + i dd (sram2). 5. wakeup with code execution from flash. average val ue given for a typical wak eup time as specified in table 38: low-power mode wakeup timings . table 35. current consumption in standby mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c table 36. current consumption in shutdown mode symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c i dd (shutdown) supply current in shutdown mode (backup registers retained) rtc disabled - 1.8 v 7.82 190 386 1 286 3 854 25.0 255 1721 5052 15543 na 2.4 v 23 229 485 1 517 4 431 34.9 270 2085 5878 17639 3 v 44.3 290 634 1 878 5 310 70.1 345 2454 6755 19984 3.6 v 212 397 977 2 516 6 656 119.1 496 2992 7939 22860 electrical characteristics STM32L432KB stm3l432kc 80/149 docid028798 rev 2 i dd (shutdown with rtc) supply current in shutdown mode (backup registers retained) rtc enabled rtc clocked by lse bypassed at 32768 hz 1.8 v 63 133 522 1 490 4 270 - - - - - na 2.4 v 165 253 710 1 830 4 980 - - - - - 3 v 316 423 990 2 340 6 050 - - - - - 3.6 v 649 787 1 530 3 220 7 710 - - - - - rtc clocked by lse quartz (2) in low drive mode 1.8 v 203 293 700 1 675 - - - - - - 2.4 v 303 411 880 2 001 - - - - - - 3 v 448 567 1 136 2 479 - - - - - - 3.6 v 744 887 1 609 3 256 - - - - - - i dd (wakeup from shutdown) supply current during wakeup from shutdown mode wakeup clock is msi = 4 mhz. see (3) . 3 v 0.780 - - - - - - - - - ma 1. guaranteed by characterization re sults, unless otherwise specified. 2. based on characterization done with a 32.768 khz crystal (mc306- g-06q-32.768, manufacturer jfvny) with two 6.8 pf loading cap acitors. 3. wakeup with code execution from flash. average va lue given for a typical wak eup time as specified in table 38: low-power mode wakeup timings . table 36. current consumption in shutdown mode (continued) symbol parameter conditions typ max (1) unit -v dd 25 c 55 c 85 c 105 c 125 c 25 c 55 c 85 c 105 c 125 c docid028798 rev 2 81/149 STM32L432KB stm3l432kc electrical characteristics 142 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge n erate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 56: i/o static characteristics . for the output pins, any external pull-down or ext ernal load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os co nfigured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: an y floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption measured previously (see table 37: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switch es, it uses the current from the i/o supply voltage to supply the i/o pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: i sw v ddiox f sw c = where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v ddiox is the i/o supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext + c s c s is the pcb board capacitance including the pad pin. the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. electrical characteristics STM32L432KB stm3l432kc 82/149 docid028798 rev 2 on-chip peripheral current consumption the current consumption of the on -chip peripherals is given in table 37 . the mcu is placed under the following conditions: ? all i/o pins are in analog mode ? the given value is calculated by measuring the difference of the current consumptions: ? when the peripheral is clocked on ? when the peripheral is clocked off ? ambient operating temperature and supply voltage conditions summarized in table 17: voltage characteristics ? the power consumption of the digital part of the on-chip peripherals is given in table 37 . the power consumption of the analog part of the peripherals (where applicable) is indicated in each related section of the datasheet. table 37. peripheral current consumption peripheral range 1 range 2 low-power run and sleep unit ahb bus matrix (1) 3.2 2.9 3.1 a/mhz adc independent clock domain 0.4 0.1 0.2 adc clock domain 2.1 1.9 1.9 crc 0.4 0.2 0.3 dma1 1.4 1.3 1.4 dma2 1.5 1.3 1.4 flash 6.2 5.2 5.8 gpioa (2) 1.7 1.4 1.6 gpiob (2) ) 1.6 1.3 1.6 gpioc (2) 1.7 1.5 1.6 gpioh (2) 0.6 0.6 0.5 qspi 7.0 5.8 7.3 rng independent clock domain 2.2 na na rng clock domain 0.5 na na sram1 0.8 0.9 0.7 sram2 1.0 0.8 0.8 tsc 1.6 1.3 1.3 all ahb peripherals 21.7 18.5 20.3 apb1 ahb to apb1 bridge (3) 0.9 0.7 0.9 can1 4.1 3.2 3.9 dac1 2.4 1.8 2.2 rtca 1.7 1.1 2.1 crs 0.3 0.3 0.6 docid028798 rev 2 83/149 STM32L432KB stm3l432kc electrical characteristics 142 apb1 usb fs independent clock domain 2.9 na na a/mhz usb fs clock domain 2.3 na na i2c1 independent clock domain 3.5 2.8 3.4 i2c1 clock domain 1.1 0.9 1.0 i2c3 independent clock domain 2.9 2.3 2.5 i2c3 clock domain 0.9 0.4 0.8 lpuart1 independent clock domain 1.9 1.6 1.8 lpuart1 clock domain 0.6 0.6 0.6 lptim1 independent clock domain 2.9 2.4 2.8 lptim1 clock domain 0.8 0.4 0.7 lptim2 independent clock domain 3.1 2.7 3.9 lptim2 clock domain 0.8 0.7 0.8 opamp 0.4 0.2 0.4 pwr 0.4 0.1 0.4 spi3 1.7 1.3 1.6 swpmi1 independent clock domain 1.9 1.6 1.9 swpmi1 clock domain 0.9 0.7 0.8 tim2 6.2 5.0 5.9 tim6 1.0 0.6 0.9 tim7 1.0 0.6 0.6 usart2 independent clock domain 4.1 3.6 3.8 usart2 clock domain 1.3 0.9 1.1 wwdg 0.5 0.5 0.5 all apb1 on 40.2 26.7 37.9 apb2 ahb to apb2 (4) 1.0 0.9 0.9 fw 0.2 0.2 0.2 sai1 independent clock domain 2.3 1.8 1.9 sai1 clock domain 2.1 1.8 2.0 spi1 1.8 1.6 1.7 syscfg/comp 0.6 0.5 0.6 table 37. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit electrical characteristics STM32L432KB stm3l432kc 84/149 docid028798 rev 2 6.3.6 wakeup time from low-po wer modes and voltage scaling transition times the wakeup times given in table 38 are the latency between the event and the execution of the first user instruction. the device goes in low-power mode after the wfe (wait for event) instruction. apb2 tim1 8.1 6.5 7.6 a/mhz tim15 3.7 3.0 3.4 tim16 2.7 2.1 2.6 usart1 independent clock domain 4.8 4.2 4.6 usart1 clock domain 1.5 1.3 1.7 all apb2 on 24.2 19.9 22.6 all 86.1 65.1 80.9 1. the busmatrix is automatica lly active when at least one master is on (cpu, dma). 2. the gpiox (x= a?h) dynamic current cons umption is approximately divided by a fact or two versus this table values when the gpio port is locked thanks to lckk and lcky bits in the gpio x_lckr register. in order to save the full gpiox current consumption, the gpiox clock should be disabled in the rcc when all port i/os ar e used in alternate function or analog mode (clock is only required to read or write into gp io registers, and is not used in af or analog modes). 3. the ahb to apb1 bridge is automatically active when at least one peripheral is on on the apb1. 4. the ahb to apb2 bridge is automatically active when at least one peripheral is on on the apb2. table 37. peripheral current consumption (continued) peripheral range 1 range 2 low-power run and sleep unit table 38. low-power mode wakeup timings (1) symbol parameter conditions typ max unit t wusleep wakeup time from sleep mode to run mode -66 nb of cpu cycles t wulpsleep wakeup time from low- power sleep mode to low- power run mode wakeup in flash with flash in power-down during low-power sleep mode (sleep_pd=1 in flash_acr) and with clock msi = 2 mhz 68.3 docid028798 rev 2 85/149 STM32L432KB stm3l432kc electrical characteristics 142 t wustop0 wake up time from stop 0 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 3.8 5.7 s wakeup clock hsi16 = 16 mhz 4.1 6.9 range 2 wakeup clock msi = 24 mhz 4.07 6.2 wakeup clock hsi16 = 16 mhz 4.1 6.8 wakeup clock msi = 4 mhz 8.45 11.8 wake up time from stop 0 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 1.5 2.9 wakeup clock hsi16 = 16 mhz 2.4 2.76 range 2 wakeup clock msi = 24 mhz 2.4 3.48 wakeup clock hsi16 = 16 mhz 2.4 2.76 wakeup clock msi = 4 mhz 8.16 10.94 t wustop1 wake up time from stop 1 mode to run in flash range 1 wakeup clock msi = 48 mhz 6.34 7.86 s wakeup clock hsi16 = 16 mhz 6.84 8.23 range 2 wakeup clock msi = 24 mhz 6.74 8.1 wakeup clock hsi16 = 16 mhz 6.89 8.21 wakeup clock msi = 4 mhz 10.47 12.1 wake up time from stop 1 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 4.7 5.97 wakeup clock hsi16 = 16 mhz 5.9 6.92 range 2 wakeup clock msi = 24 mhz 5.4 6.51 wakeup clock hsi16 = 16 mhz 5.9 6.92 wakeup clock msi = 4 mhz 11.1 12.2 wake up time from stop 1 mode to low-power run mode in flash regulator in low-power mode (lpr=1 in pwr_cr1) wakeup clock msi = 2 mhz 16.4 17.73 wake up time from stop 1 mode to low-power run mode in sram1 17.3 18.82 table 38. low-power mode wakeup timings (1) (continued) symbol parameter conditions typ max unit electrical characteristics STM32L432KB stm3l432kc 86/149 docid028798 rev 2 t wustop2 wake up time from stop 2 mode to run mode in flash range 1 wakeup clock msi = 48 mhz 8.02 9.24 s wakeup clock hsi16 = 16 mhz 7.66 8.95 range 2 wakeup clock msi = 24 mhz 8.5 9.54 wakeup clock hsi16 = 16 mhz 7.75 8.95 wakeup clock msi = 4 mhz 12.06 13.16 wake up time from stop 2 mode to run mode in sram1 range 1 wakeup clock msi = 48 mhz 5.45 6.79 wakeup clock hsi16 = 16 mhz 6.9 7.98 range 2 wakeup clock msi = 24 mhz 6.3 7.36 wakeup clock hsi16 = 16 mhz 6.9 7.9 wakeup clock msi = 4 mhz 13.1 13.31 t wustby wakeup time from standby mode to run mode range 1 wakeup clock msi = 8 mhz 12.2 18.35 s wakeup clock msi = 4 mhz 19.14 25.8 t wustby sram2 wakeup time from standby with sram2 to run mode range 1 wakeup clock msi = 8 mhz 12.1 18.3 s wakeup clock msi = 4 mhz 19.2 25.87 t wushdn wakeup time from shutdown mode to run mode range 1 wakeup clock msi = 4 mhz 261.5 315.7 s 1. guaranteed by characterization results. table 38. low-power mode wakeup timings (1) (continued) symbol parameter conditions typ max unit table 39. regulator modes transition times (1) symbol parameter conditions typ max unit t wulprun wakeup time from low-power run mode to run mode (2) code run with msi 2 mhz 5 7 s t vost regulator transition time from range 2 to range 1 or range 1 to range 2 (3) code run with msi 24 mhz 20 40 1. guaranteed by characterization results. 2. time until reglpf flag is cleared in pwr_sr2. 3. time until vosf flag is cleared in pwr_sr2. table 40. wakeup time using usart/lpuart (1) symbol parameter conditions typ max unit t wuusart t wulpuart wakeup time needed to calculate the maximum usart/lpuart baudrate allowing to wakeup up from stop mode when usart/lpuart clock source is hsi stop mode 0 - 1.7 s stop mode 1/2 - 8.5 1. guaranteed by design. docid028798 rev 2 87/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.7 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 11: high-speed external clock source ac timing diagram . figure 11. high-speed external cl ock source ac timing diagram table 41. high-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f hse_ext user external clock source frequency voltage scaling range 1 -848 mhz voltage scaling range 2 -826 v hseh ck_in input pin high level voltage - 0.7 v ddiox -v ddiox v v hsel ck_in input pin low level voltage - v ss - 0.3 v ddiox t w(hseh) t w(hsel) ck_in high or low time voltage scaling range 1 7- - ns voltage scaling range 2 18 - - 1. guaranteed by design. 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / electrical characteristics STM32L432KB stm3l432kc 88/149 docid028798 rev 2 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switch ed off and the input pin is a standard gpio. the external clock signal has to respect the i/o characteristics in section 6.3.14 . however, the recommended clock inpu t waveform is shown in figure 12 . figure 12. low-speed external clock source ac timing diagram low-speed external clock generated from a crystal resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal resonator oscillator. all the information gi ven in this paragraph are based on design simulation results obtained with typical external components specified in table 43 . in the application, the resonator and the load capa citors have to be placed as cl ose as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time . refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). table 42. low-speed external user clock characteristics (1) symbol parameter conditions min typ max unit f lse_ext user external clock source frequency - - 32.768 1000 khz v lseh osc32_in input pin high level voltage - 0.7 v ddiox -v ddiox v v lsel osc32_in input pin low level voltage - v ss -0.3 v ddiox t w(lseh) t w(lsel) osc32_in high or low time - 250 - - ns 1. guaranteed by design. 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / docid028798 rev 2 89/149 STM32L432KB stm3l432kc electrical characteristics 142 note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 13. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. table 43. lse oscillator characteristics (f lse = 32.768 khz) (1) symbol parameter conditions (2) min typ max unit i dd(lse) lse current consumption lsedrv[1:0] = 00 low drive capability -250- na lsedrv[1:0] = 01 medium low drive capability -315- lsedrv[1:0] = 10 medium high drive capability -500- lsedrv[1:0] = 11 high drive capability -630- gm critmax maximum critical crystal gm lsedrv[1:0] = 00 low drive capability --0.5 a/v lsedrv[1:0] = 01 medium low drive capability - - 0.75 lsedrv[1:0] = 10 medium high drive capability --1.7 lsedrv[1:0] = 11 high drive capability --2.7 t su(lse) (3) startup time v dd is stabilized - 2 - s 1. guaranteed by design. 2. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 3. t su(lse) is the startup time measured from the moment it is en abled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i / 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics STM32L432KB stm3l432kc 90/149 docid028798 rev 2 6.3.8 internal clock source characteristics the parameters given in table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . the provided curves are characterization results, not tested in production. high-speed internal (hsi16) rc oscillator table 44. hsi16 oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi16 hsi16 frequency v dd =3.0 v, t a =30 c 15.88 - 16.08 mhz trim hsi16 user trimming step trimming code is not a multiple of 64 0.2 0.3 0.4 % trimming code is a multiple of 64 -4 -6 -8 ducy(hsi16) (2) duty cycle - 45 - 55 % ? te m p (hsi16) hsi16 oscillator frequency drift over temperature t a = 0 to 85 c -1 - 1 % t a = -40 to 125 c -2 - 1.5 % ? vdd (hsi16) hsi16 oscillator frequency drift over v dd v dd =1.62 v to 3.6 v -0.1 - 0.05 % t su (hsi16) (2) hsi16 oscillator start-up time --0.81.2 s t stab (hsi16) (2) hsi16 oscillator stabilization time --35 s i dd (hsi16) (2) hsi16 oscillator power consumption - - 155 190 a 1. guaranteed by characterization results. 2. guaranteed by design. docid028798 rev 2 91/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 14. hsi16 frequency versus temperature 0 6 y 9 0 + ] p l q p h d q p d [ ? & electrical characteristics STM32L432KB stm3l432kc 92/149 docid028798 rev 2 multi-speed internal (msi) rc oscillator table 45. msi oscillator characteristics (1) symbol parameter conditions min typ max unit f msi msi frequency after factory calibration, done at v dd =3 v and t a =30 c msi mode range 0 98.7 100 101.3 khz range 1 197.4 200 202.6 range 2 394.8 400 405.2 range 3 789.6 800 810.4 range 4 0.987 1 1.013 mhz range 5 1.974 2 2.026 range 6 3.948 4 4.052 range 7 7.896 8 8.104 range 8 15.79 16 16.21 range 9 23.69 24 24.31 range 10 31.58 32 32.42 range 11 47.38 48 48.62 pll mode xtal= 32.768 khz range 0 - 98.304 - khz range 1 - 196.608 - range 2 - 393.216 - range 3 - 786.432 - range 4 - 1.016 - mhz range 5 - 1.999 - range 6 - 3.998 - range 7 - 7.995 - range 8 - 15.991 - range 9 - 23.986 - range 10 - 32.014 - range 11 - 48.005 - ? temp (msi) (2) msi oscillator frequency drift over temperature msi mode t a = -0 to 85 c -3.5 - 3 % t a = -40 to 125 c -8 - 6 docid028798 rev 2 93/149 STM32L432KB stm3l432kc electrical characteristics 142 ? vdd (msi) (2) msi oscillator frequency drift over v dd (reference is 3 v) msi mode range 0 to 3 v dd =1.62 v to 3.6 v -1.2 - 0.5 % v dd =2.4 v to 3.6 v -0.5 - range 4 to 7 v dd =1.62 v to 3.6 v -2.5 - 0.7 v dd =2.4 v to 3.6 v -0.8 - range 8 to 11 v dd =1.62 v to 3.6 v -5 - 1 v dd =2.4 v to 3.6 v -1.6 - ? f sampling (msi) (2)(6) frequency variation in sampling mode (3) msi mode t a = -40 to 85 c - 1 2 % t a = -40 to 125 c - 2 4 p_usb jitter(msi) (6) period jitter for usb clock (4) pll mode range 11 for next transition ---3.458 ns for paired transition ---3.916 mt_usb jitter(msi) (6) medium term jitter for usb clock (5) pll mode range 11 for next transition ---2 ns for paired transition ---1 cc jitter(msi) (6) rms cycle-to- cycle jitter pll mode range 11 - - 60 - ps p jitter(msi) (6) rms period jitter pll mode range 11 - - 50 - ps t su (msi) (6) msi oscillator start-up time range 0 - - 10 20 us range 1 - - 5 10 range 2 - - 4 8 range 3 - - 3 7 range 4 to 7 - - 3 6 range 8 to 11 - - 2.5 6 t stab (msi) (6) msi oscillator stabilization time pll mode range 11 10 % of final frequency - - 0.25 0.5 ms 5 % of final frequency --0.51.25 1 % of final frequency ---2.5 table 45. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics STM32L432KB stm3l432kc 94/149 docid028798 rev 2 i dd (msi) (6) msi oscillator power consumption msi and pll mode range 0 - - 0.6 1 a range 1 - - 0.8 1.2 range 2 - - 1.2 1.7 range 3 - - 1.9 2.5 range 4 - - 4.7 6 range 5 - - 6.5 9 range 6 - - 11 15 range 7 - - 18.5 25 range 8 - - 62 80 range 9 - - 85 110 range 10 - - 110 130 range 11 - - 155 190 1. guaranteed by characterization results. 2. this is a deviation for an individual part once the init ial frequency has been measured. 3. sampling mode means low-power run/low-power sleep modes with temper ature sensor disable. 4. average period of msi @48 mhz is compared to a real 48 mh z clock over 28 cycles. it includ es frequency tolerance + jitter of msi @48 mhz clock. 5. only accumulated jitter of msi @48 mhz is extracted over 28 cycles. for next transition: min. and max. jitter of 2 consecutive frame of 28 cycles of th e msi @48 mhz, for 1000 captures over 28 cycles. for paired transitions: min. and max. jitte r of 2 consecutive frame of 56 cycles of the msi @48 mhz, for 1000 captures over 56 cycles. 6. guaranteed by design. table 45. msi oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit docid028798 rev 2 95/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 15. typical current consumption versus msi frequency high-speed internal 48 mhz (hsi48) rc oscillator table 46. hsi48 oscillator characteristics (1) symbol parameter conditions min typ max unit f hsi48 hsi48 frequency v dd =3.0v, t a =30c - 48 - mhz trim hsi48 user trimming step - - 0.11 (2) 0.18 (2) % user trim coverage hsi48 user trimming coverage 32 steps 3 (3) 3.5 (3) -% ducy(hsi48) duty cycle - 45 (2) -55 (2) % acc hsi48_rel accuracy of the hsi48 oscillator over temperature (factory calibrated) v dd = 3.0 v to 3.6 v, t a = ?15 to 85 c --3 (3) % v dd = 1.65 v to 3.6 v, t a = ?40 to 125 c --4.5 (3) d vdd (hsi48) hsi48 oscillator frequency drift with v dd v dd = 3 v to 3.6 v - 0.025 (3) 0.05 (3) % v dd = 1.65 v to 3.6 v - 0.05 (3) 0.1 (3) t su (hsi48) hsi48 oscillator start-up time - - 2.5 (2) 6 (2) s i dd (hsi48) hsi48 oscillator power consumption --340 (2) 380 (2) a electrical characteristics STM32L432KB stm3l432kc 96/149 docid028798 rev 2 figure 16. hsi48 frequency versus temperature low-speed internal (lsi) rc oscillator n t jitter next transition jitter accumulated jitter on 28 cycles (4) --+/-0.15 (2) -ns p t jitter paired transition jitter accumulated jitter on 56 cycles (4) --+/-0.25 (2) -ns 1. v dd = 3 v, t a = ?40 to 125c unless otherwise specified. 2. guaranteed by design. 3. guaranteed by characterization results. 4. jitter measurement are performed without clock source activated in parallel. table 46. hsi48 oscillator characteristics (1) (continued) symbol parameter conditions min typ max unit 0 6 y 9 $ y j p l q p d [ ? & table 47. lsi oscillator characteristics (1) symbol parameter conditions min typ max unit f lsi lsi frequency v dd = 3.0 v, t a = 30 c 31.04 - 32.96 khz v dd = 1.62 to 3.6 v, ta = -40 to 125 c 29.5 - 34 t su (lsi) (2) lsi oscillator start- up time --80130 s t stab (lsi) (2) lsi oscillator stabilization time 5% of final frequency - 125 180 s i dd (lsi) (2) lsi oscillator power consumption --110180na 1. guaranteed by characterization results. 2. guaranteed by design. docid028798 rev 2 97/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.9 pll characteristics the parameters given in table 48 are derived from tests performed under temperature and v dd supply voltage conditions summarized in table 20: general operating conditions . table 48. pll, pllsai1 characteristics (1) symbol parameter conditions min typ max unit f pll_in pll input clock (2) -4-16mhz pll input clock duty cycle - 45 - 55 % f pll_p_out pll multiplier output clock p voltage scaling range 1 3.0968 - 80 mhz voltage scaling range 2 3.0968 - 26 f pll_q_out pll multiplier output clock q voltage scaling range 1 12 - 80 mhz voltage scaling range 2 12 - 26 f pll_r_out pll multiplier output clock r voltage scaling range 1 12 - 80 mhz voltage scaling range 2 12 - 26 f vco_out pll vco output voltage scaling range 1 96 - 344 mhz voltage scaling range 2 96 - 128 t lock pll lock time - - 15 40 s jitter rms cycle-to-cycle jitter system clock 80 mhz -40- ps rms period jitter - 30 - i dd (pll) pll power consumption on v dd (1) vco freq = 96 mhz - 200 260 a vco freq = 192 mhz - 300 380 vco freq = 344 mhz - 520 650 1. guaranteed by design. 2. take care of using the appropriate division factor m to obtai n the specified pll input clock values. the m factor is shared between the 2 plls. electrical characteristics STM32L432KB stm3l432kc 98/149 docid028798 rev 2 6.3.10 flash memory characteristics table 49. flash memory characteristics (1) 1. guaranteed by design. symbol parameter conditions typ max unit t prog 64-bit programming time - 81.69 90.76 s t prog_row one row (32 double word) programming time normal programming 2.61 2.90 ms fast programming 1.91 2.12 t prog_page one page (2 kbyte) programming time normal programming 20.91 23.24 fast programming 15.29 16.98 t erase page (2 kb) erase time - 22.02 24.47 t prog_bank one bank (512 kbyte) programming time normal programming 5.35 5.95 s fast programming 3.91 4.35 t me mass erase time (one or two banks) - 22.13 24.59 ms i dd average consumption from v dd write mode 3.4 - ma erase mode 3.4 - maximum current (peak) write mode 7 (for 2 s) - erase mode 7 (for 41 s) - table 50. flash memory endurance and data retention symbol parameter conditions min (1) 1. guaranteed by characterization results. unit n end endurance t a = ?40 to +105 c 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 15 1 kcycle (2) at t a = 125 c 7 10 kcycles (2) at t a = 55 c 30 10 kcycles (2) at t a = 85 c 15 10 kcycles (2) at t a = 105 c 10 docid028798 rev 2 99/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.11 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 51 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 51. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f hclk = 80 mhz, conforming to iec 61000-4-4 5a electrical characteristics STM32L432KB stm3l432kc 100/149 docid028798 rev 2 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.12 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the ansi/jedec standard. table 52. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8 mhz/ 80 mhz s emi peak level v dd = 3.6 v, t a = 25 c, ufqfpn32 package compliant with iec 61967-2 0.1 mhz to 30 mhz 1 dbv 30 mhz to 130 mhz 0 130 mhz to 1 ghz -1 1 ghz to 2 ghz 7 emi level 1 - table 53. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to ansi/esda/jedec js-001 2 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to ansi/esd stm5.3.1 c3 250 docid028798 rev 2 101/149 STM32L432KB stm3l432kc electrical characteristics 142 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.13 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v ddiox (for standard, 3.3 v-capable i/o pins) should be avoided during normal product operation. however, in order to gi ve an indication of the robustness of the microcontroller in cases when abnormal injection a ccidentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of the -5 a/+0 a range) or other functional failure (for example reset occurrence or oscillator freque ncy deviation). the characterization results are given in table 55 . negative induced leakage current is caused by negative injection and positive induced leakage current is caused by positive injection. table 54. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii table 55. i/o current injection susceptibility (1) 1. guaranteed by characterization results. symbol description functional susceptibility unit negative injection positive injection i inj injected current on all pins except pa4, pa5 -5 na ma injected current on pa4, pa5 pins -5 0 electrical characteristics STM32L432KB stm3l432kc 102/149 docid028798 rev 2 6.3.14 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 56 are derived from tests performed under the conditions summarized in table 20: general operating conditions . all i/os are designed as cmos- and ttl-compliant. table 56. i/o static characteristics symbol parameter conditions min typ max unit v il (1) i/o input low level voltage 1.62 v electrical characteristics STM32L432KB stm3l432kc 104/149 docid028798 rev 2 in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v ddiox, plus the maximum consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 17: voltage characteristics ). ? the sum of the currents sunk by all the i/os on v ss , plus the maximu m consumption of the mcu sunk on v ss , cannot exceed the absolute maximum rating i vss (see table 17: voltage characteristics ). output voltage levels unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . all i/os are cmos- and ttl -compliant (ft or tt unless otherwise specified). input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 18 and table 58 , respectively. table 57. output voltage characteristics (1) symbol parameter conditions min max unit v ol output low level voltage for an i/o pin cmos port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v v oh output high level voltage for an i/o pin v ddiox -0.4 - v ol (3) output low level voltage for an i/o pin ttl port (2) |i io | = 8 ma v ddiox 2.7 v -0.4 v oh (3) output high level voltage for an i/o pin 2.4 - v ol (3) output low level voltage for an i/o pin |i io | = 20 ma v ddiox 2.7 v -1.3 v oh (3) output high level voltage for an i/o pin v ddiox -1.3 - v ol (3) output low level voltage for an i/o pin |i io | = 4 ma v ddiox 1.62 v -0.45 v oh (3) output high level voltage for an i/o pin v ddiox -0.45 - v ol (3) output low level voltage for an i/o pin |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.35 ? v ddiox v oh (3) output high level voltage for an i/o pin 0.65 ? v ddiox - v olfm+ (3) output low level voltage for an ft i/o pin in fm+ mode (ft i/o with "f" option) |i io | = 20 ma v ddiox 2.7 v -0.4 |i io | = 10 ma v ddiox 1.62 v -0.4 |i io | = 2 ma 1.62 v v ddiox 1.08 v -0.4 1. the i io current sourced or sunk by the device must alwa ys respect the absolute maxi mum rating specified in table 17: voltage characteristics , and the sum of the currents sourced or sunk by all the i/os (i/o ports and control pins) must always respect the absolute maximum ratings i io . 2. ttl and cmos outputs are compatible with jedec standards jesd36 and jesd52. 3. guaranteed by design. docid028798 rev 2 105/149 STM32L432KB stm3l432kc electrical characteristics 142 unless otherwise specified, th e parameters given are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . table 58. i/o ac characteristics (1)(2) speed symbol parameter conditions min max unit 00 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 5 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 1 c=50 pf, 1.08 v v ddiox 1.62 v - 0.1 c=10 pf, 2.7 v v ddiox 3.6 v - 10 c=10 pf, 1.62 v v ddiox 2.7 v - 1.5 c=10 pf, 1.08 v v ddiox 1.62 v - 0.1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 25 ns c=50 pf, 1.62 v v ddiox 2.7 v - 52 c=50 pf, 1.08 v v ddiox 1.62 v - 140 c=10 pf, 2.7 v v ddiox 3.6 v - 17 c=10 pf, 1.62 v v ddiox 2.7 v - 37 c=10 pf, 1.08 v v ddiox 1.62 v - 110 01 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 25 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 10 c=50 pf, 1.08 v v ddiox 1.62 v - 1 c=10 pf, 2.7 v v ddiox 3.6 v - 50 c=10 pf, 1.62 v v ddiox 2.7 v - 15 c=10 pf, 1.08 v v ddiox 1.62 v - 1 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 9 ns c=50 pf, 1.62 v v ddiox 2.7 v - 16 c=50 pf, 1.08 v v ddiox 1.62 v - 40 c=10 pf, 2.7 v v ddiox 3.6 v - 4.5 c=10 pf, 1.62 v v ddiox 2.7 v - 9 c=10 pf, 1.08 v v ddiox 1.62 v - 21 electrical characteristics STM32L432KB stm3l432kc 106/149 docid028798 rev 2 10 fmax maximum frequency c=50 pf, 2.7 v v ddiox 3.6 v - 50 mhz c=50 pf, 1.62 v v ddiox 2.7 v - 25 c=50 pf, 1.08 v v ddiox 1.62 v - 5 c=10 pf, 2.7 v v ddiox 3.6 v - 100 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 37.5 c=10 pf, 1.08 v v ddiox 1.62 v - 5 tr/tf output rise and fall time c=50 pf, 2.7 v v ddiox 3.6 v - 5.8 ns c=50 pf, 1.62 v v ddiox 2.7 v - 11 c=50 pf, 1.08 v v ddiox 1.62 v - 28 c=10 pf, 2.7 v v ddiox 3.6 v - 2.5 c=10 pf, 1.62 v v ddiox 2.7 v - 5 c=10 pf, 1.08 v v ddiox 1.62 v - 12 11 fmax maximum frequency c=30 pf, 2.7 v v ddiox 3.6 v - 120 (3) mhz c=30 pf, 1.62 v v ddiox 2.7 v - 50 c=30 pf, 1.08 v v ddiox 1.62 v - 10 c=10 pf, 2.7 v v ddiox 3.6 v - 180 (3) c=10 pf, 1.62 v v ddiox 2.7 v - 75 c=10 pf, 1.08 v v ddiox 1.62 v - 10 tr/tf output rise and fall time c=30 pf, 2.7 v v ddiox 3.6 v - 3.3 ns c=30 pf, 1.62 v v ddiox 2.7 v - 6 c=30 pf, 1.08 v v ddiox 1.62 v - 16 fm+ fmax maximum frequency c=50 pf, 1.6 v v ddiox 3.6 v -1mhz tf output fall time (4) -5ns 1. the i/o speed is configured using the ospeedry[1:0] bits. the fm+ mode is configured in the syscfg_cfgr1 register. refer to the rm0393 reference manual for a descr iption of gpio port configuration register. 2. guaranteed by design. 3. this value represents the i/o capability but t he maximum system frequency is limited to 80 mhz. 4. the fall time is defined between 70% and 30% of the output waveform accordingly to i 2 c specification. table 58. i/o ac characteristics (1)(2) (continued) speed symbol parameter conditions min max unit docid028798 rev 2 107/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 18. i/o ac characteristics definition (1) 1. refer to table 58: i/o ac characteristics . 6.3.15 nrst pin characteristics the nrst pin input driver uses the cmos technology. it is connected to a permanent pull- up resistor, r pu . unless otherwise specified, th e parameters given in the table below are derived from tests performed under the ambient temperature and supply voltage conditions summarized in table 20: general operating conditions . 0 6 9 7 0 d [ l p x p i u h t x h q f \ l v d f k l h y h g l i w w ? 7 d q g l i w k h g x w \ f \ f o h l v z k h q o r d g h g e \ w k h v s h f l i l h g f d s d f l w d q f h u i u , 2 r x w w i , 2 r x w w table 59. nrst pin characteristics (1) symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage ---0.3 ? v ddiox v v ih(nrst) nrst input high level voltage -0.7 ? v ddiox -- v hys(nrst) nrst schmitt trigger voltage hysteresis --200-mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k ? v f(nrst) nrst input filtered pulse ---70ns v nf(nrst) nrst input not filtered pulse 1.71 v v dd 3.6 v 350 - - ns 1. guaranteed by design. 2. the pull-up is designed with a true re sistance in series with a switchable pmos . this pmos contribution to the series resistance is minimal (~10% order) . electrical characteristics STM32L432KB stm3l432kc 108/149 docid028798 rev 2 figure 19. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 59: nrst pin characteristics . otherwise the reset will not be taken into account by the device. 3. the external capacitor on nrst must be placed as close as pos sible to the device. 6.3.16 analog switches booster 0 6 9 5 3 8 9 ' ' , q w h u q d o u h v h w ( [ w h u q d o u h v h w f l u f x l w 1 5 6 7 ) l o w h u ? ) table 60. analog switches booster characteristics (1) 1. guaranteed by design. symbol parameter min typ max unit v dd supply voltage 1.62 - 3.6 v t su(boost) booster startup time - - 240 s i dd(boost) booster consumption for 1.62 v v dd 2.0 v --250 a booster consumption for 2.0 v v dd 2.7 v --500 booster consumption for 2.7 v v dd 3 .6 v --900 docid028798 rev 2 109/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.17 analog-to-digital converter characteristics unless otherwise specified, the parameters given in table 61 are preliminary values derived from tests performed under ambient temperature, f pclk frequency and v dda supply voltage conditions su mmarized in table 20: general operating conditions . note: it is recommended to perform a calibration after each power-up. table 61. adc characteristics (1) (2) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v ref+ positive reference voltage v dda 2 v 2 - v dda v v dda < 2 v v dda v v ref- negative reference voltage -v ssa v f adc adc clock frequency range 1 - - 80 mhz range 2 - - 26 f s sampling rate for fast channels resolution = 12 bits - - 5.33 msps resolution = 10 bits - - 6.15 resolution = 8 bits - - 7.27 resolution = 6 bits - - 8.88 sampling rate for slow channels resolution = 12 bits - - 4.21 resolution = 10 bits - - 4.71 resolution = 8 bits - - 5.33 resolution = 6 bits - - 6.15 f trig external trigger frequency f adc = 80 mhz resolution = 12 bits - - 5.33 mhz resolution = 12 bits - - 15 1/f adc v cmin input common mode differential mode (v ref+ + v ref- )/2 - 0.18 (v ref+ + v ref- )/2 (v ref+ + v ref- )/2 + 0.18 v v ain (3) conversion voltage range(2) -0-v ref+ v r ain external input impedance - - - 50 k ? c adc internal sample and hold capacitor --5-pf t stab power-up time - 1 conversion cycle t cal calibration time f adc = 80 mhz 1.45 s -1161/f adc electrical characteristics STM32L432KB stm3l432kc 110/149 docid028798 rev 2 t latr trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2.0 ckmode = 10 - - 2.25 ckmode = 11 - - 2.125 t latrinj trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3.0 ckmode = 10 - - 3.25 ckmode = 11 - - 3.125 t s sampling time f adc = 80 mhz 0.03125 - 8.00625 s - 2.5 - 640.5 1/f adc t adcvreg_stup adc voltage regulator start-up time ---20 s t conv total conversion time (including sampling time) f adc = 80 mhz resolution = 12 bits 0.1875 - 8.1625 s resolution = 12 bits ts + 12.5 cycles for successive approximation = 15 to 653 1/f adc i dda (adc) adc consumption from the v dda supply fs = 5 msps - 730 830 a fs = 1 msps - 160 220 fs = 10 ksps - 16 50 i ddv_s (adc) adc consumption from the v ref+ single ended mode fs = 5 msps - 130 160 a fs = 1 msps - 30 40 fs = 10 ksps - 0.6 2 i ddv_d (adc) adc consumption from the v ref+ differential mode fs = 5 msps - 260 310 a fs = 1 msps - 60 70 fs = 10 ksps - 1.3 3 1. guaranteed by design 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pinouts and pin description for further details. table 61. adc characteristics (1) (2) (continued) symbol parameter conditions min typ max unit r ain t s f adc c adc 2 n2 + () ln --------------------------------------------------------------- - r adc ? < docid028798 rev 2 111/149 STM32L432KB stm3l432kc electrical characteristics 142 equation 1: r ain max formula the formula above ( equation 1 ) is used to dete rm ine the maximum external impedance allowed for an error below 1/4 of lsb. here n = 12 (from 12-bit resolution). table 62. maximum adc rain (1)(2) resolution sampling cycle @80 mhz sampling time [ns] @80 mhz rain max ( ? ) fast channels (3) slow channels (4) 12 bits 2.5 31.25 100 n/a 6.5 81.25 330 100 12.5 156.25 680 470 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 4700 3900 247.5 3093.75 12000 10000 640.5 8006.75 39000 33000 10 bits 2.5 31.25 120 n/a 6.5 81.25 390 180 12.5 156.25 820 560 24.5 306.25 1500 1200 47.5 593.75 2200 1800 92.5 1156.25 5600 4700 247.5 3093.75 12000 10000 640.5 8006.75 47000 39000 8 bits 2.5 31.25 180 n/a 6.5 81.25 470 270 12.5 156.25 1000 680 24.5 306.25 1800 1500 47.5 593.75 2700 2200 92.5 1156.25 6800 5600 247.5 3093.75 15000 12000 640.5 8006.75 50000 50000 electrical characteristics STM32L432KB stm3l432kc 112/149 docid028798 rev 2 6 bits 2.5 31.25 220 n/a 6.5 81.25 560 330 12.5 156.25 1200 1000 24.5 306.25 2700 2200 47.5 593.75 3900 3300 92.5 1156.25 8200 6800 247.5 3093.75 18000 15000 640.5 8006.75 50000 50000 1. guaranteed by design. 2. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4v). it is disable when v dda 2.4 v. 3. fast channels are: pc0, pc1, pc2, pc3, pa0, pa1. 4. slow channels are: all adc i nputs except the fast channels. table 62. maximum adc rain (1)(2) (continued) resolution sampling cycle @80 mhz sampling time [ns] @80 mhz rain max ( ) fast channels (3) slow channels (4) docid028798 rev 2 113/149 STM32L432KB stm3l432kc electrical characteristics 142 table 63. adc accuracy - limited test conditions 1 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = vref+ = 3 v, ta = 25 c single ended fast channel (max speed) - 4 5 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 3.5 4.5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 1 2.5 slow channel (max speed) - 1 2.5 differential fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 eg gain error single ended fast channel (max speed) - 2.5 4.5 slow channel (max speed) - 2.5 4.5 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 2.5 slow channel (max speed) - 1.5 2.5 differential fast channel (max speed) - 1 2 slow channel (max speed) - 1 2 enob effective number of bits single ended fast channel (max speed) 10.4 10.5 - bits slow channel (max speed) 10.4 10.5 - differential fast channel (max speed) 10.8 10.9 - slow channel (max speed) 10.8 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 64.4 65 - db slow channel (max speed) 64.4 65 - differential fast channel (max speed) 66.8 67.4 - slow channel (max speed) 66.8 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - differential fast channel (max speed) 67 68 - slow channel (max speed) 67 68 - electrical characteristics STM32L432KB stm3l432kc 114/149 docid028798 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, v dda = v ref+ = 3 v, ta = 25 c single ended fast channel (max speed) - -74 -73 db slow channel (max speed) - -74 -73 differential fast channel (max speed) - -79 -76 slow channel (max speed) - -79 -76 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 63. adc accuracy - limited test conditions 1 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit docid028798 rev 2 115/149 STM32L432KB stm3l432kc electrical characteristics 142 table 64. adc accuracy - limited test conditions 2 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - 4 6.5 lsb slow channel (max speed) - 4 6.5 differential fast channel (max speed) - 3.5 5.5 slow channel (max speed) - 3.5 5.5 eo offset error single ended fast channel (max speed) - 1 4.5 slow channel (max speed) - 1 5 differential fast channel (max speed) - 1.5 3 slow channel (max speed) - 1.5 3 eg gain error single ended fast channel (max speed) - 2.5 6 slow channel (max speed) - 2.5 6 differential fast channel (max speed) - 2.5 3.5 slow channel (max speed) - 2.5 3.5 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 1.5 3.5 slow channel (max speed) - 1.5 3.5 differential fast channel (max speed) - 1 3 slow channel (max speed) - 1 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.5 - bits slow channel (max speed) 10 10.5 - differential fast channel (max speed) 10.7 10.9 - slow channel (max speed) 10.7 10.9 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 65 - db slow channel (max speed) 62 65 - differential fast channel (max speed) 66 67.4 - slow channel (max speed) 66 67.4 - snr signal-to- noise ratio single ended fast channel (max speed) 64 66 - slow channel (max speed) 64 66 - differential fast channel (max speed) 66.5 68 - slow channel (max speed) 66.5 68 - electrical characteristics STM32L432KB stm3l432kc 116/149 docid028798 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 2 v v dda single ended fast channel (max speed) - -74 -65 db slow channel (max speed) - -74 -67 differential fast channel (max speed) - -79 -70 slow channel (max speed) - -79 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 64. adc accuracy - limited test conditions 2 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit docid028798 rev 2 117/149 STM32L432KB stm3l432kc electrical characteristics 142 table 65. adc accuracy - limited test conditions 3 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - 5.5 7.5 lsb slow channel (max speed) - 4.5 6.5 differential fast channel (max speed) - 4.5 7.5 slow channel (max speed) - 4.5 5.5 eo offset error single ended fast channel (max speed) - 2 5 slow channel (max speed) - 2.5 5 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2.5 3 eg gain error single ended fast channel (max speed) - 4.5 7 slow channel (max speed) - 3.5 6 differential fast channel (max speed) - 3.5 4 slow channel (max speed) - 3.5 5 ed differential linearity error single ended fast channel (max speed) - 1.2 1.5 slow channel (max speed) - 1.2 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 3 3.5 slow channel (max speed) - 2.5 3.5 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10 10.4 - bits slow channel (max speed) 10 10.4 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 62 64 - db slow channel (max speed) 62 64 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 63 65 - slow channel (max speed) 63 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 - electrical characteristics STM32L432KB stm3l432kc 118/149 docid028798 rev 2 thd to ta l harmonic distortion adc clock frequency 80 mhz, sampling rate 5.33 msps, 1.65 v v dda = v ref+ 3.6 v, voltage scaling range 1 single ended fast channel (max speed) - -69 -67 db slow channel (max speed) - -71 -67 differential fast channel (max speed) - -72 -71 slow channel (max speed) - -72 -71 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 65. adc accuracy - limited test conditions 3 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit docid028798 rev 2 119/149 STM32L432KB stm3l432kc electrical characteristics 142 table 66. adc accuracy - limited test conditions 4 (1)(2)(3) sym- bol parameter conditions (4) min typ max unit et to ta l unadjusted error adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - 5 5.4 lsb slow channel (max speed) - 4 5 differential fast channel (max speed) - 4 5 slow channel (max speed) - 3.5 4.5 eo offset error single ended fast channel (max speed) - 2 4 slow channel (max speed) - 2 4 differential fast channel (max speed) - 2 3.5 slow channel (max speed) - 2 3.5 eg gain error single ended fast channel (max speed) - 4 4.5 slow channel (max speed) - 4 4.5 differential fast channel (max speed) - 3 4 slow channel (max speed) - 3 4 ed differential linearity error single ended fast channel (max speed) - 1 1.5 slow channel (max speed) - 1 1.5 differential fast channel (max speed) - 1 1.2 slow channel (max speed) - 1 1.2 el integral linearity error single ended fast channel (max speed) - 2.5 3 slow channel (max speed) - 2.5 3 differential fast channel (max speed) - 2 2.5 slow channel (max speed) - 2 2.5 enob effective number of bits single ended fast channel (max speed) 10.2 10.5 - bits slow channel (max speed) 10.2 10.5 - differential fast channel (max speed) 10.6 10.7 - slow channel (max speed) 10.6 10.7 - sinad signal-to- noise and distortion ratio single ended fast channel (max speed) 63 65 - db slow channel (max speed) 63 65 - differential fast channel (max speed) 65 66 - slow channel (max speed) 65 66 - snr signal-to- noise ratio single ended fast channel (max speed) 64 65 - slow channel (max speed) 64 65 - differential fast channel (max speed) 66 67 - slow channel (max speed) 66 67 - electrical characteristics STM32L432KB stm3l432kc 120/149 docid028798 rev 2 figure 20. adc accuracy characteristics thd to ta l harmonic distortion adc clock frequency 26 mhz, 1.65 v v dda = vref+ 3.6 v, voltage scaling range 2 single ended fast channel (max speed) - -71 -69 db slow channel (max speed) - -71 -69 differential fast channel (max speed) - -73 -72 slow channel (max speed) - -73 -72 1. guaranteed by design. 2. adc dc accuracy values are measured after internal calibration. 3. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. 4. the i/o analog switch voltage booster is enable when v dda < 2.4 v (boosten = 1 in the syscfg_cfgr1 when v dda < 2.4 v). it is disable when v dda 2.4 v. no oversampling. table 66. adc accuracy - limited test conditions 4 (1)(2)(3) (continued) sym- bol parameter conditions (4) min typ max unit ( 7 7 r w d o 8 q d m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h i l u v w l g h d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h v ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h 9 ' ' $ 9 6 6 $ ( 2 ( 7 ( / ( * ( ' / 6 % , ' ( $ / 0 6 9 docid028798 rev 2 121/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 21. typical connecti on diagram using the adc 1. refer to table 61: adc characteristics for the values of r ain , r adc and c adc . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (refer to table 56: i/o static characteristics for the value of the pad capacitance). a high c parasitic value will downgrade conversion a ccuracy. to remedy this, f adc should be reduced. 3. refer to table 56: i/o static characteristics for the values of ilkg. general pcb design guidelines power supply decoupling should be performed as shown in figure 8: power supply scheme . the 10 nf capacitor should be ceramic (good qualit y) and it should be placed as close as possible to the chip. 0 6 9 6 d p s o h d q g k r o g $ ' & f r q y h u w h u e l w f r q y h u w h u & s d u d v l w l f , o n j 9 7 & $ ' & 9 ' ' $ 5 $ , 1 9 $ , 1 9 7 $ , 1 [ 5 $ ' & electrical characteristics STM32L432KB stm3l432kc 122/149 docid028798 rev 2 6.3.18 digital-to-analog converter characteristics table 67. dac characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage for dac on - 1.8 - 3.6 v v ref+ positive reference voltage - 1.8 - v dda v ref- negative reference voltage -v ssa r l resistive load dac output buffer on connected to v ssa 5- - k ? connected to v dda 25 - - r o output impedance dac output buffer off 9.6 11.7 13.8 k ? r bon output impedance sample and hold mode, output buffer on v dd = 2.7 v - - 2 k ? v dd = 2.0 v - - 3.5 r boff output impedance sample and hold mode, output buffer off v dd = 2.7 v - - 16.5 k ? v dd = 2.0 v - - 18.0 c l capacitive load dac output buffer on - - 50 pf c sh sample and hold mode - 0.1 1 f v dac_out voltage on dac_out output dac output buffer on 0.2 - v ref+ ? 0.2 v dac output buffer off 0 - v ref+ t settling settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes when dac_out reaches final value 0.5lsb, 1 lsb, 2 lsb, 4 lsb, 8 lsb) normal mode dac output buffer on cl 50 pf, rl 5 k ? 0.5 lsb - 1.7 3 s 1 lsb - 1.6 2.9 2 lsb - 1.55 2.85 4 lsb - 1.48 2.8 8 lsb - 1.4 2.75 normal mode dac output buffer off, 1lsb, cl = 10 pf -22.5 t wakeup (2) wakeup time from off state (setting the enx bit in the dac control register) until final value 1 lsb normal mode dac output buffer on cl 50 pf, rl 5 k ? -4.27.5 s normal mode dac output buffer off, cl 10 pf -2 5 psrr v dda supply rejection ratio normal mode dac output buffer on cl 50 pf, rl = 5 k ? , dc --80-28db docid028798 rev 2 123/149 STM32L432KB stm3l432kc electrical characteristics 142 t samp sampling time in sample and hold mode (code transition between the lowest input code and the highest input code when dacout reaches final value 1lsb) dac_out pin connected dac output buffer on, c sh = 100 nf -0.73.5 ms dac output buffer off, c sh = 100 nf -10.5 18 dac_out pin not connected (internal connection only) dac output buffer off -23.5s i leak output leakage current sample and hold mode, dac_out pin connected -- - (3) na ci int internal sample and hold capacitor - 5.2 7 8.8 pf t trim middle code offset trim time dac output buffer on 50 - - s v offset middle code offset for 1 trim code step v ref+ = 3.6 v - 1500 - v v ref+ = 1.8 v - 750 - i dda (dac) dac consumption from v dda dac output buffer on no load, middle code (0x800) - 315 500 a no load, worst code (0xf1c) - 450 670 dac output buffer off no load, middle code (0x800) --0.2 sample and hold mode, c sh = 100 nf - 315 ? ton/(ton +toff) (4) 670 ? ton/(ton +toff) (4) i ddv (dac) dac consumption from v ref+ dac output buffer on no load, middle code (0x800) - 185 240 a no load, worst code (0xf1c) - 340 400 dac output buffer off no load, middle code (0x800) - 155 205 sample and hold mode, buffer on, c sh = 100 nf, worst case - 185 ? ton/(ton +toff) (4) 400 ? ton/(ton +toff) (4) sample and hold mode, buffer off, c sh = 100 nf, worst case - 155 ? ton/(ton +toff) (4) 205 ? ton/(ton +toff) (4) 1. guaranteed by design. 2. in buffered mode, the output can overshoot above the final value for low input code (starting from min value). table 67. dac characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics STM32L432KB stm3l432kc 124/149 docid028798 rev 2 figure 22. 12-bit buffered / non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. . 3. refer to table 56: i/o static characteristics . 4. ton is the refresh phase duration. toff is the hold phase duration. refer to rm0393 reference manual for more details. % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u % x i i h u h g q r q e x i i h u h g ' $ & ' $ & [ b 2 8 7 5 / 2 $ ' & / 2 $ ' d l g table 68. dac accuracy (1) symbol parameter conditions min typ max unit dnl differential non linearity (2) dac output buffer on - - 2 lsb dac output buffer off - - 2 - monotonicity 10 bits guaranteed inl integral non linearity (3) dac output buffer on cl 50 pf, rl 5 k ? --4 dac output buffer off cl 50 pf, no rl --4 offset offset error at code 0x800 (3) dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 12 v ref+ = 1.8 v - - 25 dac output buffer off cl 50 pf, no rl --8 offset1 offset error at code 0x001 (4) dac output buffer off cl 50 pf, no rl --5 offsetcal offset error at code 0x800 after calibration dac output buffer on cl 50 pf, rl 5 k ? v ref+ = 3.6 v - - 5 v ref+ = 1.8 v - - 7 docid028798 rev 2 125/149 STM32L432KB stm3l432kc electrical characteristics 142 gain gain error (5) dac output buffer on cl 50 pf, rl 5 k ? --0.5 % dac output buffer off cl 50 pf, no rl --0.5 tue to ta l unadjusted error dac output buffer on cl 50 pf, rl 5 k ? --30 lsb dac output buffer off cl 50 pf, no rl --12 tuecal to ta l unadjusted error after calibration dac output buffer on cl 50 pf, rl 5 k ? --23lsb snr signal-to-noise ratio dac output buffer on cl 50 pf, rl 5 k ? 1 khz, bw 500 khz -71.2- db dac output buffer off cl 50 pf, no rl, 1 khz bw 500 khz -71.6- thd total harmonic distortion dac output buffer on cl 50 pf, rl 5 k ? , 1 khz --78- db dac output buffer off cl 50 pf, no rl, 1 khz --79- sinad signal-to-noise and distortion ratio dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -70.4- db dac output buffer off cl 50 pf, no rl, 1 khz -71- enob effective number of bits dac output buffer on cl 50 pf, rl 5 k ? , 1 khz -11.4- bits dac output buffer off cl 50 pf, no rl, 1 khz -11.5- 1. guaranteed by design. 2. difference between two consecutive codes - 1 lsb. 3. difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 4095. 4. difference between the value measured at code (0x001) and the ideal value. 5. difference between ideal slope of the transfer functi on and measured slope computed from code 0x000 and 0xfff when buffer is off, and from code giving 0.2 v and (v ref+ ? 0.2) v when buffer is on. table 68. dac accuracy (1) (continued) symbol parameter conditions min typ max unit electrical characteristics STM32L432KB stm3l432kc 126/149 docid028798 rev 2 6.3.19 comparator characteristics table 69. comp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage - 1.62 - 3.6 v v in comparator input voltage range -0-v dda v bg (2) scaler input voltage - v refint v sc scaler offset voltage - - 5 10 mv i dda (scaler) scaler static consumption from v dda brg_en=0 (bridge disable) - 200 300 na brg_en=1 (bridge enable) - 0.8 1 a t start_scaler scaler startup time - - 100 200 s t start comparator startup time to reach propagation delay specification high-speed mode v dda 2.7 v - - 5 s v dda < 2.7 v - - 7 medium mode v dda 2.7 v - - 15 v dda < 2.7 v - - 25 ultra-low-power mode - - 40 t d (3) propagation delay with 100 mv overdrive high-speed mode v dda 2.7 v - 55 80 ns v dda < 2.7 v - 65 100 medium mode - 0.55 0.9 s ultra-low-power mode - 4 7 v offset comparator offset error full common mode range --520mv v hys comparator hysteresis no hysteresis - 0 - mv low hysteresis - 8 - medium hysteresis - 15 - high hysteresis - 27 - i dda (comp) comparator consumption from v dda ultra-low- power mode static - 400 600 na with 50 khz 100 mv overdrive square signal -1200- medium mode static - 5 7 a with 50 khz 100 mv overdrive square signal -6- high-speed mode static - 70 100 with 50 khz 100 mv overdrive square signal -75- 1. guaranteed by design, unless otherwise specified. docid028798 rev 2 127/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.20 operational ampl ifiers characteristics 2. refer to table 23: embedded internal voltage reference . 3. guaranteed by characterization results. table 70. opamp characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage (2) -1.8-3.6v cmir common mode input range -0-v dda v vi offset input offset voltage 25 c, no load on output. - - 1.5 mv all voltage/temp. - - 3 ? vi offset input offset voltage drift normal mode - 5 - v/c low-power mode - 10 - trimoffsetp trimlpoffsetp offset trim step at low common input voltage (0.1 ? v dda ) --0.81.1 mv trimoffsetn trimlpoffsetn offset trim step at high common input voltage (0.9 ? v dda ) --11.35 i load drive current normal mode v dda 2 v - - 500 a low-power mode - - 100 i load_pga drive current in pga mode normal mode v dda 2 v - - 450 low-power mode - - 50 r load resistive load (connected to vssa or to vdda) normal mode v dda < 2 v 4- - k ? low-power mode 20 - - r load_pga resistive load in pga mode (connected to vssa or to v dda ) normal mode v dda < 2 v 4.5 - - low-power mode 40 - - c load capacitive load - - - 50 pf cmrr common mode rejection ratio normal mode - -85 - db low-power mode - -90 - psrr power supply rejection ratio normal mode c load 50 pf, r load 4 k ? dc 70 85 - db low-power mode c load 50 pf, r load 20 k ? dc 72 90 - electrical characteristics STM32L432KB stm3l432kc 128/149 docid028798 rev 2 gbw gain bandwidth product normal mode v dda 2.4 v (opa_range = 1) 550 1600 2200 khz low-power mode 100 420 600 normal mode v dda < 2.4 v (opa_range = 0) 250 700 950 low-power mode 40 180 280 sr (3) slew rate (from 10 and 90% of output voltage) normal mode v dda 2.4 v -700- v/ms low-power mode - 180 - normal mode v dda < 2.4 v -300- low-power mode - 80 - ao open loop gain normal mode 55 110 - db low-power mode 45 110 - v ohsat (3) high saturation voltage normal mode i load = max or r load = min input at v dda . v dda - 100 -- mv low-power mode v dda - 50 -- v olsat (3) low saturation voltage normal mode i load = max or r load = min input at 0. - - 100 low-power mode - - 50 m phase margin normal mode - 74 - low-power mode - 66 - gm gain margin normal mode - 13 - db low-power mode - 20 - t wakeup wake up time from off state. normal mode c load 50 pf, r load 4 k ? follower configuration -510 s low-power mode c load 50 pf, r load 20 k ? follower configuration -1030 i bias opamp input bias current general purpose input - - - (4) na pga gain (3) non inverting gain value - -2- - -4- -8- -16- table 70. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit docid028798 rev 2 129/149 STM32L432KB stm3l432kc electrical characteristics 142 r network r2/r1 internal resistance values in pga mode (5) pga gain = 2 - 80/80 - k ? /k ? pga gain = 4 - 120/ 40 - pga gain = 8 - 140/ 20 - pga gain = 16 - 150/ 10 - delta r resistance variation (r1 or r2) --15-15% pga gain error pga gain error - -1 - 1 % pga bw pga bandwidth for different non inverting gain gain = 2 - - gbw/ 2 - mhz gain = 4 - - gbw/ 4 - gain = 8 - - gbw/ 8 - gain = 16 - - gbw/ 16 - en voltage noise density normal mode at 1 khz, output loaded with 4 k ? -500- nv/ hz low-power mode at 1 khz, output loaded with 20 k ? -600- normal mode at 10 khz, output loaded with 4 k ? -180- low-power mode at 10 khz, output loaded with 20 k ? -290- i dda (opamp) (3) opamp consumption from v dda normal mode no load, quiescent mode - 120 260 a low-power mode - 45 100 1. guaranteed by design, unless otherwise specified. 2. the temperature range is limited to 0 c-125 c when v dda is below 2 v 3. guaranteed by characterization results. 4. mostly i/o leakage, when used in analog mode. refer to i lkg parameter in table 56: i/o static characteristics . 5. r2 is the internal resistance between opamp output and opam p inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 table 70. opamp characteristics (1) (continued) symbol parameter conditions min typ max unit electrical characteristics STM32L432KB stm3l432kc 130/149 docid028798 rev 2 6.3.21 temperature sensor characteristics 6.3.22 timer characteristics the parameters given in the followi ng tables are guaranteed by design. refer to section 6.3.14: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). table 71. ts characteristics symbol parameter min typ max unit t l (1) v ts linearity with temperature - 1 2 c avg_slope (2) average slope 2.3 2.5 2.7 mv/c v 30 voltage at 30c (5 c) (3) 0.742 0.76 0.785 v t start (ts_buf) (1) sensor buffer start-up time in continuous mode (4) -815s t start (1) start-up time when entering in continuous mode (4) -70120s t s_temp (1) adc sampling time when reading the temperature 5 - - s i dd (ts) (1) temperature sensor consumption from v dd , when selected by adc -4.77 a 1. guaranteed by design. 2. guaranteed by characterization results. 3. measured at v dda = 3.0 v 10 mv. the v 30 adc conversion result is stored in the ts_cal1 byte. refer to table 6: temperature sensor calibration values . 4. continuous mode means run/sleep modes, or temperature sensor enable in low-power run/low-power sleep modes. table 72. timx (1) characteristics 1. timx , is used as a general term in which x stands for 1,2,3,4,5,6,7,8,15,16 or 17. symbol parameter conditions min max unit t res(tim) timer resolution time -1-t timxclk f timxclk = 80 mhz 12.5 - ns f ext timer external clock frequency on ch1 to ch4 -0f timxclk /2 mhz f timxclk = 80 mhz 0 40 mhz res tim timer resolution timx (except tim2) -16 bit tim2 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 80 mhz 0.0125 819.2 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 80 mhz - 53.68 s docid028798 rev 2 131/149 STM32L432KB stm3l432kc electrical characteristics 142 6.3.23 communication interfaces characteristics i 2 c interface characteristics the i2c interface meets the timings requirements of the i 2 c-bus specification and user manual rev. 03 for: ? standard-mode (sm): with a bit rate up to 100 kbit/s ? fast-mode (fm): with a bit rate up to 400 kbit/s ? fast-mode plus (fm+): with a bit rate up to 1 mbit/s. the i2c timings requirements are guaranteed by design when the i2c peripheral is properly configured (refer to rm0393 reference manual). the sda and scl i/o requirements are met with the following restrictions: the sda and scl i/o pins are not ?true? open-drain. when configured as open-drain, the pmos connected between the i/o pin and v ddiox is disabled, but is still pr esent. only ft_f i/o pins support fm+ low level output current maximum requirement. refer to section 6.3.14: i/o port characteristics for the i2c i/os characteristics. all i2c sda and scl i/os embed an analog filter. refer to the table below for the analog filter characteristics: table 73. iwdg min/max timeout period at 32 khz (lsi) (1) 1. the exact timings still depend on the phasing of the apb in terface clock versus the lsi clock so that there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout rl[11:0]= 0x000 max timeout rl[11:0]= 0xfff unit /4 0 0.125 512 ms /8 1 0.250 1024 /16 2 0.500 2048 /32 3 1.0 4096 /64 4 2.0 8192 /128 5 4.0 16384 /256 6 or 7 8.0 32768 table 74. wwdg min/max timeout value at 80 mhz (pclk) prescaler wdgtb min timeout value max timeout value unit 1 0 0.0512 3.2768 ms 2 1 0.1024 6.5536 4 2 0.2048 13.1072 8 3 0.4096 26.2144 electrical characteristics STM32L432KB stm3l432kc 132/149 docid028798 rev 2 table 75. i2c analog filter characteristics (1) 1. guaranteed by design. symbol paramete rminmaxunit t af maximum pulse width of spikes that are suppressed by the analog filter 50 (2) 2. spikes with widths below t af(min) are filtered. 260 (3) 3. spikes with widths above t af(max) are not filtered ns docid028798 rev 2 133/149 STM32L432KB stm3l432kc electrical characteristics 142 spi characteristics unless otherwise specified, the parameters given in table 76 for spi are derived from tests performed under the ambient temperature, f pclkx frequency and supply voltage conditions summarized in table 20: general operating conditions . ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (nss, sck, mosi, miso for spi). table 76. spi characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode receiver/full duplex 2.7 < v dd < 3.6 v voltage range 1 -- 40 mhz master mode receiver/full duplex 1.71 < v dd < 3.6 v voltage range 1 16 master mode transmitter 1.71 < v dd < 3.6 v voltage range 1 40 slave mode receiver 1.71 < v dd < 3.6 v voltage range 1 40 slave mode transmitter/full duplex 2.7 < v dd < 3.6 v voltage range 1 37 (2) slave mode transmitter/full duplex 1.71 < v dd < 3.6 v voltage range 1 20 (2) voltage range 2 13 t su(nss) nss setup time slave mode, spi prescaler = 2 4 ? t pclk --ns t h(nss) nss hold time slave mode, spi prescaler = 2 2 ? t pclk --ns t w(sckh) t w(sckl) sck high and low time master mode t pclk -2 t pclk t pclk +2 ns t su(mi) data input setup time master mode 4 - - ns t su(si) slave mode 1.5 - - t h(mi) data input hold time master mode 6.5 - - ns t h(si) slave mode 1.5 - - t a(so) data output access time slave mode 9 - 36 ns t dis(so) data output disable time slave mode 9 - 16 ns electrical characteristics STM32L432KB stm3l432kc 134/149 docid028798 rev 2 figure 23. spi timing diagram - slave mode and cpha = 0 t v(so) data output valid time slave mode 2.7 < v dd < 3.6 v voltage range 1 - 12.5 13.5 ns slave mode 1.71 < v dd < 3.6 v voltage range 1 -12.524 slave mode 1.71 < v dd < 3.6 v voltage range 2 -12.533 t v(mo) master mode - 4.5 6 t h(so) data output hold time slave mode 7 - - ns t h(mo) master mode 0 - - 1. guaranteed by characterization results. 2. maximum frequency in slave transmitter mode is determined by the sum of t v(so) and t su(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this value can be achieved when the spi communicates with a master having t su(mi) = 0 while duty(sck) = 50 %. table 76. spi characteristics (1) (continued) symbol parameter conditions min typ max unit d l f 6 & . , q s x w 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w 9 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w d 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 0 6 % 2 8 7 % , 7 2 8 7 / 6 % 2 8 7 w v x 6 , w k 6 , 0 6 % , 1 % , 7 , 1 / 6 % , 1 docid028798 rev 2 135/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 24. spi timing diagram - slave mode and cpha = 1 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . figure 25. spi timing diagram - master mode 1. measurement points are done at cmos levels: 0.3 v dd and 0.7 v dd . d l e 1 6 6 l q s x w w 6 8 1 6 6 w f 6 & . w k 1 6 6 6 & . l q s x w & 3 + $ & 3 2 / & 3 + $ & 3 2 / w z 6 & . + w z 6 & . / w d 6 2 w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 0 , 6 2 2 8 7 3 8 7 0 2 6 , , 1 3 8 7 w v x 6 , w k 6 , 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % 2 8 7 / 6 % , 1 % , 7 , 1 d l f 6 & . 2 x w s x w & 3 + $ 0 2 6 , 2 8 7 3 8 7 0 , 6 2 , 1 3 8 7 & 3 + $ / 6 % 2 8 7 / 6 % , 1 & 3 2 / & 3 2 / % , 7 2 8 7 1 6 6 l q s x w w f 6 & . w z 6 & . + w z 6 & . / w u 6 & . w i 6 & . w k 0 , + l j k 6 & . 2 x w s x w & 3 + $ & 3 + $ & 3 2 / & 3 2 / w v x 0 , w y 0 2 w k 0 2 0 6 % , 1 % , 7 , 1 0 6 % 2 8 7 electrical characteristics STM32L432KB stm3l432kc 136/149 docid028798 rev 2 quad spi characteristics unless otherwise specified, the parameters given in table 77 and table 78 for quad spi are derived from tests performed under the ambient temperature, f ahb frequency and v dd supply voltage condit ions summarized in table 20: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 11 ? capacitive load c = 15 or 20 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics. table 77. quad spi characteristics in sdr mode (1) symbol parameter conditions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 1.71 < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 2.7 < v dd < 3.6 v, c load = 15 pf voltage range 1 --60 1.71 < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc=0 t (ck) /2-2 - t (ck) /2 ns t w(ckl) t (ck) /2 - t (ck) /2+2 t s(in) data input setup time voltage range 1 2 - - voltage range 2 3.5 - - t h(in) data input hold time voltage range 1 5 - - voltage range 2 6.5 - - t v(out) data output valid time voltage range 1 - 1 5 voltage range 2 - 3 5 t h(out) data output hold time voltage range 1 0 - - voltage range 2 0 - - 1. guaranteed by characterization results. docid028798 rev 2 137/149 STM32L432KB stm3l432kc electrical characteristics 142 table 78. quadspi characteristics in ddr mode (1) symbol parameter conditions min typ max unit f ck 1/t (ck) quad spi clock frequency 1.71 < v dd < 3.6 v, c load = 20 pf voltage range 1 --40 mhz 2 < v dd < 3.6 v, c load = 20 pf voltage range 1 --48 1.71 < v dd < 3.6 v, c load = 15 pf voltage range 1 --48 1.71 < v dd < 3.6 v c load = 20 pf voltage range 2 --26 t w(ckh) quad spi clock high and low time f ahbclk = 48 mhz, presc=0 t (ck) /2-2 - t (ck) /2 ns t w(ckl) t (ck) /2 - t (ck) /2+2 t sr(in) data input setup time on rising edge voltage range 1 1 -- voltage range 2 3.5 t sf(in) data input setup time on falling edge voltage range 1 1 -- voltage range 2 1.5 t hr(in) data input hold time on rising edge voltage range 1 6 -- voltage range 2 6.5 t hf(in) data input hold time on falling edge voltage range 1 5.5 -- voltage range 2 5.5 t vr(out) data output valid time on rising edge voltage range 1 - 55.5 voltage range 2 9.5 14 t vf(out) data output valid time on falling edge voltage range 1 - 58.5 voltage range 2 15 19 t hr(out) data output hold time on rising edge voltage range 1 3.5 - - voltage range 2 8 - t hf(out) data output hold time on falling edge voltage range 1 3.5 - - voltage range 2 13 - 1. guaranteed by characterization results. electrical characteristics STM32L432KB stm3l432kc 138/149 docid028798 rev 2 figure 26. quad spi timing diagram - sdr mode figure 27. quad spi ti ming diagram - ddr mode 0 6 y 9 ' d w d r x w s x w ' ' ' & o r f n ' d w d l q s x w ' ' ' w & . w z & . + w z & . / w u & . w i & . w v , 1 w k , 1 w y 2 8 7 w k 2 8 7 0 6 y 9 ' d w d r x w s x w ' ' ' & o r f n ' d w d l q s x w ' ' ' w & . w z & . + w z & . / w u & . w i & . w v i , 1 w k i , 1 w y i 2 8 7 w k u 2 8 7 ' ' ' ' ' ' w y u 2 8 7 w k i 2 8 7 w v u , 1 w k u , 1 docid028798 rev 2 139/149 STM32L432KB stm3l432kc electrical characteristics 142 sai characteristics unless otherwise specified, the parameters given in table 79 for sai are derived from tests performed under the ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 20: general operating conditions , with the following configuration: ? output speed is set to ospeedry[1:0] = 10 ? capacitive load c = 30 pf ? measurement points are done at cmos levels: 0.5 ? v dd refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (ck,sd,fs). table 79. sai characteristics (1) symbol parameter conditions min max unit f mclk sai main clock output - - 50 mhz f ck sai clock frequency (2) master transmitter 2.7 v dd 3.6 voltage range 1 -18.5 mhz master transmitter 1.71 v dd 3.6 voltage range 1 -12.5 master receiver voltage range 1 -25 slave transmitter 2.7 v dd 3.6 voltage range 1 -22.5 slave transmitter 1.71 v dd 3.6 voltage range 1 -14.5 slave receiver voltage range 1 -25 voltage range 2 - 12.5 t v(fs) fs valid time master mode 2.7 v dd 3.6 -22 ns master mode 1.71 v dd 3.6 -40 t h(fs) fs hold time master mode 10 - ns t su(fs) fs setup time slave mode 1 - ns t h(fs) fs hold time slave mode 2 - ns t su(sd_a_mr) data input setup time master receiver 2 - ns t su(sd_b_sr) slave receiver 1.5 - t h(sd_a_mr) data input hold time master receiver 5 - ns t h(sd_b_sr) slave receiver 2.5 - electrical characteristics STM32L432KB stm3l432kc 140/149 docid028798 rev 2 figure 28. sai master timing waveforms t v(sd_b_st) data output valid time slave transmitter (after enable edge) 2.7 v dd 3.6 -22 ns slave transmitter (after enable edge) 1.71 v dd 3.6 -34 t h(sd_b_st) data output hold time slave transmitter (after enable edge) 10 - ns t v(sd_a_mt) data output valid time master transmitter (after enable edge) 2.7 v dd 3.6 -27 ns master transmitter (after enable edge) 1.71 v dd 3.6 -40 t h(sd_a_mt) data output hold time master tr ansmitter (after enable edge) 10 - ns 1. guaranteed by characterization results. 2. apb clock frequency must be at least twice sai clock frequency. table 79. sai characteristics (1) (continued) symbol parameter conditions min max unit - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 o u t p u t f 3 # + 3 ! ) ? 3 $ ? 8 t r a n s m i t t v & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t h & 3 3 l o t n t v 3 $ ? - 4 t h 3 $ ? - 4 3 l o t n t s u 3 $ ? - 2 t h 3 $ ? - 2 docid028798 rev 2 141/149 STM32L432KB stm3l432kc electrical characteristics 142 figure 29. sai slave timing waveforms usb characteristics the stm32l432xx usb interface is fully complia nt with the usb specification version 2.0 and is usb-if certified (for full-speed device operation). can (controller area network) interface refer to section 6.3.14: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). - 3 6 3 ! ) ? 3 # + ? 8 3 ! ) ? & 3 ? 8 i n p u t 3 ! ) ? 3 $ ? 8 t r a n s m i t t s u & 3 3 l o t n 3 ! ) ? 3 $ ? 8 r e c e i v e t w # + ( ? 8 t h & 3 3 l o t n t v 3 $ ? 3 4 t h 3 $ ? 3 4 3 l o t n t s u 3 $ ? 3 2 t w # + , ? 8 t h 3 $ ? 3 2 f 3 # + table 80. usb electrical characteristics (1) symbol parameter conditions min typ max unit v ddusb usb transceiver operating voltage 3.0 (2) -3.6v t crystal_less usb crystal less operation temperature -15 - 85 c r pui embedded usb_dp pull-up value during idle 900 1250 1600 ? r pur embedded usb_dp pull-up value during reception 1400 2300 3200 z drv (3) output driver impedance (4) driving high and low 28 36 44 ? 1. t a = -40 to 125 c unless otherwise specified. 2. the stm32l432xx usb functionality is ensured down to 2. 7 v but not the full usb electrical characteristics which are degraded in the 2.7-to-3.0 v voltage range. 3. guaranteed by design. 4. no external termination series resistors are r equired on usb_dp (d+) and usb_dm (d-); the matching impedance is already included in the embedded driver. electrical characteristics STM32L432KB stm3l432kc 142/149 docid028798 rev 2 swpmi characteristics the single wire protocol master interf ace (swpmi) and the associated swpmi_io transceiver are compliant with the etsi ts 102 613 technical specification. table 81. swpmi electrical characteristics symbol parameter conditions min typ max unit t swpstart swpmi regulator startup time swp class b 2.7 v v dd 3,3v - - 300 s t swpbit swp bit duration v core voltage range 1 500 - - ns v core voltage range 2 620 - - docid028798 rev 2 143/149 STM32L432KB stm3l432kc package information 146 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 ufqfpn32 package information figure 30. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline 1. drawing is not to scale. 2. there is an exposed die pad on the underside of t he ufqfpn package. it is recommended to connect and solder this backside pad to pcb ground. $ % b 0 ( b 9 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' package information STM32L432KB stm3l432kc 144/149 docid028798 rev 2 figure 31. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. table 82. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 - - 0.050 - - 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d1 3.400 3.500 3.600 0.1339 0.1378 0.1417 d2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e1 3.400 3.500 3.600 0.1339 0.1378 0.1417 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 docid028798 rev 2 145/149 STM32L432KB stm3l432kc package information 146 figure 32. ufqfpn32 marking (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 ' d w h f r g h 3 l q l g h q w l i l h u 3 u r g x f w l g h q w l i l f d w l r q 5 h y l v l r q f r g h $ : : < / . & package information STM32L432KB stm3l432kc 146/149 docid028798 rev 2 7.2 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 20: general operating conditions . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v ddiox ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.2.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 83. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient ufqfpn32 - 5 5 mm / 0.5 mm pitch 39 c/w docid028798 rev 2 147/149 STM32L432KB stm3l432kc part numbering 148 8 part numbering table 84. stm32l432xx ordering information scheme example: stm32 l 432 k c t 6 tr device family stm32 = arm ? based 32-bit microcontroller product type l = ultra-low-power device subfamily 432: stm32l432xx pin count k = 32 pins flash memory size b = 128 kb of flash memory c = 256 kb of flash memory package u = qfn ecopack ? 2 temperature range 6 = industrial temperature range, -40 to 85 c (105 c junction) 7 = industrial temperature range, -40 to 105 c (125 c junction) 3 = industrial temperature range, -40 to 125 c (130 c junction) packing tr = tape and reel xxx = programmed parts revision history STM32L432KB stm3l432kc 148/149 docid028798 rev 2 9 revision history table 85. document revision history date revision changes 08-feb-2016 1 initial release. 31-may-2016 2 updated document title. updated table 1: stm32l432kx fa mily device features and peripheral counts . updated section 3.24: universal synchronous/asynchronous receiver transmitter (usart) . updated table 13: stm32l432xx pin definitions . updated table 15: alternate function af8 to af15 (for af0 to af7 see table 14) . updated table 17: voltage characteristics . updated table 20: general operating conditions . added figure 10: vrefint versus temperature . updated table 22: embedded reset and power control block characteristics . updated table 24 to table 26 and table 30 to table 38 . updated table 38: low-power mode wakeup timings . added table 40: wakeup time using usart/lpuart . updated table 45: msi oscillator characteristics . added table 46: hsi48 oscillator characteristics . added figure 16: hsi48 frequency versus temperature . updated table 48: pll, pllsai1 characteristics . updated table 51: ems characteristics . updated table 52: emi characteristics . updated introduction of section 6.3.14: i/o port characteristics . added note to figure 19: recommended nrst pin protection . updated table 60: analog switches booster characteristics . updated table 61: adc characteristics . updated table 69: comp characteristics . updated table 80: usb electrical characteristics . added section : swpmi characteristics . updated table 83: package thermal characteristics . docid028798 rev 2 149/149 STM32L432KB stm3l432kc 149 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2016 stmicroelectronics ? all rights reserved |
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