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ddr2 sdram sodimm mt4htf3264hz C 256mb mt4htf6464hz C 512mb mt4htf12864hz C 1gb features ? 200-pin, small-outline dual in-line memory module (sodimm) ? fast data transfer rates: pc2-3200, pc2-4200, PC2-5300, or pc2-6400 ? 256mb (32 meg x 64), 512mb (64 meg x 64), 1gb (128 meg x 64) ? v dd = v ddq = 1.8v ? v ddspd = 1.7C3.6v ? jedec-standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? 4 n -bit prefetch architecture ? multiple internal device banks for concurrent opera- tion ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths (bl): 4 or 8 ? adjustable data-output drive strength ? 64ms, 8192-cycle refresh ? on-die termination (odt) ? halogen-free ? serial presence detect (spd) with eeprom ? gold edge contacts ? single rank figure 1: 200-pin sodimm (mo-224 r/c c) module height: 30mm (1.181in) options marking ? operating temperature C commercial (0c t a +70c) none C industrial (C40c t a +85c) 1 i ? package C 200-pin dimm (halogen-free) z ? frequency/cl 2 C 2.5ns @ cl = 5 (ddr2-800) -80e C 2.5ns @ cl = 6 (ddr2-800) -800 C 3.0ns @ cl = 5 (ddr2-667) -667 notes: 1. contact micron for industrial temperature module offerings. 2. cl = cas (read) latency. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 800 800 533 400 12.5 12.5 55 -800 pc2-6400 800 667 533 400 15 15 55 -667 PC2-5300 C 667 553 400 15 15 55 -53e pc2-4200 C C 553 400 15 15 55 -40e pc2-3200 C C 400 400 15 15 55 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm features pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 256mb 512mb 1gb refresh count 8k 8k 8k row address 8k a[12:0] 8k a[12:0] 16k a[13:0] device bank address 4 ba[1:0] 8 ba[2:0] 8 ba[2:0] device configuration 512mb (32 meg x 16) 1gb (64 meg x 16) 2gb (128 meg x16) column address 1k a[9:0] 1k a[9:0] 1k a[9:0] module rank address 1 s0# 1 s0# 1 s0# table 3: part numbers and timing parameters C 256mb base device: mt47h32m16, 1 512mb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt4htf3264h(i)z-80e__ 256mb 32 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt4htf3264h(i)z-800__ 256mb 32 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt4htf3264h(i)z-667__ 256mb 32 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 table 4: part numbers and timing parameters C 512mb base device: mt47h64m16, 1 1gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt4htf6464h(i)z-80e__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt4htf6464h(i)z-800__ 512mb 64 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt4htf6464h(i)z-667__ 512mb 64 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 table 5: part numbers and timing parameters C 1gb modules base device: mt47h128m16, 1 2gb ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt4htf12864h(i)z-80e__ 1gb 128 meg x 64 6.4 gb/s 2.5ns/800 mt/s 5-5-5 mt4htf12864h(i)z-800__ 1gb 128 meg x 64 6.4 gb/s 2.5ns/800 mt/s 6-6-6 mt4htf12864h(i)z-667__ 1gb 128 meg x 64 5.3 gb/s 3.0ns/667 mt/s 5-5-5 notes: 1. the data sheet for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. consult factory for current revision codes. example: mt4htf6464hz-667 m1. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm features pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
pin assignments table 6: pin assignments 200-pin ddr2 sodimm front 200-pin ddr2 sodimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref 51 dqs2 101 a1 151 dq42 2 v ss 52 dm2 102 a0 152 dq46 3 v ss 53 v ss 103 v dd 153 dq43 4 dq4 54 v ss 104 v dd 154 dq47 5 dq0 55 dq18 105 a10 155 v ss 6 dq5 56 dq22 106 ba1 156 v ss 7 dq1 57 dq19 107 ba0 157 dq48 8 v ss 58 dq23 108 ras# 158 dq52 9 v ss 59 v ss 109 we# 159 dq49 10 dm0 60 v ss 110 s0# 160 dq53 11 dqs0# 61 dq24 111 v dd 161 v ss 12 v ss 62 dq28 112 v dd 162 v ss 13 dqs0 63 dq25 113 cas# 163 nc 14 dq6 64 dq29 114 odt0 164 ck1 15 v ss 65 v ss 115 nc 165 v ss 16 dq7 66 v ss 116 nc/a13 2 166 ck1# 17 dq2 67 dm3 117 v dd 167 dqs6# 18 v ss 68 dqs3# 118 v dd 168 v ss 19 dq3 69 nc 119 nc 169 dqs6 20 dq12 70 dqs3 120 nc 170 dm6 21 v ss 71 v ss 121 v ss 171 v ss 22 dq13 72 v ss 122 v ss 172 v ss 23 dq8 73 dq26 123 dq32 173 dq50 24 v ss 74 dq30 124 dq36 174 dq54 25 dq9 75 dq27 125 dq33 175 dq51 26 dm1 76 dq31 126 dq37 176 dq55 27 v ss 77 v ss 127 v ss 177 v ss 28 v ss 78 v ss 128 v ss 178 v ss 29 dqs1# 79 cke0 129 dqs4# 179 dq56 30 ck0 80 nc 130 dm4 180 dq60 31 dqs1 81 v dd 131 dqs4 181 dq57 32 ck0# 82 v dd 132 v ss 182 dq61 33 v ss 83 nc 133 v ss 183 v ss 34 v ss 84 nc 134 dq38 184 v ss 35 dq10 85 nc/ba2 1 135 dq34 185 dm7 36 dq14 86 nc 136 dq39 186 dqs7# 37 dq11 87 v dd 137 dq35 187 v ss 38 dq15 88 v dd 138 v ss 188 dqs7 39 v ss 89 a12 139 v ss 189 dq58 40 v ss 90 a11 140 dq44 190 v ss 41 v ss 91 a9 141 dq40 191 dq59 42 v ss 92 a7 142 dq45 192 dq62 43 dq16 93 a8 143 dq41 193 v ss 44 dq20 94 a6 144 v ss 194 dq63 45 dq17 95 v dd 145 v ss 195 sda 46 dq21 96 v dd 146 dqs5# 196 v ss 47 v ss 97 a5 147 dm5 197 scl 48 v ss 98 a4 148 dqs5 198 sa0 49 dqs2# 99 a3 149 v ss 199 v ddspd 50 nc 100 a2 150 v ss 200 sa1 notes: 1. pin 85 is nc for 256mb, ba2 for 512mb and 1gb. 2. pin 116 is nc for 256mb and 512mb, a13 for 1gb. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm pin assignments pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr2 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 7: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific addressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ckx, ck#x input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the ddr2 sdram. dmx input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr2 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s#x input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: used to synchronize communication to and from the spd eeprom on the i 2 c bus. cbx i/o check bits. used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqs#x i/o data strobe: travels with the dq and is used to capture dq at the dram or the con- troller. output with read data; input with write data for source synchronous opera- tion. dqs# is only used when differential data strobe mode is enabled via the load mode command. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm pin descriptions pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 7: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the spd eeprom on the i 2 c bus. rdqsx, rdqs#x output redundant data strobe (x8 devices only): rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disa- bled, rdqs becomes data mask (see dmx). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. err_out# output (open drain) parity error output: parity error found on the command and address bus. v dd /v ddq supply power supply: 1.8v 0.1v. the component v dd and v ddq are connected to the mod- ule v dd . v ddspd supply spd eeprom power supply: 1.7C3.6v. v ref supply reference voltage: v dd /2. v ss supply ground. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functional- ity. nu C not used: these pins are not used in specific module configurations/operations. rfu C reserved for future use. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm pin descriptions pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram ba[2/1:0] a[13/12:0] ras# cas# we# cke0 odt0 ba[2/1:0]: ddr2 sdram a[13/12:0]: ddr2 sdram ras#: ddr2 sdram cas#: ddr2 sdram we#: ddr2 sdram cke0: ddr2 sdram odt0: ddr2 sdram ddr sdram u1, u2 ck0 ck0# ddr sdram u3, u4 ck1 ck1# a0 serial pd a1 a2 sa0 sa1 sda scl wp u5 v ref v ss ddr2 sdram ddr2 sdram v dd v ddspd serial pd ddr2 sdram dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dqs0 dqs0# dm0 dqs1 dqs1# dm1 cs# u1 dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dqs2 dqs2# dm2 dqs3 dqs3# dm3 cs# u2 dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dqs4 dqs4# dm4 dqs5 dqs5# dm5 cs# u3 dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqs7 dqs7# dm7 dqs6 dqs6# dm6 cs# u4 s0# v ss v ss 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm functional block diagram pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description ddr2 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 4 or 8-bank ddr2 sdram devices. ddr2 sdram modules use ddr architecture to achieve high-speed operation. ddr2 architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data transfers at the i/o pins. ddr2 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. a bidirectional data strobe (dqs, dqs#) is transmitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-detect eeprom operation ddr2 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to identify the mod- ule type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , permanently disabling hardware write protection. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm general description pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in the device data sheet are not implied. exposure to abso- lute maximum rating conditions for extended periods may adversely affect reliability. table 8: absolute maximum ratings symbol parameter min max units v dd /v ddq v dd /v ddq supply voltage relative to v ss C0.5 2.3 v v in , v out voltage on any pin relative to v ss C0.5 2.3 v i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) address inputs, ras#, cas#, we#, s#, cke, odt, ba C20 20 a ck, ck# C10 10 dm C5 5 i oz output leakage current; 0v v out v ddq ; dq and odt are disabled dq, dqs, dqs# C5 5 a i vref v ref leakage current; v ref = valid v ref level C8 8 a t a module ambient operating temperature commercial 0 +70 c industrial C40 +85 c t c 1 ddr2 sdram component operating tem- perature 2 commercial 0 +85 c industrial C40 +95 c notes: 1. the refresh rate is required to double when t c exceeds 85c. 2. for further information, refer to technical note tn-00-08: "thermal applications," avail- able on microns web site. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm electrical specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron's web site. module speed grades cor- relate with component speed grades. table 9: module and component speed grades ddr2 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1ga -187e -80e -25e -800 -25 -667 -3 -53e -37e -40e -5e design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the system's memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm dram operating conditions pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
i dd specifications table 10: ddr2 i dd specifications and conditions C 256mb (die revision g) values shown for mt47h32m16 ddr2 sdram only and are computed from values specified in the 512mb (32 meg x 16) component data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 320 300 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 380 360 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 28 28 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 104 96 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 120 108 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p 72 60 ma slow pdn exit mr[12] = 1 36 36 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 140 128 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 640 540 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 600 500 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 400 360 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 28 28 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 860 800 ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 11: ddr2 i dd specifications and conditions C 256mb (die revision h) values shown for mt47h32m16 ddr2 sdram only and are computed from values specified in the 512mb (32 meg x 16) component data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 tbd tbd ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 tbd tbd ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p tbd tbd ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q tbd tbd ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n tbd tbd ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p tbd tbd ma slow pdn exit mr[12] = 1 tbd tbd active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n tbd tbd ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w tbd tbd ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r tbd tbd ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 tbd tbd ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 tbd tbd ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 tbd tbd ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: ddr2 i dd specifications and conditions C 512mb (die revision e and g) values shown for mt47h64m16 ddr2 sdram only and are computed from values specified in the 1gb (64 meg x 16) com- ponent data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 600 540 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 700 520 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 28 28 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 300 260 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 320 280 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p 160 120 ma slow pdn exit mr[12] = 1 40 40 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 340 300 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 1260 800 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 1280 880 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 1200 1080 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 28 28 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 1760 1400 ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 13: ddr2 i dd specifications and conditions C 512mb (die revision h) values shown for mt47h64m16 ddr2 sdram only and are computed from values specified in the 1gb (64 meg x 16) com- ponent data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 320 300 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 380 360 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 28 28 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 104 104 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 120 104 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p 80 60 ma slow pdn exit mr[12] = 1 40 40 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 140 128 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 640 540 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 600 500 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 600 580 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 28 28 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 1040 920 ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 14: ddr2 i dd specifications and conditions C 512mb (die revision m) values shown for mt47h64m16 ddr2 sdram only and are computed from values specified in the 1gb (64 meg x 16) com- ponent data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 320 300 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 380 360 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 40 40 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 104 104 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 120 104 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p 120 112 ma slow pdn exit mr[12] = 1 80 80 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 152 144 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 640 540 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 600 500 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 640 620 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 28 28 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 1040 920 ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 15: ddr2 i dd specifications and conditions C 1gb (die revision c) values shown for mt47h128m16 ddr2 sdram only and are computed from values specified in the 2gb (128 meg x 16) component data sheet parameter symbol -80e/ -800 -667 units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd0 360 340 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i dd1 420 400 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i dd2p 48 48 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 180 160 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i dd2n 200 180 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i dd3p 100 100 ma slow pdn exit mr[12] = 1 56 56 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd3n 200 180 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4w 760 680 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i dd4r 760 680 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i dd5 680 660 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i dd6 48 48 ma operating bank interleave read current: all device banks interleaving reads; i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i dd7 1120 1000 ma 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm i dd specifications pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
serial presence-detect for the latest spd data, refer to micron's spd page: www.micron.com/spd . table 16: spd eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il C0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply current, read: scl clock frequency = 100 khz i ccr 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i ccw 2 3 ma table 17: spd eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time bus must be free before a new transition can start t buf 1.3 C s data-out hold time t dh 200 C ns sda and scl fall time t f C 300 ns 2 sda and scl rise time t r C 300 ns 2 data-in hold time t hd:dat 0 C s start condition hold time t hd:sta 0.6 C s clock high period t high 0.6 C s noise suppression time constant at scl, sda inputs t i C 50 ns clock low period t low 1.3 C s scl clock frequency t scl C 400 khz data-in setup time t su:dat 100 C ns start condition setup time t su:sta 0.6 C s 3 stop condition setup time t su:sto 0.6 C s write cycle time t wrc C 10 ms 4 notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistance, and the eeprom does not respond to its slave address. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm serial presence-detect pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
module dimensions figure 3: 200-pin ddr2 sodimm 2.45 (0.096) max pin 1 67.75 (2.67) 67.45 (2.65) 20.0 (0.787) typ 1.80 (0.071) (2x) 0.6 (0.024) typ 0.45 (0.018) typ 2.0 (0.079) r (2x) pin 199 pin 200 pin 2 front view 2.0 (0.079) typ 6.0 (0.236) typ 63.6 (2.504) typ 0.5 (0.0197) r 29.85 (1.175) 30.15 (1.187) back view 1.1 (0.043) 0.9 (0.035) 47.4 (1.87) typ 11.4 (0.45) typ 4.2 (0.165) typ 16.25 (0.64) typ 3.5 (0.138) typ 45 4x u1 u2 u5 u3 u4 no components this side of module notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. refer to the jedec mo document for ad- ditional design dimensions. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256mb, 512mb, 1gb (x64, sr) 200-pin ddr2 sodimm module dimensions pdf: 09005aef83c05a5d htf4c32_64_128x64hz.pdf - rev. d 4/14 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.

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