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data sheet, v1.0, february 2010 smartlewis tm rx+ TDA5225 enhanced sensitivity multi-channel quad-configuration receiver with digital slicer wireless control never stop thinking.
edition february 19, 2010 published by infineon technologies ag, am campeon 1 - 12 85579 neubiberg, germany ? infineon technologies ag february 19, 2010. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or the infineon technologies companies and our infineon technologies representatives worldwide ( www.infineon.com ). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system . life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
data sheet, v1.0, february 2010 smartlewis tm rx+ TDA5225 enhanced sensitivity multi-channel quad-configuration receiver with digital slicer wireless control never stop thinking.
TDA5225 revision number: 010 revision history: 2010-02-19 v1.0 previous version: TDA5225_v0.2 page subjects (major changes since last revision) page 26 update of figure 9 page 28 update of figure 10 page 30 afc limitation added page 32 agc setting proposal added page 33 new section 2.4.6.5 adc added page 34 additional information on rssiprx register inserted page 40 update of figure 19 page 41 update of figure 20 page 45 additional hint on clock and data recovery algorithm of the user software inserted page 49 limitation for isx readout and burst-read function added page 51 limitation for burst-read function added page 77 additional hints added page 79 adaption of section 4.1 page 82 new item c7 added page 90 f comments added for items i6, i7, i8, i9, j11, j12 page 90 item j1 updated page 95 bom components c7, c8, l1, r2 and r3 updated we listen to your comments any information within this document that you feel is wrong, unclear or missing at all? your feedback will help us to continuously improve the quality of this document. please send your proposal (including a reference to this document) to: wirelesscontrol@infineon.com
TDA5225 table of contents page data sheet 5 v1.0, 2010-02-19 1 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 pin definition and pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.4 functional block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 architecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.2 block overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.3 rf/if receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.4 crystal oscillator and clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4.5 sigma-delta fractional-n pll block . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.5.1 pll dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.5.2 digital modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.6 ask and fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.6.1 ask demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.6.2 fsk demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.6.3 automatic frequency control unit (afc) . . . . . . . . . . . . . . . . . . . . . 27 2.4.6.4 digital automatic gain control unit (agc) . . . . . . . . . . . . . . . . . . . . 29 2.4.6.5 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.7 rssi peak detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.4.8 digital baseband (dbb) receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.8.1 data filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4.8.2 wake-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.9 power supply circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.4.9.1 supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 2.4.9.2 chip reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.5 system interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.1 interfacing to the TDA5225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.1.1 control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.1.2 data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.5.2 digital output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.5.3 interrupt generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.5.4 digital control (4-wire spi bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.5.4.1 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.5.5 chip serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.6 system management unit (smu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.1 master control unit (mcu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.6.1.2 run mode slave (rms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
TDA5225 table of contents page data sheet 6 v1.0, 2010-02-19 2.6.1.3 hold mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 2.6.1.4 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.6.1.5 self polling mode (spm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 2.6.1.6 automatic modulation switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.6.1.7 multi-channel in self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.6.1.8 run mode self polling (rmsp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 2.6.2 polling timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 2.6.2.1 self polling mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.6.2.2 constant on-off time (coo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.6.2.3 active idle period selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.7 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.7.1 definition of bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.7.2 definition of manchester duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 2.7.3 definition of power level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 2.7.4 symbols of sfr registers and control bits . . . . . . . . . . . . . . . . . . . . . 75 2.8 digital control (sfr registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.8.1 sfr address paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 2.8.2 sfr register list and detailed sfr description . . . . . . . . . . . . . . . . . 76 3applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 3.1 configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4 reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 4.1.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 4.1.3 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.2 test circuit - evaluation board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 4.3 test board layout - evaluation board v1.0 . . . . . . . . . . . . . . . . . . . . . . . . 99 4.4 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 appendix - registers chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
data sheet 7 v1.0, 2010-02-19 TDA5225 product description 1 product description 1.1 overview the ic is a low power ask/fsk receiver for the frequency bands 300-320, 425-450, 863-870 and 902-928 mhz. the chip offers a very high level of integration and needs only a few external components. the device is qualified to automotive quality standards and operates between -40 and +105c at supply voltage ranges of 3.0-3.6 volts or 4.5-5.5 volts. the receiver is realized as a double down conversion super-heterodyne/low-if architecture each with image rejection. a fully integrated sigma-delta fractional-n pll synthesizer allows for high-resolution frequency generation and uses a crystal oscillator as the reference. the on-chip temperature sensor may be utilized for temperature drift compensation via the crystal oscillator. the high performance down converter is the key element for the exceptional sensitivity performance of the device which take it close to the theoretical top-performance limits. it demodulates the received ask or fsk data stream independently which can then be accessed via separate pins. the rssi output signal is converted to the digital domain with an adc. all these signals are accessible via the 4-wire spi interface bus. up to 4 pre-configured telegram parameters can be stored into the device offering independent pre-processing of the received data to an extent not available till now. the down converter can be also configured in single-conversion mode at moderately reduced selectivity performance but at the advantage of omitting the if ceramic filter.
TDA5225 product description data sheet 8 v1.0, 2010-02-19 1.2 features ? enhanced sensitivity receiver ? multi-band/multi-channel (300-320, 425-450, 863-870 and 902-928 mhz) ? one crystal frequency for all supported frequency bands ? 21-bit sigma-delta fractional-n pll synthesizer with high resolution of 10.5 hz ? up to 4 parallel parameter sets for autonomous scanning and receiving from different sources ? up to 12 different frequency channels are supported with 10.5 hz resolution each ? ultrafast wake-up on rssi ? selectable if filter bandwidth and optional external filters possible ? double down conversion image reject mixer ? ask and fsk capability ? automatic frequency control (afc) for carrier frequency offset compensation ? nrz data processing capability ? sliced data output ? rssi peak detectors ? wake-up generator and polling timer unit ? unique 32-bit serial number ? on-chip temperature sensor ? integrated timer usable for external watch unit ? integrated 4-wire spi interface bus ? supply voltage range 3.0 volts to 3.6 volts or 4.5 volts to 5.5 volts ? operating temperature range -40 to +105c ? esd protection +/- 2 kv on all pins ? package pg-tssop-28 1.3 applications ? remote keyless entry systems ? remote start applications ? tire pressure monitoring ? short range radio data transmission ? remote control units ? cordless alarm systems ? remote metering
data sheet 9 v1.0, 2010-02-19 TDA5225 functional description 2 functional description 2.1 pin configuration figure 1 pin-out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ifbuf_in ifbuf_out gnda ifmix _inp ifmix _inn vdd5v vddd vddd1v5 gndd pp0 pp1 pp2 p_on xtal1 if _out vdda rssi pp3 gndrf lna_inp lna_inn t2 t1 sdo sdi sck ncs xtal2 TDA5225
TDA5225 functional description data sheet 10 v1.0, 2010-02-19 2.2 pin definition and pin functionality table 1 pin definition and function pin no. pad name equivalent i/o schematic function 1 ifbuf_in analog input if buffer input note: input is biased at vdda/2 2 ifbuf_out analog output if buffer output 3 gnda analog ground 4 ifmix_inp analog input + if mixer input note: input is biased at vdda/2 5 ifmix_inn see schematic of pin 1 and 4 analog input. - if mixer input 6 vdd5v analog input 5 volt supply input ifbuf_in ifmix_inn vdda 330 330 ifbuf mix2buf vdda vdda ifbuf_out gnda vdda vdda gnda 330 ifbuf ifmix _inp vdda 330 ifmix_inn mix2buf vdda
data sheet 11 v1.0, 2010-02-19 TDA5225 functional description 7 vddd analog input digital supply input 8 vddd1v5 analog output 1.5 volt voltage regulator 9 gndd digital ground 10 pp0 digital output clk_out, rx_run, nint, low, high, data and data_matchfil are programmable via a sfr (special function register), default = clk_out pin no. pad name equivalent i/o schematic function = + - gndd vddd vdd5v vreg vdd1v5 vddd = + - gndd vreg ppx sdo vdd5v gndd vdd5v gndd
TDA5225 functional description data sheet 12 v1.0, 2010-02-19 11 pp1 see schematic of pin 10 digital output clk_out, rx_run, nint, low, high, data and data_matchfil are programmable via a sfr, default = data 12 pp2 see schematic of pin 10 digital output clk_out, rx_run, nint, low, high, data and data_matchfil are programmable via a sfr, default = nint 13 p_on digital input power-on reset 14 xtal1 analog input crystal oscillator input pin no. pad name equivalent i/o schematic function gndd vdd5v gndd vddd p_on ncs sck sdi xtal1 gndd vddd .... gndd vddd gndd
data sheet 13 v1.0, 2010-02-19 TDA5225 functional description 15 xtal2 analog output crystal oscillator output 16 ncs see schematic of pin 13 digital input spi enable 17 sck see schematic of pin 13 digital input spi clock 18 sdi see schematic of pin 13 digital input spi data in 19 sdo see schematic of pin 10 digital output spi data out 20 t1 digital input, connect to digital ground 21 t2 digital input, connect to digital ground 22 lna_inn analog input - rf input 23 lna_inp analog input + rf input 24 gndrf rf analog ground pin no. pad name equivalent i/o schematic function xtal2 gndd vddd .... gndd vddd gndd lna_inn gndrf lna lna_inp gndrf lna
TDA5225 functional description data sheet 14 v1.0, 2010-02-19 25 pp3 see schematic of pin 10 digital output rx_run, nint, low, high, data and data_matchfil are programmable via a sfr, default = rx_run 26 rssi analog output analog rssi output/ analog test pin ana_tst 27 vdda analog input analog supply 28 if_out analog output if output pin no. pad name equivalent i/o schematic function gnda vdda gnda vdda 500 rssi = + - gnda vdda vdd5v vreg if_out ppfbuf vdda vdda gnda 330 gnda
data sheet 15 v1.0, 2010-02-19 TDA5225 functional description 2.3 functional block diagram figure 2 TDA5225 block diagram 1) 1) the function on each ppx port pin can be programmed via sfr (see also table 1 ). default values are given in squared brackets in figure 2 . vreg 3v3 vreg 3v3 ? pll vreg 1v5 xtal 21.948717 mhz digital demod temp.- sensor adc i/f pll control i/f rx control i/f ir-mix, 1 st if : 10.7 mhz peripheral bus vddd ir-mix2, 2 nd if: 274.35897 khz peak detector slicer data filter spi interface system management 1.5v dig-core 3.3v dig-i/o 3.3v-analog xosc antenna lna ppf ppf buf ppf 2 afc double/single conversion (sdcsel) 1 st if = 10.7 mhz 2 nd if = 1 st if / 39 f cry stal = 2 nd if * 80 lna_inp (23) xtal1 (14) xtal2 (15) lna_inn (22) gndrf (24) gnda (3) vdda (27) vdd5v (6) vddd (7) vddd1v5 (8) pp1 (11) [data] p_on (13) t2 (21) sdi (18) sdo (19) sck (17) ncs (16) ifmix_inp (4) ifmix_inn (5) TDA5225 rssi (26) t1 (20) ifbuf_in (1) ifbuf_out (2) 10.7 mhz wide 10.7 mhz narrow ( opt ) pp3 (25) [rx_run] narrow wide matching + saw 2nd lo-q 2nd lo-i if_out (28) aaf lp serial number pp2 (12) [nint] limiter rssi (cerfsel) clock generator pp0 (10) [clk_out] 5v dig-o interrupt generator reset generator gndd (9) to rx to pll clock for digital core reset for digital core adc-mux mux a d 2 nd lo div 2 ifbuf mix2 buf bpf select bw 1st lo-i 1st lo-q
TDA5225 functional description data sheet 16 v1.0, 2010-02-19 2.4 functional block description 2.4.1 architecture overview a fully integrated sigma-delta fractional-n pll synthesizer covers the frequency bands 300-320 mhz, 425-450 mhz, 863-870 mhz, 902-928 mhz with a high frequency resolution, using only one vco running at around 3.6 ghz. this makes the ic most suitable for multi-band/multi-channel applications. for multi-channel applications a very good channel separation is essential. to achieve the necessary high sensitivity and selectivity a double down conversion super- heterodyne architecture is used. the first if frequency is located around 10.7 mhz and the second if frequency around 274 khz. for both if frequencies an adjustment-free image frequency rejection feature is realized. in the second if domain the filtering is done with an on-chip third order bandpass polyphase filter. a multi-stage bandpass limiter completes the rf/if path of the receiver. for single-channel applications with relaxed requirements to selectivity, a single down conversion low-if scheme can be selected. for multi-channel systems where even higher channel separation is required, up to two (switchable) external ceramic (cer) filters can be used to improve the selectivity. an rssi generator delivers a dc signal proportional to the applied input power and is also used as an ask demodulator. via an anti-aliasing filter this signal feeds an adc with 10 bits resolution. the harmonic suppressed limiter output signal feeds a digital fsk demodulator. this block demodulates the fsk data and delivers an afc signal which controls the divider factor of the pll synthesizer. a digital receiver, which comprises rssi peak detectors, a matched data filter and a data slicer, decodes the received ask or fsk data stream. the received data signal is accessible via one of the port pins. the crystal oscillator serves as the reference frequency for the pll phase detector, the clock signal of the sigma-delta modulator and divided by two as the 2 nd local oscillator signal. to accelerate the start up time of the crystal oscillator two modes are selectable: a low power mode (with lower precision) and a high precision mode.
data sheet 17 v1.0, 2010-02-19 TDA5225 functional description 2.4.2 block overview the TDA5225 is separated into the following main blocks: ? rf / if receiver ? crystal oscillator and clock divider ? sigma-delta fractional-n pll synthesizer ? ask / fsk demodulator incl. afc, agc and adc ? rssi peak detector ? digital baseband receiver ? power supply circuitry ? system interface ? system management unit 2.4.3 rf/if receiver the receiver path uses a double down conversion super-heterodyne/low-if architecture, where the first if frequency is located around 10.7 mhz and the second if frequency around 274 khz. for the first if frequency an adjustment-free image frequency rejection is realized by means of two low-side injected i/q-mixers followed by a second order passive polyphase filter centered at 10.7 mhz (ppf). the i/q-oscillator signals for the first down conversion are delivered from the pll synthesizer. the frequency selection in the first if domain is done by an external cer filter (optionally by two, decoupled by a buffer amplifier). for moderate or low cost applications, this ceramic filter can be substituted by a simple lc pi-filter or completely by-passed using the receiver as a single down conversion low-if scheme with 274 khz if frequency. the down conversion to the second if frequency is done by means of two high-side injected i/q-mixers together with an on-chip third order bandpass polyphase filter (ppf2 + bpf). the i/q- oscillator signals for the second down conversion are directly derived by division of two from the crystal oscillator frequency. the bandwidth of the bandpass filter (bpf) can be selected from 50 khz to 300 khz in 5 steps. for a frequency offset of -150 khz to -120 khz, the afc (automatic frequency control) function is mandatory. activated afc option might require a longer preamble sequence in the receive data stream. the receiver enable signal (rx_run) can be offered at each of the port pins to control external components. whenever the receiver is active, the rx_run output signal is active. active high or active low is configurable via ppcfg2 register.
TDA5225 functional description data sheet 18 v1.0, 2010-02-19 the frequency relations are calculated with the following formulas: figure 3 block diagram rf section the front end of the receiver comprises an lna, an image reject mixer and a digitally gain controlled buffer amplifier. this buffer amplifier allows the production spread of the on-chip signal strip, of external matching circuitry and rf saw and ceramic if filters to be trimmed. the second image reject mixer down converts the first if to the second if. f if1 10.7mhz = f if2 f if1 39 -------- - = f crystal f if2 80 = f lo2 f crystal 2 ---------------- = f lo1 f crystal nf divider = 2nd order ppf 10.7 mhz ppfbuf cer- filter if1 10 .7 mh z cer- filter if1 10.7 mhz optional cerfsel-mux i- mix2 3rd order bp /pp f2 if2 = 274 khz digital fsk demod multi modulos divider : n_fn lna i-mix q-mix ifbuf q- mix2 limite r rssi generator iq :2 ask / rssi adc rx fsk data rx ask data divider : n afc filter ? modulator crystal oscil - lator pd loop filter iq divider : 4 :1/:2/:3 vco n channel select if attenuation adjust band select lf select channel filter bandwidth select front end control unit band select channel select channel filter select if attenuation adjust lf select rssi gain/ offset adjust rx input mux sdcsel-mux mix2buf (var. gain) lp harm sup lp alias sup
data sheet 19 v1.0, 2010-02-19 TDA5225 functional description the bandpass filter follows the subsequent formula: therefore asymmetric corner frequencies can be observed. the use of afc results in more symmetry. a multi-stage bandpass limiter at a center frequency of 274 khz completes the receiver chain. the -3db corner frequencies of the bandpass limiter are typically at 75 khz and at 520 khz. an rssi generator delivers a dc signal proportional to the applied input power and is also used as an ask demodulator. via a programmable anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit adc. the limiter output signal is connected to a digital fsk demodulator. the immunity against strong interference frequencies (so called blockers) is determined by the available filter bandwidth, the filter order and the 3 rd order intercept point of the front end stages. for single-channel applications with moderate requirements to the selectivity the performance of the on-chip 3 rd order bandpass polyphase filter might be sufficient. in this case no external filters are necessary and a single down conversion architecture can be used, which converts the input signal frequency directly to the 2 nd if frequency of 274 khz. figure 4 single down conversion (sdc, no external filters required) for multi-channel applications or systems which demand higher selectivity the double down conversion scheme together with one or two external cer filters can be selected. the order of such ceramic filters is in a range of 3, so the selectivity is further improved and a better channel separation is guaranteed. f center f corner low , f corner high , = 2nd order ppf 10.7 mh z ppfbuf c erfsel-m ux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo mix2buf (var. gain) lp harm sup lp alias sup
TDA5225 functional description data sheet 20 v1.0, 2010-02-19 figure 5 double down conversion (ddc) with one external filter for applications which demand very high selectivity and/or channel separation even two cer filters may be used. also in applications where one channel requires a wider bandwidth than the other (e.g. tpms and rke) the second filter can be by-passed. figure 6 double down conversion (ddc) with two external filters 2nd order ppf 1 0.7 m h z ppfbuf cer- filter if1 10 .7 mhz cerfsel-mux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo m ix2buf (var. gain) lp harm sup lp alias sup 2nd order ppf 10.7 mhz ppfbuf cer- filter if1 10 .7 mhz cer- filter if1 10.7 mhz optional c erf sel-m ux i- mix2 3rd order bp /pp f2 if2 = 274 kh z digital fsk demod lna i-mix q-mix ifb u f q- mix2 lim ite r rssi generator ask / rssi adc rx fsk data rx ask data divider : n if attenuation adjust channel filter bandwidth select rx input mux sdcsel-mux 1 st lo 2 nd lo mix2buf (var. gain) lp harm sup lp alias sup
data sheet 21 v1.0, 2010-02-19 TDA5225 functional description 2.4.4 crystal oscillator and clock divider the crystal oscillator is a pierce type oscillator which operates together with the crystal in parallel resonance mode. an automatic amplitude regulation circuitry allows the oscillator to operate with minimum current consumption. in sleep mode, where the current consumption should be as low as possible, the load capacitor must be small and the frequency is slightly detuned, therefore all internal trim capacitors are disconnected. the internal capacitors are controlled by the crystal oscillator calibration registers xtalcalx. with a binary weighted capacitor array the necessary load capacitor can be selected. whenever a xtalcalx register value is updated, the selected trim capacitors are automatically connected to the crystal so that the frequency is precise at the desired value. the sfr control bit xtalhpms can be used to activate the high precision mode also during sleep mode. figure 7 crystal oscillator xtal2 xtal1 oscillator -core (dgnd) binary weighted capacitor-array binary weighted capacitor-array f sys xtalcal0 setting automatically controlled ( 1pf steps ) xtalhpms xtalcal1 9
TDA5225 functional description data sheet 22 v1.0, 2010-02-19 recommended trimming procedure ? set the registers xtalcal0 and xtalcal1 to the expected nominal values ? set the TDA5225 to run mode slave ? wait for 0.5ms minimum ? trim the oscillator by increasing and decreasing the values of xtalcal0/1 ? register changes larger than 1 pf are automatically handled by the TDA5225 in 1 pf steps ? after the oscillator is trimmed, the TDA5225 can be set to sleep mode and keeps these values during sleep mode ? add the settings of xtalcal0/1 to the configuration. it must be set after every power up or brownout! using the high precision mode as discussed earlier, the TDA5225 allows the crystal oscillator to be trimmed by the use of internal trim capacitors. it is also possible to use the trim functionality to compensate temperature drift of crystals. during run mode (always when the receiver is active) the capacitors are automatically connected and the oscillator is working in the high precision mode. on entering sleep mode, th e capacitor s are automatically disconnected to save power. if the high precision mode is also required for sleep mode, the automatic disconnec- tion of trim capacitors can be avoided by setting xtalhpms to 1 (enable xtal high precision mode during sleep mode). external clock generation unit a built in programmable frequency divider can be used to generate an external clock source out of the crystal reference. the 20 bit wide division factor is stored in the registers clkout0, clkout1 and clkout2. the minimum value of the programmable frequency divider is 2. this programmable divider is followed by an additional divider by 2, which generates a 50% duty cycle of the clk_out signal. so the maximum frequency at the clk_out signal is the crystal frequency divided by 4. the minimum clk_out frequency is the crystal frequency divided by 2 21 . to save power, this programmable clock signal can be disabled by the sfr control bit clkouten. in this case the external clock signal is set to low.
data sheet 23 v1.0, 2010-02-19 TDA5225 functional description the resulting clk_out frequency can be calculated by: figure 8 external clock generation unit the maximum clk_out frequency is limited by the driver capability of the ppx pin and depends on the external load connected to this pin. please be aware that large loads and/or high clock frequencies at this pin may interfere with the receiver and reduce performance. after reset the ppx pin is activated and the division factor is initialized to 11 (equals f clk_out = 998 khz). a clock output frequency higher than 1 mhz is not supported. for high sensitivity applications, the use of the external clock generation unit is not recommended. f clkout f sys 2 divisionfactor ? -------------------------------------------- - = 20 bit counter divide by 2 f clk_out 2 x f clk_out f sys clkout0 clkout1 clkout2 clkouten enable enable
TDA5225 functional description data sheet 24 v1.0, 2010-02-19 2.4.5 sigma-delta fractional-n pll block the sigma-delta fractional-n pll is fully integrated on chip. the v oltage c ontrolled o scillator (vco) with on-chip lc-tank runs at approximately 3.6 ghz and is first divided with a band select divider by 1, 2 or 3 and then with an i/q-divider by 4 which provides an orthogonal local oscillator signal for the first image reject mixer with the necessary high accuracy. the multi-modulus divider determines the channel selection and is controlled by a 3 rd order sigma-delta modulator ( sdm ). a type iv phase detector, a charge pump with programmable current and an on-chip loop filter closes the phase locked loop. figure 9 synthesizer block diagram qosc 22mhz iq divider 4 multi- modulus divider pfd ? modulator loop filter band select 1/2/3 3.6 ghz vco cp afc filter afc-data to 1 st mixer channel fn
data sheet 25 v1.0, 2010-02-19 TDA5225 functional description when defining a multi-channel system, the correct selection of channel spacing is extremely important. a general rule is not possible, but following must be con- sidered: ? if an additional saw filter is used, all channels including their tolerances have to be inside the saw filter bandwidth. ? the distance between channels must be high enough, that no overlapping can occur. strong input signals may still appear as recognizable input signal in the neighboring channel because of the limited suppression of if filters. example: a typical 330khz if filter has at 10.3 mhz ( 10.7 mhz - 0.4 mhz ) only 30 db suppression. a -70 dbm input signal appears like a -100 dbm signal, which is inside the receiver sensitivity. in critical cases the use of two if filters must be considered. see also chapter 2.4.3 rf/if receiver . 2.4.5.1 pll dividers the divider chain consists of a band select divider 1/2/3, an i/q-divider by 4 which provides an orthogonal 1st local oscillator signal for the first image reject mixer with the necessary high accuracy and a multi-modulus divider controlled by the sigma-delta modulator. with the band select divider, the wanted frequency band is selected. divide by 1 selects the 915 mhz and 868 mhz band, divide by 2 selects the 434 mhz band and divide by 3 selects the 315 mhz band. the ism band selection is done via bit group bandsel in x_pllintc1 register. 2.4.5.2 digital modulator the 3 rd order sigma-delta modulator (sdm) has a 22 bit wide input word, however the lsb is always high, and is clocked by the xtal oscillator. this determines the achievable frequency resolution. the automatic frequency control unit filters the actual frequency offset from the fsk demodulator data and calculates the necessary correction of the divider factor to achieve the nominal if center frequency.
TDA5225 functional description data sheet 26 v1.0, 2010-02-19 2.4.6 ask and fsk demodulator figure 10 functional block diagram ask/fsk demodulator the ic comprises two separate demodulators for ask and fsk. after combining fsk and ask data path, a sampling rate adaptation follows to meet an output oversampling between 8 and 16 samples per chip. finally, an oversampling of 8 samples per chip can be achieved using a fractional sample rate converter (src) with linear interpolation (for further details see figure 15 ). 2.4.6.1 ask demodulator the rssi generator delivers a dc signal proportional to the applied input power at a logarithmic scale (dbm) and is also used as an ask demodulator. via a programmable anti-aliasing filter this signal is converted to the digital domain by means of a 10-bit adc. for the am demodulation a signal proportional to the linear power is required. therefore a conversion from logarithmic scale to linear scale is necessary. this is done in the digital domain by a nonlinear filter together with an exponential function. the analog rssi signal after the anti-aliasing filter is available at the rssi pin via a buffer amplifier. to enable this buffer the sfr control bit rssimonen must be set. the anti-aliasing filter can be by-passed for visualization on the rssi pin (see aafbyp control bit). 2nd conversion delog ask fsk b = 50..300khz ppf2 bp rssi adc channel filter fm limiter image suppression / band limitation (noise) fsk demodulator 33 / 46 / 65 / 93 / 132 / 190 / 239 / 282 khz (2sided pdf bw) 8 ? 16 samples /chip (data rate dependent ) fsk/ask rf pll ctrl fsk demodulator afc loop filter div f system demodulated data rssi buffer rssi slope rssi offset peak memory filter rssi peak detector register agc rssipmf register rssipwu (internal signal) > begin of config / channel , x*wulot wu event th, bl, bh bypass rate adapter rate doubler decimation rssipwu register end of config/ channel afc track/freeze dig. gain control analog gain control mux temp vddd/2
data sheet 27 v1.0, 2010-02-19 TDA5225 functional description 2.4.6.2 fsk demodulator the limiter output signal, which has a constant amplitude over a wide range of the input signal, feeds the fsk demodulator. there is a configurable lowpass filter in front of the fsk demodulation to suppress the down conversion image and noise/limiter harmonics (fsk pre-demodulation filter, pdf). this is realized as a 3 rd order digital filter. the sampling rate after fsk demodulation is fixed and independent from the target data rate. 2.4.6.3 automatic frequency control unit (afc) in front of the image suppression filter a second fsk demodulator is used to derive the control signal for the automatic frequency control unit , which is actually the dc value of the fsk demodulated signal. this makes the afc loop independent from signal path filtering and allow so a wider frequency capture range of the afc. the derivation of the afc control signal is preferably done during the dc free preamble and is then frozen for the rest of the datagram. since the digital fsk demodulator determines the exact frequency offset between the received input frequency and the programmed input center frequency of the receiver, this offset can be corrected through the sigma delta control of the pll. as shown in figure 10 , for afc purposes a parallel demodulation path is implemented. this path does not contain the digital low pass filter (pdf, pre-demodulation filter). the entire if bandwidth, filtered by the analog bandpass filter only, is processed by the afc demodulator. there are two options for the active time of the afc loop: ? 1. always on ? 2. active for a programmable time relative to a signal identification event in the latter case the afc can either be started or frozen relative to the signal identification. after the active time the offset for the sigma-delta pll (sd pll) is frozen. the programming of the active time is especially necessary in case the expected frame structure contains a gap (noise) between wake-up and payload in order to avoid the afc from drifting. afc works both for fsk and ask. in the latter case the afc loop only regulates during ask data = high. the maximum frequency offset generated by the afc can be limited by means of the x_afclimit register. this limit can be used to avoid the afc from drifting in the presence of interferers or when no rf input signal is available (afc wander). a maximum afc limit of 42 khz is recommended. afc wandering needs to be kept in mind especially when using run mode slave.
TDA5225 functional description data sheet 28 v1.0, 2010-02-19 figure 11 afc loop filter (i-pi filtering and mapping) the bandwidth (and thus settling time) of the loop is programmed by means of the integrator gain coefficients k1 and k2 (x_afck1cfg and x_afck2cfg register). k1 mainly determines the bandwidth. k2 influences the dynamics/damping (overshoot) - smaller k2 means smaller overshoot, but slower dynamics. the bandwidth of the afc loop is approximately 1.3*k1. to avoid residual fm, limiting the afc bw to 1/20 ~ 1/40 of the bit rate is suggested, therefore k1 must be set to approximately 1/50 ~ 1/100 of the bit rate. for most applications k2 can be set equal to k1 (overshoot is then <25%). when very fast settling is necessary k1 and k2 can be increased up to bit rate/10, however, in this case approximately 1db sensitivity loss is to be expected due to the afc counteracting the input fsk signal. afc limitation at local oscillator (lo) frequencies at multiples of reference frequency (f_xtal). when afc is activated and afc drives the wanted lo frequency over the integer limit of sigma delta (sd) modulator, the sd modulator stucks at frac=1.0 or frac=0.0 due to saturation. so when afc can change the integer value for the lo (register x_pllintcy) within the frequency range lo-frequency +/- afc-limit, a change of the lo injection side or a smaller afc-limit is recommended. the frequency offset found by afc (afc loop filter output) can be readout via register afcoffset, when afc is activated. the value is in signed representation and has a frequency resolution of 2.68 khz/digit. the output can be limited by the x_afclimit register. x_afck1cfg0/1 afc demod out freqoffset sdpll scaling & limiting hold delay x_afcagcd integrator 1 x_afck2cfg0/1 x_afclimit k2 = integrator 2 gain k1 = integrator 1 gain k2 x4 + freeze * / track hol d limit hold limit integrator 2 k1 x16
data sheet 29 v1.0, 2010-02-19 TDA5225 functional description 2.4.6.4 digital automatic gain control unit (agc) automatic gain control (agc) is necessary mainly because of the limited dynamic range of the on-chip bandpass filter (bpf). the dynamic range reduces to less than 60db in case of minimum bpf bandwidth. agc is used to cover the following cases: 1. ask demodulation at large input signals 2. rssi reading at large input signals 3. improve iip3 performance in either fsk or ask mode the 1 st if buffer (ppfbuf, see figure 3 ) can be fine tuned "manually" by means of 4 bits thus optimizing the overall gain to the application (attenuation of 0db to -12db by means of ifatt0 to ifatt15 in ddc mode; sdc mode has lower ifatt range). this buffer allows the production spread of external components to be trimmed. the gain of the 2 nd if path is set to three different values by means of an agc algorithm. depending on whether the receiver is used in single down conversion or in double down conversion mode the gain control in the 2 nd if path is either after the 2 nd poly-phase network or in front of the 2 nd mixer. the agc action is illustrated in the rssi curve below: figure 12 analog rssi output curve with agc action on (blue) vs. off (black) limiter noise floor front-end noise x gain mixer2 saturation input power analog (blue ) & digital (black ) rssi output min. fe gain (if a tt 1 5 ) bpf saturation margin analog agc attack point max . fe gain (ifa tt 0) max . b w min. b w analog agc decay point hysteresis bpf bypassed agc off agc on max . b w min. b w ag ct h of fs agctlo agchys ag ct up ag ch y s
TDA5225 functional description data sheet 30 v1.0, 2010-02-19 digital rssi, agc and delog: in order to match the analog rssi signal to the digital rssi output a correction is necessary. it adds an offset (rssioffs) and modifies the slope (rssislope) such that standardized agc levels and an appropriate delog table can be applied. upon entering the agc unit the digital rssi signal is passed through a peak memory filter (pmf). this filter has programmable up and down integration time constants (pmfup, pmfdn) to set attack respectively decay time. the integration time for decay time must be significantly longer than the attack time in order to avoid the agc interfering with the ask modulation. the integrator is followed by two digital schmitt triggers with programmable thresholds (agctlo; agctup) - one schmitt trigger for each of the two attack thresholds (two digital agc switching points). the hysteresis of the schmitt triggers is programmable (agchys) and sets the decay threshold. the schmitt triggers control both the analog gain as well as the corresponding (programmable) digital gain correction (dgc). the difference ("error") signal in the pmf is actually a normalized version of the modulation. this signal is then used as input for the delog table. agc threshold programming the sfr description for the agc thresholds are in dbs. the first value to set is the agc threshold offset in agcthoffs. this value is the offset relative to 0 input (no noise, no signal), which for the default setting of gain, and assuming typical insertion loss of matching network and ceramic filter, can be extrapolated to be approximately -143dbm. in this case the default setting of the agcthoffs of 63.9db corresponds to an input power of approximately -79dbm (= -143dbm + 63.9db). the low (digital) agc threshold is then -79 + 12.8db (default agctlo) = -66dbm and the upper (digital) agc threshold is -79 + 25.6 (default agctup) = -53dbm. therefore a margin of about 6db is indicated before a degradation of the linearity of the 2 nd if can be observed when using the 50khz bpf or even about 16db when using the 300khz bpf. the input power level at which the agc switches back to maximum gain is -66dbm - 21.3db (default agchys) = -87dbm. this provides enough margin against the minimum sensitivity.
data sheet 31 v1.0, 2010-02-19 TDA5225 functional description when agc is activated, rssi is untrimmed, ifatt <= 5.6db and the same rssi offset should be applied for all bandpass filter settings, then the settings in table 2 can be applied, where a small reduction of the rssi input range can be observed. for the full rssi input range, the values in table 3 can be applied. table 2 agc settings 1 agc threshold hysteresis = 21.3 db agc digital rssi gain correction = 15.5 db bpf rssi offset compensation (untrimmed) 1) 1) note: this value needs to be used for calculating the register value agc threshold offset agc threshold low agc threshold up rssi input range reduction 300 khz 32 63.9 db 8 4 5 db 200 khz 32 63.9 db 6 2 5 db 125 khz 32 63.9 db 5 0 5 db 80 khz 32 51.1 db 11 6 2.8 db 50 khz 32 51.1 db 9 5 0 db table 3 agc settings 2 agc threshold hysteresis = 21.3 db agc digital rssi gain correction = 15.5 db bpf rssi offset compensation (untrimmed) 1) 1) note: this value needs to be used for calculating the register value agc threshold offset agc threshold low agc threshold up 300 khz -18 63.9 db 5 1 200 khz -18 51.1 db 11 7 125 khz -18 51.1 db 10 5 80 khz 4 51.1 db 9 5 50 khz 32 51.1 db 9 5
TDA5225 functional description data sheet 32 v1.0, 2010-02-19 attack and decay coefficients pmf-up & pmf-down: the settling time of the loop is determined by means of the integrator gain coefficients pmfup and pmfdn, which need to be calculated from the wanted attack and decay times. the adc is running at a fixed sampling frequency of 274khz. therefore the integrator is integrating with pmfup*274k per second, i.e. time constant is 1/(pmfup*274k). the attack times are typically 16 times faster than the decay times. typical calculation of the coefficients by means of an example: ? pmfup = 2^-round( ln(atttime / bitrate * 274khz) / ln(2) ) ? pmfdn = 2^-round( ln(dectime / bitrate * 274khz) / ln(2) ) / pmfup where atttime, dectime = attack, decay time in number of bits note: pmfdn = overall_pmfdn / pmfup example: bitrate = 2kbps atttime = 0.1 bits => pmfup = 2^-round(ln(0.1bit/2kbps*274khz)/ln(2)) = 2^-round(3.8) = 2^-4 dectime = 2 bits => pmfdn = 2^-round(ln(2bit/2kbps*274khz)/ln(2))/pmfup = 2^-round(8.1)/2^-4 = 2^-4 note: in case of ask with large modulation index the attack time (pmfup) can be up to a factor 2 slower due to the fact that the ask signal has a duty cycle of 50% - during the ask low duration the integrator is actually slightly discharged due to the decay set by pmfdn. the agc start and freeze times are programmable. the same conditions can be used as in the corresponding afc section above. they will however, be programmed in separate sfr registers.
data sheet 33 v1.0, 2010-02-19 TDA5225 functional description 2.4.6.5 analog to digital converter (adc) in front of the ad converter there is a multiplexer so that also temperature and vddd can be measured (see figure 10 ). the default value of the adc-mux is rssi (register adcinsel: 000 for rssi; 001 for temperature; 010 for vddd/2). after switching adc-mux to a value other than rssi in sleep mode, the internal references are activated and this adc start-up lasts 100s. so after this adc start-up time the readout measurements may begin. the chip stays in this mode until reconfiguration of register adcinsel to setting rssi. however, it is recommended to measure temperature during sleep mode (this is also valid for vddd). readout of the 10-bit adc has to be done via adcresh register (the lower 2 bits in adcresl register can be inconsistent and should not be used). typical the adc refresh rate is 3.7 s. time duration between two adc readouts has to be at least 3.7 s, so this is already achieved due to the maximum spi rate (16 bit for spi command and address last 8s at an spi rate of 2mbit/s). the eoc bit (end of conversion) indicates a successful conversion additionally. repetition of the readout measurement for several times is for averaging purpose. the input voltage of the adc is in the range of 1 .. 2 v. therefore vddd/2 (= 1.65 v typical) is used to monitor vddd. further details on the measurement and calibration procedure for temperature and vddd can be taken from the corresponding application note.
TDA5225 functional description data sheet 34 v1.0, 2010-02-19 2.4.7 rssi peak detector the ic possesses digital rssi peak level detectors. the rssi level is averaged over 4 samples before it is fed to the peak detectors. this prevents the evaluated peak values to be dominated by single noise peaks. figure 13 peak detector unit peak detector is used to measure rssi independent of a data transfer and to digitally trim rssi. it is read via sfr rssiprx. observation of the rssi signal is active whenever the rx_run signal is high. the rssiprx register is refreshed and the peak detector is reset after every read access to rssiprx. it may be required to read rssiprx twice to obtain the required result. this is because, for example, during a trim procedure in which the input signal power is reduced, after reading rssiprx, the peak detector will still hold the higher rssi level. after reading rssiprx the lower rssi level is loaded into the peak detector and can be read by reading rssiprx again. register rssiprx should not be read-out faster than 41s in case agc is on (as register value would not represent the actual, but a lower value). when the rx_run signal is inactive, a read access has no influence to the peak detector value. the register rssiprx is reset to 0 at power up reset. peak detector wake-up rssipwu (see figure 10 ) is used to measure the input signal power during wake-up search. the internal signal rssipwu gets initialized to 0 at start of the first observation time window at the beginning of each configuration/channel. the peak value of this signal is tracked during wake-up search. a d from rssi generator rssi i&d averaging filter adc sampling clock generation f sys divide by 4 integrate dump to ask path f adc f adc /4 peak detector rssiprx read access to register rssiprx from spi controller update compare peak value load & from fsm rx_run rssi slope rssi offset rssirx
data sheet 35 v1.0, 2010-02-19 TDA5225 functional description in case of a wake-up, the actual peak value is written in the rssipwu register. even in case no wake-up occurred, actual peak value is written in the rssipwu register at the end of the actual configuration/channel of the self polling period. so if no wake-up occurred, then the rssipwu register contains the peak value of the last configuration/channel of the self polling period, even in a multi-configuration/multi- channel setup. this functionality can be used to track rssi during unsuccessful wake- up search due to no input signal or due to blocking rssi detection. for further details please refer to chapter 2.4.8.2 wake-up generator and chapter 2.6.2 polling timer unit . figure 14 peak detector behavior recommended digital trimming procedure ? download configuration file (run mode slave; rssislope, rssioffs set to default, i.e. rssislope=1, rssioffs=0) ? turn off agc (agcstart=0) and set gain to agcgain=0 ? apply p in1 = -85 dbm rf input signal ? read rssirx eleven times (minimum 10 ms in-between readings), use average of last ten readings (always), store as rssim1 ? apply p in2 = -65 dbm rf input signal ? read rssirx eleven times (minimum 10 ms in-between readings), use average of last ten readings (always), store as rssim2 ? calculate measured rssi slope slopem=(rssim2-rssim1)/(p in2 -p in1 ) ? adjust rssislope for required rssi slope sloper as follows: rssislope=sloper/slopem ? adjust rssioffs for required value rssir2 at p in2 as follows: rssioffs=(rssir2-rssim2)+(slopem-sloper)*p in2 ? the new values for rssislope and rssioffs have to be added to the configuration! data run-in reset run-in input data pattern noise noise internal rssi internal rssiprx = rssiprx register spi read out rssiprx spi data
TDA5225 functional description data sheet 36 v1.0, 2010-02-19 notes: 1. the upper rf input level must stay well below the saturation level of the receiver (see chapter 2.4.6.4 digital automatic gain control unit (agc) ) 2. the lower rf input level must stay well above the noise level of the receiver 3. if if attenuation is trimmed, this has to be done before trimming of rssi 4. if rssi needs to be trimmed in a higher input power range the agcgain must be set accordingly 2.4.8 digital baseband (dbb) receiver figure 15 functional block diagram digital baseband receiver the digital baseband receiver comprises a matched data filter and a data slicer. the received data signal is accessible via one of the port pins. 2.4.8.1 data filter the data filter is a matched filter ( mf ). the frequency response of a matched filter has ideally the same shape as the power spectral density ( psd ) of the originally transmitted signal, therefore the signal-to-noise ratio ( snr ) at the output of the matched filter becomes maximum. the input sampling rate of the baseband receiver has to be 8 to 16 samples per chip fractional src src bypass fs out / fs in = 0.5 ? 1.0 adjust_length matched filter raw data slicer for external processing data (sliced raw data for external processing ) from ask/ fsk demodulator mux sign data_matchfil (matched filtered data for external processing ) data invert data invert dinvext
data sheet 37 v1.0, 2010-02-19 TDA5225 functional description between 8 and 16 samples per chip. the oversampling factor within this range is depending on the data rate (see figure 10 ). the mf has to be adjusted accordingly to this oversampling. after the mf a fractional sample rate converter (src) is applied using linear interpolation. depending on the data rate decimation is adjusted within the range 1...2. finally, at the output of the fractional src the sampling rate is adjusted to 8 samples per chip for further processing. 2.4.8.2 wake-up generator a wake-up generation unit is used only in the self polling mode for the detection of exceeding a predefined level for rssi, which then leads to a wake-up and to a change to run mode self polling. a configurable observation time for wake-up on rssi can be set in the x_wulot register. the wake-up on rssi criterion can be handled very quickly for fsk modulation, while in case of ask the nature of this modulation type has to be kept in mind. figure 16 wake-up generation unit the threshold x_wurssithy is used to decide whether the actual signal is a wanted signal or just noise. any kind of interfering rssi level can be blocked by using an rssi blocking window. this window is determined by the thresholds x_wurssibly and x_wurssibhy, where y represents the actual rf channel. these two thresholds can be evaluated during normal operation of the application to handle the actual interferer environment. the blocking window can be disabled by setting x_wurssibhy to the minimum value and x_wurssibly to the maximum value. wu no wu compare rssi level x_wurssithy exceeding threshold wake-up generation fsm x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibhy x_wurssibly
TDA5225 functional description data sheet 38 v1.0, 2010-02-19 figure 17 rssi blocking thresholds threshold evaluation procedure a statistical noise floor evaluation using read register rssipmf (rms operation) leads to the threshold x_wurssithy. the interferer thresholds x_wurssibly and x_wurssibhy are disabled when they are set to their default values. for evaluation of the interferer thresholds, either use register rssipmf for rms operation or during spm and wu (wake-up) on rssi use register rssipwu to statistically evaluate the interferer band. finally the thresholds x_wurssibly and x_wurssibhy can be set. further details can be seen in figure 10 , chapter 2.4.7 rssi peak detector and chapter 2.6.2.2 constant on-off time (coo) . note: if e.g. an interferer ends/starts too close after/to the beginning/end of the observation time, then a decision level error can arise. this is due to the filter dynamics (settling time). further, for interferer thresholds evaluation in spm this changes interferer statistics. several interferer measurements are recommended to suppress this, what makes sense anyway for a better distribution. noise floor wanted signal interferer wanted signal x_wurssithy x_wurssibl y x_wurssibhy rssi magnitude
data sheet 39 v1.0, 2010-02-19 TDA5225 functional description 2.4.9 power supply circuitry the chip may be operated within a 5 volts or a 3.3 volts environment. figure 18 power supply for operation within a 5 volts environment (supply voltage range 1), the chip is supplied via the vdd5v pin. in this configuration the digital i/o pads are supplied via vdd5v and a 5 v to 3.3 v voltage regulator supplies the analog/rf section (only active in run modes). when operating within a 3.3 volts environment (supply voltage range 2), the vdd5v, vdda and vddd pins must be supplied. the 5 v to 3.3 v voltage regulators are inactive in this configuration. the internal digital core is supplied by an additional 3.3 v to 1.5 v regulator. the regulators for the digital section are controlled by the signal at p_on (power on) pin. a low signal at p_on disables all regulators and set the ic in power down mode. a low to high transition at p_on enables the regulators for the digital section and initiates a power on reset. the regulator for the analog section is controlled by the master control unit and is active only when the rf section is active. to provide data integrity within the digital units, a brownout detector monitors the digital supply. in case a voltage drop of vddd below approximately 2.45 v is detected a reset will be initiated. vdd5v power-up brownout detector reset- circuit rf section analog section vddd vdda gnda gndrf digital-i/o vddd1v5 digital-core gndd p_on internal reset voltage regulator 3.3 1.5 v enable out in voltage regulator 5 3.3 v out in en able voltage regulator 5 3.3 v en able out in enable rx_run
TDA5225 functional description data sheet 40 v1.0, 2010-02-19 a typical power supply application for a 3.3 volts and a 5 volts environment is shown in the figure below. figure 19 3.3 volts and 5 volts applications 5v vdda gnda gndrf vddd vdd5v vddd1v5 gndd supply -application in 3.3v environment tda 5225 3.3v 4.7 10 100n 100n 100n vdda gnda gndrf vddd vdd5v vddd1v5 gndd TDA5225 100n 100n 100n *) 1 *) 22 *) when operating in a 5v environment, the voltage-drop across the voltage regulators 5 ? 3.3v has to be limited , to keep the regulators in a safe operating range. resistive or capacitive loads (in excess to the scheme shown above) on pins vdda and vddd are not recommended. supply -application in 5v environment 4.7 100n 100n
data sheet 41 v1.0, 2010-02-19 TDA5225 functional description 2.4.9.1 supply current in sleep mode, the master control unit switches the crystal oscillator into low power mode (all internal load capacitors are disconnected) to minimize power consumption. this is also valid for self polling mode during off time (spm_off). whenever the chip leaves the sleep mode/spm_off (t 1 ), the crystal oscillator resumes operation in high precision mode and requires t coscsettle to settle at the trimmed frequency. at t 2 the analog signal path (rf and if section) and the rf pll are activated. at t 3 the chip is ready to receive data. the chip requires t rxstartup when leaving sleep mode/spm_off until the receiver is ready to receive data. a transient supply current peak may occur at t 1 , depending on the selected trimming capacitance. the average supply current drawn during t rfstartdelay is i rf-fe-startup,bpfcal . figure 20 supply current ramp up/down if the if buffer amplifier or the clock generation feature (ppx pin active) are enabled, the respective currents must be added. i sleep_low i rf-fe-startup ,bpfcal i run t c osc settle t supply current run mode*) sleep mode**) spm off time t on rx_run signal t 3 t 2 t 1 *) run mode covers the global chip states : run mode slave / receiver active in self polling mode / run mode self polling **) i sleep_low is valid in the chip states : sleep / off time during self polling mode t rxstartup t rfstartdelay (t off )(t off )
TDA5225 functional description data sheet 42 v1.0, 2010-02-19 2.4.9.2 chip reset power down and power on are controlled by the p_on pin. a low at this pin keeps the ic in power down mode. all voltage regulators and the internal biasing are switched off. a high transition at p_on pin activates the appropriate voltage regulators and the internal biasing of the chip. a power up reset is generated at the same time. figure 21 reset behavior a second source that can trigger a reset is a brownout event. whenever the integrated brownout detector measures a voltage drop below the brownout threshold on the digital internal reset supply voltage falls below reset- / brownout-threshold reset- / brownout- threshold (typ. 2.45v) 3v supply voltage at vddd pin t reset t functional- threshold (typ. 2v) reset- / brownout- threshold (typ. 2.45v) 3v voltage at pp2 pin (nint signal) functional- threshold (typ. 2v) a ?low? is generated at nint signal supply voltage falls below functional -threshold level on nint signal is undefined supply voltage rises above functional -threshold a ?low? is generated at pp2 pin (nint signal) c reads interrupt- status-registe r a ?low? is generated at pp2 pin (nint signal) a ?high? is generated at pp2 pin (nint signal) t
data sheet 43 v1.0, 2010-02-19 TDA5225 functional description supply, the integrity of the stored data and configuration can no longer be guaranteed; thus a reset is generated. while the supply voltage stays between the brownout and the functional threshold of the chip, the nint signal is forced to low. when the supply voltage drops below the functional threshold, the levels of all digital output pins are undefined. when the supply voltage raises above the brownout threshold, the ic generates a high pulse at nint and remains in the reset state for the duration of the reset time. when the ic leaves the reset state, the interrupt status registers (is0 and is1) are set to 0xff and the nint signal is forced to low. now, the ic starts operation in the sleep mode, ready to receive commands via the spi interface. the nint signal will go high, when one of the interrupt status registers is read for the first time.
TDA5225 functional description data sheet 44 v1.0, 2010-02-19 2.5 system interface in all applications, the TDA5225 receiver ic is attached to an external microcontroller. this so-called application controller executes a firmware which governs the TDA5225 by reading data from the receiver when data has been received on the rf channel and by configuring the receiver device. the TDA5225 features an easy to use system interface, which is described in this chapter. the TDA5225 supports the so-called transparent mode, which provides a rather rudimentary interface by which the incoming rf signal is demodulated and the corresponding data is made available to the application controller. the usage of the transparent mode will be described in chapter 2.5.1.2 . 2.5.1 interfacing to the TDA5225 the TDA5225 is interfacing with an application by three logical interfaces, see figure 22 . the rf/if interface handles the reception of rf signals and is responsible for the demodulation. its physical implementation has been described in chapter 2.4.3 and chapter 2.4.8 , respectively. the other two logical interfaces establish the connection to the application controller. for the sake of clarity, the communication between the TDA5225 and the application controller is split into control flow and data flow . this separation leads to an independent definition of the data interface and the control interface, respectively. figure 22 logical and electrical system interfaces of the TDA5225 TDA5225 application controller (c) rx data data interface configuration status & alerts control interface rf interface spi & di g. out dig. out
data sheet 45 v1.0, 2010-02-19 TDA5225 functional description 2.5.1.1 control interface the control interface is used in order to configure the TDA5225 after start-up or to re- configure it during run-time, as well as to properly react on changes in the status of the receiver in the application controller?s firmware. the control interface offers a bi- directional communication link by which ? configuration data is sent from the application controller to the TDA5225, ? the receiver provides status information (e.g. information about the source of a received data stream, by reading out the interrupt status registers) as response to a request it has received from the application controller, and ? the TDA5225 autonomously alerts the application controller that a certain, configurable event has occurred (e.g. that a received signal is above a certain power level). configuration and status information are sent via the 4-wire spi interface as described in chapter 2.5.4 . the configuration data determines the behavior of the receiver, which comprises ? scheduling the inactive power-saving phases as well as the active receive phases, ? selecting the properties of the rf/if interface configuration (e.g. carrier frequency selection, filter settings), ? configuring the properties of a received message (e.g. if the received signal strength is above a certain configurable rssi threshold level). note that the TDA5225 receiver ic supports reception of multiple configuration sets on multiple channels in a time-based manner without reconfiguration. thus, the rf/if interface as well as the message properties support alternative settings, which can be activated autonomously by the receiver as part of the scheduling process. in contrast to the high-level interface used for communicating configuration instructions and status information, alerts are emitted by the receiver on a digital output pin that may trigger external interrupts in the application controller. note that the alerting conditions as well as the polarity of the output pin are configurable, see chapter 2.5.3 . 2.5.1.2 data interface the data interface between the application controller and the TDA5225 receiver ic is used for the transport of the received data, see figure 22 . the features of the data interface depend on the selected mode of operation. there are two possible receive modes: ? transparent mode - matched filter (tmmf) ? transparent mode - raw data slicer (tmrds) access points for these receive modes can be seen in figure 15 .
TDA5225 functional description data sheet 46 v1.0, 2010-02-19 transparent mode - matched filter (tmmf) the received data after the matched filter (two-chip matched filter) with an additional sign function is provided via the data_matchfil signal (ppx pin). in this mode sensitivity measurements with ideal data clock can be performed very simple. for further details see the block diagram in figure 15 . sensitivity in this transparent mode is significantly depending on the implemented clock and data recovery algorithm of the user software in the application controller. figure 23 data interface for the transparent mode transparent mode - raw data slicer (tmrds) this mode supports processing of data even without bi-phase encoding (e.g. nrz encoding) by providing the received data via the one-chip matched filter on the data signal (ppx pin). see more details in the block diagram in figure 15 . sensitivity in this transparent mode is significantly depending on the implemented clock and data recovery algorithm of the user software in the application controller. the data interface can be seen from figure 23 . self polling capabilities are possible as well, so constant on-off mode and wake-up on rssi can be used. see also example for configuration b in figure 24 . the needed on time (latency through TDA5225) is configured in the corresponding on time registers of the chip. the interrupt for wake-up config b (wub) is enabled and suitable rssi thresholds are set. if the rssi signal is in a valid threshold area, the TDA5225 changes to run mode self polling and an interrupt can be signaled to the application controller. in case the rssi signal is outside the valid threshold area, the chip stays in self polling mode and the external controller gets no interrupt (as the desired rssi level is not reached). scheduler rx data data interface rf interface TDA5225 application controller
data sheet 47 v1.0, 2010-02-19 TDA5225 functional description when the actual processed configuration is the last configuration before the off time, then the next programmed channel within the polling cycle would be the sequence of the off time. when data is available and the rssi is within a valid threshold area, an interrupt is generated (nint). so the application controller can process the data and decide about valid data. in case the controller decides that wrong data was sent, the microcontroller can send the register command "exttotim" (see figure 43 and extpcmd register). when the microcontroller detects valid data, then the controller can send the register command "exteom found" (see figure 43 and extpcmd register) after completing the data reception. the functionality described above can also be used for the receive mode tmmf, where the external microcontroller takes on responsibility for further data processing. figure 24 external data processing configb configa selfpolling mode selfpolling scenario sleep mode runmode selfpolling selfpolling / sleep interrupt signal for rssi runmode selfpolling selfpolling / sleep no input signal rssi level too low ? chip stays in self polling mode and sends no interrupt wrong input signal interrupt signal for rssi c detects invalid data and sends ?exttotim? ? goto spm off-time runmode selfpolling selfpolling / sleep good input signal interrupt signal for rssi c finished data reception, sends ?exteom found?
TDA5225 functional description data sheet 48 v1.0, 2010-02-19 2.5.2 digital output pins as long as the p_on pin is high, all digital output pins operate as described. if the p_on pin is low, all digital output pins are switched to high impedance mode. the digital outputs pp0, pp1, pp2 and pp3 are configurable, where each of the signals clk_out, rx_run, nint, a low level (gnd) and a high level, data and data_matchfil can be routed to any of the four output pins. there is only one exception, clk_out is not available on pp3. the default configuration for these four output pins can be seen in table 1 . each port pin can be inverted by usage of ppcfg2 register. the rx_run signal is active high for all configurations by default. it can be deactivated for every configuration separately. every ppx can be configured with an individual rx_run setup. this can be set in rxruncfg0 and rxruncfg1 registers. interfacing to 3.3v logic: the TDA5225 is able to interface directly to a 3.3v logic, when chip is operated in 3.3v environment. interfacing to 5v logic: the TDA5225 is able to interface directly to a 5v logic, when chip is operated in 5v environment. emc reduction of digital i/os: because electromagnetic distortion generated by digital i/os may interfere with the high sensitivity radio receiver, it is recommended that all inputs are filtered by adding an rc low pass circuit. 2.5.3 interrupt generation unit the TDA5225 is able to signal interrupts (nint signal) to the external application controller on one of the ppx port pins (for further details see chapter 2.5.2 digital output pins ). the interrupt generation unit receives all possible interrupts and sets the nint signal based on the configuration of the interrupt mask registers (im0 and im1). the interrupt status registers (is0 and is1) are set from the interrupt generation unit, depending on which interrupt occurred. the polarity of the interrupt can be changed in the ppcfg2 register. please note that during power up and brownout reset, the polarity of nint signal is always as described in chapter 2.4.9.2 chip reset . a reset event has the highest priority. it sets all bits in the status registers to ?1? and sets the interrupt signal to ?0?. the first interrupt after the reset event will clear the status registers and will set the interrupt signal to ?1?, even if this interrupt is masked. an wu interrupt clears the complementary flags for wu.
data sheet 49 v1.0, 2010-02-19 TDA5225 functional description the interrupt status register is always cleared after read out via spi. it is not possible to disable the power on reset indicator interrupt using the interrupt mask registers. figure 25 interrupt generation unit figure 26 interrupt generation waveform (example for configuration a+b) is1 + is0 interrupt-mask interrupt-signalling im1 + im0 power-up / brownout reset nint nint signal wu cfg a wua wu cfg d wu cfg c wud wuc wu cfg b wub reset wu(a,b) pp2(nint) pp2inv pp2_select=nint is0 x ff 01 10 spi read is0 00 configb configa
TDA5225 functional description data sheet 50 v1.0, 2010-02-19 the following handling mechanism for read-clear registers was chosen due to implementation of the burst read command: ? the current interrupt status (isx) register 8-bit content is latched into the spi shift register after the last address bit is clocked-in ( point a in figure 27 ) ? the is register is then cleared after last is register bit is clocked out of the spi interface ( point b in figure 27 ) consequence: any interrupt event occurring in the window-time between points a and b is cleared at point b and not stored/shown in an later readout of isx. (however: nint signal is toggling in any case, if occurring interrupt is not masked in imx register) figure 27 isx readout set clear collision please see also the important note in the burst read section ! ncs inst addr read /readb data = is(t+0) read/capture is* content sfr is* read clear @end of data frame nint irq1 (masked?) irq2 (masked?) sfr is* is(t+0) is(t+1) 0x00 is(t-1) note: sfr is(j) status flag is cleared before it can be read if an irq occurs during spi data frame spi if 8-bit @2mhz = 4us a b
data sheet 51 v1.0, 2010-02-19 TDA5225 functional description 2.5.4 digital contro l (4-wire spi bus) the control interface used for device control is a 4-wire spi interface. ? ncs - select input, active low ? sdi - data input ? sdo - data output ? sck - clock input: data bits on sdi are read in at rising sck edges and written out on sdo at falling sck edges. level definition: logic 0 = low voltage level logic 1 = high voltage level note for non-burst modes: it is possible to send multiple frames while the device is selected. it is also possible to change the access mode while the device is selected by sending a different instruction. note: in all bus transfers msb is sent first. to read from the device , the spi master has to select the spi slave unit first. therefore, the master must set the ncs line to low. after this, the instruction byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the data byte at this address is then shifted out on sdo . after completing the read operation, the master sets the ncs line to high. figure 28 read register data out sdi sdo high impedance z sck ncs d7 d6 d5 d4 instruction i7 i6 i3 i2 regist er address i1 i0 frame i5 i4 a7 a6 a3 a2 a1 a0 a5 a4 d3 d2 d1 d7 d6 d5 d4 instruction register address d3 d2 d1 d0 data out frame 181818181818 d0 i7 i6 i3 i2 i1 i0 i5 i4 a7 a6 a3 a2 a1 a0 a5 a4
TDA5225 functional description data sheet 52 v1.0, 2010-02-19 to read from the device in burst mode , the spi master has to select the spi slave unit first. therefore the master has to drive the ncs line to low. after the instruction byte and the start address byte have been transferred to the spi slave (msb first), the slave unit will respond by transferring the register contents beginning from the given start address (msb first). driving the ncs line to high will end the burst frame. figure 29 burst read registers important note - for being upwards compatible with further versions of the product, we give following strong recommendation: for read-clear registers at address (n), no read-burst access stopping at address (n-1) is allowed, because read-clear register will be cleared without being read out. use single read command to read out the register at address (n-1) or extend the burst read to include the read-clear register at address (n). to write to the device, the spi master has to select the spi slave unit first. therefore, the master must set the ncs line to low. after this, the instruction byte and the address byte are shifted in on sdi and stored in the internal instruction and address register. the following data byte is then stored at this address. after completing the writing operation, the master sets the ncs line to high. additionally the received address byte is stored into the register spiat and the received data byte is stored into the register spidt . these two trace registers are readable. therefore, an external controller is able to check the correct address and data transmission by reading out these two registers after each write instruction. the trace data out (i) sdi sdo high impedance z sck ncs d7 d6 d5 d4 instruction i7 i6 i3 i2 register start address i1 i0 i5 i4 a7 a6 a3 a 2 a1 a0 a5 a4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 data out (i+x) 181818 18 d0 d7 d6 d5 d4 d3 d2 d1 d0 data out (i+1) 18 d7 d0
data sheet 53 v1.0, 2010-02-19 TDA5225 functional description registers are updated at every write instruction, so only the last transmission can be checked by a read out of these two registers. figure 30 write register to write to the device in burst mode , the spi master has to select the spi slave unit first. therefore the master has to drive the ncs line to low. after the instruction byte and the start address byte have been transferred to the spi slave (msb first) the successive data bytes will be stored into the automatically addressed registers. to verify the spi burst write transfer, the current address (start address, start address + 1, etc.) is stored in register spiat and the current data field of the frame is stored in register spidt. at the end of the burst write frame the latest address as well as the latest data field can be read out to verify the transfer. note that some error in one of the intermediate data bytes can not be detected by reading spidt. driving the ncs line to high will end the burst frame. a single spi burst write command can be applied very efficiently for data transfer either within a register block of configuration dependent registers or within the block of configuration independent registers. figure 31 burst write registers sdi sdo high impedance z sck ncs instruction frame 18 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 regist er address 18 data byte 18 instruction frame 18 register address 18 data byte 18 a7 a6 a3 a2 a1 a0 a5 a4 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d2 a7 a6 a3 a2 a1 a0 a5 a4 sdi sdo high impedance z sck ncs instruction 18 i7 i6 i3 i2 i1 i0 i5 i4 d7 d6 d5 d4 d1 d0 d3 d 2 register start address 18 data byte (i) 18 data byte (i+1) 18 data byte (i+x) 18 a7 a6 a3 a2 a1 a0 a5 a4 d7 d6 d5 d4 d1 d0 d3 d2 d7 d6 d3 d2 d1 d0 d5 d 4
TDA5225 functional description data sheet 54 v1.0, 2010-02-19 the spi also includes a safety feature by which the checksum is calculated with an xor operation from the address and the data when writing sfr registers. the checksum is in fact an xor of the data 8-bitwise after every 8 bits of the spi write command. the calculated checksum value is automatically written in the spichksum register and can be compared with the expected value. after the spichksum register is read, its value is cleared. in case of an spi burst write frame, a checksum is calculated from the spi start address and consecutive data fields. figure 32 spi checksum generation table 4 instruction set instruction description instruction format wr write to chip 0000 0010 rd read from chip 0000 0011 wrb write to chip in burst mode 0000 0001 rdb read from chip in burst mode 0000 0101 spi shift register xor checksum sfr read/clear enable every 8 bit
data sheet 55 v1.0, 2010-02-19 TDA5225 functional description 2.5.4.1 timing diagrams figure 33 serial input timing figure 34 serial output timing ncs sdi t sdi_hold t sdi_ se tu p t not_hold t n o t_ se tu p t hold sdo high impedance z t de se le ct sck t cl k_ h t cl k_ l t se tu p z sdo sdi z addr lsb ncs sck t cl k_ sdo t sdo_disable t sdo _ r t sdo _ f t cl k_ h t cl k_ l t cl k_ sdo
TDA5225 functional description data sheet 56 v1.0, 2010-02-19 2.5.5 chip serial number every device contains a unique, preprogrammed 32-bit wide serial number. this number can be read out from sn3, sn2, sn1 and sn0 registers via the spi interface. the TDA5225 always has sn0.6 set to 0 and sn0.5 set to 1. figure 35 chip serial number table 5 spi bus timing parameter symbol parameter f clock clock frequency t clk_h clock high time t clk_l clock low time t setup active setup time t not_setup not active setup time t hold active hold time t not_hold not active hold time t deselect deselect time t sdi_setup sdi setup time t sdi_hold sdi hold time t clk_sdo clock low to sdo valid t sdo_r sdo rise time t sdo_f sdo fall time t sdo_disable sdo disable time fuses ...... fuse- readout- interface sn0 sn1 sn2 ...... sn3
data sheet 57 v1.0, 2010-02-19 TDA5225 functional description 2.6 system management unit (smu) the system management unit consists of two main units: ? master control unit , where the various operating modes can be configured. ? polling timer unit , where the receiver?s on and off times and modes are defined. the polling timer unit is only working in the self polling mode. 2.6.1 master control unit (mcu) 2.6.1.1 overview the master control unit controls the operation modes and the global states. the transparent data stream can be processed externally by the application controller (see chapter 2.5.1.2 data interface ). the following operation modes and the behavior of the master control unit are fully automatic and only influenced by sfr settings and by incoming rf data streams. the TDA5225 has two major operation modes, which are switched by sfr bit msel. in slave mode the device is controlled via spi by the external microcontroller. this mode supports: ? run mode slave (rms) , where the receiver is continuously active ? sleep mode , where the receiver is switched off for power saving. this mode can also be used to change register settings ? hold mode , allows register settings to be changed. the change to hold mode and back to rms is faster than changing to sleep mode and back to rms. in slave mode, switching between configurations and channels, as well as between run and sleep mode must be initiated by the microcontroller. in self polling mode, TDA5225 autonomously polls for incoming rf signals. the receiver switches automatically between up to four configurations (configuration a, b, c and d) and up to 3 channels per configuration (further information can be found in chapter 2.6.2 ). between the rf signal scans, the receiver is automatically switched to low power mode for reducing the average power consumption. if an incoming signal fulfills the selected wake-up criterion an interrupt can be generated and run mode self polling will be entered.
TDA5225 functional description data sheet 58 v1.0, 2010-02-19 figure 36 global state diagram 2.6.1.2 run mode slave (rms) in run mode slave, the receiver is able to continuously scan for incoming data streams. detection and validation of a wake-up criterion are not performed. the transparent data stream can be processed externally by the application controller (see chapter 2.5.1.2 data interface ). run mode slave is entered by setting sfr cmc0 bits msel to 0 and slrxen to 1. configurations are switched via sfr bit group mcs in the cmc0 register. the rf channel in use can be selected in the x_chcfg register, the frequency selection is defined by sfrs x_pllintcy, x_pllfrac0cy, x_pllfrac1cy, x_pllfrac2cy, where x = a, b, c or d and y = 1, 2 or 3. the configuration may be changed only in sleep or in hold mode before returning to the previously selected operation mode. this is necessary to restart the state machine sleep mode chip is idle init initialize rx-part run mode slave chip is permanently active bit:slrxen == 1 bit:msel == 0 init self polling mode bit:slrxen == 0 or bit:msel == 1 bit:slrxen == 1 bit:msel == 0 bit:slrxen == 0 bit:msel == 0 bit:slrxen == x bit:msel == 1 bit:slrxen == x bit:msel == 0 chip is periodically active and searching for wu criteria run mode self polling bit:slrxen == x bit:msel == 0 totim timeout == x bit:slrxen == x bit:msel == 1 wuc found == 0 bit:slrxen == 1 bit:msel == 0 bit :slrxen == x bit :msel == 1 bit:slrxen == x bit:msel == 1 wuc found == 1 chip is permanently active initialize rx-part reset bit:slrxen == x bit:msel == 1 totim timeout == 0 bit:slrxen == x bit:msel == 1 totim timeout == 1 bit:slrxen == x bit:msel == 0 bit :slrxen == 0 or bit :msel == 1 bit:slrxen == x bit:msel == 1 eom found == 1
data sheet 59 v1.0, 2010-02-19 TDA5225 functional description with defined settings at a defined state. otherwise the state machine may hang up. reconfigurations in hold mode are faster, because there is no start-up sequence. the following flowchart and explanation show and help to understand the internal behavior of the finite state machine (fsm) in run mode slave. figure 37 run mode slave 2.6.1.3 hold mode this state (item 4 in figure 37 ) is used for fast reconfiguration of the chip in run mode slave. hold state can be reached after the start-up sequencer and initialization of the chip have been completed and the chip is working in state 3. to reconfigure the chip the sfr control bit hold must be set. after reconfiguration in this state the sfr control bit hold must be cleared again. after leaving the hold state, the init state is entered and the receiver can work with the new settings. be aware that the time between changing the configuration and reinitialization of the chip has to be at least 40us. take note that one spi command for clearing the sfr control bit hold needs 24 bits or 12 s at an spi data rate of 2.0mbit/s. the remaining 28 s must be guaranteed by the application. figure 38 hold state behavior (initpllhold disabled) receive data available at port pin no change in operating mode startup finished == 0 wait wait till startup has finished startup finished == 1 init 1 2 3 hold ready for reconfiguration 4 hold == 1 hold == 0 data available at port pin fsm state address cmc0 instruction wr i te 0x02 data hold=1 spi command instruction wr i te 0x02 address x_chcfg/ x_pll.. data (sel. other channel) address cmc0 instruction write 0x02 data hold=0 hold init data available at port pin 12 us @ 2. 0mhz 40 us
TDA5225 functional description data sheet 60 v1.0, 2010-02-19 in case of large frequency steps, an additional vac routine (vco automatic calibration) has to be activated when recovering from hold mode (initpllhold bit). the maximum allowed frequency step in hold mode without activation of vac routine is depending on the selected frequency band. the limits are +/- 1 mhz for the 315 mhz band, +/- 1.5 mhz for the 434 mhz band and +/- 3 mhz for the 868/915 mhz band. when this additional vac routine is enabled, the TDA5225 starts initialization of the digital receiver block after release from hold and an additional channel hop time. figure 39 hold state behavior (initpllhold enabled) hold mode is only available in run mode slave. configuration changes in self polling mode have to be done by switching to sleep mode and returning to self polling mode after reconfiguration. 2.6.1.4 sleep mode the sleep mode is a power save mode. the complete rf part is switched off and the oscillator is in low power mode. as in hold mode, the chip can be reconfigured. when switching from sleep to run mode slave, the state machine starts with the internal start-up sequence. 2.6.1.5 self polling mode (spm) in self polling mode TDA5225 autonomously polls for incoming rf wake-up data streams. at that time there is no processing load on the host microcontroller. when a wake-up criterion has been found, an interrupt can be generated and the TDA5225 mode will be changed to run mode self polling. a general overview on a typically transmitted protocol and the behaviour of the TDA5225 is given in figure 40 . dat a available at port pin fsm state address cmc0 instruction wr ite 0x02 data hold=1 spi command instruction wr ite 0x02 address x_chcfg/ x_pll.. data (sel. other channel) address cmc0 instruction wr i te 0x02 data hold=0 hold init data available at port pin 12 us @ 2. 0m hz 40 us vac vac t c_ hop
data sheet 61 v1.0, 2010-02-19 TDA5225 functional description figure 40 spm - tx-rx interaction the transparent data stream can be processed externally by the application controller (see chapter 2.5.1.2 data interface ). self polling mode is entered by setting the msel register bit to 1. configuration changes are allowed only by switching to sleep mode, and returning to self polling mode after reconfiguration. the polling timer unit controls the timing for scanning (on time) and sleeping (off time, spm_off). up to four independent configuration sets (a, b, c and d) can automatically be processed, thus enabling scanning from different transmit sources. additionally, up to 3 different frequency channels within each configuration may be scanned to support multi-channel applications. see also chapter 2.6.2 polling timer unit . so a total number of up to 12 different frequency channels is supported. the wake-up generation unit identifies, whether an incoming data stream matches the configurable wake-up criterion. after fulfillment of the wake-up criterion, modulation can be switched automatically. see also chapter 2.6.1.6 automatic modulation switching and chapter 2.5.1.2 data interface (in subsection tmrds). the following state diagrams and explanations help to illustrate the behavior during self polling mode. first there is a search for a wake-up criterion according to configuration a on up to three different channels. then, there is an optional search for a wake-up criterion according to configuration b, c and d, again including up to 3 channels. in applications using only single-configuration, settings are always taken from configuration a. (runin) tsi payload tx - rx interaction in rx - self polling mode tx telegram: eom runin + wake-up sequence data frame wake-up frame wake-up frame continued or gap 1) rx mode: run mode self polling legend: 1) there can either be a wake -up frame directly followed by a data frame or the wake -up frame is separated from the data f rame by a gap in -between . 2) the position of the o n time can vary ( a , b , ...) as there is no synchronization between transmitted telegram and start of the receiver?s on time. on time 2) self polling mode on time 2) self polling mode a b
TDA5225 functional description data sheet 62 v1.0, 2010-02-19 figure 41 wake-up search with configuration a idle chip is idle startup finished == 0 wait wait till startup has finished startup finished == 1 init with cfg a initialize rx- part configuration a modulation switching cfg a modulation selection depending on register setting rx_run=0 load channel 1 load channel 2 load channel 3 loop counter == 10 compare compare loop counter against number of channels increment loop counter incrementation of the loop counter loop counter == 11 store channel store the current channel configuration into actual channel register loop counter <> anoc init loop counter cfgloopcounter , loop counter is initialized initialize rx- part multi channel a initialize rx-part multi channel a initialize rx-part multi channel a loop counter equal anoc == 1 cfgloopcounter <> cfgnr rx_run == 0 rx_run == 1 to init loop counter of config b from compare of config b, c, d loop counter == anoc cfgloopcounter == cfgnr generating cfg a interrupt if not masked wu search with configuration a from run mode self polling wu search cfg a coot search for a configurated wake up criteria const on off const on time on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 1 2 3 4 5 6 11 11 7 9 10 8 run mode self polling chip is permanently active 12
data sheet 63 v1.0, 2010-02-19 TDA5225 functional description figure 42 wake-up search with configuration b, c, d init with cfg b,c,d initialize rx-part configuration b ,c,d modulation switching cfg b,c,d modulation selection depending on register setting init loop counter loop counter is initialized run mode self polling chip is permanently active from compare of config a, b, c to idle of config a wu search with configuration b, c, d load channel 1 load channel 2 load channel 3 loop counter == 10 compare compare loop counter against number of channels increment loop counter incrementation of the loop counter loop counter == 11 store channel store the current channel configuration into actual channel register loop counter <> (b,c,d)noc initialize rx-part multi channel b,c,d initialize rx-part multi channel b,c,d initialize rx-part multi channel b,c,d loop counter == (b,c,d)noc cfgloopcounter == cfgnr generating cfg b ,c,d interrupt if not masked wu search cfg b,c,d coot search for a configurated wake up criteria const on off on time elapsed == 0 wu found == 0 on time elapsed == x wu found == 1 on time elapsed == 1 wu found == 0 const on time 3 4 5 6 11 7 9 10 8 12 11 loop counter equal (b,c,d)noc == 1 cfgloopcounter <> cfgnr to init loop counter of config c,d
TDA5225 functional description data sheet 64 v1.0, 2010-02-19 2.6.1.6 automatic modulation switching in self polling mode , the chip is able to automatically change the type of modulation after a wake-up criterion was fulfilled in a received data stream. the type of modulation used in the different operational modes is selected by the sfr control bit mt. 2.6.1.7 multi-cha nnel in self polling mode as previously mentioned, in self polling mode the TDA5225 allows rf scans on up to three rf channels per config uration, this can be defin ed in the x_chcfg register. channel frequencies are defined in registers x_pllintcy, x_pllfrac0cy, x_pllfrac1cy, x_pllfrac2cy, where x = a, b, c or d and y = 1, 2 or 3. the channel number at which a wake-up criterion has been found is available in register rfpllacc. see also chapter 2.4.5 sigma-delta fractional-n pll block . 2.6.1.8 run mode self polling (rmsp) wake-up criterion fulfillment in self polling mode for rssi leads to a change to run mode self polling and a transparent data stream can be processed externally by the application controller (see chapter 2.5.1.2 data interface ). modulation switching is performed automatically, depending on register settings (see chapter 2.6.1.6 automatic modulation switching ) depending on interrupt masking, the host microcontroller is alerted when the level criterion rssi is fulfilled. see also chapter 2.5.3 interrupt generation unit run mode self polling is left, when the timeout timer command ?exttotim? is sent by the application controller, or when an ?exteom found? command is sent by the microcontroller and the sfr bit eom2spm is activated, or when the operating mode is switched to sleep or run mode slave by the host microcontroller. when the TDA5225 gets the ?exttotim? command, the receiver proceeds with self polling mode and with searching for a suitable wake-up criterion on the next programmed channel (either next rf channel or next configuration, depending on the selected mode - multi-configuration or multi-channel or a mix of both) or a search for a wake-up criterion in configuration a is initiated. as long as the chip is in run mode self polling, the transparent data stream can be processed externally by the application controller. after an eom was found, the information about the rf channel and the configuration of the actual payload data is saved in the rfpllacc register. after receiving the ?exteom found? command the TDA5225 can either proceed with a search for a wake-up criterion in the next configuration or a search for wake-up in
data sheet 65 v1.0, 2010-02-19 TDA5225 functional description configuration a can follow or the TDA5225 can proceed receiving another (redundant) payload data frame within the same configuration. the transparent data stream has to be processed externally by the application controller. therefore the external controller needs the possibility to send following commands (see figure 43 and extpcmd register as well): ? exttotim: so the TDA5225 can proceed with self polling mode (either with the next programmed channel or with configuration a). ? exteom found: in this case the TDA5225 can either proceed with self polling mode (either with the next configuration or with configuration a) or stay in run mode self polling. when the actual processed configuration is right before the off time and the application controller sends one of the above mentioned commands, then the TDA5225 can proceed with the off time (in case next configuration is selected). in constant on-off time mode the polling timer is always initialized after a totim or eom event. this means a new on period is always started.
TDA5225 functional description data sheet 66 v1.0, 2010-02-19 figure 43 run mode self polling receive data avaialble at port pin modulation selection depending on register setting modulation switching all operations are done with the wake up configuration exteom found command sent by external controller eom found == 1 no change in operating mode to self polling mode (wu search with next programmed channel) init 1 2 3 6 goto next config after eom to self polling mode (wu search with next configuration) eom2ncfg == 1 9 eom 2ncfg == 0 to self polling mode (wu search with configuration a) goto sp next programmed channel 5 totim2nch == 0 to self polling mode (wu search with configuration a ) totim2nch == 1 exttotim command sent by external controller 4 totim timeout == 1 save channel and configuration information 7 goto selfpolling after eom 8 eom2spm == 1 eom2spm == 0 init 10 init digital receiver initdrxes==0 initdrxes==1
data sheet 67 v1.0, 2010-02-19 TDA5225 functional description 2.6.2 polling timer unit figure 44 polling timer unit the polling timer unit consists of a counter stage and a control fsm (finite state machine). the counter stage is divided into three sub-modules. the reference timer is used to divide the state machine clock (f sys /64) into the slower clock required for the spm timers. the on-off timer and the active idle period timer are used to generate the polling signal. the entire unit is controlled by the spm fsm. the TDA5225 is able to handle up to four different sets of configurations automatically. however, the example and figure in this subsection only show up to two configuration sets for the sake of clarity. self-polling-mode (spm) fsm spm reference-timer (8 bit) spm on -off-timer (14 bit) spm active-idle period timer (5 / 8 bit) polling mode spmrt spmofft0 spmofft1 spmap spmip f onoff f sys / 64 f rt timer-control timer-control timer-control timer-status timer-status spmc receiver-enable to master-control-unit no wu spmontx0 spmontx1
TDA5225 functional description data sheet 68 v1.0, 2010-02-19 2.6.2.1 self polling mode an actual value for rssi exceeding a certain adjustable threshold forces the TDA5225 into run mode self polling. the timing resolution is defined by the reference timer, which scales the incoming frequency (f sys /64) corresponding to the value, which is defined in the self polling mode reference timer (spmrt) register. changing values of spmrt helps to fit the final on- off timing to the calculated ideal timing. 2.6.2.2 constant on-off time (coo) in this mode there is a constant on and a constant off time. therefore also the resulting master period time is constant. the on and off time are set in the spmonta0, spmonta1, spmontb0, spmontb1, spmontc0, spmontc1, spmontd0, spmontd1, spmofft0 and spmofft1 registers. the on time configuration is done separately for configuration a, b, c and d. when single-configuration is selected then only configuration a is used. the number of rf channels is defined in the a_chcfg register ( single-channel or multi-channel mode). multi-configuration mode allows reception of up to 4 different transmit sources. the corresponding rf channels can be defined in the a_chcfg, b_chcfg, c_chcfg and d_chcfg registers. in the case of multi-channel or combination of multi-channel and multi-configuration mode, the configured on time is used for each rf channel in a configuration. the diagram below shows possible scenarios. all receive modes described in chapter 2.5.1.2 data interface can be used.
data sheet 69 v1.0, 2010-02-19 TDA5225 functional description figure 45 constant on-off time calculation of the on time: the on time for each channel must be long enough to ensure proper detection of a specified wake-up criterion. therefore the on time depends on the wake-up pattern. it has to include transmitter data rate tolerances. t on also must include the relevant start-up times. in case of the first channel after t off , this is the receiver start-up time. in case of following channels (rf receiver is already on, there is only a change of the channel or the configuration), e.g. if configuration b is used, this is the channel hop latency time. calculation of the off time: the longer the off time, the lower the average power consumption in self polling mode. on the other hand, the off time has to be short enough that no transmitted wake-up pattern is missed. therefore the off time depends mainly on the duration of the expected wake-up pattern. if there are further channels scanned, t off has to be reduced by the related additional on times. a 1 a 2 a 3 a 1 t aon t off t masterperiod t aon t aon t aon t off t masterperiod single channel, single config multi channel, single config multi channel, multi config a 1 a 2 a 3 t aon t aon t aon t off t masterperiod b 1 b 2 t bon t bon channels = 1 t masterperiod = t aon + t off channels = m t masterperiod = m*t aon + t off channels config a = m channels config b = n t masterperiod = m*t aon + n*t bon + t off rx polling run mode sleep mode rx polling run mode sleep mode rx polling run mode sleep mode
TDA5225 functional description data sheet 70 v1.0, 2010-02-19 for basic timing of wu on rssi in coo mode, please see figure 46 . figure 46 coo polling in wu on rssi mode always check at the end of the current observation time window, if there is a wu (wake- up) event or not. this means, in algorithmic description (see also figure 10 , chapter 2.4.7 rssi peak detector and chapter 2.4.8.2 wake-up generator ): if (rssipwu_value > x_wurssithy) and (rssipwu_value > x_wurssibhy) then wu else not here, ?not? means to keep on evaluating and move on to the next observation time window, also keep on peak value tracking of rssipwu signal. keep on walking through the observation time windows until there is a wu event from the algorithm above or finally decide at the end of the on time with the following algorithm: if (rssipwu_value > x_wurssithy) and (rssipwu_value < x_wurssibly or rssipwu_value > x_wurssibhy) then wu else not if there is a wu event at the end of an observation time window while walking through the observation time windows, freeze/hold this decision/peak value in register rssipwu for optional read out and switch to run mode self polling. rf signal e.g . ask rx on sleep t startup t on t t t wulot t wulot 12 t wulot t wulot_part n-1 n partially last observation time window is forced to end by end of t on latest decision here !
data sheet 71 v1.0, 2010-02-19 TDA5225 functional description 2.6.2.3 active idle period selection this mode is used to deactivate some polling periods and can additionally be applied to the above mentioned polling mode. normally, polling starts again after the t masterperiod . with this active idle period selection some of the polling periods can be deactivated, independent from the polling mode. the active and the idle sequence is set with the spmap and the spmip registers. the values of these registers determine the factor m and n. figure 47 active idle period sleep mode rx polling run mode t on t off t masterperiod n*t masterperiod m*t masterperiod active idle
TDA5225 functional description data sheet 72 v1.0, 2010-02-19 2.7 definitions 2.7.1 definition of bit rate the definition for the bit rate in the following description is: if a symbol contains n chips (for manchester n=2; for nrz n=1) the chip rate is n times the bit rate: 2.7.2 definition of manchester duty cycle several different definitions for the manchester duty cycle (mdc) are in place. to avoid wrong interpretation some of the definitions are given below. figure 48 definition a: level-based definition this definition determinates the duty cycle to be the ratio of the high pulse width and the ideal symbol period. the dc content is constant and directly proportional to the specified duty cycle. for t > 0 the high period is longer than the chip-period and for t < 0 the high period is shorter than the chip-period. bitrate symbols s --------------------- - = chiprate n bitrate = level-based definition mdc = duration of h-level / symbol period bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p mdc < 50% 1 0 0 1 1 t bit t h t bit t h t c h i p t mdc > 50% t bit t h t bit t h t c h i p t
data sheet 73 v1.0, 2010-02-19 TDA5225 functional description depending on the bit content, the same type of edge (e.g. rising edge) is sometimes shifted and sometimes not. with this definition the manchester duty cycle is calculated to figure 49 definition b: chip-based definition this definition determinates the duty cycle to be the ratio of the first symbol chip and the ideal symbol period independently of the information bit content. the dc content depends on the information bit and it is balanced only if the message itself is balanced. for t > 0 the first chip-period is longer than the ideal chip-period and for t < 0 the first chip-period is shorter than the ideal chip-period. depending on the bit content, the same type of edge (e.g. rising edge) is sometimes shifted and sometimes not. mdc a t h t bit --------- t chip t + t bit -------------------------- - == bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p chip-based definition mdc = duration of the first chip / symbol period mdc < 50% 1 0 0 1 1 mdc > 50% t bit t 1.chip t c h i p t t bit t 1.chip t bit t 1.chip t bit t 1.chip t c h i p t
TDA5225 functional description data sheet 74 v1.0, 2010-02-19 with this definition the manchester duty cycle is calculated to figure 50 definition c: edge delay definition this definition determinates the duty cycle to be the ratio of the duration of the delayed high-chip and the ideal symbol period independently of the information bit content. the position of the high-chip is determined by the delayed rising edge and/or the delayed falling edge. for t = t fall -t rise the manchester duty cycle is calculated to independent on the bit content, the same type of edge (rising edge and/or falling edge) is shifted. mdc b t 1.chip t bit ---------------- t chip t + t bit -------------------------- == bit = 1 0 0 1 1 1. chip 2. chip t bit t c h i p edge delay definition mdc = duration delayed edge / symbol period 1 0 0 1 1 mdc < 50% t f = 0 t c h i p t t bit t h t bit t r t h 1 0 0 1 1 mdc > 50% t r = 0 t c h i p t t bit t bit t f t h t f t bit t h t bit t r mdc c t delayedhighchip t bit ---------------------------------------- t chip t + t bit -------------------------- t chip t fall t rise ? + t bit ----------------------------------------------- - ===
data sheet 75 v1.0, 2010-02-19 TDA5225 functional description 2.7.3 definition of power level the reference plane for the power level is the input of the receiver board. this means, the power level at this point (p r ) is corrected for all offsets in the signal path (e.g. attenuation of cables, power combiners etc.). the specification value of power levels in terms of sensitivity is related to the peak power of p r in case of on-off keying (ook). this is noted by the unit dbm peak. specification value of power levels is related to a manchester encoded signal with a manchester duty cycle of 50% in case of ask modulation. an rf signal generator usually displays the level of the unmodulated carrier (p carrier ). this has following consequences for the different modulation types: for power levels in sensitivity parameters given as average power, this is noted by the unit dbm. peak power can be calculated by adding 3 db to the average power level in case of ask modulation and a manchester duty cycle of 50%. 2.7.4 symbols of sfr registers and control bits figure 51 sfr symbols table 6 power level modulation scheme realization with rf signal generator power level specification value ask am 100% p r = p carrier + 6db ask pulse modulation (=ook) p r = p carrier fsk fm with deviation f: f 1 = f carrier - f f 2 = f carrier + f p r = p carrier symbolizes unique sfr registers or sfr control bit (s), which are common for all configuration sets . control control symbolizes sfr registers or sfr control bit(s) with multi-configuration capability (protocol specific). in case of sfr register, the name starts with a _, b_, c_ or d_, depending on the selected configuration. this is generally noted by the prefix ?x _?.
TDA5225 functional description data sheet 76 v1.0, 2010-02-19 2.8 digital control (sfr registers) 2.8.1 sfr address paging an spi instruction allows a maximum address space of 8 bit. the address space for supporting more than one configuration set is exceeding this 8 bit address room. therefore a page switch is introduced, which can be applied via register sfrpage (see figure 52 ). figure 52 sfr address paging 2.8.2 sfr register list and detailed sfr description the register list is attached in the appendix at the end of the document. registers for configurations b, c and d are equivalent and not shown in detail. all registers with prefix ?a_? are related to configuration a. all these registers are also available for configuration b, c and d having the prefix ?b_?, ?c_? and ?d_?. logical address space 0x000 0x 0f f 0x100 0x180 0x200 0x 1f f 0x280 0x 2f f 0x300 0x380 0x 3f f physical address space 384 d d d 255 256 d 511 d 512 d d 640 d 767 768 d d 896 0 1) configuration dependent register block (4 protocol specific sets) page switch via sfrpage register 2), 4) reserved ? forbidden area 3) configuration independent registers (common for all configurations ) map (?mirror? ) to the same physical address space d 1023 0x080 d 128 common registers 3) reserved 4) common registers 3) reserved 4) common registers 3) reserved 4) common registers 3) reserved 4) configuration c 1) - page 2 reserved 2) configuration c 1) - page 2 reserved 2) configuration d 1) - page 3 reserved 2) configuration d 1) - page 3 reserved 2) configuration b 1) - page 1 reserved 2) configuration b 1) - page 1 reserved 2) common registers 3) reserved 4) configuration a 1) - page 0 reserved 2) configuration a 1) - page 0 reserved 2)
data sheet 77 v1.0, 2010-02-19 TDA5225 applications 3 applications figure 53 typical application schematic note: as a good practice in any rf design, shielding around sensitive nodes can improve the emc performance of the application. for achieving the best sensitivity results the following has to be kept in mind. every digital system generates certain frequencies (f src , e.g. the crystal frequency or a microcontroller clock) and harmonics (n * f src ) of it, which can act as interferer (emi source) and therefore sensitivity can be reduced. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ifbuf_in ifbuf_out gnda ifmix_inp ifmix_inn vdd5v vddd vddd1v5 gndd pp0 pp1 pp2 p_on xt al1 if_out vdda rssi pp3 gndrf lna_inp lna_inn t2 t1 sdo sdi sck ncs xtal2 TDA5225 saw filter rf in if cer filter (opt.) if cer filter (opt.) vs vs spi bus to/from c to c
TDA5225 applications data sheet 78 v1.0, 2010-02-19 there are two different cases, which need to be checked for the desired receive channel(s): elimination of in-band emi mixing with (2*m + 1) * f lo , where m > 0: a square wave is used as lo (local oscillator) for the switching-type mixer, which also has odd harmonics. when the harmonics of the emi source are exactly the if frequency away from the harmonics of the lo, these spurs will be down-converted to the if frequency and act as a co-channel interferer within the receiver?s channel bandwidth mainly in the 315 mhz band. in this case a change of the lo injection side (high side or low side injection) can be applied. example (low side lo-injection): wanted channel f rf = 314.233mhz ==> f lo = 303.533mhz ==> 3*f lo = 910.599mhz f xosc = 21.948717 mhz ==> 41 * f xosc = 899.8974 mhz resulting if = 910.599 - 899.8974 mhz = 10.702 mhz ==> co-channel interferer within the receiver?s channel bandwidth ==> change lo injection side example (high side lo-injection): wanted channel f rf = 314.233 mhz ==> f lo = 324.933 mhz ==> 3*f lo = 974.799 mhz f xosc = 21.948717 mhz ==> 44 * f xosc = 965.744 mhz; 45 * f xosc = 987.692 mhz ==> both xosc harmonics are not generating a co-channel interferer at 10.7 mhz a final sensitivity measurement on the application hardware is recommended. elimination of in-band emi mixing with 1 * f lo : assuming a harmonic (n * f src ) is falling within the bw of the wanted channel and has an impact on the sensitivity there. in this case another xtal frequency shall be selected, e.g. 10 khz away | n * f src - f localoscillator | < bw channel example (e.g. emi source TDA5225 xosc): f xosc = 21.948717 mhz ==> 42 * f xosc = 921.846114 mhz for further details please refer to the corresponding application note or to the latest configuration software. 3.1 configuration example please see configuration files supplied with the explorer tool.
data sheet 79 v1.0, 2010-02-19 TDA5225 reference 4 reference 4.1 electrical data 4.1.1 absolute maximum ratings attention: the maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the ic may result. table 7 absolute maximum ratings # parameter symbol limit values unit remarks min. max. a1 supply voltage at vdd5v pin v smax -0.3 +6 v a2 supply voltage at vddd, vdda pin v smax -0.3 +4 v a3 voltage between vdd5v vs vddd and vdd5v vs vdda v smax -0.3 +4 v a4 junction temperature t j -40 +125 c a5 storage temperature t s -40 +150 c a6 thermal resistance junction to air r th(ja) 140 k/w a7 total power dissipation at t amb = 105c p tot 100 mw a8 esd hbm integrity v hbmrf -2 2 kv according to esd standard jedec eia / jesd22-a114-b a9 esd sdm integrity (all pins except corner pins) v sdm -500 500 v a10 esd sdm integrity (all corner pins) v sdm -750 750 v a11 latch up i lu 100 ma aec-q100 (transient current) a12 maximum input voltage at digital input pins v inmax -0.3 v dd5v +0.5 or 6.0 v whichever is lower a13 maximum current into digital input and output pins i iomax 4ma
TDA5225 reference data sheet 80 v1.0, 2010-02-19 4.1.2 operating range table 8 supply operating range and ambient temperature # parameter symbol limit values unit remarks min. max. b1 supply voltage at pin vdd5v v dd5v 4.5 5.5 v supply voltage range 1 b2 supply voltage at pin vdd5v=vddd=vdda v dd3v3 3.0 3.6 v supply voltage range 2 b3 ambient temperature t amb -40 105 c
data sheet 81 v1.0, 2010-02-19 TDA5225 reference 4.1.3 ac/dc characteristics supply voltage vdd5v = 4.5 to 5.5 volt or vdd5v = vdda = vddd = 3.0 to 3.6 volt ambient temperature t amb = -40...105 o c; t amb = +25 o c and vdd5v = 5.0v or vdd5v = vdda = vddd = 3.3v for typical parameters, unless otherwise specified. not subject to production test - verified by characterization/design table 9 ac/dc characteristics # parameter symbol limit values unit test conditions remarks min. typ. max. general dc characteristics c1.1 supply current in run mode and double down conversion mode i run, double 12 15 ma ask or fsk mode p in < -50dbm c1.2 supply current in run mode and single down conversion mode i run, single 10.5 14 ma ask or fsk mode p in < -50dbm c2 supply current in sleep mode i sleep_low crystal oscillator in low power mode; clock generator off; valid for sleep mode and during spm off time t amb = 25 c 40 50 a t amb = 85 c 60 110 a t amb = 105 c 90 160 a c3 supply current in sleep mode i sleep_high 115 350 a crystal oscillator in high precision mode c load = 25 pf; clock generator off; valid for sleep mode and during spm off time c4 supply current in power down mode i pdn t amb = 25 c 0.8 1.5 a t amb = 85 c 3.7 13 a t amb = 105 c 9.0 27 a c5 supply current clock generator i clock 23 27 a f clockout = 1 khz c load = 10 pf c6 supply current if-buffer i buffer 0.5 0.7 ma f if_1 = 10.7 mhz r load = 330 no ac signal
TDA5225 reference data sheet 82 v1.0, 2010-02-19 c7 supply current during rf-fe startup / bpf calibration i rf-fe- startup,bpfcal 2.2 2.9 ma c8 brownout detector threshold v bor 2.3 2.45 2.6 v c9 receiver reset time t reset 1.0 3.0 ms note: no spi communication is allowed before xosc start-up is finished and chip reset is already finished c10 receiver startup time t rxstartup 455 455 455 s time to startup rf frontend (comprises time required to switch crystal oscillator from low power mode to high precision mode c11 rf channel hop latency time and configuration (hop) change latency time (e.g. cfg a to cfg b) t c_hop 111 111 111 s time to switch rf pll between different rf channels (does not include settling of data clock recovery) and time to change configuration c12 rf frontend startup delay t rfstartdelay 350 350 350 s delay of startup of rf frontend c13 p_on pulse width t p_on 15 s minimal pulse width to reset the chip c14 nint pulse length t nint_pulse 12 s pulse width of interrupt c15 accuracy of temperature sensor valid for temperature range -40c .. +105c; using upper 8 adc bits (adcresh) c15.1 uncalibrated t error, uncal +/- 23 c uncalibrated (3 sigma) value c15.2 calibrated t error, cal +/- 4.5 c after 1-point calibration at room temperature (3 sigma) c16 accuracy of vddd readout valid for temperature range -40c .. +105c; using upper 8 adc bits (adcresh) c16.1 uncalibrated v ddd, error, uncal +/- 200 mv uncalibrated (3 sigma) value c16.2 calibrated v ddd, error, cal +/- 25 mv after 1-point calibration at room temperature (3 sigma) # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 83 v1.0, 2010-02-19 TDA5225 reference general rf characteristics (overall) d1 frequency range 1 f band_1 300 320 mhz 1 st local oscillator low side lo-injection and high side lo- injection allowed; see also chapter 3 range 2 f band_2 425 450 mhz range 3 f band_3 863 870 mhz range 4 f band_4 902 928 mhz d2 frequency step of sigma-delta pll f step 10.5 hz f step = f xtal / 2 21 d3 ask demodulation data rate r data 0.5 40 kchip/s data rate tol. r data_tol -10 +10 % modulation index m ask 50 100 % ask m ook 99 100 % on-off keying d4 fsk demodulation data rate r data 0.5 112 kchip/s including tolerance data rate tol. r data_tol -10 +10 % frequency deviation f 1 64 khz frequency deviation zero-peak modulation index m fsk 1.0 m = frequency_ deviation zero-peak / maximum_occuring_data _frequency; m >= 1.25 is recommended at small frequency deviation d5 decoding schemes manchester, differential manchester, bi-phase mark / bi-phase space duty cycle ask t chip / t data 35 55 % see chapter 2.7.2 definition c duty cycle fsk t chip / t data 45 55 % see chapter 2.7.2 definition b d6 overall noise figure rf input matched to 50 @ t amb = 25 c noise figure nf 6 8 db # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 84 v1.0, 2010-02-19 d7 ber sensitivity (fsk) ber = 2*10 -3 rf input matched to 50 @ t amb = 25 c; single-ended matching without saw; insertion loss of input matching network = 1db; receive mode = tmmf (sampled with ideal data clock); double down conversion manchester coding; for additional test conditions see right after this table d7.1 data rate 2 kbit/s; f = 10 khz sfsk1 ber -119 -116 dbm 2 nd if bw = 50 khz pdf = 33 khz, afc off, ifatt=0 d7.2 data rate 10 kbit/s; f = 14 khz sfsk2 ber -114 -111 dbm 2 nd if bw = 50 khz pdf = 65 khz, afc off, ifatt=0 d7.3 data rate 10 kbit/s; f = 50 khz sfsk3 ber -112 -109 dbm 2 nd if bw = 125 khz pdf = 132 khz, afc off, ifatt=0 d7.4 data rate 50 kbit/s; f = 50 khz sfsk4 ber -105 -102 dbm 2 nd if bw = 300 khz pdf = 239 khz, afc off, ifatt=0 d7.5 data rate 2 kbit/s; f = 10 khz sfsk5 ber -110 -107 dbm 2 nd if bw = 300 khz pdf = 282khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on d7.6 data rate 10 kbit/s; f = 14 khz sfsk6 ber -106 -103 dbm 2 nd if bw = 300 khz pdf = 282khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on d7.7 data rate 10 kbit/s; f = 50 khz sfsk7 ber -110 -107 dbm 2 nd if bw = 300 khz pdf = 282khz, ifatt=7 note: 3db sensitivity loss @ f offset =+/-90khz @ afc on # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 85 v1.0, 2010-02-19 TDA5225 reference d8 ber sensitivity (ook) ber = 2*10 -3 rf input matched to 50 @ t amb = 25 c, peak power level (see chapter 2.7.3 ); single-ended matching without saw; insertion loss of input matching network = 1db; receive mode = tmmf (sampled with ideal data clock); double down conversion manchester coding; for additional test conditions see right after this table d8.1 data rate 0.5 kbit/s sask1 ber -120 -117 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.2 data rate 2 kbit/s sask2 ber -116 -113 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.3 data rate 10 kbit/s sask3 ber -111 -108 dbm peak m = 100%, ifatt=0 2 nd if bw = 50 khz d8.4 data rate 16 kbit/s sask4 ber -109 -106 dbm peak m = 100%, ifatt=0 2 nd if bw = 80 khz d8.5 data rate 0.5 kbit/s sask5 ber -115 -112 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.6 data rate 2 kbit/s sask6 ber -112 -109 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.7 data rate 10 kbit/s sask7 ber -106 -103 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d8.8 data rate 16 kbit/s sask8 ber -104 -101 dbm peak m = 100%, ifatt=7 2 nd if bw = 300 khz; note: 3db sensitivity loss @ f offset = +/-100 khz d9.1 sensitivity increase for single down conversion mode s sdc 00.51 db d9.2 double down conversion sensitivity decrease for higher blocking performance (ifatt=0 => ifatt=7) s ddc, ifatt7 12 db # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 86 v1.0, 2010-02-19 d9.3 single down conversion sensitivity decrease for higher blocking performance (ifatt=4 => ifatt=7) s sdc, ifatt7 0.5 1 db d10.1 sensitivity variation due to temperature (-40...+105c) p in 2 db relative to t amb = 25 c; temperature drift of crystal not considered d10.2 sensitivity variation due to frequency offset 1) p in 3 db afc inactive; for sensitivity bandwidth see table 10 d10.3 sensitivity variation due to frequency offset p in 3 db afc active, slow afc; for sensitivity bandwidth see table 10 and applied afclimit d10.4 sensitivity loss when afc active at center frequency p in 1 db afc active; center frequency - no afc wander (see chapter 2.4.6.3 ) d11 3 rd order intercept iip3 p iip3 -16 -14 dbm input matched to 50 ; insertion loss of input matching network = 1db; ifatt = 7; valid for single and double down conversion mode d12 1 db compression point cp1db p cp1db -27 -25 dbm input matched to 50 ; insertion loss of input matching network = 1db; ifatt = 7; valid for single and double down conversion mode d13 1 st if image rejection d image1 30 40 db 1 st if = 10.7 mhz without front end saw filter; valid for double down conversion mode d14 2 nd if image rejection d image2 30 34 db 2 nd if = 274 khz without 1 st if cer filter; valid for single and double down conversion mode # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 87 v1.0, 2010-02-19 TDA5225 reference rf front end characteristics (unless otherwise noted, all values apply for the specified frequency ranges) e1 lna input impedance e1.1 f rf = 315 mhz r in_p,diff 680 differential parallel equivalent input between lna_inp and lna_inn c in_p,diff 1.05 pf e1.2 f rf = 434mhz r in_p,diff 570 c in_p,diff 0.87 pf e1.3 f rf = 868mhz r in_p,diff 550 c in_p,diff 0.63 pf e1.4 f rf = 915mhz r in_p,diff 540 c in_p,diff 0.63 pf e1.5 f rf = 315 mhz r in_p, se 500 single-ended parallel equivalent input between lna_inp and gndrf / lna_inn and gndrf c in_p, se 1.87 pf e1.6 f rf = 434mhz r in_p, se 400 c in_p, se 1.63 pf e1.7 f rf = 868mhz r in_p, se 322 c in_p, se 1.59 pf e1.8 f rf = 915mhz r in_p, se 312 c in_p, se 1.56 pf e2 fe output impedance r out_if 290 330 380 f if = 10.7 mhz e3 fe voltage conversion gain av fe, max 34 36 38 db min. if attenuation (ifatt = 0); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz e4 fe voltage conversion gain av fe_7 29 31 33 db if attenuation (ifatt = 7); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 88 v1.0, 2010-02-19 e5 fe voltage conversion gain av fe, min 22 24 26 db max. if attenuation (ifatt = 15); input matched to 50 ; insertion loss of input matching network = 1db r load_if = 330 ; tested at 434 mhz e6 fe voltage conversion gain step 0.8 db 12db / 15 = 0.8db/step double down conversion: 16 gain settings (4 bit) single down conversion: 7 gain settings e7 1 st local oscillator ssb noise closed loop e7.1 pll loop bandwidth bw 100 150 200 khz bw and its tolerances e7.2 f in_r1 = 315mhz d ssb_lo -81 -76 dbc/hz @ f offset = 1 khz -85 -80 @ f offset = 10 khz -82 -77 @ f offset = 100 khz -120 -115 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.3 f in_r2 = 434mhz d ssb_lo -78 -73 dbc/hz @ f offset = 1 khz -83 -78 @ f offset = 10 khz -82 -77 @ f offset = 100 khz -117 -112 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.4 f in_r3 = 868mhz d ssb_lo -75 -70 dbc/hz @ f offset = 1 khz -79 -74 @ f offset = 10 khz -77 -72 @ f offset = 100 khz -114 -109 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e7.5 f in_r4 = 915mhz d ssb_lo -71 -66 dbc/hz @ f offset = 1 khz -79 -74 @ f offset = 10 khz -77 -72 @ f offset = 100 khz -116 -111 @ f offset = 1 mhz -130 -125 @ f offset => 10 mhz e8.1 spurious emission < 1 ghz -57 dbm e8.2 spurious emission > 1 ghz -47 dbm # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 89 v1.0, 2010-02-19 TDA5225 reference e9 inband fractional spur -40 dbc e10 3db overall analog frontend bandwidth bw ana 230 khz lna input to limiter output, excluding external cer filter 1 st if buffer characteristics f1 input impedance r in_if 290 330 370 f if = 10...12 mhz f2 output impedance r out_if 290 330 370 f if = 10...12 mhz f3 voltage gain av buffer 345 dbf if = 10...12 mhz z source = 330 z load = 330 f4 buffer switch isolation (cerfsel) d isolation 60 db f if = 10...12 mhz see figure 6 2 nd if mixer, rssi and filter characteristics g1 mixer input impedance r in_if 290 330 390 f if = 10...12 mhz g6 rssi related to rf input matched to 50 g2.1 dynamic range (linearity +/- 2 db) dr rssi -110 -30 dbm applies for digital rssi; agc on -115 -60 dbm applies for analog rssi @ 50khz bpf, afgc off -110 -50 dbm applies for analog rssi @ 300khz bpf, afgc off g2.2 linearity dr lin -1 +1 db -95 dbm...-35 dbm; applies for digital rssi g2.3 temperature drift within linear dynamic range dr temp -2.5 +1.5 db -95 dbm...-35 dbm; applies for digital rssi g2.4 output dynamic range v rssi+ 0.8 2.0 v g2.5 analog rssi error, untrimmed drssi ana -4 +2 db at rssi pin g2.6 analog rssi slope, untrimmed dv rssi / dv mix_in 8 10 12 mv/db at rssi pin; typical 600 mv/60 db = 10 mv/db g2.7 digital rssi error, untrimmed drssi dig_u -4 +2 db rssi register readout # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 90 v1.0, 2010-02-19 g2.8 digital rssi error, user trimmed via sfrs rssislope and rssioffs drssi dig_t -1 +1 db rssi register readout g2.9 digital rssi slope, untrimmed dv rssi / dv mix_in 22.53 lsb /db rssi register readout; typical 600 mv/60 db = 10 mv/db, 1mv = 1 lsb (10-bit adc) 8-bit readout: 4mv=1lsb g2.10 digital rssi slope, user trimmed via sfrs rssislope and rssioffs dv rssi / dv mix_in 2.35 2.5 2.65 lsb /db rssi register readout; typical 600 mv/60 db = 10 mv/db, 1mv = 1 lsb (10-bit adc) 8-bit readout: 4mv=1lsb g2.11 resistive load at rssi pin r l,rssimax 100 k g2.12 capacitive load at rssi pin c l,rssi 20 pf g3 2nd if filter (3rd order bandpass filter) g3.1 center frequency f center 262 274 288 khz asymmetric bpf corners: f_center=sqrt(f low * f high ); use afc for more symmetry g3.2 -3 db bw bw -3db 50 80 125 200 300 khz g3.3 -3 db bw tolerance tol_bw -3db -5 +5 % for bw = 125, 200, 300 khz g3.4 -3 db bw tolerance tol_bw -3db -6 +6 % for bw = 50, 80 khz # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 91 v1.0, 2010-02-19 TDA5225 reference crystal oscillator characteristics h1 frequency range f xtal 21.948 717 mhz h2 crystal parameters h2.1 motional capacitance c 1 3610ff h2.2 motional resistance r 1 18 80 h2.3 shunt capacitance c 0 24 pf h2.4 load capacitance c load 12 pf nominal value h2.5 initial frequency tolerance f xtal_tol -30 +30 ppm oscillator untrimmed (trim capacitor default settings, usage of recommended crystal); not including crystal tolerances h2.6 frequency trimming range f xtal -50 +50 ppm larger trimming range possible via sd pll h2.7 trimming step f x_step 1 4 ppm see also step size of sd pll h3 clock output frequency at ppx pin f clock_out 11 5.5m hz 10pf load h4 crystal oscillator settling time (switching from low power to high precision mode) t coscsettle 292 292 292 s h5 start up time t start_up 0.45 1 ms crystal type: ndk nx5032sd; see also bom for ext. load caps; note: no spi communication is allowed before xosc start-up is finished and chip reset is already finished # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 92 v1.0, 2010-02-19 digital inputs/outputs characteristics i1 high level input voltage v in_high 0.7* vddd vdd5v +0.1 v i2 high level input leakage current i in_high 5a i3 low level input voltage (except p_on pin) v in_low 00.8v i4 low level input voltage (at p_on pin) v in_low_pon 00.5v i5 low level input leakage current i in_low -5 a i6 high level output voltage 1 v out_high1 vdd5v -0.4 vdd5v v ioh=-500 a, static driver capability; normal pad mode (see register ppcfg2 and cmc0) i7 low level output voltage 1 v out_low1 0 0.4 v iol=500 a, static driver capability; normal pad mode (see register ppcfg2 and cmc0) i8 high level output voltage 2 v out_high2 vdd5v -0.8 vdd5v v ioh=-4 ma, static driver capability; high power pad mode (see register ppcfg2 and cmc0) i9 low level output voltage 2 v out_low2 0 0.8 v iol=4 ma, static driver capability; high power pad mode (see register ppcfg2 and cmc0) # parameter symbol limit values unit test conditions remarks min. typ. max.
data sheet 93 v1.0, 2010-02-19 TDA5225 reference timing spi-bus characteristics j1 clock frequency f clock 2.2 mhz note: a high spi clock rate during data reception can reduce sensitivity j2 clock high time t clk_h 200 ns j3 clock low time t clk_l 200 ns j4 active setup time t setup 200 ns j5 not active setup time t not_setup 200 ns j6 active hold time t hold 200 ns j7 not active hold time t not_hold 200 ns j8 deselect time t deselect 200 ns j9 sdi setup time t sdi_setup 100 ns j10 sdi hold time t sdi_hold 100 ns j11 clock low to sdo valid t clk_sdo 145 ns @ c load = 80 pf high power pad not enabled (normal mode) (see register ppcfg2 and cmc0) j12 clock low to sdo valid t clk_sdo 40 ns @ c load = 10 pf high power pad not enabled (normal mode) (see register ppcfg2 and cmc0) j13 sdo rise time t sdo_r 90 ns @ c load = 80 pf j14 sdo fall time t sdo_f 90 ns @ c load = 80 pf j15 sdo rise time t sdo_r 15 ns @ c load = 10 pf j16 sdo fall time t sdo_f 15 ns @ c load = 10 pf j17 sdo disable time t sdo_disable 25 ns 1) please note that the system bandwidth is smaller than the smallest bandwidth in the signal path. # parameter symbol limit values unit test conditions remarks min. typ. max.
TDA5225 reference data sheet 94 v1.0, 2010-02-19 unless explicitly otherwise noted, the following test conditions apply to the given specification values in the items d7 and d8: * hardware: tda5240 platform testboard v1.0 * single-ended matching for 315.0 mhz / 433.92 mhz / 868.3 mhz / 915.0 mhz * rf input matched to 50 ; insertion loss of input matching network = 1db * receive frequency 315.0 mhz / 433.92 mhz / 868.3 mhz / 915.0 mhz; lo-side lo-injection * reference clock: xtal=21.948717 mhz * if-gain: attenuation set to default value (ifatt = 7) * double down conversion * 1 if-filter: center=10.7mhz; bw=330khz; connected between if_out and ifbuf_in * 2 nd if filter bw: depending on data rate and fsk deviation * received signal at zero offset to if center frequency * rssi trimmed * fsk pre-demodulation filter (pdf) bw: depending on data rate and fsk deviation * no spi-traffic during telegram reception, clk_out disabled * afc and agc are off, unless otherwise noted ber sensitivity measurements use receive mode tmmf (sampled with ideal data clock) * dre ... data date error of received telegram vs. adjusted data rate * dc ... duty cycle * ber ... bit error rate (using a prbs9 pseudo-random binary sequence) [ber = 1 - (number_of_correctly_received_bits / number_of_transmitted bits)]
data sheet 95 v1.0, 2010-02-19 TDA5225 reference table 10 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k bpf = 300 k pdf = 282 k ask - 3 db 230 230 230 230 230 - 6 db 280 280 280 280 280 - fsk 0.5 k 3 db 160 150 - - - - 6 db 230 220 - - - - 1 k 3 db 140 160 - - - - 6 db 220 230 - - - - 5 k 3 db 120 130 150 140 - - 6 db 200 210 220 220 - - 10 k 3 db 120 120 140 140 150 - 6 db 180 190 210 210 210 - 15 k 3 db - - 130 140 150 - 6 db - - 200 200 210 - 20 k 3 db 110 - 130 130 140 - 6 db 160 - 190 190 190 - 40 k 3 db - - - 120 - - 6 db - - - 160 - - 50 k 3 db 110 110 110 110 100 100 6 db 140 140 140 140 140 140
TDA5225 reference data sheet 96 v1.0, 2010-02-19 bpf = 200 k pdf = 239 k ask - 3 db 180 180 180 180 180 - 6 db 220 220 220 220 220 - fsk 0.5 k 3 db 140 140 - - - - 6 db 190 190 - - - - 1 k 3 db 130 130 - - - - 6 db 180 190 - - - - 5 k 3 db 100 120 130 130 - - 6 db 160 170 180 180 - - 10 k 3 db 100 100 120 120 140 - 6 db 140 150 170 170 170 - 15 k 3 db - - 110 110 120 - 6 db - - 150 150 160 - 20 k 3 db 90 - 100 100 110 - 6 db 130 - 140 150 150 - 40 k 3 db - - - 90 - - 6 db - - - 120 - - 50 k 3 db ------ 6 db ------ table 10 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k
data sheet 97 v1.0, 2010-02-19 TDA5225 reference bpf = 125 k pdf = 132 k ask - 3 db 120 120 120 120 120 - 6 db 150 150 150 150 150 - fsk 0.5 k 3 db 100 100 - - - - 6 db 120 120 - - - - 1 k 3 db 90 100 - - - - 6 db 120 120 - - - - 5 k 3 db 70 80 80 90 - - 6 db 100 110 110 110 - - 10 k 3 db 70 70 80 80 80 - 6 db 90 100 100 100 100 - 15 k 3 db - - 70 80 80 - 6 db - - 90 90 100 - 20 k 3 db 60 - 70 70 70 - 6 db 80 - 90 90 90 - 40 k 3 db ------ 6 db ------ 50 k 3 db ------ 6 db ------ table 10 typical achievable sensitivity bandwidth [khz] ceramic filter bw = 330 khz table is valid for ddc (double down conversion) and sdc (single down conversion) valid for afc=off; for fsk & afc=on the bw can be increased by 2*afclimit, where afclimit < 43 khz bpf/pdf filter [hz] modulation fsk deviation [+/- hz] sensitivity loss data rate [bit/s], manchester 0.5 k 1 k 5 10 k 20 k 50 k
TDA5225 reference data sheet 98 v1.0, 2010-02-19 4.2 test circuit - evaluation board v1.0 figure 54 test circuit schematic
data sheet 99 v1.0, 2010-02-19 TDA5225 reference 4.3 test board layout - evaluation board v1.0 figure 55 test board layout, top view figure 56 test board layout, bottom view
TDA5225 reference data sheet 100 v1.0, 2010-02-19 figure 57 test board layout, component view
data sheet 101 v1.0, 2010-02-19 TDA5225 reference 4.4 bill of materials pos part value package device / type tolerance manufacturer remark/options (rf+supply variant) 1 ic1 TDA5225 pg-tssop-28 infineon 2 c1 3.9 pf 0603 c0g +/- 0.1 pf crystal oscillator load 3 c2 3.9 pf 0603 c0g +/- 0.1 pf crystal oscillator load 4 c3 100 nf 0603 x7r +/- 10 % 5 c4 100 nf 0603 x7r +/- 10 % 6 c5 100 nf / ( 1 f ) 0603 x7r / x5r +/- 10 % 3.3v / ( 5 v environment) 7 c6 100 nf 0603 x7r +/- 10 % 8 c7 1 pf 0603 c0g +/- 0.1 pf matching for 315mhz 0.5 pf 0603 c0g +/- 0.1 pf matching for 434mhz open 0603 c0g matching for 868mhz 1 pf 0603 c0g +/- 0.1 pf matching for 915mhz 9 c8 open 0603 c0g matching for 315mhz open 0603 c0g matching for 434mhz 2.7 pf 0603 c0g +/- 0.1 pf matching for 868mhz 5.1 pf 0603 c0g +/- 0.1 pf matching for 915mhz 10 c9 1 f smc-a tantal +/- 10% polarized capacitor 11 c10 100 nf 0603 x7r +/- 10% 12 c11 10 nf 0603 x7r +/- 10% 13 l1 68 nh 0603 +/- 2% matching for 315mhz 39 nh 0603 +/- 2% matching for 434mhz 22 nh 0603 +/- 2% matching for 868mhz 15 nh 0603 +/- 2% matching for 915mhz 14 r1 10 ohm / (open) 0603 +/- 5% 3.3 v / ( 5 v environment) 15 r2 4.7 ohm / (open) 0603 +/- 5% 3.3 v / ( 5 v environment) 16 r3 4.7 ohm / (22 ohm) 0603 +/- 5% 3.3 v / ( 5 v environment) 17 r4 0 ohm 0603 18 if1 sfecf10 m7ea00 murata bw = 330 khz 19 q1 21.948717 mhz nx5032sd c0=1.7 pf c1=7 ff cl=12 pf ndk (frischer electronic), exs00a- cs01580 smd crystal
TDA5225 reference data sheet 102 v1.0, 2010-02-19 interface / optional 20 ic2 at24c32 c-sh-b or at24c512 soic8 eeprom for board detection 21 c12 open 0603 x7r +/- 10% rssi measurement low pass 22 c13 100 nf 0603 x7r +/- 10% 23 c14 1 f smc-a tantal +/- 10% polarized capacitor 24 c15 10 nf 0603 x7r +/- 10% filter network on supply line 25 c16 10 nf 0603 x7r +/- 10% filter network on supply line 26 l2 0 ohm 0603 no filter network on supply line 27 r5 open 0603 rssi measurement low pass 28 r6 1 kohm 0603 29 r7 0 ohm 0603 write protection for eeprom 30 d1 led ls m676- p251-1 status indication led 31 if2 open murata 2nd if filter is optional 32 x1 sma socket rf input 33 x2 3 pins board supply 34 x3 2 pins chip supply current (jumper closed) 35 x4 50 pins sib-qts-025- 01-x-d-ra samtec connector to pc/c/interface 36 x5 2 pins rssi measuring point 37 x6 12 pins interface line measuring point 38 x7 4 pins gnd 39 x8 4 pins gnd 40 jum- per 1 2 pins jumper for x3 41 jum- per 2 2 pins jumper for x2 - supply by interface board material 1.5mm fr4 with 35m copper on both sides pos part value package device / type tolerance manufacturer remark/options (rf+supply variant)
data sheet 103 v1.0, 2010-02-19 TDA5225 package outlines 5 package outlines figure 58 pg-tssop-28 package outline (green package) table 11 order information type ordering code package TDA5225 sp000507672 pg-tssop-28 does not include dambar protrusion does not include plastic or metal protrusion of 0.15 max. per side 1 28 index marking 1) ?.1 9.7 a 14 15 0.1 m 28x ac 0.65 0.22 2) -0.03 +0.08 0.1 ?.05 c 0.1 +0.05 -0.2 1.2 max. 1 -0.035 b 0.125 +0.075 ?.1 4.4 1) ...8? +0.15 0.6 0? 0.2 6.4 -0.1 2 8x b 1) 2) you can find all of our packages, sorts of packing and others in our infineon internet page ?products?: http://www.infineon.com/products dimensions in mm smd = surface mounted device
TDA5225 list of tables page data sheet 104 v1.0, 2010-02-19 table 1 pin definition and function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 agc settings 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 3 agc settings 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 4 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 5 spi bus timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 6 power level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 7 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 8 supply operating range and ambient temperature . . . . . . . . . . . . . . 80 table 9 ac/dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 10 typical achievable sensitivity bandwidth [khz] . . . . . . . . . . . . . . . . . . 95 table 11 order information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TDA5225 list of figures page data sheet 105 v1.0, 2010-02-19 figure 1 pin-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2 TDA5225 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 3 block diagram rf section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 4 single down conversion (sdc, no external filters required) . . . . . . . . 19 figure 5 double down conversion (ddc) with one external filter . . . . . . . . . . . 20 figure 6 double down conversion (ddc) with two external filters . . . . . . . . . . 20 figure 7 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 8 external clock generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9 synthesizer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10 functional block diagram ask/fsk demodulator . . . . . . . . . . . . . . . 26 figure 11 afc loop filter (i-pi filtering and mapping) . . . . . . . . . . . . . . . . . . . . 28 figure 12 analog rssi output curve with agc action on (blue) vs. off (black) 29 figure 13 peak detector unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 14 peak detector behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 15 functional block diagram digital baseband receiver. . . . . . . . . . . . . 36 figure 16 wake-up generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 17 rssi blocking thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 18 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 19 3.3 volts and 5 volts applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 20 supply current ramp up/down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21 reset behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22 logical and electrical system interfaces of the TDA5225 . . . . . . . . . . 44 figure 23 data interface for the transparent mode . . . . . . . . . . . . . . . . . . . . . . . 46 figure 24 external data processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 25 interrupt generation unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 26 interrupt generation waveform (example for configuration a+b). . . . 49 figure 27 isx readout set clear collision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 28 read register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 29 burst read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 30 write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 31 burst write registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 32 spi checksum generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 33 serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 34 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 35 chip serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 36 global state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 37 run mode slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 38 hold state behavior (initpllhold disabled) . . . . . . . . . . . . . . . . . 59 figure 39 hold state behavior (initpllhold enabled) . . . . . . . . . . . . . . . . . 60 figure 40 spm - tx-rx interaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 41 wake-up search with configuration a . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 42 wake-up search with configuration b, c, d . . . . . . . . . . . . . . . . . . . . 63
TDA5225 data sheet 106 v1.0, 2010-02-19 figure 43 run mode self polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 44 polling timer unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 45 constant on-off time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 46 coo polling in wu on rssi mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 47 active idle period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 48 definition a: level-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 49 definition b: chip-based definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 50 definition c: edge delay definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 51 sfr symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 52 sfr address paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 53 typical application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 54 test circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 55 test board layout, top view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 56 test board layout, bottom view . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 57 test board layout, component view . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 58 pg-tssop-28 package outline (green package). . . . . . . . . . . . . . . 103
data sheet 107 v1.0, 2010-02-19 TDA5225 appendix - registers chapter
TDA5225 appendix register overview data sheet 108 v1.0, 2010-02-19 appendix - registers chapter register overview table 1 register overview register short name register long name offset address page number appendix - registers chapter , register description a_if1 if1 register 016 h 122 a_wurssith1 rssi wake-up threshold for channel 1 register 01b h 122 a_wurssibl1 rssi wake-up blocking level low channel 1 register 01c h 123 a_wurssibh1 rssi wake-up blocking level high channel 1 register 01d h 123 a_wurssith2 rssi wake-up threshold for channel 2 register 01e h 124 a_wurssibl2 rssi wake-up blocking level low channel 2 register 01f h 124 a_wurssibh2 rssi wake-up blocking level high channel 2 register 020 h 124 a_wurssith3 rssi wake-up threshold for channel 3 register 021 h 125 a_wurssibl3 rssi wake-up blocking level low channel 3 register 022 h 125 a_wurssibh3 rssi wake-up blocking level high channel 3 register 023 h 126 a_wulot wake-up on level observation time register 025 h 126 a_afclimit afc limit configuration register 02a h 127 a_afcagcd afc/agc freeze delay register 02b h 127 a_afcsfcfg afc start/freeze configuration register 02c h 128 a_afck1cfg0 afc integrator 1 gain register 0 02d h 129 a_afck1cfg1 afc integrator 1 gain register 1 02e h 129 a_afck2cfg0 afc integrator 2 gain register 0 02f h 129 a_afck2cfg1 afc integrator 2 gain register 1 030 h 130 a_pmfudsf peak memory filter up-down factor register 031 h 130 a_agcsfcfg agc start/freeze configuration register 032 h 131 a_agccfg0 agc configuration register 0 033 h 132 a_agccfg1 agc configuration register 1 034 h 133 a_agcthr agc threshold register 035 h 133 a_digrxc digital receiver configuration register 036 h 134 a_isupfcsel image supression fc selection register 038 h 134 a_pdecf pre decimation factor register 039 h 135 a_pdecscfsk pre decimation scaling register fsk mode 03a h 135 a_pdecscask pre decimation scaling register ask mode 03b h 136
TDA5225 appendix register overview data sheet 109 v1.0, 2010-02-19 a_mfc matched filter control register 03c h 136 a_src sampe rate converter nco tune 03d h 137 a_extslc externel data slicer configuration 03e h 137 a_chcfg channel configuration register 058 h 138 a_pllintc1 pll mmd integer value register channel 1 059 h 139 a_pllfrac0c1 pll fractional division ratio register 0 channel 1 05a h 139 a_pllfrac1c1 pll fractional division ratio register 1 channel 1 05b h 140 a_pllfrac2c1 pll fractional division ratio register 2 channel 1 05c h 140 a_pllintc2 pll mmd integer value register channel 2 05d h 141 a_pllfrac0c2 pll fractional division ratio register 0 channel 2 05e h 141 a_pllfrac1c2 pll fractional division ratio register 1 channel 2 05f h 142 a_pllfrac2c2 pll fractional division ratio register 2 channel 2 060 h 142 a_pllintc3 pll mmd integer value register channel 3 061 h 143 a_pllfrac0c3 pll fractional division ratio register 0 channel 3 062 h 143 a_pllfrac1c3 pll fractional division ratio register 1 channel 3 063 h 143 a_pllfrac2c3 pll fractional division ratio register 2 channel 3 064 h 144 sfrpage special function register page register 080 h 144 ppcfg0 pp0 and pp1 configuration register 081 h 145 ppcfg1 pp2 and pp3 configuration register 082 h 146 ppcfg2 ppx port configuration register 083 h 147 rxruncfg0 rx run configuration register 0 084 h 148 rxruncfg1 rx run configuration register 1 085 h 149 clkout0 clock divider register 0 086 h 150 clkout1 clock divider register 1 087 h 150 clkout2 clock divider register 2 088 h 151 rfc rf control register 089 h 151 bpfcalcfg0 bpf calibration configuration register 0 08a h 152 bpfcalcfg1 bpf calibration configuration register 1 08b h 152 xtalcal0 xtal coarse calibration register 08c h 153 xtalcal1 xtal fine calibration register 08d h 153 rssimonc rssi monitor configuration register 08e h 154 adcinsel adc input selection register 08f h 155 rssioffs rssi offset register 090 h 155 rssislope rssi slope register 091 h 156 im0 interrupt mask register 0 094 h 156 im1 interrupt mask register 1 095 h 157 spmap self polling mode active periods register 096 h 157 spmip self polling mode idle periods register 097 h 158 table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 110 v1.0, 2010-02-19 spmc self polling mode control register 098 h 158 spmrt self polling mode reference timer register 099 h 159 spmofft0 self polling mode off time register 0 09a h 159 spmofft1 self polling mode off time register 1 09b h 160 spmonta0 self polling mode on time config a register 0 09c h 160 spmonta1 self polling mode on time config a register 1 09d h 161 spmontb0 self polling mode on time config b register 0 09e h 161 spmontb1 self polling mode on time config b register 1 09f h 162 spmontc0 self polling mode on time config c register 0 0a0 h 162 spmontc1 self polling mode on time config c register 1 0a1 h 163 spmontd0 self polling mode on time config d register 0 0a2 h 163 spmontd1 self polling mode on time config d register 1 0a3 h 164 extpcmd external processing command register 0a4 h 164 cmc1 chip mode control register 1 0a5 h 165 cmc0 chip mode control register 0 0a6 h 166 rssipwu wakeup peak detector readout register 0a7 h 167 is0 interrupt status register 0 0a8 h 167 is1 interrupt status register 1 0a9 h 168 rfpllacc rf pll actual channel and configuration register 0aa h 169 rssiprx rssi peak detector readout register 0ab h 169 adcresh adc result high byte register 0ae h 170 adcresl adc result low byte register 0af h 170 vacres vco autocalibration result readout register 0b0 h 171 afcoffset afc offset read register 0b1 h 171 agcgainr agc gain readout register 0b2 h 172 spiat spi address tracer register 0b3 h 172 spidt spi data tracer register 0b4 h 172 spichksum spi checksum register 0b5 h 173 sn0 serial number register 0 0b6 h 173 sn1 serial number register 1 0b7 h 174 sn2 serial number register 2 0b8 h 174 sn3 serial number register 3 0b9 h 174 rssirx rssi readout register 0ba h 175 rssipmf rssi peak memory filter readout register 0bb h 175 b_if1 if1 register 116 h b_wurssith1 rssi wake-up threshold for channel 1 register 11b h b_wurssibl1 rssi wake-up blocking level low channel 1 register 11c h table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 111 v1.0, 2010-02-19 b_wurssibh1 rssi wake-up blocking level high channel 1 register 11d h b_wurssith2 rssi wake-up threshold for channel 2 register 11e h b_wurssibl2 rssi wake-up blocking level low channel 2 register 11f h b_wurssibh2 rssi wake-up blocking level high channel 2 register 120 h b_wurssith3 rssi wake-up threshold for channel 3 register 121 h b_wurssibl3 rssi wake-up blocking level low channel 3 register 122 h b_wurssibh3 rssi wake-up blocking level high channel 3 register 123 h b_wulot wake-up on level observation time register 125 h b_afclimit afc limit configuration register 12a h b_afcagcd afc/agc freeze delay register 12b h b_afcsfcfg afc start/freeze configuration register 12c h b_afck1cfg0 afc integrator 1 gain register 0 12d h b_afck1cfg1 afc integrator 1 gain register 1 12e h b_afck2cfg0 afc integrator 2 gain register 0 12f h b_afck2cfg1 afc integrator 2 gain register 1 130 h b_pmfudsf peak memory filter up-down factor register 131 h b_agcsfcfg agc start/freeze configuration register 132 h b_agccfg0 agc configuration register 0 133 h b_agccfg1 agc configuration register 1 134 h b_agcthr agc threshold register 135 h b_digrxc digital receiver configuration register 136 h b_isupfcsel image supression fc selection register 138 h b_pdecf pre decimation factor register 139 h b_pdecscfsk pre decimation scaling register fsk mode 13a h b_pdecscask pre decimation scaling register ask mode 13b h b_mfc matched filter control register 13c h b_src sampe rate converter nco tune 13d h b_extslc externel data slicer configuration 13e h b_chcfg channel configuration register 158 h b_pllintc1 pll mmd integer value register channel 1 159 h b_pllfrac0c1 pll fractional division ratio register 0 channel 1 15a h b_pllfrac1c1 pll fractional division ratio register 1 channel 1 15b h b_pllfrac2c1 pll fractional division ratio register 2 channel 1 15c h b_pllintc2 pll mmd integer value register channel 2 15d h table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 112 v1.0, 2010-02-19 b_pllfrac0c2 pll fractional division ratio register 0 channel 2 15e h b_pllfrac1c2 pll fractional division ratio register 1 channel 2 15f h b_pllfrac2c2 pll fractional division ratio register 2 channel 2 160 h b_pllintc3 pll mmd integer value register channel 3 161 h b_pllfrac0c3 pll fractional division ratio register 0 channel 3 162 h b_pllfrac1c3 pll fractional division ratio register 1 channel 3 163 h b_pllfrac2c3 pll fractional division ratio register 2 channel 3 164 h c_if1 if1 register 216 h c_wurssith1 rssi wake-up threshold for channel 1 register 21b h c_wurssibl1 rssi wake-up blocking level low channel 1 register 21c h c_wurssibh1 rssi wake-up blocking level high channel 1 register 21d h c_wurssith2 rssi wake-up threshold for channel 2 register 21e h c_wurssibl2 rssi wake-up blocking level low channel 2 register 21f h c_wurssibh2 rssi wake-up blocking level high channel 2 register 220 h c_wurssith3 rssi wake-up threshold for channel 3 register 221 h c_wurssibl3 rssi wake-up blocking level low channel 3 register 222 h c_wurssibh3 rssi wake-up blocking level high channel 3 register 223 h c_wulot wake-up on level observation time register 225 h c_afclimit afc limit configuration register 22a h c_afcagcd afc/agc freeze delay register 22b h c_afcsfcfg afc start/freeze configuration register 22c h c_afck1cfg0 afc integrator 1 gain register 0 22d h c_afck1cfg1 afc integrator 1 gain register 1 22e h c_afck2cfg0 afc integrator 2 gain register 0 22f h c_afck2cfg1 afc integrator 2 gain register 1 230 h c_pmfudsf peak memory filter up-down factor register 231 h c_agcsfcfg agc start/freeze configuration register 232 h c_agccfg0 agc configuration register 0 233 h c_agccfg1 agc configuration register 1 234 h c_agcthr agc threshold register 235 h c_digrxc digital receiver configuration register 236 h c_isupfcsel image supression fc selection register 238 h c_pdecf pre decimation factor register 239 h c_pdecscfsk pre decimation scaling register fsk mode 23a h table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 113 v1.0, 2010-02-19 c_pdecscask pre decimation scaling register ask mode 23b h c_mfc matched filter control register 23c h c_src sampe rate converter nco tune 23d h c_extslc externel data slicer configuration 23e h c_chcfg channel configuration register 258 h c_pllintc1 pll mmd integer value register channel 1 259 h c_pllfrac0c1 pll fractional division ratio register 0 channel 1 25a h c_pllfrac1c1 pll fractional division ratio register 1 channel 1 25b h c_pllfrac2c1 pll fractional division ratio register 2 channel 1 25c h c_pllintc2 pll mmd integer value register channel 2 25d h c_pllfrac0c2 pll fractional division ratio register 0 channel 2 25e h c_pllfrac1c2 pll fractional division ratio register 1 channel 2 25f h c_pllfrac2c2 pll fractional division ratio register 2 channel 2 260 h c_pllintc3 pll mmd integer value register channel 3 261 h c_pllfrac0c3 pll fractional division ratio register 0 channel 3 262 h c_pllfrac1c3 pll fractional division ratio register 1 channel 3 263 h c_pllfrac2c3 pll fractional division ratio register 2 channel 3 264 h d_if1 if1 register 316 h d_wurssith1 rssi wake-up threshold for channel 1 register 31b h d_wurssibl1 rssi wake-up blocking level low channel 1 register 31c h d_wurssibh1 rssi wake-up blocking level high channel 1 register 31d h d_wurssith2 rssi wake-up threshold for channel 2 register 31e h d_wurssibl2 rssi wake-up blocking level low channel 2 register 31f h d_wurssibh2 rssi wake-up blocking level high channel 2 register 320 h d_wurssith3 rssi wake-up threshold for channel 3 register 321 h d_wurssibl3 rssi wake-up blocking level low channel 3 register 322 h d_wurssibh3 rssi wake-up blocking level high channel 3 register 323 h d_wulot wake-up on level observation time register 325 h d_afclimit afc limit configuration register 32a h d_afcagcd afc/agc freeze delay register 32b h d_afcsfcfg afc start/freeze configuration register 32c h d_afck1cfg0 afc integrator 1 gain register 0 32d h d_afck1cfg1 afc integrator 1 gain register 1 32e h d_afck2cfg0 afc integrator 2 gain register 0 32f h table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 114 v1.0, 2010-02-19 d_afck2cfg1 afc integrator 2 gain register 1 330 h d_pmfudsf peak memory filter up-down factor register 331 h d_agcsfcfg agc start/freeze configuration register 332 h d_agccfg0 agc configuration register 0 333 h d_agccfg1 agc configuration register 1 334 h d_agcthr agc threshold register 335 h d_digrxc digital receiver configuration register 336 h d_isupfcsel image supression fc selection register 338 h d_pdecf pre decimation factor register 339 h d_pdecscfsk pre decimation scaling register fsk mode 33a h d_pdecscask pre decimation scaling register ask mode 33b h d_mfc matched filter control register 33c h d_src sampe rate converter nco tune 33d h d_extslc externel data slicer configuration 33e h d_chcfg channel configuration register 358 h d_pllintc1 pll mmd integer value register channel 1 359 h d_pllfrac0c1 pll fractional division ratio register 0 channel 1 35a h d_pllfrac1c1 pll fractional division ratio register 1 channel 1 35b h d_pllfrac2c1 pll fractional division ratio register 2 channel 1 35c h d_pllintc2 pll mmd integer value register channel 2 35d h d_pllfrac0c2 pll fractional division ratio register 0 channel 2 35e h d_pllfrac1c2 pll fractional division ratio register 1 channel 2 35f h d_pllfrac2c2 pll fractional division ratio register 2 channel 2 360 h d_pllintc3 pll mmd integer value register channel 3 361 h d_pllfrac0c3 pll fractional division ratio register 0 channel 3 362 h d_pllfrac1c3 pll fractional division ratio register 1 channel 3 363 h d_pllfrac2c3 pll fractional division ratio register 2 channel 3 364 h table 2 register overview and reset value register short name register long name offset address reset value appendix - registers chapter , register description a_if1 if1 register 016 h 20 h a_wurssith1 rssi wake-up threshold for channel 1 register 01b h 00 h a_wurssibl1 rssi wake-up blocking level low channel 1 register 01c h ff h a_wurssibh1 rssi wake-up blocking level high channel 1 register 01d h 00 h a_wurssith2 rssi wake-up threshold for channel 2 register 01e h 00 h table 1 register overview (cont?d) register short name register long name offset address page number
TDA5225 appendix register overview data sheet 115 v1.0, 2010-02-19 a_wurssibl2 rssi wake-up blocking level low channel 2 register 01f h ff h a_wurssibh2 rssi wake-up blocking level high channel 2 register 020 h 00 h a_wurssith3 rssi wake-up threshold for channel 3 register 021 h 00 h a_wurssibl3 rssi wake-up blocking level low channel 3 register 022 h ff h a_wurssibh3 rssi wake-up blocking level high channel 3 register 023 h 00 h a_wulot wake-up on level observation time register 025 h 00 h a_afclimit afc limit configuration register 02a h 02 h a_afcagcd afc/agc freeze delay register 02b h 00 h a_afcsfcfg afc start/freeze configuration register 02c h 00 h a_afck1cfg0 afc integrator 1 gain register 0 02d h 00 h a_afck1cfg1 afc integrator 1 gain register 1 02e h 00 h a_afck2cfg0 afc integrator 2 gain register 0 02f h 00 h a_afck2cfg1 afc integrator 2 gain register 1 030 h 00 h a_pmfudsf peak memory filter up-down factor register 031 h 42 h a_agcsfcfg agc start/freeze configuration register 032 h 00 h a_agccfg0 agc configuration register 0 033 h 2b h a_agccfg1 agc configuration register 1 034 h 03 h a_agcthr agc threshold register 035 h 08 h a_digrxc digital receiver configuration register 036 h 40 h a_isupfcsel image supression fc selection register 038 h 07 h a_pdecf pre decimation factor register 039 h 00 h a_pdecscfsk pre decimation scaling register fsk mode 03a h 00 h a_pdecscask pre decimation scaling register ask mode 03b h 20 h a_mfc matched filter control register 03c h 07 h a_src sampe rate converter nco tune 03d h 00 h a_extslc externel data slicer configuration 03e h 02 h a_chcfg channel configuration register 058 h 44 h a_pllintc1 pll mmd integer value register channel 1 059 h 93 h a_pllfrac0c1 pll fractional division ratio register 0 channel 1 05a h f3 h a_pllfrac1c1 pll fractional division ratio register 1 channel 1 05b h 07 h a_pllfrac2c1 pll fractional division ratio register 2 channel 1 05c h 09 h a_pllintc2 pll mmd integer value register channel 2 05d h 13 h a_pllfrac0c2 pll fractional division ratio register 0 channel 2 05e h f3 h a_pllfrac1c2 pll fractional division ratio register 1 channel 2 05f h 07 h a_pllfrac2c2 pll fractional division ratio register 2 channel 2 060 h 09 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 116 v1.0, 2010-02-19 a_pllintc3 pll mmd integer value register channel 3 061 h 13 h a_pllfrac0c3 pll fractional division ratio register 0 channel 3 062 h f3 h a_pllfrac1c3 pll fractional division ratio register 1 channel 3 063 h 07 h a_pllfrac2c3 pll fractional division ratio register 2 channel 3 064 h 09 h sfrpage special function register page register 080 h 00 h ppcfg0 pp0 and pp1 configuration register 081 h 50 h ppcfg1 pp2 and pp3 configuration register 082 h 12 h ppcfg2 ppx port configuration register 083 h 00 h rxruncfg0 rx run configuration register 0 084 h ff h rxruncfg1 rx run configuration register 1 085 h ff h clkout0 clock divider register 0 086 h 0b h clkout1 clock divider register 1 087 h 00 h clkout2 clock divider register 2 088 h 00 h rfc rf control register 089 h 07 h bpfcalcfg0 bpf calibration configuration register 0 08a h 07 h bpfcalcfg1 bpf calibration configuration register 1 08b h 04 h xtalcal0 xtal coarse calibration register 08c h 10 h xtalcal1 xtal fine calibration register 08d h 00 h rssimonc rssi monitor configuration register 08e h 01 h adcinsel adc input selection register 08f h 00 h rssioffs rssi offset register 090 h 80 h rssislope rssi slope register 091 h 80 h im0 interrupt mask register 0 094 h 00 h im1 interrupt mask register 1 095 h 00 h spmap self polling mode active periods register 096 h 01 h spmip self polling mode idle periods register 097 h 01 h spmc self polling mode control register 098 h 00 h spmrt self polling mode reference timer register 099 h 01 h spmofft0 self polling mode off time register 0 09a h 01 h spmofft1 self polling mode off time register 1 09b h 00 h spmonta0 self polling mode on time config a register 0 09c h 01 h spmonta1 self polling mode on time config a register 1 09d h 00 h spmontb0 self polling mode on time config b register 0 09e h 01 h spmontb1 self polling mode on time config b register 1 09f h 00 h spmontc0 self polling mode on time config c register 0 0a0 h 01 h spmontc1 self polling mode on time config c register 1 0a1 h 00 h spmontd0 self polling mode on time config d register 0 0a2 h 01 h spmontd1 self polling mode on time config d register 1 0a3 h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 117 v1.0, 2010-02-19 extpcmd external processing command register 0a4 h 00 h cmc1 chip mode control register 1 0a5 h 04 h cmc0 chip mode control register 0 0a6 h 10 h rssipwu wakeup peak detector readout register 0a7 h 00 h is0 interrupt status register 0 0a8 h ff h is1 interrupt status register 1 0a9 h ff h rfpllacc rf pll actual channel and configuration register 0aa h 00 h rssiprx rssi peak detector readout register 0ab h 00 h adcresh adc result high byte register 0ae h 00 h adcresl adc result low byte register 0af h 00 h vacres vco autocalibration result readout register 0b0 h 00 h afcoffset afc offset read register 0b1 h 00 h agcgainr agc gain readout register 0b2 h 00 h spiat spi address tracer register 0b3 h 00 h spidt spi data tracer register 0b4 h 00 h spichksum spi checksum register 0b5 h 00 h sn0 serial number register 0 0b6 h 00 h sn1 serial number register 1 0b7 h 00 h sn2 serial number register 2 0b8 h 00 h sn3 serial number register 3 0b9 h 00 h rssirx rssi readout register 0ba h 00 h rssipmf rssi peak memory filter readout register 0bb h 00 h b_if1 if1 register 116 h 20 h b_wurssith1 rssi wake-up threshold for channel 1 register 11b h 00 h b_wurssibl1 rssi wake-up blocking level low channel 1 register 11c h ff h b_wurssibh1 rssi wake-up blocking level high channel 1 register 11d h 00 h b_wurssith2 rssi wake-up threshold for channel 2 register 11e h 00 h b_wurssibl2 rssi wake-up blocking level low channel 2 register 11f h ff h b_wurssibh2 rssi wake-up blocking level high channel 2 register 120 h 00 h b_wurssith3 rssi wake-up threshold for channel 3 register 121 h 00 h b_wurssibl3 rssi wake-up blocking level low channel 3 register 122 h ff h b_wurssibh3 rssi wake-up blocking level high channel 3 register 123 h 00 h b_wulot wake-up on level observation time register 125 h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 118 v1.0, 2010-02-19 b_afclimit afc limit configuration register 12a h 02 h b_afcagcd afc/agc freeze delay register 12b h 00 h b_afcsfcfg afc start/freeze configuration register 12c h 00 h b_afck1cfg0 afc integrator 1 gain register 0 12d h 00 h b_afck1cfg1 afc integrator 1 gain register 1 12e h 00 h b_afck2cfg0 afc integrator 2 gain register 0 12f h 00 h b_afck2cfg1 afc integrator 2 gain register 1 130 h 00 h b_pmfudsf peak memory filter up-down factor register 131 h 42 h b_agcsfcfg agc start/freeze configuration register 132 h 00 h b_agccfg0 agc configuration register 0 133 h 2b h b_agccfg1 agc configuration register 1 134 h 03 h b_agcthr agc threshold register 135 h 08 h b_digrxc digital receiver configuration register 136 h 40 h b_isupfcsel image supression fc selection register 138 h 07 h b_pdecf pre decimation factor register 139 h 00 h b_pdecscfsk pre decimation scaling register fsk mode 13a h 00 h b_pdecscask pre decimation scaling register ask mode 13b h 20 h b_mfc matched filter control register 13c h 07 h b_src sampe rate converter nco tune 13d h 00 h b_extslc externel data slicer configuration 13e h 02 h b_chcfg channel configuration register 158 h 44 h b_pllintc1 pll mmd integer value register channel 1 159 h 93 h b_pllfrac0c1 pll fractional division ratio register 0 channel 1 15a h f3 h b_pllfrac1c1 pll fractional division ratio register 1 channel 1 15b h 07 h b_pllfrac2c1 pll fractional division ratio register 2 channel 1 15c h 09 h b_pllintc2 pll mmd integer value register channel 2 15d h 13 h b_pllfrac0c2 pll fractional division ratio register 0 channel 2 15e h f3 h b_pllfrac1c2 pll fractional division ratio register 1 channel 2 15f h 07 h b_pllfrac2c2 pll fractional division ratio register 2 channel 2 160 h 09 h b_pllintc3 pll mmd integer value register channel 3 161 h 13 h b_pllfrac0c3 pll fractional division ratio register 0 channel 3 162 h f3 h b_pllfrac1c3 pll fractional division ratio register 1 channel 3 163 h 07 h b_pllfrac2c3 pll fractional division ratio register 2 channel 3 164 h 09 h c_if1 if1 register 216 h 20 h c_wurssith1 rssi wake-up threshold for channel 1 register 21b h 00 h c_wurssibl1 rssi wake-up blocking level low channel 1 register 21c h ff h c_wurssibh1 rssi wake-up blocking level high channel 1 register 21d h 00 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 119 v1.0, 2010-02-19 c_wurssith2 rssi wake-up threshold for channel 2 register 21e h 00 h c_wurssibl2 rssi wake-up blocking level low channel 2 register 21f h ff h c_wurssibh2 rssi wake-up blocking level high channel 2 register 220 h 00 h c_wurssith3 rssi wake-up threshold for channel 3 register 221 h 00 h c_wurssibl3 rssi wake-up blocking level low channel 3 register 222 h ff h c_wurssibh3 rssi wake-up blocking level high channel 3 register 223 h 00 h c_wulot wake-up on level observation time register 225 h 00 h c_afclimit afc limit configuration register 22a h 02 h c_afcagcd afc/agc freeze delay register 22b h 00 h c_afcsfcfg afc start/freeze configuration register 22c h 00 h c_afck1cfg0 afc integrator 1 gain register 0 22d h 00 h c_afck1cfg1 afc integrator 1 gain register 1 22e h 00 h c_afck2cfg0 afc integrator 2 gain register 0 22f h 00 h c_afck2cfg1 afc integrator 2 gain register 1 230 h 00 h c_pmfudsf peak memory filter up-down factor register 231 h 42 h c_agcsfcfg agc start/freeze configuration register 232 h 00 h c_agccfg0 agc configuration register 0 233 h 2b h c_agccfg1 agc configuration register 1 234 h 03 h c_agcthr agc threshold register 235 h 08 h c_digrxc digital receiver configuration register 236 h 40 h c_isupfcsel image supression fc selection register 238 h 07 h c_pdecf pre decimation factor register 239 h 00 h c_pdecscfsk pre decimation scaling register fsk mode 23a h 00 h c_pdecscask pre decimation scaling register ask mode 23b h 20 h c_mfc matched filter control register 23c h 07 h c_src sampe rate converter nco tune 23d h 00 h c_extslc externel data slicer configuration 23e h 02 h c_chcfg channel configuration register 258 h 44 h c_pllintc1 pll mmd integer value register channel 1 259 h 93 h c_pllfrac0c1 pll fractional division ratio register 0 channel 1 25a h f3 h c_pllfrac1c1 pll fractional division ratio register 1 channel 1 25b h 07 h c_pllfrac2c1 pll fractional division ratio register 2 channel 1 25c h 09 h c_pllintc2 pll mmd integer value register channel 2 25d h 13 h c_pllfrac0c2 pll fractional division ratio register 0 channel 2 25e h f3 h c_pllfrac1c2 pll fractional division ratio register 1 channel 2 25f h 07 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 120 v1.0, 2010-02-19 c_pllfrac2c2 pll fractional division ratio register 2 channel 2 260 h 09 h c_pllintc3 pll mmd integer value register channel 3 261 h 13 h c_pllfrac0c3 pll fractional division ratio register 0 channel 3 262 h f3 h c_pllfrac1c3 pll fractional division ratio register 1 channel 3 263 h 07 h c_pllfrac2c3 pll fractional division ratio register 2 channel 3 264 h 09 h d_if1 if1 register 316 h 20 h d_wurssith1 rssi wake-up threshold for channel 1 register 31b h 00 h d_wurssibl1 rssi wake-up blocking level low channel 1 register 31c h ff h d_wurssibh1 rssi wake-up blocking level high channel 1 register 31d h 00 h d_wurssith2 rssi wake-up threshold for channel 2 register 31e h 00 h d_wurssibl2 rssi wake-up blocking level low channel 2 register 31f h ff h d_wurssibh2 rssi wake-up blocking level high channel 2 register 320 h 00 h d_wurssith3 rssi wake-up threshold for channel 3 register 321 h 00 h d_wurssibl3 rssi wake-up blocking level low channel 3 register 322 h ff h d_wurssibh3 rssi wake-up blocking level high channel 3 register 323 h 00 h d_wulot wake-up on level observation time register 325 h 00 h d_afclimit afc limit configuration register 32a h 02 h d_afcagcd afc/agc freeze delay register 32b h 00 h d_afcsfcfg afc start/freeze configuration register 32c h 00 h d_afck1cfg0 afc integrator 1 gain register 0 32d h 00 h d_afck1cfg1 afc integrator 1 gain register 1 32e h 00 h d_afck2cfg0 afc integrator 2 gain register 0 32f h 00 h d_afck2cfg1 afc integrator 2 gain register 1 330 h 00 h d_pmfudsf peak memory filter up-down factor register 331 h 42 h d_agcsfcfg agc start/freeze configuration register 332 h 00 h d_agccfg0 agc configuration register 0 333 h 2b h d_agccfg1 agc configuration register 1 334 h 03 h d_agcthr agc threshold register 335 h 08 h d_digrxc digital receiver configuration register 336 h 40 h d_isupfcsel image supression fc selection register 338 h 07 h d_pdecf pre decimation factor register 339 h 00 h d_pdecscfsk pre decimation scaling register fsk mode 33a h 00 h d_pdecscask pre decimation scaling register ask mode 33b h 20 h d_mfc matched filter control register 33c h 07 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register overview data sheet 121 v1.0, 2010-02-19 d_src sampe rate converter nco tune 33d h 00 h d_extslc externel data slicer configuration 33e h 02 h d_chcfg channel configuration register 358 h 44 h d_pllintc1 pll mmd integer value register channel 1 359 h 93 h d_pllfrac0c1 pll fractional division ratio register 0 channel 1 35a h f3 h d_pllfrac1c1 pll fractional division ratio register 1 channel 1 35b h 07 h d_pllfrac2c1 pll fractional division ratio register 2 channel 1 35c h 09 h d_pllintc2 pll mmd integer value register channel 2 35d h 13 h d_pllfrac0c2 pll fractional division ratio register 0 channel 2 35e h f3 h d_pllfrac1c2 pll fractional division ratio register 1 channel 2 35f h 07 h d_pllfrac2c2 pll fractional division ratio register 2 channel 2 360 h 09 h d_pllintc3 pll mmd integer value register channel 3 361 h 13 h d_pllfrac0c3 pll fractional division ratio register 0 channel 3 362 h f3 h d_pllfrac1c3 pll fractional division ratio register 1 channel 3 363 h 07 h d_pllfrac2c3 pll fractional division ratio register 2 channel 3 364 h 09 h table 2 register overview and reset value (cont?d) register short name re gister long name offset address reset value
TDA5225 appendix register description data sheet 122 v1.0, 2010-02-19 register description if1 register rssi wake-up threshold for channel 1 register a_if1 offset reset value if1 register 016 h 20 h field bits type description unused 7 - unused reset: 0 h ssbsel 6 w rxrf receive side band select 0 b rf = lo + if1 (lo-side lo-injection) 1 b rf = lo - if1 (hi-side lo-injection) reset: 0 h bpfbwsel 5:3 w band pass filter bandwidth selection 000 b 50 khz 001 b 80 khz 010 b 125 khz 011 b 200 khz 100 b 300 khz 101 b not used 110 b not used 111 b not used reset: 4 h sdcsel 2 w single / double conversion selection 0 b double conversion (10.7 mhz/274 khz) 1 b single conversion (274 khz) reset: 0 h ifbufen 1 w if buffer enable 0 b disabled 1 b enabled reset: 0 h cerfsel 0 w number of external ceramic filters 0 b 1 ceramic filter 1 b 2 ceramic filters reset: 0 h 8186(' z 66%6(/ z %3)%:6(/ z 6'&6(/ z ,)%8)(1 z &(5)6(/
TDA5225 appendix register description data sheet 123 v1.0, 2010-02-19 rssi wake-up blocking level low channel 1 register rssi wake-up blocking level high channel 1 register a_wurssith1 offset reset value rssi wake-up threshold for channel 1 register 01b h 00 h field bits type description wurssith1 7:0 w wake up on rssi threshold level for channel 1 wake up request generated when actual rssi level is above this threshold reset: 00 h a_wurssibl1 offset reset value rssi wake-up blocking level low channel 1 register 01c h ff h field bits type description wurssibl1 7:0 w wake up on rssi blocking level low for channel 1 reset: ff h a_wurssibh1 offset reset value rssi wake-up blocking level high channel 1 register 01d h 00 h z :8566,7+ z :8566,%/ z :8566,%+
TDA5225 appendix register description data sheet 124 v1.0, 2010-02-19 rssi wake-up threshold for channel 2 register rssi wake-up blocking level low channel 2 register rssi wake-up blocking level high channel 2 register field bits type description wurssibh1 7:0 w wake up on rssi blocking level high for channel 1 reset: 00 h a_wurssith2 offset reset value rssi wake-up threshold for channel 2 register 01e h 00 h field bits type description wurssith2 7:0 w wake up on rssi threshold level for channel 2 wake up request generated when actual rssi level is above this threshold reset: 00 h a_wurssibl2 offset reset value rssi wake-up blocking level low channel 2 register 01f h ff h field bits type description wurssibl2 7:0 w wake up on rssi blocking level low for channel 2 reset: ff h z :8566,7+ z :8566,%/
TDA5225 appendix register description data sheet 125 v1.0, 2010-02-19 rssi wake-up threshold for channel 3 register rssi wake-up blocking level low channel 3 register a_wurssibh2 offset reset value rssi wake-up blocking level high channel 2 register 020 h 00 h field bits type description wurssibh2 7:0 w wake up on rssi blocking level high for channel 2 reset: 00 h a_wurssith3 offset reset value rssi wake-up threshold for channel 3 register 021 h 00 h field bits type description wurssith3 7:0 w wake up on rssi threshold level for channel 3 wake up request generated when actual rssi level is above this threshold reset: 00 h a_wurssibl3 offset reset value rssi wake-up blocking level low channel 3 register 022 h ff h z :8566,%+ z :8566,7+ z :8566,%/
TDA5225 appendix register description data sheet 126 v1.0, 2010-02-19 rssi wake-up blocking level high channel 3 register wake-up on level observation time register field bits type description wurssibl3 7:0 w wake up on rssi blocking level low for channel 3 reset: ff h a_wurssibh3 offset reset value rssi wake-up blocking level high channel 3 register 023 h 00 h field bits type description wurssibh3 7:0 w wake up on rssi blocking level high for channel 3 reset: 00 h a_wulot offset reset value wake-up on level observation time register 025 h 00 h field bits type description wulotps 7:5 w wake-up level observation time prescaler 000 b 4 001 b 8 010 b 16 011 b 32 100 b 64 101 b 128 110 b 256 111 b 512 reset: 0 h z :8566,%+ z :8/2736 z :8/27
TDA5225 appendix register description data sheet 127 v1.0, 2010-02-19 afc limit configuration register afc/agc freeze delay register wulot 4:0 w wake-up level observation time min. 01h : twulot = 1 * wulotps * 64 / fsys max 1fh : twulot = 31 * wulotps * 64 / fsys value 00h : twulot = 32 * wulotps * 64 / fsys reset: 00 h a_afclimit offset reset value afc limit configuration register 02a h 02 h field bits type description unused 7:4 - unused reset: 0 h afclimit 3:0 w afc frequency offset saturation limit ==> 1...15 x 21.4 khz min: 1h = +/- fsys / 2^(22-12) hz max: fh = +/- 15 * fsys / 2^(22-12) hz reg. value 0h = 0 hz - no afc correction reset: 2 h a_afcagcd offset reset value afc/agc freeze delay register 02b h 00 h field bits type description afcagcd 7:0 w afc/agc freeze delay counter division ratio the base period for the delay counter is the 8-16 samples/chip (predecimation strobe) divided by 4 reset: 00 h field bits type description 8186(' z $)&/,0,7 z $)&$*&'
TDA5225 appendix register description data sheet 128 v1.0, 2010-02-19 afc start/freeze configuration register a_afcsfcfg offset reset value afc start/freeze configuration register 02c h 00 h field bits type description unused 7 - unused reset: 0 h afcblask 6 w afc blocking during a low phase in the ask signal 0 b disabled 1 b enabled reset: 0 h afcresatc c 5 w enable afc restart at channel change and at the beginning of the current configuration in self polling mode and at leaving the hold state (when bit cmc0.initpllhold is set) in run mode slave 0 b disabled 1 b enabled reset: 0 h afcfreeze 4:2 w afc freeze configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 000 b stay on 001 b freeze on rssi event + delay (afcagcdel) 010 b not used 011 b not used 100 b spi command - write to extpcmd.afcmanf bit 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h afcstart 1:0 w afc start configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 00 b off 01 b direct on 10 b start on rssi event 11 b not used reset: 0 h 8186(' z $)&%/$6 . z $)&5(6$ 7&& z $)&)5((=( z $)&67$57
TDA5225 appendix register description data sheet 129 v1.0, 2010-02-19 afc integrator 1 gain register 0 afc integrator 1 gain register 1 afc integrator 2 gain register 0 a_afck1cfg0 offset reset value afc integrator 1 gain register 0 02d h 00 h field bits type description afck1_0 7:0 w afc filter coefficient k1, afck1(11:0) = afck1_1(msb) & afck1_0(lsb) reset: 00 h a_afck1cfg1 offset reset value afc integrator 1 gain register 1 02e h 00 h field bits type description unused 7:4 - unused reset: 0 h afck1_1 3:0 w afc filter coefficient k1, afck1(11:0) = afck1_1(msb) & afck1_0(lsb) reset: 0 h a_afck2cfg0 offset reset value afc integrator 2 gain register 0 02f h 00 h z $)&.b 8186(' z $)&.b
TDA5225 appendix register description data sheet 130 v1.0, 2010-02-19 afc integrator 2 gain register 1 peak memory filter up-down factor register field bits type description afck2_0 7:0 w afc filter coefficient k2, afck2(11:0) = afck2_1(msb) & afck2_0(lsb) reset: 00 h a_afck2cfg1 offset reset value afc integrator 2 gain register 1 030 h 00 h field bits type description unused 7:4 - unused reset: 0 h afck2_1 3:0 w afc filter coefficient k2, afck2(11:0) = afck2_1(msb) & afck2_0(lsb) reset: 0 h a_pmfudsf offset reset value peak memory filter up-down factor register 031 h 42 h field bits type description unused 7 - unused reset: 0 h z $)&.b 8186(' z $)&.b 8186(' z 30)83 8186(' z 30)'1
TDA5225 appendix register description data sheet 131 v1.0, 2010-02-19 agc start/freeze configuration register pmfup 6:4 w peak memory filter attack (up) factor 000 b 2^-1 001 b 2^-2 010 b 2^-3 011 b 2^-4 100 b 2^-5 101 b 2^-6 110 b 2^-7 111 b 2^-8 reset: 4 h unused 3 - unused reset: 0 h pmfdn 2:0 w peak memory filter decay (down) factor (additional to attack factor) 000 b 2^-2 001 b 2^-3 010 b 2^-4 011 b 2^-5 100 b 2^-6 101 b 2^-7 110 b 2^-8 111 b 2^-9 reset: 2 h a_agcsfcfg offset reset value agc start/freeze configuration register 032 h 00 h field bits type description unused 7:6 - unused reset: 0 h agcresatc c 5 w enable agc restart at channel change and at the beginning of the current configuration in self polling mode and at leaving the hold state (when bit cmc0.initpllhold is set) in run mode slave 0 b disabled 1 b enabled reset: 0 h field bits type description 8186(' z $*&5(6$ 7&& z $*&)5((=( z $*&67$57
TDA5225 appendix register description data sheet 132 v1.0, 2010-02-19 agc configuration register 0 agcfreeze 4:2 w agc freeze configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 000 b stay on 001 b freeze on rssi event + delay (afcagcdel) 010 b not used 011 b not used 100 b spi command - write to extpcmd.agcmanf bit 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h agcstart 1:0 w agc start configuration when selecting a level criterion here, please note to use the same level criterion as for wake-up 00 b off 01 b direct on 10 b start on rssi event 11 b not used reset: 0 h a_agccfg0 offset reset value agc configuration register 0 033 h 2b h field bits type description unused 7 - unused reset: 0 h agcdgc 6:4 w agc digital rssi gain correction tuning 000 b 14.5 db 001 b 15.0 db 010 b 15.5 db 011 b 16.0 db 100 b 16.5 db 101 b 17.0 db 110 b 17.5 db 111 b 18.0 db reset: 2 h field bits type description 8186(' z $*&'*& z $*&+<6 z $*&*$,1
TDA5225 appendix register description data sheet 133 v1.0, 2010-02-19 agc configuration register 1 agc threshold register agchys 3:2 w agc threshold hysteresis 00 b 12.8 db 01 b 17.1 db 10 b 21.3 db 11 b 25.6 db reset: 2 h agcgain 1:0 w agc gain control 00 b 0 db 01 b -15 db 10 b -30 db 11 b automatic reset: 3 h a_agccfg1 offset reset value agc configuration register 1 034 h 03 h field bits type description unused 7:2 - unused reset: 00 h agcthoffs 1:0 w agc threshold offset 00 b 25.5 db 01 b 38.3 db 10 b 51.1 db 11 b 63.9 db reset: 3 h a_agcthr offset reset value agc threshold register 035 h 08 h field bits type description 8186(' z $*&7+2))6 z $*&783 z $*&7/2
TDA5225 appendix register description data sheet 134 v1.0, 2010-02-19 digital receiver configuration register image supression fc selection register field bits type description agctup 7:4 w agc upper attack threshold [db] agc upper threshold = a_agccfg1.agcthoffs + 25.6 + agctup*1.6 reset: 0 h agctlo 3:0 w agc lower attack threshold [db] agc lower threshold = a_agccfg1.agcthoffs + agctlo*1.6 reset: 8 h a_digrxc offset reset value digital receiver configuration register 036 h 40 h field bits type description initdrxes 7 w init the digital receiver at eom signa l (e.g. for initialization of the peak memory filter) 0 b disabled 1 b enabled reset: 0 h unused 6:3 w unused reset: 8 h dinvext 2 w data inversion of signal data and data_matchfil for external processing 0 b not inverted 1 b inverted reset: 0 h aafbyp 1 w anti-alliasing filter bypass for rssi pin 0 b not bypassed 1 b bypassed reset: 0 h aaffcsel 0 w anti-alliasing filter co rner frequency select 0 b 40 khz 1 b 80 khz reset: 0 h z ,1,7'5; (6 z 8186(' z ',19(;7 z $$)%<3 z $$))&6( /
TDA5225 appendix register description data sheet 135 v1.0, 2010-02-19 pre decimation factor register pre decimation scaling register fsk mode a_isupfcsel offset reset value image supression fc selection register 038 h 07 h field bits type description unused 7:4 - unused reset: 0 h fcsel 2:0 w image supression filter corner frequency selection for fsk signal path 000 b 33 khz 001 b 46 khz 010 b 65 khz 011 b 93 khz 100 b 132 khz 101 b 190 khz 110 b 239 khz 111 b 282 khz reset: 7 h a_pdecf offset reset value pre decimation factor register 039 h 00 h field bits type description unused 7 - unused reset: 0 h predecf 6:0 w predecimation filter decimation factor predecimation factor = predecf + 1 reset: 00 h 8186(' 5hv z )&6(/ 8186(' z 35('(&)
TDA5225 appendix register description data sheet 136 v1.0, 2010-02-19 pre decimation scaling register ask mode matched filter control register a_pdecscfsk offset reset value pre decimation scaling register fsk mode 03a h 00 h field bits type description intpolenf 5 w fsk data interpolation enable 0 b disabled 1 b enabled reset: 0 h pdscalef 4:0 w predecimation block scaling factor for fsk min 00h : 2^-10 max 17h : 2^13 reset: 00 h a_pdecscask offset reset value pre decimation scaling register ask mode 03b h 20 h field bits type description unused 7 - unused reset: 0 h intpolena 5 w ask data interpolation enable 0 b disabled 1 b enabled reset: 1 h pdscalea 4:0 w predecimation block scaling factor for ask min 00h : 2^-10 max 17h : 2^13 reset: 00 h 5hv z ,1732/( 1) z 3'6&$/() 8186(' 5hv z ,1732/( 1$ z 3'6&$/($
TDA5225 appendix register description data sheet 137 v1.0, 2010-02-19 sampe rate converter nco tune externel data slicer configuration a_mfc offset reset value matched filter control register 03c h 07 h field bits type description unused 7:4 - unused reset: 0 h mfl 3:0 w matched filter length mf length = mfl + 1 reset: 7 h a_src offset reset value sampe rate converter nco tune 03d h 00 h field bits type description srcnco 7:0 w sample rate converter nco tune min 00h : fout = fin max ffh : fout = fin / 2 reset: 00 h a_extslc offset reset value externel data slicer configuration 03e h 02 h 8186(' z 0)/ z 65&1&2 8186(' 5hv z (6/&6&$ z (6/&%:
TDA5225 appendix register description data sheet 138 v1.0, 2010-02-19 channel configuration register field bits type description unused 7 - unused reset: 0 h eslcsca 4:3 w external slicer bw selection scaling 00 b 1/2 01 b 1/4 10 b 1/8 11 b 1/16 reset: 0 h eslcbw 2:0 w external slicer manual bw selection 000 b 1/8 001 b 1/16 010 b 1/24 011 b 1/32 100 b 1/40 101 b 1/48 110 b n.u. 111 b n.u. reset: 2 h a_chcfg offset reset value channel configuration register 058 h 44 h field bits type description unused 7:5 - unused reset: 2 h eom2spm 4 w continue with self polling mode after eom detected in run mode self polling 0 b disabled - stay in run mode self polling (next payload frame is expected) 1 b enabled - leave run mode self polling after eom reset: 0 h 8186(' z (20630 z 12& z 07
TDA5225 appendix register description data sheet 139 v1.0, 2010-02-19 pll mmd integer value register channel 1 pll fractional division ratio register 0 channel 1 noc 3:2 w number of channels (run mode slave / self polling mode - run mode self polling) 00 b channel 1 / channel 1 01 b channel 1 / channel 1 10 b channel 2 / channel 1 + 2 11 b channel 3 / channel 1 + 2 + 3 reset: 1 h mt 1:0 w modulation type (run mode slave / self polling mode - run mode self polling) 00 b ask / ask - ask 01 b fsk / fsk - fsk 10 b ask / fsk - ask 11 b fsk / ask - fsk reset: 0 h a_pllintc1 offset reset value pll mmd integer value register channel 1 059 h 93 h field bits type description bandsel 7:6 w frequency band selection 00 b not used 01 b 915mhz/868mhz 10 b 434mhz 11 b 315mhz reset: 2 h pllintc1 5:0 w sdpll multi modulus divider integer offset value for channel 1 pllint(5:0) = dec2hex(int(f_lo / f_xtal)) reset: 13 h a_pllfrac0c1 offset reset value pll fractional division ratio register 0 channel 1 05a h f3 h field bits type description z %$1'6(/ z 3//,17&
TDA5225 appendix register description data sheet 140 v1.0, 2010-02-19 pll fractional division ratio register 1 channel 1 pll fractional division ratio register 2 channel 1 field bits type description pllfrac0c1 7:0 w synthesizer channel frequency value (21 bits, bits 7:0), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: f3 h a_pllfrac1c1 offset reset value pll fractional division ratio register 1 channel 1 05b h 07 h field bits type description pllfrac1c1 7:0 w synthesizer channel frequency value (21 bits, bits 15:8), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 07 h a_pllfrac2c1 offset reset value pll fractional division ratio register 2 channel 1 05c h 09 h z 3//)5$&& z 3//)5$&& 8186(' z 3//)&20 3& z 3//)5$&&
TDA5225 appendix register description data sheet 141 v1.0, 2010-02-19 pll mmd integer value register channel 2 pll fractional division ratio register 0 channel 2 field bits type description unused 7:6 - unused reset: 0 h pllfcompc1 5 w fractional spurii compensation enable for channel 1 0 b disabled 1 b enabled reset: 0 h pllfrac2c1 4:0 w synthesizer channel frequency value (21 bits, bits 20:16), fractional division ratio for channel 1 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 09 h a_pllintc2 offset reset value pll mmd integer value register channel 2 05d h 13 h field bits type description unused 7:6 - unused reset: 0 h pllintc2 5:0 w sdpll multi modulus divider integer offset value for channel 2 pllint(5:0) = dec2hex(int(f_lo / f_xtal)) reset: 13 h a_pllfrac0c2 offset reset value pll fractional division ratio register 0 channel 2 05e h f3 h 8186(' z 3//,17& z 3//)5$&&
TDA5225 appendix register description data sheet 142 v1.0, 2010-02-19 pll fractional division ratio register 1 channel 2 pll fractional division ratio register 2 channel 2 field bits type description pllfrac0c2 7:0 w synthesizer channel frequency value (21 bits, bits 7:0), fractional division ratio for channel 2 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: f3 h a_pllfrac1c2 offset reset value pll fractional division ratio register 1 channel 2 05f h 07 h field bits type description pllfrac1c2 7:0 w synthesizer channel frequency value (21 bits, bits 15:8), fractional division ratio for channel 2 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 07 h a_pllfrac2c2 offset reset value pll fractional division ratio register 2 channel 2 060 h 09 h field bits type description unused 7:6 - unused reset: 0 h pllfcompc2 5 w fractional spurii compensation enable for channel 2 0 b disabled 1 b enabled reset: 0 h z 3//)5$&& 8186(' z 3//)&20 3& z 3//)5$&&
TDA5225 appendix register description data sheet 143 v1.0, 2010-02-19 pll mmd integer value register channel 3 pll fractional division ratio register 0 channel 3 pll fractional division ratio register 1 channel 3 pllfrac2c2 4:0 w synthesizer channel frequency value (21 bits, bits 20:16), fractional division ratio for channel 2 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 09 h a_pllintc3 offset reset value pll mmd integer value register channel 3 061 h 13 h field bits type description unused 7:6 - unused reset: 0 h pllintc3 5:0 w sdpll multi modulus divider integer offset value for channel 3 pllint(5:0) = dec2hex(int(f_lo / f_xtal)) reset: 13 h a_pllfrac0c3 offset reset value pll fractional division ratio register 0 channel 3 062 h f3 h field bits type description pllfrac0c3 7:0 w synthesizer channel frequency value (21 bits, bits 7:0), fractional division ratio for channel 3 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: f3 h field bits type description 8186(' z 3//,17& z 3//)5$&&
TDA5225 appendix register description data sheet 144 v1.0, 2010-02-19 pll fractional division ratio register 2 channel 3 special function register page register a_pllfrac1c3 offset reset value pll fractional division ratio register 1 channel 3 063 h 07 h field bits type description pllfrac1c3 7:0 w synthesizer channel frequency value (21 bits, bits 15:8), fractional division ratio for channel 3 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 07 h a_pllfrac2c3 offset reset value pll fractional division ratio register 2 channel 3 064 h 09 h field bits type description unused 7:6 - unused reset: 0 h pllfcompc3 5 w fractional spurii compensation enable for channel 3 0 b disabled 1 b enabled reset: 0 h pllfrac2c3 4:0 w synthesizer channel frequency value (21 bits, bits 20:16), fractional division ratio for channel 3 pllfrac(20:0) = dec2hex(((f_lo / f_xtal) - pllint) * 2^21) reset: 09 h z 3//)5$&& 8186(' z 3//)&20 3& z 3//)5$&&
TDA5225 appendix register description data sheet 145 v1.0, 2010-02-19 pp0 and pp1 configuration register sfrpage offset reset value special function register page register 080 h 00 h field bits type description unused 7:2 - unused reset: 00 h sfrpage 1:0 w selection of register page file (configuration a..d) for spi communication 00 b page 0 (config. a, start address: 000 h ) 01 b page 1 (config. b, start address: 100 h ) 10 b page 2 (config. c, start address: 200 h ) 11 b page 3 (config. d, start address: 300 h ) reset: 0 h ppcfg0 offset reset value pp0 and pp1 configuration register 081 h 50 h field bits type description unused 7 w unused reset: 0 h pp1cfg 6:4 w port pin 1 output signal selection 000 b clk_out 001 b rx_run 010 b nint 011 b low 100 b high 101 b data 110 b data_matchfil 111 b n.u. reset: 5 h 8186(' z 6)53$*( z 8186(' z 33&)* z 8186(' z 33&)*
TDA5225 appendix register description data sheet 146 v1.0, 2010-02-19 pp2 and pp3 configuration register unused 3 w unused reset: 0 h pp0cfg 2:0 w port pin 0 output signal selection 000 b clk_out 001 b rx_run 010 b nint 011 b low 100 b high 101 b data 110 b data_matchfil 111 b n.u. reset: 0 h ppcfg1 offset reset value pp2 and pp3 configuration register 082 h 12 h field bits type description unused 7 w unused reset: 0 h pp3cfg 6:4 w port pin 3 output signal selection 000 b n.u. 001 b rx_run 010 b nint 011 b low 100 b high 101 b data 110 b data_matchfil 111 b n.u. reset: 1 h unused 3 w unused reset: 0 h field bits type description z 8186(' z 33&)* z 8186(' z 33&)*
TDA5225 appendix register description data sheet 147 v1.0, 2010-02-19 ppx port configuration register pp2cfg 2:0 w port pin 2 output signal selection 000 b clk_out 001 b rx_run 010 b nint 011 b low 100 b high 101 b data 110 b data_matchfil 111 b n.u. reset: 2 h ppcfg2 offset reset value ppx port configuration register 083 h 00 h field bits type description pp3hppen 7 w pp3 high power pad enable 0 b normal 1 b high power reset: 0 h pp2hppen 6 w pp2 high power pad enable 0 b normal 1 b high power reset: 0 h pp1hppen 5 w pp1 high power pad enable 0 b normal 1 b high power reset: 0 h pp0hppen 4 w pp0 high power pad enable 0 b normal 1 b high power reset: 0 h pp3inv 3 w pp3 inversion enable 0 b not inverted 1 b inverted reset: 0 h field bits type description z 33+33( 1 z 33+33( 1 z 33+33( 1 z 33+33( 1 z 33,19 z 33,19 z 33,19 z 33,19
TDA5225 appendix register description data sheet 148 v1.0, 2010-02-19 rx run configuration register 0 pp2inv 2 w pp2 inversion enable 0 b not inverted 1 b inverted reset: 0 h pp1inv 1 w pp1 inversion enable 0 b not inverted 1 b inverted reset: 0 h pp0inv 0 w pp0 inversion enable 0 b not inverted 1 b inverted reset: 0 h rxruncfg0 offset reset value rx run configuration register 0 084 h ff h field bits type description rxrunpp1d 7 w rxrun active level on pp1 for configuration d 0 b active low 1 b active high reset: 1 h rxrunpp1c 6 w rxrun active level on pp1 for configuration c 0 b active low 1 b active high reset: 1 h rxrunpp1b 5 w rxrun active level on pp1 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp1a 4 w rxrun active level on pp1 for configuration a 0 b active low 1 b active high reset: 1 h rxrunpp0d 3 w rxrun active level on pp0 for configuration d 0 b active low 1 b active high reset: 1 h field bits type description z 5;58133 ' z 5;58133 & z 5;58133 % z 5;58133 $ z 5;58133 ' z 5;58133 & z 5;58133 % z 5;58133 $
TDA5225 appendix register description data sheet 149 v1.0, 2010-02-19 rx run configuration register 1 rxrunpp0c 2 w rxrun active level on pp0 for configuration c 0 b active low 1 b active high reset: 1 h rxrunpp0b 1 w rxrun active level on pp0 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp0a 0 w rxrun active level on pp0 for configuration a 0 b active low 1 b active high reset: 1 h rxruncfg1 offset reset value rx run configuration register 1 085 h ff h field bits type description rxrunpp3d 7 w rxrun active level on pp3 for configuration d 0 b active low 1 b active high reset: 1 h rxrunpp3c 6 w rxrun active level on pp3 for configuration c 0 b active low 1 b active high reset: 1 h rxrunpp3b 5 w rxrun active level on pp3 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp3a 4 w rxrun active level on pp3 for configuration a 0 b active low 1 b active high reset: 1 h rxrunpp2d 3 w rxrun active level on pp2 for configuration d 0 b active low 1 b active high reset: 1 h field bits type description z 5;58133 ' z 5;58133 & z 5;58133 % z 5;58133 $ z 5;58133 ' z 5;58133 & z 5;58133 % z 5;58133 $
TDA5225 appendix register description data sheet 150 v1.0, 2010-02-19 clock divider register 0 clock divider register 1 rxrunpp2c 2 w rxrun active level on pp2 for configuration c 0 b active low 1 b active high reset: 1 h rxrunpp2b 1 w rxrun active level on pp2 for configuration b 0 b active low 1 b active high reset: 1 h rxrunpp2a 0 w rxrun active level on pp2 for configuration a 0 b active low 1 b active high reset: 1 h clkout0 offset reset value clock divider register 0 086 h 0b h field bits type description clkout0 7:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 0b h clkout1 offset reset value clock divider register 1 087 h 00 h field bits type description z &/.287 z &/.287
TDA5225 appendix register description data sheet 151 v1.0, 2010-02-19 clock divider register 2 rf control register field bits type description clkout1 7:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 00 h clkout2 offset reset value clock divider register 2 088 h 00 h field bits type description unused 7:4 - unused reset: 0 h clkout2 3:0 w clock out divider: clkout(19:0) = clkout2(msb) & clkout1 & clkout0(lsb) min: 00002h = clock divided by 2*2 max: fffffh = clock divided by ((2^20)-1)*2 reg. value 00000h = clock divided by (2^20)*2 reset: 0 h rfc offset reset value rf control register 089 h 07 h field bits type description unused 7:5 - unused reset: 0 h 8186(' z &/.287 8186(' z 5)2)) z ,)$77
TDA5225 appendix register description data sheet 152 v1.0, 2010-02-19 bpf calibration configuration register 0 bpf calibration configuration register 1 rfoff 4 w switch off rf-path (for rssi trimming) 0 b rf path enabled 1 b rf path disabled reset: 0 h ifatt 3:0 w adjust if attenuation from lna_in to if_out (double-down conversion / single-down conversion) used to trim out external component tolerances. 0000 b 0 db / n.u. 0001 b 0.8 db / n.u. 0010 b 1.6 db / n.u. 0011 b 2.4 db / n.u. 0100 b 3.2 db / 0 db 0101 b 4.0 db / 0.8 db 0110 b 4.8 db / 1.6 db 0111 b 5.6 db / 2.4 db 1000 b 6.4 db / 3.2 db 1001 b 7.2 db / 4.0 db 1010 b 8.0 db / 4.8 db 1011 b 8.8 db / n.u. 1100 b 9.6 db / n.u. 1101 b 10.4 db / n.u. 1110 b 11.2 db / n.u. 1111 b 12.0 db / n.u. reset: 7 h bpfcalcfg0 offset reset value bpf calibration configuration register 0 08a h 07 h field bits type description unused 7:5 - unused reset: 0 h bpfcalst 3:0 w bpf calibration time (use default = 07 h ) min: 0h= txtal * 80 * 7 * (0 + 4) max: fh= txtal * 80 * 7 * (15 + 4) reset: 7 h field bits type description 8186(' 5hv z %3)&$/67
TDA5225 appendix register description data sheet 153 v1.0, 2010-02-19 xtal coarse calibration register xtal fine calibration register bpfcalcfg1 offset reset value bpf calibration configuration register 1 08b h 04 h field bits type description unused 7:6 - unused reset: 0 h bpfcalbw 5:0 w band pass filter bandwidth selection during calibration 04 h - 50 khz (=default) 0d h - 80 khz 16 h - 125 khz 1f h - 200 khz 27 h - 300 khz reset: 04 h xtalcal0 offset reset value xtal coarse calibration register 08c h 10 h field bits type description unused 7:5 - unused reset: 0 h xtalswc 4:0 w xtal trim capacitor value min 00h: 0pf value 01h: 1pf max 18h: 24pf higher values than 18h are automatically mapped to 24pf reset: 10 h 8186(' z %3)&$/%: 8186(' z ;7$/6:&
TDA5225 appendix register description data sheet 154 v1.0, 2010-02-19 rssi monitor configuration register xtalcal1 offset reset value xtal fine calibration register 08d h 00 h field bits type description unused 7:4 - unused reset: 0 h xtalswf3 3 w connect 500 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf2 2 w connect 250 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf1 1 w connect 125 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h xtalswf0 0 w connect 62.5 ff xtal trim capacitor 0 b not connected 1 b connected reset: 0 h rssimonc offset reset value rssi monitor configuration register 08e h 01 h field bits type description unused 7:3 - unused reset: 00 h 8186(' z ;7$/6:) z ;7$/6:) z ;7$/6:) z ;7$/6:) 8186(' 5hv z 566,021 (1
TDA5225 appendix register description data sheet 155 v1.0, 2010-02-19 adc input selection register rssi offset register rssimonen 0 w enable buffer for rssi pin 0 b disabled 1 b enabled reset: 1 h adcinsel offset reset value adc input selection register 08f h 00 h field bits type description unused 7:3 - unused reset: 00 h adcinsel 2:0 w adc input selection 000 b rssi 001 b temperature 010 b vddd / 2 011 b n.u. 100 b n.u. 101 b n.u. 110 b n.u. 111 b n.u. reset: 0 h rssioffs offset reset value rssi offset register 090 h 80 h field bits type description 8186(' z $'&,16(/ z 566,2))6
TDA5225 appendix register description data sheet 156 v1.0, 2010-02-19 rssi slope register interrupt mask register 0 field bits type description rssioffs 7:0 w rssi offset compensation value min: 00h= -256 max: ffh= 254 reset: 80 h rssislope offset reset value rssi slope register 091 h 80 h field bits type description rssislope 7:0 w rssi slope compensation value (multiplication value) multiplication factor = rssislope * 2^-7 min: 00h= 0.0 max: ffh= 1.992 reset: 80 h im0 offset reset value interrupt mask register 0 094 h 00 h field bits type description unused 7:5 - unused reset: 0 h imwub 4 w mask interrupt on "wake-up" for configuration b 0 b interrupt enabled 1 b interrupt disabled reset: 0 h z 566,6/23( 8186(' z ,0:8% 8186(' z ,0:8$
TDA5225 appendix register description data sheet 157 v1.0, 2010-02-19 interrupt mask register 1 self polling mode active periods register unused 3:1 - unused reset: 0 h imwua 0 w mask interrupt on "wake-up" for configuration a 0 b interrupt enabled 1 b interrupt disabled reset: 0 h im1 offset reset value interrupt mask register 1 095 h 00 h field bits type description unused 7:5 - unused reset: 0 h imwud 4 w mask interrupt on "wake-up" for configuration d 0 b interrupt enabled 1 b interrupt disabled reset: 0 h unused 3:1 - unused reset: 0 h imwuc 0 w mask interrupt on "wake-up" for configuration c 0 b interrupt enabled 1 b interrupt disabled reset: 0 h spmap offset reset value self polling mode active periods register 096 h 01 h field bits type description 8186(' z ,0:8' 8186(' z ,0:8& 8186(' z 630$3
TDA5225 appendix register description data sheet 158 v1.0, 2010-02-19 self polling mode idle periods register self polling mode control register field bits type description unused 7:5 - unused reset: 0 h spmap 4:0 w self polling mode active periods value min: 01h = 1 (master) period max: 1fh = 31(master) periods reg. value 00h = 32 (master) periods reset: 01 h spmip offset reset value self polling mode idle periods register 097 h 01 h field bits type description spmip 7:0 w self polling mode idle periods value min: 01h = 1 (master) period max: ffh = 255 (master) periods reg. value 00h = 256 (master) periods reset: 01 h spmc offset reset value self polling mode control register 098 h 00 h field bits type description unused 7:3 - unused reset: 00 h z 630,3 8186(' z 630$,(1 z 8186('
TDA5225 appendix register description data sheet 159 v1.0, 2010-02-19 self polling mode reference timer register self polling mode off time register 0 spmaien 2 w self polling mode active idle enable 0 b disabled 1 b enabled reset: 0 h unused 1:0 w unused reset: 0 h spmrt offset reset value self polling mode reference timer register 099 h 01 h field bits type description spmrt 7:0 w self polling mode reference timer value the output of this timer is used as input for the on/off timer incoming periodic time = 64 / fsys output periodic time = trt = (64 * spmrt) / fsys min: 01h = (64*1) / fsys max: 00h = (64 * 256) / fsys reset: 01 h spmofft0 offset reset value self polling mode off time register 0 09a h 01 h field bits type description z 63057 z 6302))7
TDA5225 appendix register description data sheet 160 v1.0, 2010-02-19 self polling mode off time register 1 self polling mode on time config a register 0 field bits type description spmofft0 7:0 w self polling mode off time value: spmofft(13:0) = spmofft1(msb) & spmofft0(lsb) off -time = trt * spmofft min: 0001h = 1 * trt reg.value 3fffh = 16383 * trt max: 0000h = 16384 * trt reset: 01 h spmofft1 offset reset value self polling mode off time register 1 09b h 00 h field bits type description unused 7:6 - unused reset: 0 h spmofft1 5:0 w self polling mode off time value: spmofft(13:0) = spmofft1(msb) & spmofft0(lsb) off -time = trt * spmofft min: 0001h = 1 * trt reg.value 3fffh = 16383 * trt max: 0000h = 16384 * trt reset: 00 h spmonta0 offset reset value self polling mode on time config a register 0 09c h 01 h 8186(' z 6302))7 z 630217$
TDA5225 appendix register description data sheet 161 v1.0, 2010-02-19 self polling mode on time config a register 1 self polling mode on time config b register 0 field bits type description spmonta0 7:0 w set value self polling mode on time: spmonta(13:0) = spmonta1(msb) & spmonta0(lsb) on-time = trt *spmonta min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmonta1 offset reset value self polling mode on time config a register 1 09d h 00 h field bits type description unused 7:6 - unused reset: 0 h spmonta1 5:0 w set value self polling mode on time: spmonta(13:0) = spmonta1(msb) & spmonta0(lsb) on-time = trt *spmonta min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h spmontb0 offset reset value self polling mode on time config b register 0 09e h 01 h 8186(' z 630217$ z 630217%
TDA5225 appendix register description data sheet 162 v1.0, 2010-02-19 self polling mode on time config b register 1 self polling mode on time config c register 0 field bits type description spmontb0 7:0 w set value self polling mode on time: spmontb(13:0) = spmontb1(msb) & spmontb0(lsb) on-time = trt *spmontb min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmontb1 offset reset value self polling mode on time config b register 1 09f h 00 h field bits type description unused 7:6 - unused reset: 0 h spmontb1 5:0 w set value self polling mode on time: spmontb(13:0) = spmontb1(msb) & spmontb0(lsb) on-time = trt *spmontb min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h spmontc0 offset reset value self polling mode on time config c register 0 0a0 h 01 h 8186(' z 630217% z 630217&
TDA5225 appendix register description data sheet 163 v1.0, 2010-02-19 self polling mode on time config c register 1 self polling mode on time config d register 0 field bits type description spmontc0 7:0 w set value self polling mode on time: spmontc(13:0) = spmontc1(msb) & spmontc0(lsb) on-time = trt *spmontc min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmontc1 offset reset value self polling mode on time config c register 1 0a1 h 00 h field bits type description unused 7:6 - unused reset: 0 h spmontc1 5:0 w set value self polling mode on time: spmontc(13:0) = spmontc1(msb) & spmontc0(lsb) on-time = trt *spmontc min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h spmontd0 offset reset value self polling mode on time config d register 0 0a2 h 01 h 8186(' z 630217& z 630217'
TDA5225 appendix register description data sheet 164 v1.0, 2010-02-19 self polling mode on time config d register 1 external processing command register field bits type description spmontd0 7:0 w set value self polling mode on time: spmontd(13:0) = spmontd1(msb) & spmontd0(lsb) on-time = trt *spmontd min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 01 h spmontd1 offset reset value self polling mode on time config d register 1 0a3 h 00 h field bits type description unused 7:6 - unused reset: 0 h spmontd1 5:0 w set value self polling mode on time: spmontd(13:0) = spmontd1(msb) & spmontd0(lsb) on-time = trt *spmontd min: 0001h = 1*trt reg.value: 3fffh = 16383*trt max: 0000h = 16384*trt reset: 00 h extpcmd offset reset value external processing command register 0a4 h 00 h 8186(' z 630217' 5hv 8186(' zf $*&0$1) zf $)&0$1) zf (;7727, 0 zf (;7(20
TDA5225 appendix register description data sheet 165 v1.0, 2010-02-19 chip mode control register 1 field bits type description unused 6:4 - unused reset: 0 h agcmanf 3 wc agc manual freeze when *_agcsfcfg.agcfreeze set to spi command, this bit sets the agc to freeze mode 0 b inactive 1 b active reset: 0 h afcmanf 2 wc afc manual freeze when *_afcsfcfg.afcfreeze set to spi command, this bit sets the afc to freeze mode 0 b inactive 1 b active reset: 0 h exttotim 1 wc force totim signal 0 b no external totim signal forced 1 b external totim signal forced reset: 0 h exteom 0 wc force eom signal 0 b no external eom signal forced 1 b external eom signal forced reset: 0 h cmc1 offset reset value chip mode control register 1 0a5 h 04 h field bits type description unused 7:6 - unused reset: 0 h eom2ncfg 5 w continue with next configuration in self polling mode after eom detected in run mode self polling 0 b continue with configuration a in self polling mode 1 b continue with next configuration in self polling mode reset: 0 h 8186(' z (201&) * z 727,01 &+ z 8186(' z ;7$/+30 6
TDA5225 appendix register description data sheet 166 v1.0, 2010-02-19 chip mode control register 0 totim2nch 4 w continue with next rf channel in self polling mode after totim detected in run mode self polling . in case of single rf channel application this means "continue wi th next configuration" instead of "continue with next rf channel". 0 b continue with configuration a in self polling mode 1 b continue with next rf channel in self polling mode reset: 0 h unused 3:1 w unused reset: 2 h xtalhpms 0 w xtal high precision mode in sleep mode 0 b disabled 1 b enabled reset: 0 h cmc0 offset reset value chip mode control register 0 0a6 h 10 h field bits type description sdohppen 7 w sdo high power pad enable 0 b normal 1 b high power reset: 0 h initpllhold 6 w init pll after coming from hold (when new channel programmed). this requires an additional channel hop time before initialization of the digital receiver. 0 b no init of pll 1 b init of pll reset: 0 h hold 5 w holds the chip in the register configuration state (only in run mode slave) 0 b normal operation 1 b jump into the register config state hold reset: 0 h clkouten 4 w clk_out enable 0 b disabled 1 b enable programmable clock output reset: 1 h field bits type description z 6'2+33( 1 z ,1,73// +2/' z +2/' z &/.287( 1 z 0&6 z 6/5;(1 z 06(/
TDA5225 appendix register description data sheet 167 v1.0, 2010-02-19 wakeup peak detector readout register interrupt status register 0 mcs 3:2 w multi configuration selection (run mode slave / self polling mode) 00 b config a / config a 01 b config b / config a + b 10 b config c / config a + b + c 11 b config d / config a + b + c + d reset: 0 h slrxen 1 w slave receiver enable this bit is only used in operating mode run mode slave / sleep mode 0 b receiver is in sleep mode 1 b receiver is in run mode slave reset: 0 h msel 0 w operating mode selection 0 b run mode slave / sleep mode 1 b self polling mode reset: 0 h rssipwu offset reset value wakeup peak detector readout register 0a7 h 00 h field bits type description rssipwu 7:0 r peak detector level at wakeup set at every wu event and also set at the end of every configuration/channel cycle within a self polling period. cleared at reset only. reset: 00 h is0 offset reset value interrupt status register 0 0a8 h ff h field bits type description u 566,3:8 uf 8186(' uf :8% uf 8186(' uf :8$
TDA5225 appendix register description data sheet 168 v1.0, 2010-02-19 interrupt status register 1 field bits type description unused 7:5 rc unused reset: 7 h wub 4 rc interrupt request by "wake up" from configuration b (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h unused 3:1 rc unused reset: 7 h wua 0 rc interrupt request by "wake up" from configuration a (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h is1 offset reset value interrupt status register 1 0a9 h ff h field bits type description unused 7:5 rc unused reset: 7 h wud 4 rc interrupt request by "wake up" from configuration d (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h unused 3:1 rc unused reset: 7 h wuc 0 rc interrupt request by "wake up" from configuration c (reset event sets all bits to 1) 0 b not detected 1 b detected reset: 1 h uf 8186(' uf :8' uf 8186(' uf :8&
TDA5225 appendix register description data sheet 169 v1.0, 2010-02-19 rf pll actual channel and configuration register rssi peak detector readout register rfpllacc offset reset value rf pll actual channel and configuration register 0aa h 00 h field bits type description unused 7:6 r unused reset: 0 h rmspacfg 5:4 r rf pll run mode self polling actual configuration 00 b configuration a 01 b configuration b 10 b configuration c 11 b configuration d reset: 0 h unused 3:2 r unused reset: 0 h spmac 1:0 r rf pll self polling mode actual channel 00 b no wake up from any channel was actually found 01 b wake up was found from channel 1 10 b wake up was found from channel 2 11 b wake up was found from channel 3 reset: 0 h rssiprx offset reset value rssi peak detector readout register 0ab h 00 h u 8186(' u 5063$&)* u 8186(' u 630$& uf 566,35;
TDA5225 appendix register description data sheet 170 v1.0, 2010-02-19 adc result high byte register adc result low byte register field bits type description rssiprx 7:0 rc rssi peak level during receiving tracking is active when digital receiver is enabled set at higher peak levels than stored cleared at reset and spi read out reset: 00 h adcresh offset reset value adc result high byte register 0ae h 00 h field bits type description adcresh 7:0 rc adc result value adcres(9:0) = adcresh(7:0) & adcresl(1:0) note: rc for control signal generation only, no clear reset: 00 h adcresl offset reset value adc result low byte register 0af h 00 h field bits type description unused 7:3 - unused reset: 00 h adceoc 2 r adc end of conversion detected 0 b not detected 1 b detected reset: 0 h uf $'&5(6+ 8186(' u $'&(2& u $'&5(6/
TDA5225 appendix register description data sheet 171 v1.0, 2010-02-19 vco autocalibration result readout register afc offset read register adcresl 1:0 r adc result value adcres(9:0) = adcresh(7:0) & adcresl(1:0) the 2 lsbs of the adc result are captured when the sfr register adcresh is readout. reset: 0 h vacres offset reset value vco autocalibration result readout register 0b0 h 00 h field bits type description unused 7:5 - unused reset: 0 h vacres 3:0 r vco autocalibration result returns the vco range selected by vco autocalibration reset: 0 h afcoffset offset reset value afc offset read register 0b1 h 00 h field bits type description afcoffs 7:0 r readout of the frequency offset found by afc (afc loop filter output). value is in signed representation. frequency resolution is 2.68 khz/digit output can be limited by x_afclimit register update rate is 548 khz reset: 00 h field bits type description 8186(' 5hv u 9$&5(6 u $)&2))6
TDA5225 appendix register description data sheet 172 v1.0, 2010-02-19 agc gain readout register spi address tracer register spi data tracer register agcgainr offset reset value agc gain readout register 0b2 h 00 h field bits type description unused 7:3 - unused reset: 00 h if2gain 2:1 r agc if2 gain readout 00 b 0 db 01 b -15 db 10 b -30 db 11 b n.u. reset: 0 h mix2gain 0 r agc mix2 gain readout 0 b 0 db 1 b -15 db reset: 0 h spiat offset reset value spi address tracer register 0b3 h 00 h field bits type description spiat 7:0 r spi address tracer, readout of the last address of a sfr register written by spi reset: 00 h 8186(' u ,)*$,1 u 0,;*$, 1 u 63,$7
TDA5225 appendix register description data sheet 173 v1.0, 2010-02-19 spi checksum register serial number register 0 spidt offset reset value spi data tracer register 0b4 h 00 h field bits type description spidt 7:0 r spi data tracer, readout of the last written data to a sfr register by spi reset: 00 h spichksum offset reset value spi checksum register 0b5 h 00 h field bits type description spichksum 7:0 rc spi checksum readout reset: 00 h sn0 offset reset value serial number register 0 0b6 h 00 h u 63,'7 uf 63,&+.680 u 61
TDA5225 appendix register description data sheet 174 v1.0, 2010-02-19 serial number register 1 serial number register 2 serial number register 3 field bits type description sn0 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn1 offset reset value serial number register 1 0b7 h 00 h field bits type description sn1 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn2 offset reset value serial number register 2 0b8 h 00 h field bits type description sn2 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h sn3 offset reset value serial number register 3 0b9 h 00 h u 61 u 61
TDA5225 appendix register description data sheet 175 v1.0, 2010-02-19 rssi readout register rssi peak memory filter readout register field bits type description sn3 7:0 r serial number: sn(31:0) = sn 3(msb) & sn2 & sn1 & sn0(lsb) reset: 00 h rssirx offset reset value rssi readout register 0ba h 00 h field bits type description rssirx 7:0 r rssi value after averaging over 4 samples reset: 00 h rssipmf offset reset value rssi peak memory filter readout register 0bb h 00 h field bits type description rssipmf 7:0 r rssi peak memory filter level reset: 00 h u 61 u 566,5; u 566,30)
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