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r19ds0069ej0105 rev. 1.05 page 1 of 39 dec 16, 2016 datasheet TPS-1 single chip interface solution for profinet io devices description the TPS-1 is a single-chip profinet interface component integrating a cpu, a 2-port switch supporting latest profinet specifications, the ethernet phys and peripheral modules to interface to the application layer of any application building a profinet io device. the internal structure is designed to fulfill the requirements of the irt protocol. the integrated components realize the complete interface functionality. TPS-1 rounds off the basic technology range of profinet specifically for compact devices, and complies with profinet specification 2.3. detailed functions are described in the following user ?s manual. be sure to read this manual when you design your systems. TPS-1 user?s manual: hardware (r19uh0081ed) features ? applications ? industrial drives ? compact and modular remote i/os ? product features ? integrated profinet io cpu ? compliant with conformance class c ? 2 ethernet ports, 100 mbps, full duplex ? 2 integrated phys with an auto negotiation, auto crossover ? integrated irt switch, 8 priority levels ? support rj45 or fiber optic interfaces ? fiber optic diagnosis via i 2 c interface per port ? irt bridge-delay < 3 s ? hardware support for profinet protocols including ptcp and lldp ? versatile host interface for serial or parallel conn ection of external cpus or local inputs/outputs ? small package(15 x 15 mm),1mm ball pitch ? application interface the TPS-1 provid es 48 general purpose i/o (gpi o) pins that you ca n individually configure according to your specific application requirements. ? 48 gpio for digital i/os ? 8- or 16-bit parallel host interface ? serial host interface (spi slave) ? 5gpio for internal signals (e.g. leds) ? serial flash interface the TPS-1 interfaces to an application cpu via the in ternal shared memory either through the fast spi slave interface or through the 8- or 16-bit parallel port. ordering information part no. application package mc-10105f1-821-fna-m1-a TPS-1 profinet io device fpbga 196 pins 15 x 15 mm the information in this document is subject to change without notice. before using this document, please confirm that this is t he latest version. not all products and/or types are available in every country. pl ease check with our sales representative for availability and a dditional information. r19ds0069ej0105 rev.1.05 dec 16, 2016
TPS-1 internal block diagram r19ds0069ej0105 rev. 1.05 page 2 of 39 dec 16, 2016 internal block diagram the block diagram shows the internal structure and main components of the TPS-1. the additional serial boot flash component , the oscillator and the physical adapta tion for the ethernet interfaces are not listed.
TPS-1 pin identification r19ds0069ej0105 rev. 1.05 page 3 of 39 dec 16, 2016 pin identification spi master for boot flash rom cs_flash_out : fw flash: chip select spi3_sclk_out : fw flash: clock spi3_srxd_in : fw flash: receive data ? miso spi3_stxd_out : fw flas h: send data ? mosi synchronisation signals test_sync : clock signal for certification t(6:1) : clock signals(6:1) (isochronous mode, irt) led signals device status profinet io led_bf_out : control led ?bus failure? led_sf_out : control led ?system fail? led_ready_out : control led ?device ready? led_mt_out : control led ?maintenance? phy port 1 and 2 i2c_(2:1)_d_inout : fo i 2 c-bus ?data? sclk_(2:1)_inout :fo i 2 c-bus ?clock? link_phy(2:1) : ethernet link indication (up or down) act_phy(2:1) : activity ethernet p(2:1)_tx_p : ethernet transmit data (positive) p(2:1)_tx_n : ethernet transmit data (negative) p(2:1)_rx_p : ethernet receive data (positive) p(2:1)_rx_n : ethernet receive data (negative) p(2:1)_sd_p : fo signal detect (positive) p(2:1)_sd_n : fo signal detect (negative) p(2:1)_rd_p : fo receive data (positive) p(2:1)_rd_n : fo receive data (negative) p(2:1)_td_out_p : fo tr ansmit data (negative) p(2:1)_td_out_n : fo transmit data (positive) p(2:1)_fx_en_out : fo transmitter enable (active high) oscillator xclk1 :connection external oscillator (1) in, 25 mhz xclk2 :connection external oscillator (2) out, 25 mhz jtag ? interface tm(1:0) : test input (1:0) trstn : test reset tms : test mode select tdo : test data output tck : test clock tdi : test data input reset / test resetn : TPS-1 reset (global reset) atp : test pin for production test (n.c.) extres : external reference resistor tmc(2:1) : test mode control(2:1) (production test) test_(2:1)_in : test pin (2:1) for hw test of TPS-1 testdout(7:5) : test data output (7:5) (high speed signals for phy) host interface wd_in : watchdog input (from the host) wd_out : watchdog output (to the host) int_out : interrupt output (to the host) boot interface (serial) uart6_tx : boot uart ?transmit data? uart6_rx : boot uart ?receive data? boot_1 : forced boot
TPS-1 pin identification r19ds0069ej0105 rev. 1.05 page 4 of 39 dec 16, 2016 test signals for switching regulator test(3:1) : test pin switching regulator (in combination with another test pins) phy supply voltages vdd33esd : analog test supply, 3.3 v vddq_pecl_b(2:1) : pecl buffer power supply 3.3 v (port(2:1)) p(2:1)vddarxtx : analog rx/tx power supply 1.5 v ? port (2:1) vddacb : analog central power supply 3.3 v vssapllcb : analog central gnd vddapll : analog central power supply 1.5 v pins for core pll power supply pll_agnd : pll analog gnd (core pll) pll_avdd : pll analog 1.0 v (core pll) pins for switching regulator bvdd : supply voltage for the switching regulator (3.3 v supply for the switching transistor) bgnd : gnd for switching regulator (please place bypass capacitor between analog power supply and gnd). avdd_reg : analog vdd for regulator (3.3 v supply),smoothed voltage to feed the internal por. agnd_reg : analog gnd switching regulator lx : 1.5 v output of the internal switching regulator fb : feedback (regulator) configurable gpios gpio_(47:0) :gpio pins alternate use of the gpios lbu_wr_en_in : write enable lbu_read_en_in : read enable lbu_cs_in : chip select lbu_be_(2:1)_in : byte selection (1:low,2:high) lbu_ready_out : ready signal TPS-1 lbu_data(15:0) : data bits lbu_a(13:0)_in : address bits lbu_seg(1:0)_in : segment select (2:1) host_reset_in : reset host spi interface host_sfrn_in : start new spi transfer host_srxd_in : spi receive data host_sclk_in : spi clock host_stxd_out : spi transmit data host_shdr_out : h eader recognized local_sclk_out : spi clock local_sfrm_out : spi chip select local_srxd_in : spi receive data local_stxd_out : spi transmit data
TPS-1 pin configuration r19ds0069ej0105 rev. 1.05 page 5 of 39 dec 16, 2016 pin configuration 196-pin plastic bga(15x15)
TPS-1 pin configuration r19ds0069ej0105 rev. 1.05 page 6 of 39 dec 16, 2016 pin designation pin designation pin designation pin designation a1 gnd d8 testdout5 h1 lx l8 testdout7 a2 vdd15 d9 testdout6 h2 vdd33 l9 pll_agnd a3 gpio_7 d10 act_phy1 h3 test1 l10 pll_avdd a4 gpio_4 d11 t6 h4 gpio_26 l11 sclk_2_inout a5 p1_fx_en_out d12 agnd h5 gpio_25 l12 agnd a6 p1_td_out_n d13 agnd h6 gnd l13 agnd a7 vdd15 d14 p1vddarxt x h7 gnd l14 p2vddarxtx a8 p1_sd_n e1 test3 h8 gnd m1 gpio_36 a9 p1_rd_n e2 gpio_16 h9 gnd m2 gpio_35 a10 act_phy2 e3 gpio_17 h10 gnd m3 gpio_37 a11 wd_in e4 gpio_18 h11 t2 m4 gpio_42 a12 resetn e5 gpio_19 h12 atp m5 gpio_45 a13 vdd15 e6 vdd10 h13 extres m6 gpio_46 a14 gnd e7 vdd10 h14 vddacb m7 gpio_47 b1 vdd33 e8 vdd10 j1 bvdd m8 vddq_pecl_b2 b2 gpio_9 e9 vdd10 j2 gnd m9 vdd15 b3 gpio_8 e10 tmc1 j3 gpio_28 m10 gnd b4 gpio_5 e11 t5 j4 gpio_27 m11 i2c_2_d_inout b5 gpio_1 e12 vdd33esd j5 tck m12 cs_flash_out b6 p1_td_out_p e13 p1_rx_ p j6 gnd m13 spi3_srxd_in b7 gnd e14 p1_rx_n j7 gnd m14 spi3_stxd_out b8 p1_sd_p f1 fb j8 gnd n1 vdd33 b9 p1_rd_p f2 avdd_reg j9 gnd n2 gpio_40 b10 led_mt_out f3 gpio_22 j10 tm1 n3 gpio_39 b11 led_sf_out f4 gpio_21 j11 t1 n4 gpio_41 b12 wd_out f5 gpio_20 j12 gnd n5 gpio_44 b13 led_bf_out f6 vdd33 j13 p2_tx_p n6 p2_td_out_p b14 vdd33 f7 gnd j14 p2_tx_n n7 gnd c1 gpio_12 f8 gnd k1 vdd15 n8 p2_sd_p c2 gpio_13 f9 gnd k2 gpio_31 n9 p2_rd_p c3 gpio_6 f10 vdd33 k3 gpio_29 n10 gnd c4 gpio_3 f11 t4 k4 gpio_30 n11 xclk1 c5 gpio_2 f12 vdd15 k5 trstn n12 test_sync c6 sclk_1_inout f13 p1_tx_p k6 vdd10 n13 spi3_sclk_out c7 vdd33 f14 p1_tx_n k7 vdd10 n14 vdd33 c8 vddq_pecl_b1 g1 bgnd k8 vdd10 p1 gnd c9 i2c_1_d_inout g2 agnd_reg k9 vdd10 p2 vdd15 c10 led_ready_out g3 test2 k10 tmc2 p3 gpio_38 c11 link_phy2 g4 gpio_24 k11 int_out p4 gpio_43 c12 link_phy1 g5 gpio_23 k12 vdd15 p5 p2_fx_en_out c13 uart6_rx g6 gnd k13 p2_rx_p p6 p2_td_out_n c14 uart6_tx g7 gnd k14 p2_rx_n p7 vdd33 d1 gpio_15 g8 gnd l1 gpio_34 p8 p2_sd_n d2 gpio_14 g9 gnd l2 gpio_32 p9 p2_rd_n d3 gpio_10 g10 gnd l3 gpio_33 p10 vdd33 d4 gpio_11 g11 t3 l4 tm0 p11 xclk2 d5 gpio_0 g12 gnd l5 tdi p12 boot_1 d6 test_1_in g13 vssapllcb l6 tms p13 vdd15 d7 test_2_in g14 vddapll l7 tdo p14 gnd
TPS-1 table of contents r19ds0069ej0105 rev. 1.05 page 7 of 39 dec 16, 2016 table of contents ? 1. ? pin functions ................................................................................................................. ... 10 ? 1.1. ? list of pin functions ......................................................................................................... 10 ? 1.1.1. ? host interface ?par allel inte rface ........................................................................ 10 ? 1.1.2. ? host interface ?spi slave interface ...................................................................... 10 ? 1.1.3. ? profinet io switch ......................................................................................... 11 ? 1.1.4. ? integrated peripherals........................................................................................... 12 ? 1.2. ? pin charact eristic s ........................................................................................................... . 16 ? 2. ? electrical spec ifications .................................................................................................... 20 ? 2.1. ? absolute maximum ratings ............................................................................................. 20 ? 2.2. ? operating c onditions ........................................................................................................ 2 1 ? 2.3. ? thermal charac teristic s .................................................................................................... 22 ? 2.4. ? ac charact eristics ............................................................................................................ 23 ? 2.4.1. ? clock timing ....................................................................................................... 23 ? 2.4.2. ? i/o timing spec ification ....................................................................................... 24 ? 2.4.2.1. ? jtag interface timing ......................................................................................... 25 ? 2.4.2.2. ? parallel host interface timing diag rams ............................................................... 26 ? 2.4.2.2.1. ? host read from TPS-1 with separate read/w rite line ......................................... 26 ? 2.4.2.2.2. ? host write to TPS-1 with se parate read/w rite line............................................. 27 ? 2.4.2.2.3. ? host read from TPS-1 with common read/write line ........................................ 28 ? 2.4.2.2.4. ? host write to TPS-1 with common read/write line ............................................ 29 ? 2.4.2.3 ? spi slave timing ................................................................................................ 30 ? 2.4.3. ? i2c-bus timing definition ................................................................................... 31 ? 2.4.3.1. ? phy dc specifications(100 base-tx) ............................................................ 32 ? 2.4.3.2. ? phy ac specificati ons (100bas e-tx) ............................................................ 33 ? 2.4.4. ? power-up sequence .............................................................................................. 34 ? 2.4.5. ? reset timing ......................................................................................................... 35 ? 3. ? package drawing .............................................................................................................. 36 ? 4. ? recommended solderin g conditi ons ................................................................................ 37 ? ?
TPS-1 list of figures r19ds0069ej0105 rev. 1.05 page 8 of 39 dec 16, 2016 list of figures figure 2-1: clock waveforms ................................................................................................... 23 figure 2-2: input setup and hold waveforms ............................................................................ 24 figure 2-3: output delay waveforms ........................................................................................ 24 figure 2-4: host read with separa te read/wr ite line .................................................................. 26 figure 2-5: host write with separa te read/write line ................................................................. 27 figure 2-6: host read with common read/write line ................................................................. 28 figure 2-7: host write with common read/write line ................................................................ 29 figure 2-8: spi slave timing .................................................................................................. .. 30 figure 2-9: i2c-bus timing definition ...................................................................................... 31 figure 2-10: phy dc speci fication ........................................................................................... 32 figure 2-11: phy ac speci fication ........................................................................................... 33 figure 2-12: power-up sequence timing diagram.................................................................... 34 figure 2-13: reset timing diagram ........................................................................................... 35 figure 3-1: 196-ball fpbga pack age drawing ....................................................................... 36
TPS-1 list of tables r19ds0069ej0105 rev. 1.05 page 9 of 39 dec 16, 2016 list of tables table 1-1: paralle l host in terface ........................................................................................... .. 10 table 1-2: spi host in terface ................................................................................................. .. 10 table1-3: status signals of the et hernet interface (por t 1/port2) .................................... 11 table 1-4: signal lines 100base-tx interface (port 1/port2) .................................................. 11 table 1-5: signal lines 100base-fx interface (port 1/port2) .................................................. 11 table1-6: additiona l TPS-1 pins ............................................................................................ 11 table 1-7: boot flash sp i master inte rface ............................................................................ 12 table 1-8: general purpos e i/o pin functions ......................................................................... 13 table 1-9: status le ds profinet io................................................................................... 14 table 1-10: i2c interface lines ............................................................................................... ... 14 table 1-11: boot uart lines ................................................................................................... . 14 table 1-12: watc hdog si gnals .................................................................................................. . 15 table 1-13: jtag interfa ce pin defi nition ................................................................................. 15 table 1-14: supply vo ltage circ uitry ....................................................................................... 15 table 1-15: signal character istics ............................................................................................ .. 16 table 2-1: absolute maximum ratings ................................................................................... 20 table 2-2: recommended operating co nditions (supply voltages) ........................................ 21 table 2-3: recommended operating cond itions (input / out put level) ................................... 21 table 2-4: TPS-1 power c onsumption overview ..................................................................... 21 table 2-5: thermal characteri stics of the package ................................................................. 22 table 2-6: clock ac characteris tics ....................................................................................... 23 table 2-7: timing jtag interface .......................................................................................... 25 table 2-8: host read with se parate read/wr ite line .................................................................. 26 table 2-9: host write with se parate read/wr ite line ................................................................. 27 table 2-10: host read with common read/write line ................................................................. 28 table 2-11: host write with common read/write line ................................................................ 29 table 2-12: spi slave timing .................................................................................................. . 30 table 2-13: characteristics of the scl and sda lines ............................................................. 31 table 2-14: phy dc specifica tion ........................................................................................... 32 table 2-15: phy ac timing .................................................................................................... 33 table 2-16: signals for power-up ............................................................................................. 34 table 2-17: signals for reset timing ........................................................................................ 3 5 table 4-1: recommended so ldering cond itions ...................................................................... 37
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 10 of 39 dec 16, 2016 1. pin functions 1.1. list of pin functions 1.1.1. host interface ?parallel interface table 1-1: parallel host interface pin name i/o function remarks alternate function lbu_wr_en_in i write control active low (intel mode) gpio_0 0:write; 1:read (motorola mode) lbu_read_en_in i read control active low (intel mode) gpio_1 no function (motorola mode) lbu_cs_in i chip select gpio_2 lbu_be_1_in i byte select 1 gpio_3 lbu_be_2_in i byte select 2 gpio_4 lbu_ready_out o ready signal polarity configurable gpio_5 lbu_data(15:0) i/o data line 0 ? 15 gpio_(21:6) lbu_a(13:0)_in i address lines 0 - 13 gpio_(35:22) lbu_seg0_in i low bit of the segment select page selection gpio_36 lbu_seg1_in i high bit of the segment select page selection gpio_37 1.1.2. host interface ?spi slave interface table 1-2: spi host interface pin name i/o function remarks alternate function host_reset_in i serial reset the spi slave interface can be reset by using this signal. (signal is active high) gpio_38 host_sfrn_in i serial frame the start of a new spi transfer is signaled. gpio_39 host_srxd_in i serial data input mosi (master out slave in) gpio_40 host_sclk_in i serial clock input serial clock driven by the spi master gpio_41 host_stxd_out o serial data output miso (master in slave out) gpio_42 host_shdr_out o serial header information header information available gpio_43
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 11 of 39 dec 16, 2016 1.1.3. profinet io switch table 1-3: status signals of th e ethernet interface (port 1/port2) pin name i/o function remarks link_phy(2:1) o link ethernet active high act_phy(2:1) o activity ethernet active high table 1-4: signal lines 100base-tx interface (port 1/port2) pin name i/o function remarks p(2:1)_tx_p o transmit data+ e.g. rj45 p(2:1)_tx_n o transmit data- e.g. rj45 p(2:1)_rx_p i receive data+ e.g. rj45 p(2:1)_rx_n i receive data- e.g. rj45 table 1-5: signal lines 100base-fx interface (port 1/port2) pin name i/o function remarks i2c_(2:1)_d_inout i/o i 2 c data line e.g. sc-rj sclk_(2:1)_inout o i 2 c clock line e.g. sc-rj p(2:1)_sd_p i signal detect (differential, +) e.g. sc-rj p(2:1)_sd_n i signal detect (differential, -) e.g. sc-rj p(2:1)_rd_n i receive signal (differential, -) e.g. sc-rj p(2:1)_rd_p i receive signal (differential, +) e.g. sc-rj p(2:1)_fx_en_out o transmitter enable (transceiver output) e.g. sc-rj p(2:1)_td_out_p o transmit signal (differential, +) e.g. sc-rj p(2:1)_td_out_n o transmit signal (differential, -) e.g. sc-rj table 1-6: additional TPS-1 pins pin name i/o function remarks atp ai/o (analog i/o) analog test: this signal is used for the manufacturing process. pin is left open. extres ai/o (analog i/o) reference resistor: connect via a resistor 12.4 k ? / 1% to gnd. this external resistor should be placed as close as possible to the chip. it must be terminated to analog gnd.
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 12 of 39 dec 16, 2016 1.1.4. integrated peripherals table 1-7: boot flash spi master interface pin name i/o function cs_flash_out o spi-master-interface firmware flash: chip select (TPS-1) ? active low spi3_sclk_out o spi-master-interface firmware flash: clock (TPS-1) spi3_srxd_in i spi-master-interface firmware flash: receive data (TPS-1) ? miso spi3_stxd_out o spi- master-interface firmware flash: send data (TPS-1) ? mosi
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 13 of 39 dec 16, 2016 table 1-8: general purpose i/o pin functions pin name i/o function alternate function gpio_0 i/o general purpose digital i/o signal / write enabl e lbu_wr_en_in gpio_1 i/o general purpose digital i/o signal / read enable lbu_read_en_in gpio_2 i/o general purpose digital i/o signal / chip select lbu_cs_in gpio_3 i/o general purpose digital i/o signa l / byte selection (low) lbu_be_1_in gpio_4 i/o general purpose digital i/o signa l / byte selection (high) lbu_be_2_in gpio_5 i/o general purpose digita l i/o signal / ready signal TPS-1 note2 lbu_ready_out gpio_6 i/o general purpose digita l i/o signal / data bit lbu_data0 gpio_7 i/o general purpose digita l i/o signal / data bit lbu_data1 gpio_8 i/o general purpose digita l i/o signal / data bit lbu_data2 gpio_9 i/o general purpose digita l i/o signal / data bit lbu_data3 gpio_10 i/o general purpose digita l i/o signal / data bit lbu_data4 gpio_11 i/o general purpose digita l i/o signal / data bit lbu_data5 gpio_12 i/o general purpose digita l i/o signal / data bit lbu_data6 gpio_13 i/o general purpose digita l i/o signal / data bit lbu_data7 gpio_14 i/o general purpose digita l i/o signal / data bit lbu_data8 gpio_15 i/o general purpose digita l i/o signal / data bit lbu_data9 gpio_16 i/o general purpose digita l i/o signal / data bit lbu_data10 gpio_17 i/o general purpose digita l i/o signal / data bit lbu_data11 gpio_18 i/o general purpose digita l i/o signal / data bit lbu_data12 gpio_19 i/o general purpose digita l i/o signal / data bit lbu_data13 gpio_20 i/o general purpose digita l i/o signal / data bit lbu_data14 gpio_21 i/o general purpose digita l i/o signal / data bit lbu_data15 gpio_22 i/o general purpose digital i/o signal / address bit lbu_a0_in gpio_23 i/o general purpose digital i/o signal / address bit lbu_a1_in gpio_24 i/o general purpose digital i/o signal / address bit lbu_a2_in gpio_25 i/o general purpose digital i/o signal / address bit lbu_a3_in gpio_26 i/o general purpose digital i/o signal / address bit lbu_a4_in gpio_27 i/o general purpose digital i/o signal / address bit lbu_a5_in gpio_28 i/o general purpose digital i/o signal / address bit lbu_a6_in gpio_29 i/o general purpose digital i/o signal / address bit lbu_a7_in gpio_30 i/o general purpose digital i/o signal / address bit lbu_a8_in gpio_31 i/o general purpose digital i/o signal / address bit lbu_a9_in gpio_32 i/o general purpose digital i/o signal / address bit lbu_a10_in gpio_33 i/o general purpose digital i/o signal / address bit lbu_a11_in gpio_34 i/o general purpose digital i/o signal / address bit lbu_a12_in gpio_35 i/o general purpose digital i/o signal / address bit lbu_a13_in gpio_36 i/o general purpose digital i/o si gnal / segment select 1 lbu_seg0_in gpio_37 i/o general purpose digital i/o si gnal / segment select 2 lbu_seg1_in gpio_38 i/o general purpose digital i/o signal / reset host spi inte rface host_reset_in gpio_39 i/o general purpose digital i/o signa l / start new spi transfer host_sfrn_in gpio_40 i/o general purpose digital i/o si gnal / spi receive data host_srxd_in gpio_41 i/o general purpose digital i/o signal / spi clock host_sclk_in gpio_42 i/o general purpose digital i/o si gnal / spi transmit data host_stxd_out gpio_43 i/o general purpose digital i/o si gnal / header recognized host_shdr_out gpio_44 i/o general purpose digital i/o signal / spi clock local_sclk_out gpio_45 i/o general purpose digital i/o signa l / start new spi transfer local_sfrm_out gpio_46 i/o general purpose digital i/o si gnal / spi receive data local_srxd_in gpio_47 i/o general purpose digital i/o si gnal / spi transmit data local_stxd_out notes: 1. you can only use one interface exclusively. it is not allowed to use e.g. the parallel and serial host interface at the same time.
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 14 of 39 dec 16, 2016 notes: 2 the signal ?lbu_ready_out? is designed to connect only to a single microcontroller. if you want to connect additional devices, you must add circuitr y to realize the high-impedance state. 3. if the cpu does not have a ready input for connecti on to lbu_ready_out, customers can choose a wait time of 80 ns (8 cpu cycles) during each transfer cycle. table 1-9: status leds profinet io pin name(led) color i/o state function led_bf_out red o bus communication (active low): on no link status available. flashing link status ok; no communication link to a profinet io- controller. off the profinet io-controller has an active communication link to this profinet io-device. led_sf_out red o system fail (active low): on profinet diagnostic exists. off no profinet diagnostic. led_mt_out yellow o maintenance required (active low): manufacturer specific ? depends on the ability of the device. led_ready_out green o device ready (active low): off TPS-1 has not started correctly. flashing TPS-1 is waiting for the synchronization of the host cpu (firmware start is complete). on TPS-1 has started correctly. table 1-10: i 2 c interface lines pin name i/o function i2c_(2:1)_d_inou t i/o fiber optic port(2:1) i 2 c-bus ?data? sclk_(2:1)_inout o fiber optic port(2:1) i 2 c-bus ?clock? table 1-11: boot uart lines pin name i/o function uart6_tx o boot uart ?transmit data? uart6_rx i boot uart ?receive data? boot_1 i forced boot value function 0x0 brom: boot from boot flash is enabled (normal operating mode). 0x1 uart: boot via uart is enabled. table 1-12: interrupt signals pin name i/o function remark int_out o interrupt output (to the host) interrupt to host can be generated by a configur- able set of internal TPS-1 events (active high).
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 15 of 39 dec 16, 2016 table 1-13: watchdog signals pin name i/o function remark wd_in i watchdog input (from the host) this signal triggers the TPS-1 watchdog that monitors the host cpu. a rising edge of this signal restarts the watchdog counter (active high). wd_out o watchdog output (to the host) this signal is set when a watchdog trigger of the TPS-1 occurs (active low). table 1-14: jtag interface pin definition pin name i/o function remark trstn i test reset jtag reset. inpu t: reset signal of the target port. external pull-down (4.7k ? to gnd) tms i test mode select jtag interf ace is activated from the debug unit. pull-up (4.7k ? to v dd ) tdo o test data output can be left open tck i test clock jtag clock signal to the t ps-1. it is recommended that this pin is set to a defined state on the target board. external pull-up (4.7k ? to v dd ) tdi i test data input external pull-up(4.7k ? to v dd ) table 1-15: supply voltage circuitry pin name function supply voltage generation p(2:1)vddarxtx analog port rx/tx po wer supply, 1.5 v (phy port 2:1) must be generated from vdd15 via a filter. vddapll analog central power supply, 1.5 v (phy) vddacb analog central power supply, 3.3 v (phy) must be generated from vdd33 via a filter. vdd33esd analog test power supply, 3.3 v (phy) vssapllcb analog central gnd (phy) must be generated from gnd core/io via a filter or connected to gnd core/io at the far end from TPS-1. vddq_pecl_b(2:1) pecl buffer power supply 3.3 v (port 1 and port 2) pll_agnd analog ground for the internal cpu clock generation pll_avdd power supply for the internal cpu clock generation (1.0v) gnd digital gnd agnd analog ground for phys vdd33 voltage supply 3.3 v (external) vdd15 voltage supply 1.5 v from switching regulator or external vdd10 voltage supply 1.0 v (external) agnd_reg analog ground for switching regulator. avdd_reg supply voltage for regulator(3.3v supply), smoothed voltage to feed the internal por. bgnd gnd for switching regulator please place bypass capacitor between analog power supply and gnd bvdd supply voltage for the switching regu lator (3.3v) for the switching transistor
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 16 of 39 dec 16, 2016 1.2. pin characteristics table 1-16: signal characteristics pin name i/o input type output type pull up / down pull up / down capacity load (pf) drive capability internal external i oh i ol spi-master for flash rom cs_flash_out o - 3.3v cmos - 30 6 ma 6 ma spi3_sclk_out o - 3.3v cmos - 30 6 ma 6 ma spi3_srxd_in i schmitt 3.3v cmos - - - - spi3_stxd_out o - 3.3v cmos - 30 6 ma 6 ma synchronization signals test_sync o - 3.3v cmos - 30 6 ma 6 ma t1 o - 3.3v cmos - 30 6 ma 6 ma t2 o - 3.3v cmos - 30 6 ma 6 ma t3 o - 3.3v cmos - 30 6 ma 6 ma t4 o - 3.3v cmos - 30 6 ma 6 ma t5 o - 3.3v cmos - 30 6 ma 6 ma t6 o - 3.3v cmos - 30 6 ma 6 ma led signals for profinet io status led_bf_out o - 3.3v cmos - 30 6 ma 6 ma led_sf_out o - 3.3v cmos - 30 6 ma 6 ma led_ready_out o - 3.3v cmos - 30 6 ma 6 ma led_mt_out o - 3.3v cmos 30 6 ma 6 ma phy port 1 i2c_1_d_inout i/o schmitt 3.3v cmos - 30 6 ma 6 ma sclk_1_inout i/o schmitt 3.3v cmos - 30 6 ma 6 ma link_phy1 o - 3.3v cmos - 30 6 ma 6 ma act_phy1 o - 3.3v cmos - 30 6 ma 6 ma p1_tx_p o - analog - - - - p1_tx_n o - analog - - - - p1_rx_p i - analog - - - - p1_rx_n i - analog - - - - p1_sd_p i pecl - - - - - p1_sd_n i pecl - - - - - p1_rd_p i pecl - - - - - p1_rd_n i pecl - - - - - p1_td_out_p o - 3.3v cmos - - 12 ma 12 ma p1_td_out_n o - 3.3v cmos - - 12 ma 12 ma p1_fx_en_out o - 3.3v cmos - 30 12 ma 12 ma phy port 2 i2c_2_d_inout i/o schmitt 3.3v cmos - 30 6 ma 6 ma sclk_2_inout i/o schmitt 3.3v cmos - 30 6 ma 6 ma link_phy2 o - 3.3v cmos - 30 6 ma 6 ma act_phy2 o - 3.3v cmos - 30 6 ma 6 ma p2_tx_p o - analog - - - - p2_tx_n o - analog - - - - p2_rx_p i - analog - - - - p2_rx_n i - analog - - - - p2_sd_p i pecl - - - - - p2_sd_n i pecl - - - - - p2_rd_p i pecl - - - - - p2_rd_n i pecl - - - - - p2_td_out_p o - 3.3v cmos - - 12 ma 12 ma
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 17 of 39 dec 16, 2016 pin name i/o input type output type pull up / down pull up / down capacity load (pf) drive capability internal external i oh i ol p2_td_out_n o - 3.3v cmos - - 12 ma 12 ma p2_fx_en_out o - 3.3v cmos - 30 12 ma 12 ma oscillator xclk1 i osc. in - - - - - xclk2 o osc. out - - 25 6 ma 6 ma jtag ? interface tm0 i schmitt pull-up 50 k ? pull-down 1 k ? - - - tm1 i schmitt - pull-down 1 k ? - - - trstn i schmitt 3.3v cmos - pull-down 4.7 k ? - - - tms i schmitt 3.3v cmos - pull-up 4.7 k ? - - - tdo o - 3.3v cmos - - 30 6 ma 6 ma tck i schmitt 3.3v cmos - pull-up 4.7 k ? - - - tdi i schmitt 3.3v cmos pull-up 4.7 k ? - - - reset / test resetn i schmitt 3.3v cmos - - - - atp io - - - - - extres io analog - - - - - tmc1 i 3.3v cmos pull-down (50 k ? ) - - - tmc2 i 3.3v cmos pull-down (l 50 k ? ) - - - test_1_in i schmitt 3.3v cmos pull-down (50 k ? ) - - - test_2_in i schmitt 3.3v cmos pull-down ( 50 k ? ) - - - testdout5 o 3.3v cmos - - 12 ma 12 ma testdout6 o 3.3v cmos - - 12 ma 12 ma testdout7 o 3.3v cmos - - 12 ma 12 ma host interface wd_in i schmitt 3.3v cmos - - - - wd_out o - 3.3v cmos - 30 6 ma 6 ma int_out o - 3.3v cmos - 30 6 ma 6 ma boot interface (serial) uart6_tx o - 3.3v cmos - 30 6 ma 6 ma uart6_rx i schmitt 3.3v cmos - - 6 ma 6 ma boot_1 i schmitt - pull-down (50 k ? ) - - - test signals ? switching regulator test1 i - - - see note 1 - - - test2 i - - - see note 1 - - - test3 i - - - see note 1 - - - power supplies gnd - - - - - - - vdd33 - - - - - - -
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 18 of 39 dec 16, 2016 pin name i/o input type output type pull up / down pull up / down capacity load (pf) drive capability internal external i oh i ol vdd15 - - - - - - - vdd10 - - - - - - - vdd33esd - - - - - - - vddapll - - - - - - - vddacb - - - - - - - vddq_pecl_b1 i - - - - - - vddq_pecl_b2 i - - - - - - p1vddarxtx i - - - - - - p2vddarxtx i - - - - - - vssapllcb - - - - - - - lx o - - - - - - fb (1.5v analog) i - - - - - - avdd_reg i - - - - - - bgnd - - - - - - - agnd_reg - - - - - - - bvdd - - - - - - - pll_agnd i - - - - - - pll_avdd i - - - - - - gpios gpio_00 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6ma gpio_01 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6ma gpio_02 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6ma gpio_03 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6ma gpio_04 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6ma gpio_05 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_06 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_07 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_08 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_09 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_10 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_11 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_12 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_13 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_14 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_15 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_16 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_17 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_18 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_19 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_20 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_21 i/o schmitt 3.3v cmos - see note 2 50 9 ma 9 ma gpio_22 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_23 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_24 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_25 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_26 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_27 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_28 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_29 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma
TPS-1 1. pin functions r19ds0069ej0105 rev. 1.05 page 19 of 39 dec 16, 2016 pin name i/o input type output type pull up / down pull up / down capacity load (pf) drive capability internal external i oh i ol gpio_30 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_31 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_32 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_33 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_34 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_35 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_36 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_37 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_38 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_39 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_40 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_41 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_42 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_43 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_44 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_45 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_46 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma gpio_47 i/o schmitt 3.3v cmos - see note 2 30 6 ma 6 ma note 1: these pins (test(3:1)) must not be left open. fo r the required connection please consult the TPS-1 user manual. note 2: the gpio pins gpio_00 to gpio_47 can be configured as diagnosis input lines (local io mode). the gpio pins are configured into groups of 8 bit. unused diagnosis inpu ts must have a pull-down or pull-up resistor (depending on customer?s design). a missing terminat ion can cause undefined diagnosis. note 3: generally unused gpio pins should be pulled up (10 k ? to vdd33). from profinet stack version v1.4 onwards all unused gpios should be left open, because the stack will configure them to outputs. this does not apply to pins handled in note 2. abbreviations: i input o output i/o input/output
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 20 of 39 dec 16, 2016 2. electrical specifications 2.1. absolute maximum ratings table 2-1: absolute maximum ratings parameter symbol rating unit power supply for core v dd10 -0.5 to +1.4 v power supply for io vdd33 -0.5 to +4.6 v power supply for phys v dd15 -0.5 to +2.0 v analog power supply for pll pll_avdd -0.5 to +1.4 v analog central 3.3v supply for phys vddacb -0.5 to +4.6 v analog central 1.5v supply for phys vddapll -0.5 to +2.0 v analog rx/tx port power supply p(2:1)vddarxtx -0.5 to +2.0 v pecl buffer power supply phy 1 v ddq_pecl_b1 -0.5 to +4.6 v pecl buffer power supply phy 2 v ddq_pecl_b2 -0.5 to +4.6 v analog test supply vdd33 esd -0.5 to +4.6 v input voltage 3.3v cmos v i < vdd + 0.5v v i -0.5 to +4.6 v operating temperature t j -40 to + 125 0 c storage temperature t stg -65 to + 150 0 c caution: product quality may suffer if the absolute maximu m rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditio ns that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation.
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 21 of 39 dec 16, 2016 2.2. operating conditions table 2-2: recommended operating conditions (supply voltages) parameter symbol min. typ. max. unit power supply for core (digital) vdd10 0.9 1.0 1.1 v power supply for io (digital) vdd33 3.0 3.3 3.6 v power supply for phys (digital) vdd15 1.35 1.5 1.65 v analog power supply for phys avdd_reg 3.0 3.3 3.6 v analog central 3.3v supply for phys vddacb 3.0 3.3 3.6 v analog central 1.5v supply for phys vddapll 1.35 1.5 1.65 v pecl buffer power supply phy 1 vddq_pecl_b1 3.0 3.3 3.6 v pecl buffer power supply phy 2 vddq_pecl_b2 3.0 3.3 3.6 v analog test supply vdd33esd 3.0 3.3 3.6 v analog power supply for pll pll_avdd 0.9 1.0 1.1 v ambient temperature t a -40 +85 0 c table 2-3: recommended operating conditions (input / output level) parameter symbol test conditions min. typ. max. unit output voltage high 3.3v cmos v oh i oh = 0 ma vdd33 ? 0.1v v nominal output current 2.4 v output voltage low 3.3v cmos v ol i ol = 0 ma 0.1 v nominal output current 0.4 v input voltage high 3.3v cmos v ih 2 vdd33 v 3.3v pecl difference to vddq_pecl_b(2:1) -0.880 1.165 v input voltage low 3.3v cmos v il 0 0.8 v 3.3v pecl difference to vddq_pecl_b(2:1) -1.474 -1.880 v positive trigger voltage 3.3v buffer v p 1.2 2.4 v negative trigger voltage 3.3v buffer v n 0.6 1.8 v hysteresis voltage 3.3v buffer v h 0.3 1.5 v table 2-4: TPS-1 power consumption overview parameter min. typ. max. unit power consumption 1.0 v 300 mw 1.5v 240 mw 3.3v 363 mw total: 800 note 903 mw note: the power consumption of the TPS-1 is approx. 800mw (average).
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 22 of 39 dec 16, 2016 2.3. thermal characteristics table 2-5: thermal characteristics of the package parameter symbol airflow (m/s) unit 0 0.2 1 2 thermal resistance junction to ambient note1 ja 21.99 20.91 18.86 17.80 k/w thermal resistance junction to top center of the package surface note1 jt 0.12 0.17 0.31 0.37 k/w thermal resistance junction to case note2 jc 7.38 k/w note 1. the parameters are valid, if no heat sink is used and pcb with 4 layers and massive ground and power planes. 2. the parameter is valid, if a heat sink is used.
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 23 of 39 dec 16, 2016 2.4. ac characteristics 2.4.1. clock timing table 2-6: clock ac characteristics (using a crystal) parameter symbol min. typ. max. unit oscillator clock frequency (xclk1, pin n11) xclk2, pin p11) note 1 f c - 25 - mhz frequency tolerance f tol -50 ppm - + 50 ppm extal clock cycle time t excyc - 40 - ns extal clock rising time note 2 t exr 0 - 4 ns extal clock falling time note 2 t exf 0 - 4 ns input capacity (incl. package), xclk1, n11 c in - 4.2 - pf output capacity (incl. package), xclk2, p11 c out 3 4 5 pf high level input voltage v ih 2.0 - v low level input voltage v il - - 0.8 v jtag clock frequency - - - 20 mhz notes: 1. see TPS-1 user?s manual: hardware () for recommended xtal 2. i nput voltage rising from 10% to 90% or falling from 90% to 10% of its nominal value. figure 2-1: clock waveforms table 2-7: clock ac char acteristics (using an external oscillator) parameter symbol min. typ. max. unit external clock source frequency f in - 25 - mhz frequency tolerance note 1 f tol -50 ppm - + 50 ppm xclk1 high level voltage v ih 2 3.3 vddacb v xclk1 low level voltage v il 0 - 0.8 v xclk1 rise or fall time t rfc 0 1 4 ns xclk1 high or low time note 2 t w 16 20 24 pf xclk1 jitter tolerance t jit - 20 - ps (rms) xclk1 duty cycle ducy 40 50 60 % notes: 1. the specified frequency tolerance must be maintained over all lifetime and temperature. 2. t w was calculated at f in(typ) =25 mhz, e.g. t w(min) = 10 * (ducy (min) / f in(typ) )
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 24 of 39 dec 16, 2016 2.4.2. i/o timing specification figure 2-2: input setup and hold waveforms figure 2-3: output delay waveforms
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 25 of 39 dec 16, 2016 2.4.2.1. jtag interface timing table 2-8: timing jtag interface signal input output unit clock notes setup time (t is min.) hold time (t ih min.) valid delay (t ov max.) hold time (t oh min.) trstn 8 0 ns tck tms 8 0 ns tck tdi 8 0 ns tck tck - - - - - - note 2 tdo 10 2 ns tck note 1 note 1: minimum hold time is measured with 10 pf load and maximum valid delay is measured with 30 pf load. 2: for tck a maximum speed of 20 mhz is allowed.
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 26 of 39 dec 16, 2016 2.4.2.2. parallel host interface timing diagrams 2.4.2.2.1. host read from TPS-1 with separate read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-9: host read with separate read/write line parameter symbol condition min. max. unit chip select asserted to read pulse asserted delay t csrs - 0 - ns address valid to read pulse asserted setup time t ars - 0 - ns read pulse asserted to ready enabled delay t rre - 5 12 ns read pulse asserted to data enable delay t rde - 5 12 ns ready asserted to data valid delay t rtd - - 5 ns read pulse deasserted to chip select deasserted delay t rcsh - 0 - ns address valid to read pulse deasserted hold time t rha - 0 - ns data valid/enable to read pulse deasserted hold time t rdh - 0 12 ns read recovery time t rr - 25 - ns figure 2-4: host read with separate read/write line
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 27 of 39 dec 16, 2016 2.4.2.2.2. host write to TPS-1 with separate read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-10: host write with separate read/write line parameter symbol condition min. max. unit chip select asserted to write pulse asserted delay t csws - 0 - ns address valid to write pulse asserted setup time t aws - 0 - ns write pulse asserted to ready enabled delay t wre - 5 12 ns write pulse asserted to data valid delay t wdv - - 40 ns write pulse deasserted to chip select deasserted delay t wcsh - 0 - ns address hold time after write strobe deasserted t wah - 0 - ns ready asserted to write pulse deasserted delay t rtw - 0 - ns data hold time after write pulse deasserted t wdh - 0 - ns write recovery time t wr - 25 - ns lbu_a(13:0)_in lbu_seg(1:0)_in lbu_be_(2:1)_in lbu_ready_out lbu_data(15:0) lbu_cs_n lbu_wd_en_n t csws t aws t wre t wdv t wdh t wah t wr t wcsh t rtw figure 2-5: host write with separate read/write line
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 28 of 39 dec 16, 2016 2.4.2.2.3. host read from TPS-1 with common read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-11: host read with common read/write line parameter symbol condition min. max. unit write signal deasserted to chip select asserted setup time t wcs - 2 - ns address valid to chip sele ct asserted setup time t acs - 0 - ns chip select asserted to ready enabled delay t cre - 5 12 ns chip select asserted to data enable delay t cde - 5 12 ns ready asserted to data valid delay t rtd - - 5 ns write signal inactive to chip select deasserted hold time t cwh - 0 - ns chip select deasserted to address invalid hold time t cah - 0 - ns chip select deasserted to data invalid hold time t cdh - 0 12 ns read recovery time t rr - 25 - ns figure 2-6: host read with common read/write line
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 29 of 39 dec 16, 2016 2.4.2.2.4. host write to TPS-1 with common read/write line (lbu_ready_out active low) t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-12: host write with common read/write line parameter symbol condition min. max. unit write signal deasserted to chip select asserted setup time t wcs - 2 - ns address valid to chip sele ct asserted setup time t acs - 0 - ns chip select asserted to ready enabled delay t cre - 5 12 ns chip select asserted to data valid delay t cdv - - 40 ns write signal deasserted to chip select deasserted hold time t cwh - 0 - ns address hold time after ch ip select deasserted t cah - 0 - ns ready asserted to chip select deasserted delay t rtc - 0 - ns chip select deasserted to data invalid hold time t cdh - 0 - ns read recovery time t wr - 25 - ns figure 2-7: host write with common read/write line
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 30 of 39 dec 16, 2016 2.4.2.3 spi slave timing t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-13: spi slave timing parameter symbol condition min. max. unit spi clock t cl - 40 - ns setup time t su - 13 - ns hold time t h - 13 - ns figure 2-8: spi slave timing
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 31 of 39 dec 16, 2016 2.4.3. i2c-bus timing definition t a = - 40 to +85 o c; v dd15 = 1.35 v ~ 1.65 v; v dd33 = 3.0 v ~ 3.6 v table 2-14: characteristics of the scl and sda lines parameter symbol standard-mode fast-mode unit min. max. min. max. scl clock frequency f scl 0 100 0 400 khz bus free time between a stop and start condition t buf 4.7 - 1.3 - s hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - s low period of the scl clock t low 4.7 - 1.3 - s high period of the scl clock t high 4.0 - 0.6 - s set-up time for repeated start condition t su;dat 4.7 - 0.6 - s data hold time t hd;dat 0 (1) - 0 (1) 0.9 s data set-up time t su;sta 250 - 100 (2) - ns rise time of both sda and scl signals t r - 1000 20+0.1c b 300 ns fall time of both sda and scl signals t f - 300 20+0.1c b 300 ns capacitive load for each bus line c b - 400 - 400 pf notes: 1. the device must internally provide a hold time of at least 300 ns for the sda signal in order to bridge the undefined region of the falling edge of scl. 2. a fast-mode device can be used in a st andard-bus system, but the requirement t su;sta must be met. figure 2-9: i2c-bus timing definition
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 32 of 39 dec 16, 2016 2.4.3.1. phy dc specifications(100 base-tx) t a = -40 to +85 o c, avdd33 = 3.0 to 3.6v, avdd15 = 1.35 to 1.65v, dvdd = 1.35 to 1.65v table 2-15: phy dc specification parameter symbol min. typ. max. unit tx output, high level differential signal, txp/txn v outh 0.95 1.05 v tx output, low level differential signal, txp/txn v outl -0.95 -1.05 v tx output, mid. level differential signal, txp/txn v outm -0.05 +0.05 v tx output, overshoot differential signal, txp/txn v 0vs 0 5 % these specifications are comp lying with ansi/ieee 802.3 std. figure 2-10: phy dc specification
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 33 of 39 dec 16, 2016 2.4.3.2. phy ac speci fications (100base-tx) t a = -40 to +85 o c, avdd33 = 3.0 to 3.6v, avdd15 = 1.35 to 1.65v, dvdd = 1.35 to 1.65v table 2-16: phy ac timing parameter symbol min. typ. max. unit rise time and fall time, txp/txn t r , t f 3 5 ns duty cycle distortion, txp/txn 0.5 ns transmit jitter, txp/txn 1.4 ns these specifications are complyi ng with ansi/ieee 802.3 std. figure 2-11: phy ac specification
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 34 of 39 dec 16, 2016 2.4.4. power-up sequence for operation the TPS-1 needs three supply voltages. these are 3.3v, 1.5v and 1.0v, whereby the 1.5v power supply can be generated internally by a switch regulator. it is also pos sible to feed this power supply from an external circuitry. table 2-17: signals for power-up signal TPS-1 description remark vdd power supply (all voltages) reset_n external reset active low xclk_1 quartz connection (input) figure 2-12: power-up sequence timing diagram
TPS-1 2. electrical specifications r19ds0069ej0105 rev. 1.05 page 35 of 39 dec 16, 2016 2.4.5. reset timing table 2-18: signals for reset timing signal TPS-1 description remark xclk1 quartz connection (input) external signal clk_arm clock for the arm cpu internal signal reset_n external reset external signal (active low) por_out power on reset internal signal (supply voltages stable) pll_lock clocks are synchronous to xclk1 internal signal the start-up time of the oscillator cannot be defined by the semiconducto r vendor, because the timing heavily depends on the external components (external resonator crystal). check the TPS-1 user?s manual: hardware (r19uh0081ed) for details. xclk1 (25 mhz) reset_n clk_arm (100 mhz) pll_lock (internal) 3.3v supply stable 1.5v supply active por_out 30 us 500 us 1.0v supply active figure 2-13: reset timing diagram (internal) (internal)
TPS-1 3. package drawing r19ds0069ej0105 rev. 1.05 page 36 of 39 dec 16, 2016 3. package drawing figure 3-1: 196-ball fpbga package drawing package: package fpbga 196 pins ball pitch 1.0 mm pitch dimensions 15 mm * 15 mm
TPS-1 4. recommended soldering conditions r19ds0069ej0105 rev. 1.05 page 37 of 39 dec 16, 2016 4. recommended soldering conditions solder this product under the following recommended conditions. for details of the recommended soldering conditions, refer to the information document. renesas semiconductor package mount manual, (rev.5.0, feb 2015) (r50zz0003ej0500) the applied standard is ?ir60-107-3?. table 4-1: recommended soldering conditions condition symbol soldering conditions ir60 package peak temperature: 260 0 c, time: 60 seconds max. (at 220 0 c or higher). -107 exposure limit: 7 days note (after that, prebake at 125 0 c for 20 to 72 hours). -3 count: three times or less. note: after opening the dry pack, store it at 25 0 c or less and 65% rh or less for the allowable storage period.
TPS-1 r19ds0069ej0105 rev. 1.05 page 38 of 39 dec 16, 2016 instructions for the use of product in this section, the precautions are de scribed for over whole of cmos device. please refer to this manual about individual precaution. when there is a mention unlike the text of this manual, a mention of the text takes first priority 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. - the input pins of cmos products are generally in th e high-impedance state. in operation with an unused pin in the open-circuit state, extra electrom agnetic noise is induced in the vicinity of lsi, associated shoot-through current flows internally, and malfunctions occur due to t he false recognition of the pin state as an input signal become possible. unused pins should be handled as descri bed under handling of unused pins in the manual. 2. processing at power-on the state of the product is undefined at the moment when power is supplied. - the states of internal circuits in the lsi are indet erminate and the states of r egister settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supp lied until the reset process is completed. in a similar way, the states of pins in a product t hat is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. - the reserved addresses are provided for the possible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. - when the clock signal is generated with an external reso nator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabili zation of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable.
TPS-1 r19ds0069ej0105 rev. 1.05 page 39 of 39 dec 16, 2016 renesas electronics corporation sales offices http://www.renesas.com renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-651-700, fax: +44-1628-651-804 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06-02 hyflux innovation centre singapore 339949 tel: +65-6213-0200, fax: +65-6213-0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 ? 2012-2015 renesas electronics corporation. all rights reserved notice 1. descriptions of circuits, software and other related inform ation in this document are provided only to illustrate the opera tion of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas e lectronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronic s does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the info rmation included herein. 3. renesas electronics does not assume any liability for infrin gement of patents, copyrights, or other intellectual property r ights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby unde r any patents, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in par t. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas elec tronics product. 5. renesas electronics products are classified according to the following two quality grades: "standard" and "high quality". t he recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. 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