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l q QT1103 qt ouch ? 10-k ey s ensor ic this datasheet is applicable to all revision 3 chips at a glance number of keys: 1 to 10 technology: patented spread-spectrum charge-transfer (one-per-key mode) key outline sizes: 5mm x 5mm or larger (panel thickness dependent); widely different sizes and shapes possible key spacings: 6mm or wider, center to center (panel thickness, human factors dependent) electrode design: single solid or ring shaped electrodes; wide variety of possible layouts layers required: one layer substrate; electrodes and components can be on same side substrates: fr-4, low cost cem-1 or fr-2 pcb materials; polyamide fpcb; pet films, glass electrode materials: copper, silver, carbon, ito, orgacon ? ink (virtually anything electrically conductive) panel materials: plastic, glass, composites, painted surfaces (low particle density metallic paints possible) adjacent metal: compatible with grounded metal immediately next to keys panel thickness: up to 50mm glass, 20mm plastic (key size dependent) key sensitivity: settable via change in reference capacitor (cs) value outputs: rs-232 based serial output , capable of single-wire operation moisture tolerance: good power: 2.8v ~ 5.0v package: 32-pin 5 x 5mm qfn rohs compliant signal processing: self-calibration, auto drift compensation, noise filtering, aks ? applications: portable devices, domestic appliances and a/v gear, pc peripherals, office equipment patents: aks? (patented adjacent key suppression) qtouch? (patented charge-transfer method) ? orgacon is a registered trademark of agfa-gevaert n.v l qc copyright ? 2006-2007 qrg ltd QT1103_3r0.03_0607 the QT1103 is designed for low cost appliance, mobile, and consumer electronics applications. qtouch? technology is a type of patented charge-transfer sensing method well known for its robust, stable, emc-resistant characteristics. it is the only all-digital capacitive sensing technology in the market today. this technology has over a decade of applications experience spanning thousands of designs. qtouch circuits are renowned for simplicity, reliability, ease of design, and cost effectiveness. qtouch? sensors employ a single reference capacitor tied to two pins of the chip for each sensing key; a signal trace leads from one of the pins to the sensing electrode which forms the key. the sensing electrode can be a simple solid shape such as a rectangle or circle. an led can be placed near or inside the solid circle for illumination. the key electrodes can be designed into a conventional printed circuit board (pcb) or flexible printed circuit board (fpcb) as a copper pattern, or as printed conductive ink on plastic film. QT1103-isg -40 0 c to +85 0 c 32-qfn t a available options /rst vdd osc n/c sns0 sns0k sns1 sync/lp detect vss sns7k sns7 sns6k sns6 sns5k 1w /change n/c sns9k sns9 sns8k sns8 ss rx 1 2 3 4 5 67 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 QT1103 sns1k sns2 sns2k sns3 sns3k sns4 sns4k sns5
9 2.8 fast detect mode ................................... 9 2.7 mod_0, mod_1 inputs ............................... 9 2.6 aks? function pins ................................. 8 2.5.3 low power (lp) mode ............................... 8 2.5.2 sync mode ..................................... 8 2.5.1 introduction ..................................... 8 2.5 sync/lp pin ...................................... 8 2.4 /change pin ...................................... 8 2.3 detect pin ...................................... 8 2.2 option resistors .................................... 8 2.1 reset and startup time ............................... 8 2 device operation .................................... 5 1.3 wiring ........................................... 4 1.2.12 simplified mode .................................. 4 1.2.11 outputs ....................................... 4 1.2.10 adjacent key suppression (aks?) ...................... 3 1.2.9 low power (lp) mode ............................... 3 1.2.8 sync mode ..................................... 3 1.2.7 spread-spectrum operation ............................ 3 1.2.6 detection integrator confirmation ........................ 3 1.2.5 drift compensation ................................. 3 1.2.4 autorecalibration .................................. 3 1.2.3 self-calibration ................................... 3 1.2.2 burst operation ................................... 3 1.2.1 introduction ..................................... 3 1.2 parameters ....................................... 3 1.1 differences with qt1101 .............................. 3 1 overview ........................................... 21 5.2 numbering convention .............................. 21 5.1 changes ........................................ 21 5 datasheet control ................................... 20 4.10 moisture sensitivity level (msl) ....................... 20 4.9 part marking ..................................... 19 4.8 mechanical dimensions .............................. 18 4.7 lp mode typical response times ...................... 15 4.6 idd curves ....................................... 14 4.5 signal processing ................................. 13 4.4 dc specifications .................................. 13 4.3 ac specifications .................................. 13 4.2 recommended operating conditions .................... 13 4.1 absolute maximum specifications ....................... 13 4 specifications ...................................... 12 3.6 pcb layout and construction .......................... 12 3.5 power supply ..................................... 12 3.4 rsns resistors .................................... 12 3.3 cs sample capacitors - sensitivity ...................... 12 3.2 spread-spectrum circuit ............................. 11 3.1 oscillator frequency ................................ 11 3 design notes ....................................... 11 2.11.4 2w operation .................................. 11 2.11.3 lp mode effects on 1w ............................ 10 2.11.2 basic 1w operation .............................. 10 2.11.1 introduction ................................... 10 2.11 serial 1w interface ................................ 10 2.10 unused keys .................................... 10 2.9 simplified mode ................................... l q QT1103_3r0.03_0607 contents
1 overvie w 1.1 differences with qt110 1 the QT1103 is a general replacement device for the highly popular qt1101. it has all of the same features as the older device but differs in the following ways: ? rs resistors on each channel eliminated ? up to 4x more sensitive for a given value of cs ? shorter burst lengths, less power for a given value of cs ? ?burst a and b? only mode for up to eight keys, with less power ? ?burst b? only mode for up to four keys, with less power than ?burst a and b? mode ? requires an external reset signal the QT1103 should be used instead of the qt1101 for new designs due to a simpler circuit, lower power and lower cost. 1.2 parameters 1.2.1 introduction the QT1103 is an easy to use, ten touch-key sensor ic based on quantum?s patented charge-transfer (?qt?) principles for robust operation and ease of design. this device has many advanced features which provide for reliable, trouble-free operation over the life of the product. 1.2.2 burst operation the device operates in ?burst mode?. each key is acquired using a burst of charge-transfer sensing pulses whose count varies depending on the value of the reference capacitor cs and the load capacitance cx. in lp mode, the device sleeps in an ultra-low current state between bursts to conserve power. the keys signals are acquired using three successive bursts of pulses: burst a: keys 0, 1, 4, 5 burst b: keys 2, 3, 6, 7 burst c: keys 8, 9 bursts always operate in c-a-b sequence. 1.2.3 self-calibration on power-up, all ten keys are self-calibrated within 300ms (typical) to provide reliable operation under almost any conditions. 1.2.4 autorecalibration the device can time out and recalibrate each key independently after a fixed interval of continuous touch detection, so that the keys can never become ?stuck on? due to foreign objects or other sudden influences. after recalibration the key will continue to function normally. the delay is selectable to be either 10s, 60s, or infinite (disabled). the device also autorecalibrates a key when its signal reflects a sufficient decrease in capacitance. in this case the device recalibrates after ~2 seconds so as to recover normal operation quickly. 1.2.5 drift compensation drift compensation operates to correct the reference level of each key slowly but automatically over time, to suppress false detections caused by changes in temperature, humidity, dirt and other environmental effects. 1.2.6 detection integrator confirmation detection integrator (di) confirmation reduces the effects of noise on the QT1103. the di mechanism requires consecutive detections over a number of measurement bursts for a touch to be confirmed and indicated on the outputs. in a like manner, the end of a touch (loss of signal) has to be confirmed over a number of measurement bursts. this process acts as a type of ?debounce? against noise. a per-key counter is incremented each time the key has exceeded its threshold and stayed there for a number of measurement bursts. when this counter reaches a preset limit the key is finally declared to be touched. for example, if the limit value is six, then the device has to exceed its threshold and stay there for six measurement bursts in succession without going below the threshold level, before the key is declared to be touched. if on any measurement burst the signal is not seen to exceed the threshold level, the counter is cleared and the process has to start from the beginning. in normal operation, the start of a touch must be confirmed for six measurement bursts and the end of a touch for three. in a special ?fast detect? mode (available via jumper resistors) (tables 1.2 and 1.6), confirmation of the start of a touch requires only three and the end of a touch requires two measurement bursts. fast detect is only available when aks is disabled. 1.2.7 spread-spectrum operation the bursts operate over a spread of frequencies, so that external fields will have minimal effect on key operation and emissions are very weak. spread spectrum operation works with the di mechanism to dramatically reduce the probability of false detection due to noise. 1.2.8 sync mode the QT1103 features a sync mode to allow the device to slave to an external signal source, such as a mains signal (50/60hz), to limit interference effects. this is performed using the sync/lp pin. sync mode operates by triggering three sequential acquire bursts, in sequence c-a-b from the sync signal. thus, each sync pulse causes all ten keys to be acquired (see section 2.5.2, page 8). 1.2.9 low power (lp) mode the device features an lp mode for microamp levels of current drain with a slower response time, to allow use in battery operated devices. on detection of touch, the device automatically reverts to its normal mode and asserts the detect pin active to wake up a host controller. the device remains in normal, full acquire speed mode until another pulse is seen on its sync/lp pin, upon which it goes back to lp mode (see optimization of lp mode , page 9). when eight or fewer keys are required, current drain in lp mode can be further reduced by choosing appropriate channels on the QT1103 (see the end of section 2.5.3, page 8). l q 3 QT1103_3r0.03_0607
1.2.10 adjacent key suppression (aks?) aks ? is a quantum-patented feature that can be enabled via a resistor strap option. aks works to prevent multiple keys from responding to a single touch, a common complaint about capacitive touch panels. this can happen with closely spaced keys, or with control surfaces that have water films on them. aks operates by comparing signal strengths from keys within a group of keys to suppress touch detections from those that have a weaker signal change than the dominant one. the QT1103 has two different aks groupings of keys, selectable via option resistors. these groupings are: ? aks operates in three groups of keys ? aks operates over all ten keys these two modes allow the designer to provide aks while also providing for shift or function operations. if aks is disabled, all keys can operate simultaneously. 1.2.11 outputs the QT1103 has a serial output using one or two wires, rs-232 data format, and automatic baud rate detection. a simple protocol is employed. the QT1103 operates in slave mode, i.e. it only sends data to the host after receiving a request from the host. an additional /change (state changed) signal allows the use of the serial interface to be optimised, rather than being polled continuously. 1.2.12 simplified mode to reduce the need for option resistors, the simplified operating mode places the part into fixed settings with only the aks feature being selectable. lp mode is also possible in this configuration. simplified mode is suitable for most applications. l q 4 QT1103_3r0.03_0607
1.3 wiring vdd input for 2w mode 2w receive i rx 32 - requires pull-up to vdd 1w mode serial i/o i/od 1w 31 100k resistor to vss 0 = a key state has changed requires pull-up state changed od /change 30 open - - - n/c 29 open to cs9 + key sense pin i/o sns9k 28 open to cs9 sense pin i/o sns9 27 open to cs8 + key sense pin i/o sns8k 26 open to cs8 sense pin i/o sns8 25 open see table 1.4 detect status o/od detect 24 vdd or vss** rising edge sync or lp pulse sync in or lp in i sync/lp ? 23 - 0v ground p vss 22 open to cs7 + key sense pin i/o sns7k 21 open or mode resistor ? or option resistor* to cs7 and/or mode resistor ? or option resistor* sense pin and mode or option select i/o sns7 20 open or mode resistor ? to cs6 + key and/or mode resistor ? sense pin and mode select i/o sns6k 19 open or option resistor* to cs6 and/or option resistor* sense pin and option select i/o sns6 18 open to cs5 + key sense pin i/o sns5k 17 open or option resistor* to cs5 and/or option resistor * sense pin and option select i/o sns5 16 open to cs4 + key sense pin i/o sns4k 15 open to cs4 sense pin i/o sns4 14 open to cs3 + key sense pin i/o sns3k 13 open or option resistor* to cs3 and/or option resistor* sense pin and option select i/o sns3 12 open to cs2 + key sense pin i/o sns2k 11 open or option resistor* to cs2 and/or option resistor* sense pin and option select i/o sns2 10 open to cs1 + key sense pin i/o sns1k 9 open or option resistor* to cs1 and/or option resistor* sense pin and option select i/o sns1 8 open to cs0 + key sense pin i/o sns0k 7 open or option resistor* to cs0 and/or option resistor sense pin and option select i/o sns0 6 - leave open - - n/c 5 - resistor to vdd and optional spread spectrum rc network oscillator i osc 4 - +2.8 ~ +5.0v power p vdd 3 - active low reset reset input i /rst 2 100k resistor to vss spread spectrum drive spread spectrum od ss 1 if unused notes function type name pin table 1.1 pin descriptions pin type i cmos input only i/o cmos i/o od cmos open drain output i/od cmos input or open drain output o/od cmos push-pull or open-drain output (option selected) p ground or power notes ? mode resistor is required only in simplified mode (see figure 1.2) * option resistor is required only in full options mode (see figure 1.1) ? pin is either sync or lp depending on options selected (functions sl_0, sl_1, see figure 1.1) ** see text l q 5 QT1103_3r0.03_0607
table 1.2 aks / fast-detect options table 1.3 max on-duration table 1.4 detect pin drive table 1.5 sync/lp function l q 6 QT1103_3r0.03_0607 figure 1.1 connection diagram - full options (32-qfn package) vdd *100nf 3 vss 22 detect sync/lp 24 23 detect out sync or lp pull-up not required for push-pull mode see detect pin mode table 100k vdd QT1103 32-qfn 100k rx 1w /change n.c. 32 31 30 29 /change data 2w data vdd 100k vdd 100k vdd n.c. 5 osc ss 4 1 rb1 rb2 css vdd with spread-spectrum no spread-spectrum vdd range rb1 rb2 vdd range rb1 rb2 2.8 ~ 2.99v 12k 27k 3.0 ~ 3.59v 12k 22k 3.6 ~ 5v 15k 27k 2.8 ~ 2.99v 15k dni 3.0 ~ 3.59v 18k dni 3.6 ~ 5v 20k dni dni = do not install recommended rb1, rb2 value *note: one bypass capacitor to be tightly wired between vdd and vss. follow regulator manufacturer?s recommendations for input and output capacitors. sns6 sns6k sns7 sns7k 18 19 20 21 key 6 key 7 keep these parts close to the ic 1m v / v dd ss sl_0 r sns6 c s6 1m v / v dd ss sl_1 r sns7 c s7 sns4 sns4k sns5 sns5k 14 15 16 17 key 4 key 5 r sns4 c s4 1m v / v dd ss r sns5 c s5 out_d sns3 sns3k 12 13 key 3 1m v / v dd ss mod_1 r sns3 c s3 sns8 sns8k sns9 sns9k 25 26 27 28 key 8 key 9 r sns8 c s8 r sns9 c s9 sns2k sns2 key 2 1m vv dd ss / mod_0 11 10 c s2 r sns2 sns1k sns1 9 8 key 1 sns0k sns0 7 6 key 0 keep these parts close to the ic c s1 r sns1 c s0 r sns0 1m vv dd ss / aks_1 1m vv dd ss / aks_0 vunreg voltage reg vdd /rst 2 reset in off on, global vdd vdd off on, in 3 groups vss vdd enabled off vdd vss off off vss vss fast-detect aks mode aks_0 aks_1 (reserved) vdd vdd infinite (disabled) vss vdd 60 seconds to recalibrate vdd vss 10 seconds to recalibrate vss vss max on-duration mode mod_0 mod_1 push-pull, active high vdd open drain, active low vss detect pin mode out_d lp mode: 190ms response time vdd vdd lp mode: 110ms response time vss vdd lp mode: 70ms response time vdd vss sync vss vss sync/lp pin mode sl_0 sl_1
table 1.6 aks resistor options table 1.7 functions in simplified mode suggested regulator manufacturers: ? toko (xc6215 series) ? seiko (s817 series) ? bcdsemi (ap2121 series) re figures 1.1 and 1.2 check the following sections for the variable component values: ? section 3.3, page 12: cs capacitors (c s ) ? section 3.4, page 12: sample resistors (r sns ) ? section 3.5, page 12: voltage levels ? section 3.2, page 12: css capacitor l q 7 QT1103_3r0.03_0607 figure 1.2 connection diagram - simplified mode (32-qfn package) vss /rst 22 vdd vunreg voltage reg vdd *100nf with spread-spectrum no spread-spectrum vdd range rb1 rb2 vdd range rb1 rb2 2.8 ~ 2.99v 12k 27k 3.0 ~ 3.59v 12k 22k 3.6 ~ 5v 15k 27k 2.8 ~ 2.99v 15k dni 3.0 ~ 3.59v 18k dni 3.6 ~ 5v 20k dni dni = do not install recommended rb1, rb2 values osc ss 4 1 rb1 rb2 vdd *note: one bypass capacitor to be tightly wired between vdd and vss. follow regulator manufacturer?s recommendations for input and output capacitors. QT1103 32-qfn css detect sync/lp 24 23 detect out lp in sns6 sns6k sns7 sns7k 18 19 20 21 key 6 key 7 keep these parts close to the ic r sns6 c s6 1m smr r sns7 c s7 sns4 sns4k sns5 sns5k 14 15 16 17 key 4 key 5 r sns4 c s4 r sns5 c s5 sns3 sns3k 12 13 key 3 r sns3 c s3 sns8 sns8k sns9 sns9k 25 26 27 28 key 8 key 9 r sns8 c s8 r sns9 c s9 3 sns2k sns2 key 2 11 10 c s2 r sns2 sns1k sns1 9 8 key 1 sns0k sns0 7 6 key 0 keep these parts close to the ic c s1 r sns1 c s0 r sns0 1m vv dd ss / aks_0 2 reset in 100k rx 1w /change n.c. 32 31 30 29 /change data 2w data vdd 100k vdd 100k vdd n.c. 5 off on, global vdd enabled off vss fast-detect aks mode aks_0 push-pull, active high detect pin 60 seconds max on-duration delay 110ms lp function; sync not available sync/lp pin
2 device operation 2.1 reset and startup time after a reset event, the device typically requires 260ms to initialize, calibrate, and start operating normally. keys will work properly once all keys have been calibrated after reset. the QT1103 does not have a brownout detector; its reset input must be taken active (low) following power-up and when vdd falls below 2v. 2.2 option resistors the option resistors are read on power-up only. there are two primary option mode configurations: full, and simplified. full options mode: seven 1m option resistors are required as shown in figure 1.1. all seven resistors are mandatory. simplified mode: a 1m resistor should be connected from sns6k to sns7. in simplified mode, only one additional 1m option resistor is required for the aks feature (figure 1.2). note that the presence and connection of option resistors will influence the required values of cs; this effect will be especially noticeable if the cs values are under 22nf. cs values should be adjusted for optimal sensitivity after the option resistors are connected. 2.3 detect pin detect represents the functional logical-or of all ten keys. detect can be used to wake a battery-operated product upon human touch. the output polarity and drive of detect are governed according to table 1.4, page 6, and table 1.7, page 7. 2.4 /change pin the /change pin can be used to tell the host that a change in touch state has been detected (i.e. a key has been touched or released), and that the host should read the new key states over the serial interface. /change is pulled low when a key state change has occurred. /change is very useful to prevent transmissions with duplicate data. if /change is not used, the host would need to keep polling the QT1103 constantly, even if there are no changes in touch. upon detection of a key, /change will pull low and stay low until the serial interface has been polled by the host. /change will then be released and return high until the next change of key state, either on or off, on any key (figures 2.6, 2.9). the /change pin is open-drain, and requires a ~100k pull-up resistor to vdd in order to function properly. 2.5 sync/lp pin 2.5.1 introduction the sync / lp pin function is configured according to the sl_0 and sl_1 resistor connections to either vdd or vss (see table 1.5). 2.5.2 sync mode sync mode allows the designer to synchronize acquire bursts to an external signal source, such as mains frequency (50/60hz), to suppress interference. it can also be used to synchronize two qt parts which operate near each other, so that they will not cross-interfere if two or more of the keys (or associated wiring) of the two parts are near each other. the sync input is positive pulse triggered. following each rising edge the device will generate three acquire bursts in c-a-b sequence. figure 2.1 acquire bursts in c-a-b sequence sync burst c burst a burst b if the sync input does not change level for ~150ms, the QT1103 will free-run, generating a continuous stream of acquire bursts c-a-b-c-a-b-c-a-... . while the QT1103 is in free-run operation, a rising edge on the sync input will return the QT1103 to synchronised operation. note that the sync input must remain at one level (high or low) for >150s to guarantee that the QT1103 will recognise that level. 2.5.3 low power (lp) mode lp mode allows the device to be switched between full speed operation (14ms (normal mode) or 28ms (fast mode) typical response time and normal power consumption), and low power operation (low average power consumption but an increased maximum response time) according to the needs of the application. there are three maximum response time settings for low power operation: 70ms, 110ms, and 190ms nominal; the response time setting is determined by option resistors sl_1 and sl_0 (see table 1.5). slower response times result in a lower average power drain. operation in low power mode is governed by the state of the lp input and whether at least one key has a confirmed touch. if the lp input is at a constant low level, then the QT1103 will remain in full speed operation (14ms or 28ms typical response time and normal power consumption), as in figure 2.2. figure 2.2 full speed operation touch lp pin bursts full speed operation l q 8 QT1103_3r0.03_0607
if the lp input is at a constant high level, then the QT1103 will enter low power operation whenever it is not detecting a touch. it will switch automatically to full speed operation while there is a touch, and revert to low power operation at the end of the touch. this is shown in figure 2.3. figure 2.3 low power/full speed operation e touch lp pin bursts full speed low power low power while there is no touch, if the lp input is driven high then low, the QT1103 will enter low power operation, as described previously, and remain in low power operation when lp is taken low. when there is a touch the QT1103 will switch automatically to full speed operation. at the end of the touch the choice of operation depends on the state of the lp input. this is shown in figures 2.4 and 2.5 - the first with the lp pin being low at the end of the touch, and the second with the lp pin being high at the end of the touch. figure 2.4 lp pin low at end of touch e touch lp pin bursts full speed low powe r figure 2.5 lp pin high at end of touch e touch lp pin bursts full speed low power low power note that the lp input must remain at one level (high or low) for >150s to guarantee that the QT1103 will recognise that level. optimization of lp mode for low power consumption, when up to eight keys are required, all keys should be connected to QT1103 channels that are measured during acquire bursts a and b (i.e. k0...k7). for the lowest possible power consumption, when up to four keys are required, all keys should be connected to QT1103 channels that are measured during acquire burst b (i.e. k2, k3, k6, k7). if this is done the QT1103 automatically selects an optimized lp operation, which gives a significantly lower power consumption than would be achieved if additional acquire bursts were used. optimized lp operation is identical to the standard lp operation in all other ways; it is controlled as described previously. 2.6 aks? function pins the QT1103 features an adjacent key suppression (aks?) function with two modes. option resistors act to set this feature according to tables 1.2 and 1.6. aks can be disabled, allowing any combination of keys to become active at the same time. when operating, the modes are: global: the aks function operates across all ten keys. this means that only one key can be active at any one time. groups: the aks function operates among three groups of keys: 0-1-4-5, 2-3-6-7, and 8-9. this means that up to three keys can be active at any one time. in group mode, keys in one group have no aks interaction with keys in any other group. note that in fast detect mode, aks can only be off. 2.7 mod_0, mod_1 inputs in full option mode, the mod_0 and mod_1 resistors are used to set the 'max on-duration' recalibration timeouts. if a key becomes stuck on for a lengthy duration of time, this feature will cause an automatic recalibration event of that specific key only once the specified on-time has been exceeded. settings of 10s, 60s, and infinite are available. the max on-duration feature operates on a key-by-key basis; when one key is stuck on, its recalibration has no effect on other keys. the logic combination on the mod option pins sets the timeout delay; see table 1.3. simplified mode mod timing: in simplified mode, the max on-duration is fixed at 60s. 2.8 fast detect mode in many applications, it is desirable to sense touch at high speed. examples include scrolling ?slider? strips or ?off? buttons. it is possible to place the device into a ?fast detect? mode that usually requires under 14ms (typical) to respond. this is accomplished internally by setting the detect integrator to only three counts, i.e. only three successive detections are required to detect touch. in lp mode, ?fast? detection will not speed up the initial delay (which could be up to 190ms typical depending on the option setting). however, once a key is detected the device is forced back into normal speed mode. it will remain in this faster mode until requested to return to lp mode. when used in a ?slider? application, it is normally desirable to run the keys without aks. in fast mode the time required to process a key release is reduced from three samples to two. fast detect mode can be enabled as shown in tables 1.2 and 1.6. l q 9 QT1103_3r0.03_0607
2.9 simplified mode a simplified operating mode which does not require the majority of option resistors is available. this mode is set by connecting a resistor labeled smr between pins sns6k and sns7 (see figure 1.2). in this mode there is only one option available - aks enable or disable. when aks is disabled, fast detect mode is enabled; when aks is enabled, fast detect mode is off. aks in this mode is global only (i.e. operates across all functioning keys). the other option features are fixed as follows: detect pin: push-pull, active high sync/lp function: lp mode, ~110ms response time max on-duration: 60 seconds see also tables 1.6 and 1.7. 2.10 unused keys unused keys should be disabled by removing the corresponding cs and rsns components and connecting sns pins as shown in the ?unused? column of table 1.1. unused keys are ignored and do not factor into the aks function (section 2.6). 2.11 serial 1w interface 2.11.1 introduction the 1w serial interface is an rs-232 based auto baud rate serial asynchronous interface that requires only one wire between the host mcu and the QT1103. the serial data are extremely short and simple to interpret. auto baud rate detection takes place by having the host device send a specific character to the QT1103, which allows the QT1103 to set its baud rate to match that of the host. one feature of this method is that the baud rate can be any rate between 8,000 and 38,400 bits per second. neither the QT1103 nor the host device has to be accurate in their transmission rates, i.e. crystal control is not required. depending on the timing of a 1w host transmission, the QT1103 device may need to abort an acquisition burst, and rerun it after the transmission is complete and a reply has been sent. as a consequence, each host request can potentially result in a small, unnoticeable increase in detection delay. 1w connection: the 1w pin should be pulled high with a resistor. when not in use it floats high, hence this causes no increase in supply current. during transmission from the host, the host may drive the 1w line with either an open-drain or a push-pull driver. however, if the host uses push-pull driving, it must release the 1w line as soon as it is done with its stop bit so that there is no drive conflict when the QT1103 sends its reply. if open-drain transmission is used by the host, the value of the pull-up resistor should be optimized for the desired baud rate: faster rates require a lower value of resistor to prevent rise-time problems. a typical value for 19,200 baud might be 100k . an oscilloscope should be used to confirm that the resistor is not causing excessive timing skew that might cause bit errors. the QT1103 uses push-pull drive to transmit data out on the 1w line back to the host. when the stop bit level is established, 1w is floated; for this reason, a pull-up resistor should always be used on the 1w pin to prevent the signal from drifting to an undefined state. a 100k pull-up resistor on 1w is recommended, unless the host uses open-drain drive to the QT1103, in which case a lower value may be required (see prior paragraph). 2.11.2 basic 1w operation the basic sequence of 1w serial operation is shown in figure 2.6. the 1w line is bi-directional and must be pulled high with a resistor to prevent a floating, undefined state (see section 2.11.1). oscillator tolerance: while the auto baud rate detection mechanism has a wide tolerance for oscillator error, the qt?s oscillator should still not vary by more than 20 percent from the recommended value. beyond a 20 percent error, communications at either the lower or upper stated limits could fail. the oscillator frequency can be checked with an oscilloscope by probing the pulse width on the sns lines (see section 3.1, page 11). host request byte: the host requests the key state from the QT1103 by sending an ascii "p" character (ascii decimal code 80, hex 0x50) over the 1w line. the character is formatted according to conventional rs-232: 8 data bits no parity 1 stop bit baud rate: 8,000 - 38,400 figure 2.7 shows the bit pattern of the host request byte (?p?). the first bit labeled ?s? is the start bit, the last ?s? is the stop bit. this bit pattern should never be changed. the QT1103 will respond at the same baud rate as the received ?p? character. l q 10 QT1103_3r0.03_0607 figure 2.6 basic 1w sequence *see figure 2.8 figure 2.7 1w uart host pattern 1 ~ 3 bit periods 1w /change key state change request from host (1 byte) driven repl y (2 bytes)* floating floating floating floating from QT1103 s01234 7s serial bits 56 1w (from host)
after sending the ?p? character the host must immediately float the 1w signal to prevent a drive conflict between the host and the QT1103 (see figure 2.6). the delay from the received stop bit to the QT1103 driving the 1w pin is in the range 1-3 bit periods, so the host should float the pin within one bit period to prevent a drive conflict. data reply: before sending a reply, the QT1103 returns the /change signal to its inactive (float-high) state. the QT1103 then replies by sending two eight-bit characters to the host over the 1w line using the same baud rate as the request. with no keys pressed, both reply bytes are ascii ?@? (0x40) characters; any keys that are pressed at the time of the reply result in their associated bits being set in the reply. figure 2.8 shows the reply bytes when keys 0, 2 and 7 are pressed - 0x45, 0x42, and the associations between keys and bits in the reply. the QT1103 floats the 1w pin again after establishing the level of the stop bit. 2.11.3 lp mode effects on 1w the use of low power (lp) mode presents some additional 1w timing requirements. in lp mode (section 2.5), the QT1103 will only respond to a request from the host when it is making one of its infrequent checks for a key press. hence, in that condition most requests from the host to the QT1103 will be ignored, since the QT1103 will be sleeping and unresponsive. however, if either /change or detect are active the QT1103 will be at full speed, and hence will always respond to ?p? requests. note that when sleeping in lp mode, there are by definition no keys active, so there should not be a reason for the host to send the ?p? query command in the first place. three strategies are available to the host to ensure that lp mode operates correctly: ? /change used . the host monitors /change, and only sends a ?p? request when it is low. the part is awake by definition when /change is low. if /change is high, key states are known to be unchanged since the last reply received from the QT1103, and so additional ?p? requests are not needed. before triggering lp mode the host should wait for /change to go high after all keys have become inactive. ? detect used . the host monitors detect, and if it is active (i.e. the part is awake) it polls the device regularly to obtain key status. when detect is inactive (the part may be sleeping) no requests are sent because it is known that no keys are active. before triggering lp mode the host should wait for detect to become inactive, and then send one additional 'p' request to ensure /change is also made inactive. ? neither /change nor detect used . the host polls the device regularly to obtain key status, with a timeout in operation when awaiting the reply to each ?p? request. not receiving a reply within the timeout period only occurs when the part is sleeping, and hence when no keys are active. before triggering lp mode the host should wait for all keys to become inactive and then send an additional 'p' request to the QT1103 to ensure /change is also inactive. 2.11.4 2w operation 1w operation, as described in section 2.11.3, requires that the host float the 1w line while awaiting a reply from the QT1103; this is not always possible. to solve this problem, the QT1103 can also receive the ?p? character from the host on its ?rx? pin separately from the 1w pin (figure 2.9). the host need not float the rx line since the QT1103 will never try to drive it. following a ?p? on rx, the QT1103 will send the same response pattern (figure 2.8) over the 1w line as in pure 1w mode. all other comments and timings given for 1w operation are applicable for 2w operation. lp operation is the same for 2w mode as for 1w. if the rx pin is not used, it must be tied to vdd. 3 design notes 3.1 oscillator frequency the QT1103?s internal oscillator runs from an external network connected to the osc and ss pins as shown in figures 1.1 and 1.2. the charts in these figures show the recommended values to use depending on nominal operating voltage and spread spectrum mode. if spread spectrum mode is not used, only resistor rb1 should be used, the css capacitor eliminated, and the ss pin pulled to vss with a 100k resistor. l q 11 QT1103_3r0.03_0607 figure 2.9 2w operation 1w /change rx (from host) key state change request from host (1 byte) driven repl y (2 bytes) floating floating floating floating 1 ~ 3 bit periods (from QT1103) (from QT1103) figure 2.8 uart response pattern on 1w pin s01234567 s01234567s 012345 ** 6789uu ** serial bits associated key # 1w (from QT1103) s floating floating floating (shown with keys 0, 2 and 7 detecting) * fixed bit values u - unused bits
an out-of-spec oscillator can induce timing problems such as large variations in max on-duration times and response times as well as the serial port baud rate range. effect on serial communications: the oscillator frequency has no nominal effect on serial communications since the baud rate is set by an auto-sensing mechanism. however, if the oscillator is too far outside the recommended settings, the possible range of serial communications will shrink. for example, if the oscillator is too slow, the upper baud rate will be reduced. the oscillator frequency can be verified by measuring the burst pulses at the start of a burst. ? in spread-spectrum mode, the first pulses of a burst should ideally be 2.87s ? in non spread-spectrum mode, the target value is 2.67s if in doubt, make the pulses on the narrower side (i.e. a faster oscillator) when using the higher baud rates, and conversely on the wider side when using the lowest baud rates. 3.2 spread-spectrum circuit the QT1103 offers the ability to spectrally spread its frequency of operation to heavily reduce susceptibility to external noise sources and to limit rf emissions. the ss pin is used to modulate an external passive rc network that modulates the osc pin. osc is the main oscillator current input. the circuits and recommended values are shown in figures 1.1 and 1.2. the resistors rb1 and rb2 should be changed depending on vdd. as shown in figures 1.1 and 1.2, three sets of values are recommended for these resistors depending on vdd. the power curves in section 4.6 also show the effect of these resistors. the circuit can be eliminated, if it is not desired, by using a resistor from osc to v dd to drive the oscillator, and connecting ss to vss with a 100k ? resistor (see section 3.1). the spread-spectrum rc network might need to be modified slightly with longer burst lengths. the sawtooth waveform observed on ss should reach a crest height as follows: ? vdd >= 3.6v: 17 percent of vdd ? vdd < 3.6v: 20 percent of vdd the css capacitor connected to ss (figures 1.1 and 1.2) should be adjusted so that the waveform approximates the above amplitude, 10 percent, during normal operation in the target circuit. where the bursts are of differing lengths, the adjustment should be done for the longer burst. if this is done, the circuit will give a spectral modulation of 12-15 percent. a typical value of css is 100nf. 3.3 cs sample capacitors - sensitivity the cs sample capacitors accumulate the charge from the key electrodes and hence determine sensitivity. the values of cs can differ for each channel, permitting differences in sensitivity from key to key or to balance unequal sensitivities. higher values of cs make the corresponding key more sensitive. unequal sensitivities can occur due to key size and placement differences, stray wiring capacitances, and option resistor connection. ? more stray capacitance on an electrode or sense trace will decrease sensitivity on the corresponding key; cs will have to be increased to compensate. ? an option resistor pulling low will increase sensitivity on the corresponding key; cs will have to be reduced to compensate. the cs capacitors can be virtually any plastic film or low to medium-k ceramic capacitor. acceptable capacitor types for most uses include pps film, polypropylene film, and np0 and x5r / x7r ceramics. lower grades than x5r / x7r are not advised. for most applications cs will be in the range 680pf to 50nf; larger values of cs require better quality capacitors to ensure reliable sensing. in a few applications sufficient sensitivity will be achieved with cs less than 680pf. if very high sensitivity is required then the 50nf value may be exceeded hence the 100nf maximum in section 4.2, page 13; in this case greater care should be taken over the QT1103 circuit layout and interactions with neighboring electronics. as the sensitivity of the keys, and hence the required values of cs, are affected by the presence and connection of the option resistors (see section 2.2, page 9), then final selection of cs values should take place after the options choice has been finalized. 3.4 rsns resistors series resistors r sns (r sns 0...r sns 9) are in line with the electrode connections and should be used to limit electrostatic discharge (esd) currents and to suppress radio frequency interference (rfi). for most applications r sns will be in the range 4.7k to 33k each. in a few applications with low loading on the sense keys the value may be up to 100k . although these resistors may be omitted, the device may become susceptible to external noise or rfi. for details of how to select these resistors see the application note an-kd02, downloadable from the quantum website http://www.qprox.com (go to the support tab and click application notes). 3.5 power supply the power supply can range from 2.8v to 5.0v. if this fluctuates slowly with temperature, the device will track and compensate for these changes automatically with only minor changes in sensitivity. if the supply voltage drifts or shifts quickly, the drift compensation mechanism will not be able to keep up, causing sensitivity anomalies or false detections. the power supply should be locally regulated using a three-terminal device, to between 2.8v and 5.0v. if the supply is shared with another electronic system, care should be taken to ensure that the supply is free of digital spikes, sags, and surges which can cause adverse effects. it is not recommended to include a series inductor in the power supply to the QT1103. for proper operation a 0.1f or greater bypass capacitor must be used between vdd and vss. the bypass capacitor should be routed with very short tracks to the device?s vss and vdd pins. 3.6 pcb layout and construction refer to quantum application note an-kd02 for information related to layout and construction matters. l q 12 QT1103_3r0.03_0607
4 specifications 4.1 absolute maximum specifications operating temperature, ta ............................................................................. -40 o ~ +85 o c storage temp, ts .................................................................................... -50 o ~ +125 o c vdd.................................................................................................. -0.3 ~ +6.0v max continuous pin current, any control or drive pin ............................................................ 20ma short circuit duration to ground or vdd, any pin ................................................................. infinite voltage forced onto any pin .................................................................. -0.3v ~ (vdd + 0.3) volts 4.2 recommended operating conditions operating temperature, ta ............................................................................. -40 o ~ +85 o c v dd ................................................................................................. +2.8 ~ +5.0v short-term supply ripple+noise .............................................................................. 5mv/s long-term supply stability .................................................................................. 100mv cs range ................................................................................................. [ 100nf cx range ................................................................................................ 0 ~ 50pf 4.3 ac specifications vdd = 5.0v, ta = recommended, cx = 5pf, cs = 4.7nf; circuit of figure 1.1 baud 38,400 8,000 serial communications speed bps s 1 external reset low pulse width tres end of touch ms 14 release time - normal mode tdrn end of touch ms 10 release time - fast mode tdrf 110ms lp setting ms 110 response time - lp mode tdtl ms 28 response time - normal mode tdtn ms 14 response time - fast mode tdtf all three bursts ms 2.5 burst duration tbd ms 260 startup time from cold start tsu pulses appear 33 percent longer when viewed on an oscillosco p e. s 2 sample pulse duration tpc total deviation % 15 burst modulation, percent fm khz 132 burst center frequency fc ms 150 recalibration time trc notes units max typ min description parameter 4.4 dc specifications vdd = 5.0v, ta = recommended, cx = 5pf, cs = 4.7nf, ta = recommended range; circuit of figure 1.1 unless noted bits 8 acquisition resolution ar a 1 input leakage current iil 2.5ma source v vdd-0.5 high output voltage voh 7ma sink v 0.5 low output voltage vol v 3.5 high input logic level vhl v 0.7 low input logic level vil v/s 100 average supply turn-on slope vdds @ v dd = 3.3v @ v dd = 2.8v a 20 14 average supply current, lp mode, keys on burst b only @ v dd = 3.3v @ v dd = 2.8v a 36 24 average supply current, lp mode, keys on bursts a and b only @ v dd = 3.3v @ v dd = 2.8v a 48 34 average supply current, lp mode @ v dd = 3.3v; 190ms lp mode @ v dd = 2.8v; 190ms lp mode a 22 15 average supply current, lp mode* iddl @ v dd = 5.0 @ v dd = 4.0 @ v dd = 3.3 @ v dd = 2.8 ma 8 4.2 2.5 1.8 1.4 average supply current, normal mode* iddn notes units max typ min description parameter *no spread spectrum circuit l q 13 QT1103_3r0.03_0607
4.5 signal processing vdd = 5.0v, ta = recommended, cx = 5pf, cs = 4.7nf, 2s qt pulses towards decreasing cx load ms/level 500 anti drift compensation rate towards increasing cx load ms/level 2,000 normal drift compensation rate option pin selected secs 10, 60, inf max on-duration must be consecutive or detection fails samples 3 detect integrator filter, fast mode must be consecutive or detection fails samples 6 detect integrator filter, normal mode time to recalibrate if cx load has exceeded anti-detection threshold secs 2 anti-detection recalibration delay threshold for decrease of cx load counts 6 anti-detection threshold counts 2 detection hysteresis threshold for increase in cx load counts 10 detection threshold notes units value description l q 14 QT1103_3r0.03_0607
4.6 idd curves all idd curves are average values, under the following conditions: cx = 5pf, cs = 4.7nf, ta = 20 o c; no spread-spectrum circuit. refer to page 9 for more information about optimization of lp modes. full speed operation QT1103, average idd (190ms optimized lp operation) 0.0 100.0 200.0 300.0 400.0 500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (110ms optimized lp operation) 0.0 200.0 400.0 600.0 800.0 1000.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (70ms optimized lp operation) 0.0 250.0 500.0 750.0 1000.0 1250.0 1500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v low power operation (optimized - only burst b in use) l q 15 QT1103_3r0.03_0607 QT1103, average idd (full speed operation) 0.0 1.0 2.0 3.0 4.0 5.0 0123456 burst length (ms) idd (ma) vdd=5v vdd=4v vdd=3.3v vdd=2.8v
QT1103, average idd (190ms optimized lp operation) 0.0 100.0 200.0 300.0 400.0 500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (110ms optimized lp operation) 0.0 200.0 400.0 600.0 800.0 1000.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (70ms optimized lp operation) 0.0 250.0 500.0 750.0 1000.0 1250.0 1500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v low power operation (optimized - only burst a and b in use) l q 16 QT1103_3r0.03_0607
QT1103, average idd (190ms lp operation) 0.0 100.0 200.0 300.0 400.0 500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (110ms lp operation) 0.0 200.0 400.0 600.0 800.0 1000.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v QT1103, average idd (70ms lp operation) 0.0 250.0 500.0 750.0 1000.0 1250.0 1500.0 0123456 burst length (ms) idd (ua) vdd=5v vdd=4v vdd=3.3v vdd=2.8v low power operation (non-optimized) l q 17 QT1103_3r0.03_0607
4.7 lp mode typical response times response time vs vdd - 190ms setting 150 160 170 180 190 200 210 220 230 240 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vdd response time, ms response time vs vdd - 110ms setting 80 90 100 110 120 130 140 2.50 3.00 3.50 4.00 4.50 5.00 5.50 vdd response time, ms response time vs vdd - 70ms setting 60 65 70 75 80 85 90 2.533.544.555.5 vdd response time, ms l q 18 QT1103_3r0.03_0607
4.8 mechanical dimensions symbol minimum nominal maximum a 0.70 - 0.95 a1 0.00 0.02 0.05 b 0.18 0.25 0.32 c-0.20ref- d 4.90 5.00 5.10 d2 3.05 - 3.65 e 4.90 5.00 5.10 e2 3.05 - 3.65 e-0.50- l 0.30 0.40 0.50 y0.00 -0.075 dimensions in millimeters note: that there is no functional requirement for the large pad on the underside of the 32-qfn package to be soldered to the substr ate. if the final application does require this area to be soldered for mechanical reasons, the pad(s) to which it is soldered to must be isolated and contained under the 32-qfn footprint only. l q 19 QT1103_3r0.03_0607
4.9 part marking 4.10 moisture sensitivity level (msl) ipc/jedec j-std-020c 260 o c msl3 specifications peak body temperature msl rating l q 20 QT1103_3r0.03_0607 yywwg run nr. ?yy? = year of manufacture ?ww? = week of manufacture ?g? = green/rohs compliant pin 1 identification qrg revision code QT1103 ?qrg 3 qrg part number 'run nr.' = 6 digit run number
5 datasheet control 5.1 changes changes this issue (datasheet issue 03) front page. 5.2 numbering convention part number QT1103_mxn.nn_mmyy chip revision (where m= major chip revision, n = minor chip revision, x = prereleased product [or r = released product]) datasheet issue number datasheet release date; (where mm = month, yy = year) a minor chip revision (n) is defined as a revision change which does not affect product functionality or datasheet. the value of n is only stated for released parts (r). l q 21 QT1103_3r0.03_0607
l q copyright ? 2006-2007 qrg ltd. all rights reserved. patented and patents pending corporate headquarters 1 mitchell point ensign way, hamble so31 4rf great britain tel: +44 (0)23 8056 5600 fax: +44 (0)23 8045 3939 www.qprox.com north america 651 holiday drive bldg. 5 / 300 pittsburgh, pa 15220 usa tel: 412-391-7367 fax: 412-291-1015 the specifications set out in this document are subject to change without notice. all produc ts sold and services supplied by qr g are subject to qrg?s terms and conditions of sale and services. qrg patents, trademar ks and terms and conditions can be found onlin e at http://www.qprox.com /about/legal.php. numerous further patents are pending, one or more which may apply to this device or the applications thereof. qrg products are not suitable for medical (including lifesaving equipment) , safety or mission critical applications or other si milar purposes. except as expressly set out in qrg's terms and conditions, no licenses to patents or other intellectual property of q rg (express or implied) are granted by qrg in connection with the sa le of qrg products or provisi on of services. qrg will not be l iable for customer product design and customers are entirely responsible for their products and applications which incorporate qrg's prod ucts. development team: john dubery, alan bowens, matthew trend

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