SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 1 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 e series power mosfet features ? low figure-of- merit (fom) r on x q g ? low input capacitance (c iss ) ? reduced switching and conduction losses ? ultra low gate charge (q g ) ? avalanche energy rated (uis) ? material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 applications ? server and telecom power supplies ? switch mode power supplies (smps) ? power factor correctio n power supplies (pfc) ? lighting - high-intensity discharge (hid) - fluorescent ballast lighting ? industrial - welding - induction heating - motor drives - battery chargers - renewable energy - solar (pv inverters) notes a. repetitive rating; puls e width limited by maximu m junction temperature. b. v dd = 50 v, starting t j = 25 c, l = 28.2 mh, r g = 25 ? , i as = 2 a. c. 1.6 mm from case. d. i sd ? i d , di/dt = 100 a/s, starting t j = 25 c. product summary v ds (v) at t j max. 700 r ds(on) max. at 25 c ( ? )v gs = 10 v 0.6 q g max. (nc) 48 q gs (nc) 6 q gd (nc) 11 configuration single n-channel mo s fet g d s dpak (to-252) s d g ordering information package dpak (to-252) lead (pb)-free and halogen-free SIHD6N65E-ge3 SIHD6N65Et1-ge3 SIHD6N65Et4-ge3 SIHD6N65Et5-ge3 absolute maximum ratings (t c = 25 c, unless otherwise noted) parameter symbol limit unit drain-source voltage v ds 650 v gate-source voltage v gs 30 continuous drain current (t j = 150 c) v gs at 10 v t c = 25 c i d 7 a t c = 100 c 5 pulsed drain current a i dm 18 linear derating factor 0.63 w/c single pulse avalanche energy b e as 56 mj maximum power dissipation p d 78 w operating junction and storage temperature range t j , t stg -55 to +150 c drain-source voltage slope t j = 125 c dv/dt 37 v/ns reverse diode dv/dt d 27 soldering recommendations (peak temperature) c for 10 s 300 c
SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 2 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes a. c oss(er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 % to 80 % v dss . b. c oss(tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 % to 80 % v dss . thermal resistanceratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -62 c/w maximum junction-to-case (drain) r thjc -1.6 specifications (t j = 25 c, unless otherwise noted) parameter symbol test cond itions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 650 - - v v ds temperature coefficient ? v ds /t j reference to 25 c, i d = 1 ma -0.73- v/c gate-source threshold voltage (n) v gs(th) v ds = v gs , i d = 250 a 2 - 4 v gate-source leakage i gss v gs = 20 v - - 100 na v gs = 30 v - - 1 a zero gate voltage drain current i dss v ds = 650 v, v gs = 0 v - - 1 a v ds = 520 v, v gs = 0 v, t j = 125 c - - 10 drain-source on-sta te resistance r ds(on) v gs = 10 v i d = 3 a - 0.5 0.6 ? forward transconductance g fs v ds = 30 v, i d = 3 a - 2 - s dynamic input capacitance c iss v gs = 0 v, v ds = 100 v, f = 1 mhz - 820 - pf output capacitance c oss -40- reverse transfer capacitance c rss -4- effective output capacitance, energy related a c o(er) v ds = 0 v to 520 v, v gs = 0 v -36- effective output capacitance, time related b c o(tr) - 117 - total gate charge q g v gs = 10 v i d = 3 a, v ds = 520 v -2448 nc gate-source charge q gs -6- gate-drain charge q gd -11- turn-on delay time t d(on) v dd = 520 v, i d = 3 a, v gs = 10 v, r g = 9.1 ? -1428 ns rise time t r -1224 turn-off delay time t d(off) -3060 fall time t f -2040 gate input resistance r g f = 1 mhz, open drain - 1.4 - ? drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the ? integral reverse ? p - n junction diode --7 a pulsed diode forward current i sm --18 diode forward voltage v sd t j = 25 c, i s = 3 a, v gs = 0 v - - 1.3 v reverse recovery time t rr t j = 25 c, i f = i s = 3 a, di/dt = 100 a/s, v r = 25 v - 237 - ns reverse recovery charge q rr -2.2-c reverse recovery current i rrm -16-a s d g
SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 3 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (25 c, unless otherwise noted) fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical gate charge vs. gate-to-source voltage v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 5 10 15 20 25 0 5 10 15 20 25 30 top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 8 v 7 v 6 v bottom 5 v t j = 25 c v ds , drain-to-source voltage (v) i d , drain-to-source current (a) 0 5 10 15 20 25 0 5 10 15 20 25 30 top 15 v 14 v 13 v 12 v 11 v 10 v 9 v 8 v 7 v 6 v bottom 5 v t j = 150 c v gs , gate-to-source voltage (v) i d , drain-to-source current (a) 0 5 10 15 20 0 5 10 15 20 25 t j = 25 c t j = 150 c v d s = 32 v t j , junction temperature (c) r d s (on) , drain-to- s ource - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 on re s i s tance (normalized) 0 0.5 1 1.5 2 2.5 3 v gs = 10 v i d = 3 a v d s , drain-to- s ource voltage (v) capacitance (pf) 100 10 0 200 400 10 000 1 1000 100 300 500 600 c i ss c o ss c r ss v gs = 0 v, f = 1 mhz c i ss = c g s + c gd , c d s s horted c r ss = c gd c o ss = c d s + c gd ! ! ! ! q g , total g ate charge (nc) v gs , g ate-to- s ource voltage (v) 16 4 0 24 20 12 8 0 10 20 30 50 40 v d s = 520 v v d s = 325 v v d s = 130 v
SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 4 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical source-drain diode forward voltage fig. 8 - maximum safe operating area fig. 9 - maximum drain cu rrent vs. case temperature fig. 10 - temperature vs . drain-to-source voltage fig. 11 - normalized thermal transient impedance, junction-to-case v s d , s ource-drain voltage (v) i s d , rever s e drain current (a) 0.1 1 10 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 t j = 150 c t j = 25 c v gs = 0 v v d s , drain-to- s ource voltage (v) i d , drain current (a) * v gs > minimum v gs at which r d s (on) i s s pecified i dm = limited bvd ss limited operation in thi s area limited by r d s (on) 100 s 1 m s 10 m s t c = 25 c t j = 150 c s ingle pul s e s limited by r d (on) * 0.01 0.1 1 10 100 1 10 100 1000 t c , case temperature (c) i d , drain current (a) 25 50 75 100 125 150 2 4 6 8 0 t j , junction temperature (c) v ds , drain-to-source - 60 0 160 breakdown voltage (v) - 40 - 20 20 40 60 80 100 120 140 650 675 700 725 750 775 800 825 850 0.01 0.1 1 0.0001 0.001 0.01 0.1 1 normalized effective tran s ient thermal impedance pul s e time ( s ) duty cycle = 0.5 0.2 0.1 s ingle pul s e 0.05 0.02
SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 5 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 12 - switching time test circuit fig. 13 - switching time waveforms fig. 14 - unclamped inductive test circuit fig. 15 - unclamped inductive waveforms fig. 16 - basic ga te charge waveform fig. 17 - gate charge test circuit pulse width 1 s duty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f r g i as 0.01 t p d.u.t l v ds + - v dd 10 v var y t p to obtain required i as i as v ds v dd v ds t p q gs q gd q g v g charge 10 v d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v current regulator current sampling resistors same type as d.u.t. + -
SIHD6N65E www.vishay.com vishay siliconix s15-2971-rev. c, 21-dec-15 6 document number: 91546 for technical questions, contact: hvm@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 18 - for n-channel ? ? ? ? ? ? ? ? ? ? vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qu alified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91546 . p.w. period di/dt diode recovery dv/dt ripple 5 % body diode forward drop re-applied voltage rever s e recovery current body diode forward current v gs = 10 v a i s d driver gate drive d.u.t. l s d waveform d.u.t. v d s waveform inductor current d = p.w. period + - + + + - - - peak dio d e recovery d v/ d t test circuit v dd ? dv/dt controlled by r g ? driver s ame type a s d.u.t. ? i s d controlled by duty factor d ? d.u.t. - device under te s t d.u.t. circuit layout con s ideration s ? low s tray inductance ? g round plane ? low leakage inductance current tran s former r g note a. v gs = 5 v for logic level device s v dd
package information www.vishay.com vishay siliconix revision: 16-may-16 1 document number: 71197 for technical questions, contact: pmostechsupport @vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to-252aa case outline notes ? dimension l3 is for reference only. l3 d l4 l5 b b2 e1 e1 d1 c a1 gage plane height (0.5 mm) e b3 e c2 a l h millimeters inches dim. min. max. min. max. a 2.18 2.38 0.086 0.094 a1 - 0.127 - 0.005 b 0.64 0.88 0.025 0.035 b2 0.76 1.14 0.030 0.045 b3 4.95 5.46 0.195 0.215 c 0.46 0.61 0.018 0.024 c2 0.46 0.89 0.018 0.035 d 5.97 6.22 0.235 0.245 d1 4.10 - 0.161 - e 6.35 6.73 0.250 0.265 e1 4.32 - 0.170 - h 9.40 10.41 0.370 0.410 e 2.28 bsc 0.090 bsc e1 4.56 bsc 0.180 bsc l 1.40 1.78 0.055 0.070 l3 0.89 1.27 0.035 0.050 l4 - 1.02 - 0.040 l5 1.01 1.52 0.040 0.060 ecn: t16-0236-rev. p, 16-may-16 ? dwg: 5347
application note 826 vishay siliconix document number: 72594 www.vishay.com revision: 21-jan-08 3 application note recommended minimum pads for dpak (to-252) 0.420 (10.668) recommended mi nimum pads dimensions in inches/(mm) 0.224 (5.690) 0.180 (4.572) 0.055 (1.397) 0.243 (6.180) 0.087 (2.202) 0.090 (2.286) return to index return to index
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