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1. general description the pcu9655 is a ufm i 2 c-bus controlled 16-channel led driver optimized for voltage switch dimming and blinking 100 ma red/ green/blue/amber (rgba) leds. each led output has its own 8-bit resolution (256 step s) fixed frequency individual pwm controller that operates at approximately 31.25 khz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the led to be set to a specific brightness value. an additional 8-bit resolution (256 steps) group pwm controller has both a fixed frequency of about 122 hz and an adjustable frequency roughly between 15 hz to once every 16.8 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all leds with the same value. each led output can be off, on (no pwm control), set at its individual pwm controller value or at both individual and group pwm controller values. the pcu9655 operates with a supply voltage range of 3 v to 5.5 v and the 100 ma open-drain outputs allow voltages up to 40 v. the pcu9655 is one of the first led controller devices in a new ultra fast mode (ufm) family. ufm devices offer higher frequency (up to 5 mhz). software programmable led group and three sub call i 2 c-bus addresses allow all or defined groups of pcu9655 devices to respond to a common i 2 c-bus address, allowing for example, all red leds to be turned on or off at the same time, thus minimizing i 2 c-bus commands. on power-up, pcu9655 will have a uni que sub call address to identify it as a 16-channel led driver. this allows mixing of devices with different channel widths. five hardware address pins on pcu9655 allow up to 32 devices on the same bus. the software reset (swrst) function allows the master to perform a reset of the pcu9655 through the i 2 c-bus, identical to th e power-on reset (por) that initializes the registers to their default stat e causing the output voltage switches to be off (led off). this allows an easy and quick way to reco nfigure all device registers to the same condition. additionally, a thermal shutdown feature protects the device when the internal junction temperature exceeds the overtemperature threshold. pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver rev. 2 ? 2 october 2012 product data sheet
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 2 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 2. features and benefits ? 16 led drivers. each output programmable at: ? off ? on ? programmable led brightness ? programmable group dimming/blinking mi xed with individual led brightness ? programmable led output enable delay to reduce emi and surge currents ? 16 output channels can sink up to 100 ma, tolerate up to 40 v when off ? 5 mhz ultra fast-mode unidirec tional interface (write only) ? 256-step (8-bit) linear programmable brightness per led output varying from fully off (default) to maximum brightness using a 31.25 khz pwm signal ? 256-step group brightness control allows general dimming (using a 122 hz pwm signal) from fully off to maximum brightness (default) ? 256-step group blinking with frequency programmable from 15 hz to 16.8 s and duty cycle from 0 % to 99.6 % ? output state change programmable on the a cknowledge (this ninth bit is always set to 1 by ufm i 2 c-bus master) or the stop command to update outputs byte-by-byte or all at the same time (default to ?change on stop?). ? five hardware address pins allow 32 pcu9655 devices to be connected to the same ufm bus and to be individually programmed ? four software programmable i 2 c-bus addresses (one led group call address and three led sub call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one re gister used for ?all call? so that all the pcu9655s on the ufm bus can be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus can be addressed at the same time in a group). software enable and disable for each programmable ufm bus address. ? unique power-up default sub call address a llows mixing of devices with different channel widths ? software reset feature (s wrst call) allows the devic e to be reset through the ufm bus ? 8 mhz internal oscillator requ ires no external components ? internal power-on reset ? noise filter on usda/uscl inputs ? glitch free led outputs on power-up ? thermal shutdown with thermal protection ? operating power supply voltage (v dd ) range of 3 v to 5.5 v ? 5.5 v tolerant inputs on non-led pins ? ? 40 ? c to +85 ? c operation ? esd protection exceeds 2000 v hbm per jesd22-a114 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 class ii, level b ? packages offered: tssop28
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 3 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 3. applications ? amusement products ? rgb or rgba led drivers ? led status information ? led displays ? lcd backlights ? keypad backlights for cellular phones or handheld devices 4. ordering information 5. block diagram table 1. ordering information type number topside mark package name description version PCU9655PW pcu9655 tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 PCU9655PW1 pu96551 tssop28 plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 dim repetition rate = 122 hz. blink repetition rate = 15 hz to every 16.8 seconds. fig 1. block diagram of PCU9655PW a0 a1 a2 a3 a4 002aaf629 ufm control input filter pcu9655 power-on reset uscl usda v dd v ss led state select register pwm register x brightness control grpfreq register grppwm register (duty cycle control) mux/ control '0' C permanently off '1' C permanently on dim clock 31.25 khz 256 8 mhz oscillator reset 200 k input filter led0 fet driver led1 led15
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 4 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 6. pinning information 6.1 pinning 6.2 pin description a. PCU9655PW b. PCU9655PW1 fig 2. pin configuration for tssop28 a0 a1 a2 a3 a4 led0 led1 led2 led3 v ss led4 led5 led6 led7 PCU9655PW 002aaf630 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 v dd usda uscl reset v ss led15 led14 led13 led12 v ss led11 led10 led9 led8 a0 a1 a2 a3 a4 v ss led0 led1 led2 led3 led4 led5 led6 led7 PCU9655PW1 002aag257 1 2 3 4 5 6 7 8 9 10 11 12 13 14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 v dd usda uscl n.c. n.c. led15 led14 led13 led12 led11 led10 led9 led8 v ss table 2. pin description symbol pin type description PCU9655PW PCU9655PW1 a0 1 1 i address input 0 [1] a1 2 2 i address input 1 [1] a2 3 3 i address input 2 [1] a3 4 4 i address input 3 [1] a4 5 5 i address input 4 [1] led0 6 7 o led driver 0 led1 7 8 o led driver 1 led2 8 9 o led driver 2 led3 9 10 o led driver 3 v ss 10, 19, 24 6, 15 ground supply ground led4 11 11 o led driver 4 led5 12 12 o led driver 5 led6 13 13 o led driver 6 led7 14 14 o led driver 7 led8 15 16 o led driver 8 led9 16 17 o led driver 9 led10 17 18 o led driver 10
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 5 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver [1] in order to obtain the best system level esd performance, a standard pull-up resistor (10 k ? typical) is required for any address pin connecting to v dd . for additional information on system level esd performance, please refer to appl ication notes an10897 and an11131. 7. functional description refer to figure 1 ? block diagram of PCU9655PW ? . 7.1 device addresses following a start condition, the bus master must output the address of the slave it is accessing. for pcu9655 there are a maximum of 32 possible programmable addresses using the five hardware addres s pins a[4:0]. 7.1.1 regular ufm i 2 c-bus slave address the i 2 c-bus slave address of the pcu9655 is shown in figure 3 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low externally. remark: reserved i 2 c-bus addresses must be used with caution since they can interfere with: ? ?reserved for future use? i 2 c-bus addresses (0000 011, 1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) ? slave devices that are designed to resp ond to the general call address (0000 000) ? high-speed mode (hs-mode) master code (0000 1xx) led11 18 19 o led driver 11 led12 20 20 o led driver 12 led13 21 21 o led driver 13 led14 22 22 o led driver 14 led15 23 23 o led driver 15 reset 25 - i active low reset input n.c. - 24, 25 - do not connect; reserved input uscl 26 26 i ufm serial clock line usda 27 27 i ufm serial data line v dd 28 28 power supply supply voltage table 2. pin description ?continued symbol pin type description PCU9655PW PCU9655PW1
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 6 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver the last bit of the address byte defines the operation to be performed. only writes to pcu9655 are supported, therefore the last bit is set to 0. 7.1.2 led all call ufm i 2 c-bus address ? default power-up value (allcalladr register): a0h or 1010 000x ? programmable through i 2 c-bus (volatile programming) ? at power-up, led all call i 2 c-bus address is enabled see section 7.3.9 ? allcalladr, led all call i 2 c-bus address ? for more detail. remark: the default led all call i 2 c-bus address (a0h or 1010 000x) must not be used as a regular i 2 c-bus slave address since this addre ss is enabled at power-up. all of the pcu9655s on the ufm i 2 c-bus will respond to the address if sent by the i 2 c-bus master. 7.1.3 led sub call ufm i 2 c-bus addresses ? 3 different i 2 c-bus addresses can be used ? default power-up values: ? subadr1 register: ach or 1010 110x ? subadr2 register: ach or 1010 110x ? subadr3 register: ach or 1010 110x ? programmable through ufm i 2 c-bus (volatile programming) ? at power-up, subadr1 is enabled while subadr2 and subadr3 i 2 c-bus addresses are disabled. remark: at power-up subadr1 identifies this device as a 16-channel driver. see section 7.3.8 ? subadr[3:1] led s ub call ufm i 2 c-bus addresses for pcu9655 ? for more detail. remark: the default led sub call i 2 c-bus addresses may be used as regular i 2 c-bus slave addresses as long as they are disabled in bit [3:1] = 000 of mode1 register. 7.2 control register following slave address, led all call address or led sub call address, the bus master will send a byte to the pcu9655, which will be stored in the control register. the lowest 7 bits are used as a pointer to determine which re gister will be accessed (d[6:0]). the highest bit is used as auto-increme nt flag (aif). the aif is active by default at power-up. fig 3. pcu9655 slave address 002aaf631 1 1 a4 a3 a2 a1 a0 0 fixed hardware selectable slave address w (write only)
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 7 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver this aif bit along with the mode1 register bit 5 and bit 6 provide the auto-increment feature. when the auto-increment flag is set (aif = 1), the seven low-order bits of the control register are automatically incremented after a write. this allows the user to program the registers sequentially. four different types of auto-increment are possible, depending on ai1 and ai0 values of mode1 register. [1] ai1 and ai0 come from mode1 register. remark: other combinations not shown in ta b l e 3 (aif + ai[1:0] = 001b, 010b and 011b) are reserved and must not be used for proper device operation. aif + ai[1:0] = 000b is used when the same register must be accessed several times during a single i 2 c-bus communication, for example, changes the brightness of a single led. data is overwritten each time the register is accessed during a write operation. aif + ai[1:0] = 100b is used when all the regist ers, except 42h pwmall register, must be sequentially accessed, for example, power-up programming. aif + ai[1:0] = 101b is used when the 16 led drivers must be individually programmed with different values during the same i 2 c-bus communication, for example, changing color setting to another color setting. aif + ai[1:0] = 110b is used when mode1 to pwm15 registers must be programmed with different settings during the same i 2 c-bus communication. aif + ai[1:0] = 111b is used when the 16 led drivers must be individually programmed with different values in addition to global programming. only the 7 least significant bits d[6:0] ar e affected by the aif, ai1 and ai0 bits. reset state = 80h remark: the control register does not apply to the software reset i 2 c-bus address. fig 4. control register table 3. auto-increment options aif ai1 [1] ai0 [1] function 0 0 0 no auto-increment 1 0 0 auto-increment for registers (00h to 41h) . d[6:0] roll over to 00h after register 41h is accessed. 1 0 1 auto-increment for individual brig htness registers only (0ah to 19h). d[6:0] roll over to 0ah after the last register (19h) is accessed. 1 1 0 auto-increment for mode1 to pwm15 control registers (00h to 19h). d[6:0] roll over to 00h after the last register (19h) is accessed. 1 1 1 auto-increment for global control regi sters and individual brightness registers (08h to 19h). d[6:0] roll over to 08h after the last register (19h) is accessed. 002aad850 aif d6 d5 d4 d3 d2 d1 d0 auto-increment flag register address
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 8 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver when the control register is written, the regi ster entry point determined by d[6:0] is the first register that will be addressed (write operation), and can be anywhere between 00h and 41h (as defined in ta b l e 4 ). when aif = 1, the auto-increment flag is set and the rollover value at which the register incr ement stops and goes to the next one is determined by aif, ai1 and ai0. see ta b l e 3 for rollover values. for example, if mode1 register bit ai1 = 0 and ai0 = 1 and if the cont rol register = 1001 0000, then the register addressing sequence will be (in hexadecimal): 10 ? 11 ? ? ? 19 ? 0a ? 0b ? ? ? 19 ? 0a ? 0b ? ? as long as the master keeps writing data. if mode1 register bit ai1 = 0 and ai0 = 0 and if the control register = 1010 0010, then the register addressing sequen ce will be (in hexadecimal): 22 ? 23 ? ? ? 41 ? 00 ? 01 ? ? ? 19 ? 0a ? 0b ? ? as long as the master keeps writing data. if mode1 register bit ai1 = 0 and ai0 = 1 and if the control register = 1000 0101, then the register addressing sequen ce will be (in hexadecimal): 05 ? 06 ? ? ? 19 ? 0a ? 0b ? ? ? 19 ? 0a ? 0b ? ? as long as the master keeps writing data. 7.3 register definitions table 4. register summary [1] register number (hexadecimal) d6 d5 d4 d3 d2 d1 d0 name type function 00h 0000000mode1 write only mode register 1 01h 0000001mode2 write only mode register 2 02h 0000010ledout0 write only led output state 0 03h 0000011ledout1 write only led output state 1 04h 0000100ledout2 write only led output state 2 05h 0000101ledout3 write only led output state 3 06h 0000110- write only not used [1] 07h 0000111- write only not used [1] 08h 0001000grppwm write only group duty cycle control 09h 0001001grpfreq write only group frequency 0ah 0001010pwm0 write only brightness control led0 0bh 0001011pwm1 write only brightness control led1 0ch 0001100pwm2 write only brightness control led2 0dh 0001101pwm3 write only brightness control led3 0eh 0001110pwm4 write only brightness control led4 0fh 0001111pwm5 write only brightness control led5 10h 0010000pwm6 write only brightness control led6 11h 0010001pwm7 write only brightness control led7 12h 0010010pwm8 write only brightness control led8 13h 0010011pwm9 write only brightness control led9 14h 0010100pwm10 write only brightness control led10
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 9 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver [1] remark: writing to registers marked ?not used? will be ignored. [2] remark: writing to registers marked ?reserved? wi ll not change any functionality in the chip. 15h 0010101pwm11 write only brightness control led11 16h 0010110pwm12 write only brightness control led12 17h 0010111pwm13 write only brightness control led13 18h 0011000pwm14 write only brightness control led14 19h 0011001pwm15 write only brightness control led15 1ah to 39h -------- write onlynot used [1] 3ah 0111010offset write only offset/delay on ledn outputs 3bh 0111011subadr1 write only i 2 c-bus subaddress 1 3ch 0111100subadr2 write only i 2 c-bus subaddress 2 3dh 0111101subadr3 write only i 2 c-bus subaddress 3 3eh 0111110allcalladr write only all call i 2 c-bus address 3fh 0111111r eserved1 write only reserved [2] 40h 1000000r eserved2 write only reserved [2] 41h 1000001r eserved3 write only reserved [2] 42h 1000010pwmall write only brightness control for all ledn 43h to 7fh -------- write onlynot used [1] table 4. register summary [1] ?continued register number (hexadecimal) d6 d5 d4 d3 d2 d1 d0 name type function
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 10 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 7.3.1 mode1 ? mode register 1 [1] it takes 500 ? s max. for the oscillator to be up and running once sleep bit has been set to logic 0. timings on ledn outputs are not guaranteed if pwmx, grppwm or grpfreq registers are accessed within the 500 ? s window. [2] no blinking or dimming is possi ble when the oscillator is off. 7.3.2 mode2 ? mode register 2 [1] change of the outputs at the stop command allows synchroniz ing outputs of more than one pcu9655. applicable to registers fro m 02h (ledout0) to 3ah (offset) only. table 5. mode1 - mode register 1 (address 00h) bit description legend: * default value. bit symbol access value description 7 aif - - not used 6 ai1 w only 0* auto-increment bit 1 = 0. auto-increment range as defined in table 3 . 1 auto-increment bit 1 = 1. auto-increment range as defined in table 3 . 5 ai0 w only 0* auto-increment bit 0 = 0. auto-increment range as defined in table 3 . 1 auto-increment bit 0 = 1. auto-increment range as defined in table 3 . 4 sleep w only 0* normal mode [1] . 1 low power mode. oscillator off [2] . 3 sub1 w only 0 pcu9655 does not respond to i 2 c-bus subaddress 1. 1* pcu9655 responds to i 2 c-bus subaddress 1. 2 sub2 w only 0* pcu9655 does not respond to i 2 c-bus subaddress 2. 1 pcu9655 responds to i 2 c-bus subaddress 2. 1 sub3 w only 0* pcu9655 does not respond to i 2 c-bus subaddress 3. 1 pcu9655 responds to i 2 c-bus subaddress 3. 0 allcall w only 0 pcu9655 does not respond to led all call i 2 c-bus address. 1* pcu9655 responds to led all call i 2 c-bus address. table 6. mode2 - mode register 2 (address 01h) bit description legend: * default value. bit symbol access value description 7 - - - not used 6 - - - not used 5 dmblnk w only 0* group control = dimming 1 group control = blinking 4 - - 0* reserved 3 och w only 0* outputs change on stop command [1] 1 outputs change on ninth clock cycle (uscl) 2 - - 1* reserved 1 - - 0* reserved 0 - - 1* reserved
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 11 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 7.3.3 ledout0 to ledout3, led driver output state ldrx = 00 ? led driver x is off (default power-up state). ldrx = 01 ? led driver x is fully on (individual brightness and group dimming/blinking not controlled). ldrx = 10 ? led driver x individual brightness can be controlled through its pwmx register. ldrx = 11 ? led driver x individual brightness and group dimming/blinking can be controlled through its pwmx register and the grppwm registers. 7.3.4 grppwm, group duty cycle control when dmblnk bit (mode2 register) is programmed with logic 0, a 122 hz fixed frequency signal is superimposed with the 31. 25 khz individual brightness control signal. grppwm is then used as a global brightness control allowing the led outputs to be dimmed with the same value. the value in grpfreq is then a ?don?t care?. general brightness for the 16 outputs is co ntrolled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (9 9.6 % duty cycle = maximum brightness). applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout3 registers). table 7. ledout0 to ledout3 - led driver ou tput state registers (address 02h to 05h) bit description legend: * default value. address register bit symbol access value description 02h ledout0 7:6 ldr3 w only 00* led3 output state control 5:4 ldr2 w only 00* led2 output state control 3:2 ldr1 w only 00* led1 output state control 1:0 ldr0 w only 00* led0 output state control 03h ledout1 7:6 ldr7 w only 00* led7 output state control 5:4 ldr6 w only 00* led6 output state control 3:2 ldr5 w only 00* led5 output state control 1:0 ldr4 w only 00* led4 output state control 04h ledout2 7:6 ldr11 w only 00* le d11 output state control 5:4 ldr10 w only 00* led10 output state control 3:2 ldr9 w only 00* led9 output state control 1:0 ldr8 w only 00* led8 output state control 05h ledout3 7:6 ldr15 w only 00* le d15 output state control 5:4 ldr14 w only 00* led14 output state control 3:2 ldr13 w only 00* led13 output state control 1:0 ldr12 w only 00* led12 output state control table 8. grppwm - group brightness control register (address 08h) bit description legend: * default value address register bit symbol access value description 08h grppwm 7:0 gdc[7:0] w only 1111 1111* grppwm register
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 12 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver when dmblnk bit is programmed with logic 1, grppwm and grpfreq registers define a global blinking pattern, where grpfreq contains the blinking period (from 15 hz to 16.8 s) and grppwm the duty cycle (on/off ratio in %). (1) 7.3.5 grpfreq, group frequency grpfreq is used to program the global blinking period when dmblnk bit (mode2 register) is equal to 1. value in this re gister is a ?don?t care? when dmblnk = 0. applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout3 registers). blinking period is controlled through 256 linear steps from 00h (67 ms, frequency 15 hz) to ffh (16.8 s). (2) 7.3.6 pwm0 to pwm15, individual brightness control duty cycle gdc 7 : 0 ?? 256 -------------------------- = table 9. grpfreq - group frequency register (address 09h) bit description legend: * default value. address register bit symbol access value description 09h grpfreq 7:0 gfrq[7:0] w only 0000 0000* grpfreq register global blinking period gfrq 7 : 0 ?? 1 + 15.26 --------------------------------------- - s ?? = table 10. pwm0 to pwm15 - pwm registers 0 to 15 (address 0ah to 19h) bit description legend: * default value. address register bit symbol access value description 0ah pwm0 7:0 idc0[7:0] w only 0000 0000* pwm0 individual duty cycle 0bh pwm1 7:0 idc1[7:0] w only 0000 0000* pwm1 individual duty cycle 0ch pwm2 7:0 idc2[7:0] w only 0000 0000* pwm2 individual duty cycle 0dh pwm3 7:0 idc3[7:0] w only 0000 0000* pwm3 individual duty cycle 0eh pwm4 7:0 idc4[7:0] w only 0000 0000* pwm4 individual duty cycle 0fh pwm5 7:0 idc5[7:0] w only 0000 0000* pwm5 individual duty cycle 10h pwm6 7:0 idc6[7:0] w only 0000 0000* pwm6 individual duty cycle 11h pwm7 7:0 idc7[7:0] w only 0000 0000* pwm7 individual duty cycle 12h pwm8 7:0 idc8[7:0] w only 0000 0000* pwm8 individual duty cycle 13h pwm9 7:0 idc9[7:0] w only 0000 0000* pwm9 individual duty cycle 14h pwm10 7:0 idc10[7:0] w only 0000 0000* pwm10 individual duty cycle 15h pwm11 7:0 idc11[7:0] w only 0000 0000* pwm11 individual duty cycle 16h pwm12 7:0 idc12[7:0] w only 0000 0000* pwm12 individual duty cycle 17h pwm13 7:0 idc13[7:0] w only 0000 0000* pwm13 individual duty cycle 18h pwm14 7:0 idc14[7:0] w only 0000 0000* pwm14 individual duty cycle 19h pwm15 7:0 idc15[7:0] w only 0000 0000* pwm15 individual duty cycle
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 13 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver a 31.25 khz fixed frequency signal is used fo r each output. duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = led output at maximum brightness). applicable to led outputs programmed with ldrx = 10 or 11 (ledout0 to ledout3 registers). (3) 7.3.7 offset ? ledn output delay offset register the pcu9655 can be programmed to have turn-on delay between led outputs. this helps to reduce peak current for the v dd supply and reduces emi. the order in which the led outputs are enabled will always be the same (channel 0 will enable first an d channel 15 will enable last). offset control register bits [3:0] determine the delay used between the turn-on times as follows: 0000 = no delay between outputs (all on, all off at the same time) 0001 = delay of 1 clock cycle (1 25 ns) between successive outputs 0010 = delay of 2 clock cycles (250 ns) between successive outputs 0011 = delay of 3 clock cycles (375 ns) between successive outputs : 1111 = delay of 15 clock cycles (1.875 ? s) between successive outputs example: if the value in the offset register is 1000 the corresponding delay = 8 ? 125 ns = 1 ? s delay between successive outputs. channel 0 turns on at time 0 ? s channel 1 turns on at time 1 ? s channel 2 turns on at time 2 ? s channel 3 turns on at time 3 ? s channel 4 turns on at time 4 ? s channel 5 turns on at time 5 ? s channel 6 turns on at time 6 ? s channel 7 turns on at time 7 ? s channel 8 turns on at time 8 ? s channel 9 turns on at time 9 ? s channel 10 turns on at time 10 ? s channel 11 turns on at time 11 ? s channel 12 turns on at time 12 ? s duty cycle idcx 7 : 0 ?? 256 --------------------------- = table 11. offset - ledn output delay offset register (address 3ah) bit description legend: * default value. address register bit access value description 3ah offset 7:4 - 0000h* not used 3:0 w only 1000h* ledn output delay offset factor
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 14 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver channel 13 turns on at time 13 ? s channel 14 turns on at time 14 ? s channel 15 turns on at time 15 ? s 7.3.8 subadr[3:1] led sub call ufm i 2 c-bus addresses for pcu9655 default power-up values are ach, ach, ach. at power-up, subadr1 is enabled while subadr2 and subadr3 are disabled. the power-up default bit subaddress of ach indicates that this device is a 16-channel led driver. all three subaddresses are programmable. once subaddresses have been programmed to their right values, subx bits in mode1 register (00h) need to be set to logic 1 in order to have the device respond to these addresses. when subx is set to logic 1, the corresponding i 2 c-bus subaddress can be used during an ufm i 2 c-bus write sequence. 7.3.9 allcalladr, led all call i 2 c-bus address the led all call i 2 c-bus address allows all the pcu9655s on the bus to be programmed at the same time (allcall bit in register mode1 must be equal to logic 1 (power-up default state)). this address is programmable through the i 2 c-bus and can be used during an i 2 c-bus write sequence. the register address can also be programmed as a sub call. only the 7 msbs representing the all call i 2 c-bus address are valid. the lsb in the allcalladr register is a 0. 7.3.10 reserved1 this register is reserved. 7.3.11 reserved2, reserved3 these registers are reserved. table 12. subadr1 to subadr3 - i 2 c-bus subaddress registers 1 to 3 (address 3bh to 3dh) bit description legend: * default value. address register bit symbol access value description 3bh subadr1 7:1 a1[7:1] w only 1010 110* i 2 c-bus subaddress 1 0 a1[0] w only 0* reserved 3ch subadr2 7:1 a2[7:1] w only 1010 110* i 2 c-bus subaddress 2 0 a2[0] w only 0* reserved 3dh subadr3 7:1 a3[7:1] w only 1010 110* i 2 c-bus subaddress 3 0 a3[0] w only 0* reserved table 13. allcalladr - led all call i 2 c-bus address register (address 3eh) bit description legend: * default value. address register bit symbol access value description 3eh allcalladr 7:1 ac[7:1] w only 1010 000* allcall i 2 c-bus address register 0 ac[0] w only 0* reserved
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 15 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 7.3.12 pwmall ? brightness control for all ledn outputs when programmed, the value in this register will be used fo r pwm duty cycle for all the ledn outputs. remark: write to any of the pwm0 to pwm15 registers will overwrite the value in corresponding pwmn register. 7.3.13 overtemperature protection if the pcu9655 chip temperature exceeds its limit (t th(otp) , see ta b l e 1 7 ), all output channels will be disabled unt il the temperature drops belo w its limit minus a small hysteresis (t hys , see ta b l e 1 7 ). once the die temperature reduces below the t th(otp) ? t hys , the chip will return to the same condit ion it was prior to the overtemperature event. 7.4 power-on reset when power is applied to v dd , an internal power-on reset holds the pcu9655 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the pcu9655 registers and i 2 c-bus state machine are initializ ed to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be pulled lower than 1 v and stay low for longer than 20 ? s. the device will reset itself, and allow 2 ms for the device to fully wake up. 7.5 hardware r eset recovery when a reset of pcu9655 is activated using an active low input on the reset pin, a reset pulse width of 2.5 ? s minimum is required. the maximum wait time after reset pin is released is 2 ms. table 14. pwmall - brightness control for all ledn outputs register (address 42h) bit description legend: * default value. address register bit access value description 42h pwmall 7:0 w only 0000 0000h* dut y cycle for all ledn outputs
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 16 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 7.6 software reset the software reset call (swrst call) allows all the devices in the ufm i 2 c-bus to be reset to the power-up state value through a specific formatted i 2 c-bus command. the maximum wait time after software reset is 1 ms. the swrst call function is defined as the following: 1. a start command is sent by the ufm i 2 c-bus master. 2. the reserved general call address ?0000 000? with the w bit set to ?0? (write) is sent by the ufm i 2 c-bus master. 3. since pcu9655 is a ufm i 2 c-bus device, no acknowledge is returned to the i 2 c-bus master. 4. once the general call address has been se nt, the master sends 1 byte with 1 specific value (swrst data byte 1): byte 1 = 06h. if more than 1 byte of data is sent, they will be ignored by the pcu9655. 5. once the correct byte (swrst data byte 1) has been sent, the master sends a stop command to end the swrst function: the pcu9655 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t buf ). remark: the reset stage is also the standby stat e with the internal oscillator turned off. it takes 500 ? s for the oscillator to be up and running on ce the sleep bit has been set to a logic 1. pwm registers should not be accessed within the 500 ? s window. fig 5. swrst call 0 0 0 0 0 0 0 1 s 0 general call address start condition this bit always = 1 002aag258 swrst data byte 1 1 this bit always = 1 p stop condition 0000110 0 w (write bit)
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 17 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 7.7 individual brightness contro l with group dimming/blinking a 31.25 khz fixed frequency signal with progr ammable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each led. on top of this signal, one of the following si gnals can be superimposed (this signal can be applied to the 16 led outputs led0 to led15 because the count started at 0): ? a lower 122 hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. ? a programmable frequency signal from 15 hz to every 16.8 seconds (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. minimum pulse width for ledn brightness control is 125 ns. minimum pulse width for group dimming is 32 ? s. when m = 1 (grppwm register value), the re sulting ledn brightness control + group dimming signal will have 1 pulse of the led brightness control signal (pulse width = n ? 125 ns, with ?n? defined in pwmx register). this resulting brightness + group dimming signal above shows a resulting control signal with m = 8. fig 6. brightness + group dimming signals 123456789101112 251 252 253 254 255 256 1234567891011 brightness control signal (ledn) m 256 125 ns with m = (0 to 255) (grppwm register) n 125 ns with n = (0 to 255) (pwmx register) 256 125 ns = 32 s (31.25 khz) 12345678 12345678 group dimming signal resulting brightness + group dimming signal 256 256 125 ns = 8.19 ms (122 hz) 002aaf935
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 18 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 8. characteristics of the pcu9655 ultra fast-mode i 2 c-bus the pcu9655 led controller uses the new ultra fast-mode (ufm) i 2 c-bus to communicate with the ufm i 2 c-bus capable host controller. like the standard mode and fast-mode plus (fm+) i 2 c-bus, it uses two lines for communication. they are a serial data line (usda) and a serial clock line (uscl). the ufm is a unidirectional bus that is capable of higher frequency (up to 5 mhz). the ufm i 2 c-bus slave devices operate in receive-only mode. that is, only i 2 c writes to pcu9655 are supported. 8.1 bit transfer one data bit is transferred during each cl ock pulse. the data on the usda line must remain stable during the high period of the cl ock pulse as changes in the data line at this time will be interpreted as control signals (see figure 7 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 8 ). fig 7. bit transfer 002aaf113 data line stable; data valid change of data allowed usda uscl fig 8. definition of start and stop conditions 002aaf114 usda uscl p stop condition s start condition
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 19 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 8.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 9 ). 8.3 data transfer the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one bit that is always set to 1. the master gene rates an extra related clock pulse. fig 9. system configuration 002aaf100 slave ufm receiver usda uscl master ufm transmitter slave ufm receiver slave ufm receiver fig 10. data transfer 002aaf101 s start condition 9 8 2 1 usda data output by master ufm transmitter uscl clock from master
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 20 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 9. bus transactions (1) see table 4 for register definition. fig 11. write to a specific register 1 a4 a3 a2 a1 a0 0 1 s 1 slave address start condition w this bit always = 1 002aaf632 data for register d[7:0] d6 d5 d4 d3 d2 d1 d0 aif control register (1) auto-increment flag 1 this bit always = 1 1 this bit always = 1 p stop condition (1) ai1, ai0 = 00. see table 3 for auto-increment options. remark: care should be taken to load the appropriate value here in the ai1 and ai0 bits of the mode1 register for programming the part with the required auto-increment options. fig 12. write to all registers using the auto-increment feature 1 a4 a3 a2 a1 a0 0 1 s 1 slave address start condition w this bit always = 1 002aaf633 mode1 register data (1) 0 0 0 0 0 0 0 1 control register auto-increment on 1 this bit always = 1 1 this bit always = 1 p stop condition (cont.) (cont.) mode1 register selection mode2 register data 1 this bit always = 1 reserved3 register data 1 this bit always = 1
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 21 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver this example assumes that aif + ai[1:0] = 101b. fig 13. multiple writes to indivi dual brightness registers only using the auto-increment feature 1 a4 a3 a2 a1 a0 0 1 s 1 slave address start condition w this bit is always = 1 002aaf634 pwm0 register data 0 0 0 1 0 1 0 1 control register auto-increment on 1 this bit is always = 1 1 this bit is always = 1 p stop condition (cont.) (cont.) pwm0 register selection pwm1 register data 1 this bit is always = 1 pwm14 register data 1 this bit is always = 1 pwm15 register data 1 this bit is always = 1 pwm0 register data 1 this bit is always = 1 register rollover pwm14 register data 1 this bit is always = 1 pwm15 register data 1 this bit is always = 1
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 22 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver (1) in this example, several pcu9655s are used and the same sequence (a) (above) is sent to each of them. (2) allcall bit in mode1 register is pr eviously set to 1 for this example. (3) och bit in mode2 register is prev iously set to 1 for this example. fig 14. led all call i 2 c-bus address programming and led all call sequence example 1 a4 a3 a2 a1 a0 0 1 s 1 slave address (1) start condition w this bit always set to 1 002aaf635 0 1 1 1 1 1 0 1 control register auto-increment on 1 this bit always set to 1 allcalladr register selection 0 1 0 1 0 1 x 1 new led all call i 2 c address (2) p stop condition 1 this bit always set to 1 0 1 0 1 0 1 0 1 s 1 led all call i 2 c address start condition w this bit always set to 1 0 0 0 0 0 1 0 1 control register 1 this bit always set to 1 ledout register selection 1 0 1 0 1 0 1 0 ledout0 register (led fully on) p stop condition 1 the 16 leds are on at the ninth bit (3) sequence (a) sequence (b) (cont.) (cont.) 1 0 1 0 1 0 1 0 ledout1 register (led fully on) 1 the 16 leds are on at the ninth bit (3) 1 0 1 0 1 0 1 0 ledout2 register (led fully on) 1 the 16 leds are on at the ninth bit (3) this bit always set to 1 this bit always set to 1 this bit always set to 1 1 0 1 0 1 0 1 0 ledout3 register (led fully on) 1 the 16 leds are on at the ninth bit (3) this bit always set to 1
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 23 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 10. application design-in information (1) a standard 10 k ? pull-up resistor is required to obtain the best system level esd performance. fig 15. typical application pcu9655 led0 led1 usda uscl reset v dd = 2.5 v, 3.3 v or 5.0 v ufm master usda uscl i/o led2 led3 a0 a1 a2 v dd a3 a4 v ss 10 k up to 40 v led8 led9 led10 led11 led4 led5 led6 led7 up to 40 v led light bar led12 led13 led14 led15 up to 40 v led light bar 002aaf636 v ss up to 40 v 10 k (1)
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 24 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 10.1 thermal considerations since the pcu9655 device integrates 16 volt age switches, thermal considerations should be taken into account to prevent overheating, which can cause the device to go into thermal shutdown. in order to en sure that the device will no t go into thermal shutdo wn when operating under certain application conditions, its junction temperature (t j ) should be calculated to ensure that is below the overtemperature threshold limit (125 ? c). the t j of the device depends on the ambient temperature (t amb ), device?s total power dissipation (p tot ), and thermal resistance. the device junction temperature can be calculated by using the following equation: (4) where: t j = junction temperature t amb = ambient temperature r th(j-a) = junction to ambient thermal resistance p tot = (device) total power dissipation an example of this calculation is show below: conditions: t amb = 50 ? c r th(j-a) = 65 ? c/w (per jedec 51 standard for multilayer pcb) i led = 100 ma / channel i dd(max) = 12 ma v dd = 5 v p tot calculation: p tot = ic_power + led drivers_power; ic_power = (i dd ? v dd ) ic_power = (0.012 a ? 5 v) = 0.06 w led drivers_power = 16 ? (i led 2 ? r on ) led drivers_power = 16 ? ((0.1 a) 2 ? 5 ? ) = 0.8 w p tot = 0.06 w + 0.8 w = 0.86 w t j calculation: t j = t amb + r th(j-a) ? p tot t j = 50 ? c + (65 ? c/w ? 0.86 w) = 105.9 ? c this confirms that the junction temperat ure is below the minimum overtemperature threshold of 125 ? c, which ensures the device will not go into thermal shutdown under these conditions. t j t amb r th j - a ?? p tot ? +=
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 25 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver it is important to mention that the value of the thermal resistance junction-to-ambient (r th(j-a) ) strongly depends on the pcb design. therefore, the device pins should be attached to a big enough pcb copper area to ensure proper thermal dissipation (similar to jedec 51 standard). several thermal vias shou ld be used as well in a multi-layer pcb design to increase the effectiveness of the heat dissipation. finally it is important to poin t out that this calculation should be taken as a reference only and therefore ev aluations should still be performed under the app lication environment and conditions to confirm proper system operation. 11. limiting values [1] class ii, level b for a2, a3. a ll other pins are class ii, level a ( ? 100 ma). 12. thermal characteristics [1] per jedec 51 standard for multilayer pcb. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.0 v v i/o voltage on an input/output pin v ss ? 0.5 5.5 v v drv(led) led driver voltage v ss ? 0.5 40 v i o(ledn) output current on pin ledn - 105 ma i ss ground supply current per v ss pin - 1.0 a i lu latch-up current jesd [1] -9 0m a p tot total power dissipation t amb =25 ? c- 1.54w t amb =85 ? c- 0.61w t stg storage temperature ? 65 +150 ?c t amb ambient temperature operating ? 40 +85 ?c t j junction temperature ? 40 +125 ?c table 16. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient tssop28 [1] 65 ?c/w
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 26 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 13. static characteristics [1] v dd must be lowered to 0.8 v in order to reset part. [2] maximum on-state voltage across the switch. [3] if the ledn output is set to 100 % duty cycle during the shorted condition (v led > 2 3 v dd ), the output will be latched off until the next por. if the ledn output is duty cycling (pwm duty cycle < 100 %), the output will turn off 300 ns after it is turned on during the shorted condition (v led > 2 3 v dd ). table 17. static characteristics v dd = 3 v to 5.5 v; v ss =0v; t amb = ? 40 ? cto+85 ? c; unless otherwise specified. symbol parameter conditions min typ max unit supply v dd supply voltage 3 - 5.5 v i dd supply current on pin v dd ; operating mode; no load; f uscl =5mhz v dd =3.3v - 6.5 16 ma v dd =5.5v - 7.0 16 ma i stb standby current on pin v dd ; no load; f uscl =0hz; mode1[4] = 1; v i =v dd v dd = 3.3 v - 550 950 ? a v dd = 5.5 v - 550 950 ? a v por power-on reset voltage no load; v i =v dd or v ss -2.652.8v v pdr power-down reset voltage no load; v i =v dd or v ss [1] 0.8 1.25 - v input uscl; input usda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i l leakage current v i =v dd or v ss ? 1- +1 ? a c i input capacitance v i =v ss - 6 10 pf led driver outputs (led[15:0]) v drv(led) led driver voltage 0 - 40 v i l(off) off-state leakage current v o =40v ? 1- +1 ? a r on on-state resistance i o = 100 ma; v dd =3v - 2 5.0 ? v trip trip voltage [2] [3] - 2 3 v dd -v i olim output current limit v o =3v; v dd =5v - 0.4 0.6 a c o output capacitance - 2.5 5 pf address inputs, reset input v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 ? a c i input capacitance - 3.7 5 pf overtemperature protection t th(otp) overtemperature protection threshold temperature rising 125 - 150 ?c t hys hysteresis temperature - 20 - ?c
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 27 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 14. dynamic characteristics [1] minimum uscl clock frequency is limited by the bus time-out feature, which resets t he serial bus interface if either usda or uscl is held low for a minimum of 25 ms. disable bus time-out feature for dc operation. [2] from led off to fully on, led fully on to off, or led individual brightness control to off. [3] for led off state to on with individual brightness control or for changes in the individual brightness control value, there is a synchronization that may take up to 15 ? s for the change to take effect. table 18. dynamic characteristics all the timing limits are valid within the operating supply voltage and ambient temperature range; v dd =3v ? 0.2 v and 5.5 v ? 0.3 v; t amb = ? 40 ? c to +85 ? c; and refer to v il and v ih with an input voltage of v ss to v dd . symbol parameter conditions min typ max unit f uscl uscl clock frequency [1] 0- 5mhz t buf bus free time between a stop and start condition 0.08 - - ? s t hd;sta hold time (repeated) start condition 0.05 - - ? s t su;sta set-up time for a repeated start condition 0.05 - - ? s t su;sto set-up time for stop condition 0.05 - - ? s t hd;dat data hold time 10 - - ns t su;dat data set-up time 30 - - ns t low low period of the uscl clock 50 - - ns t high high period of the uscl clock 50 - ns t f fall time of both usda and uscl signals - 50 ns t r rise time of both usda and uscl signals - 50 ns t sp pulse width of spikes that must be suppressed by the input filter -10ns output port timing [2] [3] t d(uscl-q) delay time from uscl to data output uscl to ledn; mode2[3] = 1; ledoutx = 01; outputs change on ninth clock cycle (uscl) --450ns t d(usda-q) delay time from usda to data output usda to ledn; mode2[3] = 0; ledoutx = 01; outputs change on stop condition --450ns
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 28 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver fig 16. definition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto usda uscl 002aaf115 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd rise and fall times refer to v il and v ih . fig 17. ufm i 2 c-bus timing diagram uscl usda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high 002aag614 t su;sto protocol start condition (s) bit 7 msb bit 6 bit 1 (d1) bit 0 (d0) 1 / f uscl t r (always set to 1 by master) stop condition (p) 9th clock 0.3 v dd 0.7 v dd 0.3 v dd 0.7 v dd output data led[0:15] t d(uscl-q) t d(usda-q) output data led[0:15]
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 29 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 15. test information r l = load resistor for ledn. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 18. test circuitry for switching times pulse generator v o c l 50 pf r l 50 002aag290 r t v i v dd dut v dd
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 30 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 16. package outline fig 19. package outline sot361-1 (tssop28) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot361-1 mo-153 99-12-27 03-02-19 0.25 w m b p z e 11 4 28 15 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm sot361-1 a max. 1.1
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 31 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 17. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 18. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 18.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 18.3 wave soldering key characteristics in wave soldering are:
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 32 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 18.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 20 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 9 and 20 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 20 . table 19. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 20. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 33 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 19. abbreviations msl: moisture sensitivity level fig 20. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 21. abbreviations acronym description cdm charged-device model dut device under test esd electrostatic discharge fet field-effect transistor hbm human body model i 2 c-bus inter-integrated circuit bus led light emitting diode lcd liquid crystal display lsb least significant bit msb most significant bit nmos negative-channel metal-oxide semiconductor pcb printed-circuit board pmos positive-channel metal-oxide semiconductor pwm pulse width modulation rgb red/green/blue rgba red/green/blue/amber smbus system management bus ufm ultra fast mode
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 34 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 20. references [1] an10897, ?a guide to designing for esd and emc? ? nxp semiconductors [2] an11131, ?how to improve system level esd performance? ? nxp semiconductors 21. revision history table 22. revision history document id release date data sheet status change notice supersedes pcu9655 v.2 20121002 product data sheet - pcu9655 v.1 modifications: ? figure 2 b: sub-title corrected from ?pcu9665pw1? to ?PCU9655PW1? ? section 7.2 ? control register ? , second paragraph on page 8: changed from ?ai0 = 1? to ?ai0 = 0? ? table 5 ? mode1 - mode register 1 (address 00h) bit description ? , table note [1] : changed from ?set to logic 1? to ?set to logic 0? ? section 7.5 ? hardware reset recovery ? : first paragraph, second s entence: deleted ?(typical)? ? section 7.6 ? software reset ? : second paragraph, first sentence: deleted ?(typical)? ? table 18 ? dynamic characteristics ? : added sub-section ?output port timing? ? figure 17 ? ufm i 2 c-bus timing diagram ? updated (added t d(uscl-q) and t d(usda-q) timing) pcu9655 v.1 20111117 product data sheet - -
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 35 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 22.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 22.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pcu9655 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 2 ? 2 october 2012 36 of 37 nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 22.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 23. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pcu9655 16-channel ufm 5 mhz bus 100 ma 40 v led driver ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 2 october 2012 document identifier: pcu9655 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 24. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 5 7.1 device addresses . . . . . . . . . . . . . . . . . . . . . . . 5 7.1.1 regular ufm i 2 c-bus slave address . . . . . . . . 5 7.1.2 led all call ufm i 2 c-bus address. . . . . . . . . . 6 7.1.3 led sub call ufm i 2 c-bus addresses. . . . . . . 6 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.3 register definitions . . . . . . . . . . . . . . . . . . . . . . 8 7.3.1 mode1 ? mode register 1 . . . . . . . . . . . . . . 10 7.3.2 mode2 ? mode register 2 . . . . . . . . . . . . . . 10 7.3.3 ledout0 to ledout 3, led driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7.3.4 grppwm, group duty cycle control . . . . . . . . 11 7.3.5 grpfreq, group frequency . . . . . . . . . . . . . 12 7.3.6 pwm0 to pwm15, individual brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.3.7 offset ? ledn output delay offset register 13 7.3.8 subadr[3:1] led sub call ufm i 2 c-bus addresses for pcu9655 . . . . . . . . . . . . . . . . . 14 7.3.9 allcalladr, led all call i 2 c-bus address. 14 7.3.10 reserved1 . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3.11 reserved2, reserved3 . . . . . . . . . . . . . 14 7.3.12 pwmall ? brightness control for all ledn outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.13 overtemper ature protection . . . . . . . . . . . . . . 15 7.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 hardware reset recovery . . . . . . . . . . . . . . . . 15 7.6 software reset. . . . . . . . . . . . . . . . . . . . . . . . . 16 7.7 individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 17 8 characteristics of the pcu9655 ultra fast-mode i 2 c-bus . . . . . . . . . . . . . . . . . . . . . . 18 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1.1 start and stop conditions . . . . . . . . . . . . . 18 8.2 system configuration . . . . . . . . . . . . . . . . . . . 19 8.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 20 10 application design-in information . . . . . . . . . 23 10.1 thermal considerations . . . . . . . . . . . . . . . . . 24 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 12 thermal characteristics . . . . . . . . . . . . . . . . . 25 13 static characteristics . . . . . . . . . . . . . . . . . . . 26 14 dynamic characteristics. . . . . . . . . . . . . . . . . 27 15 test information . . . . . . . . . . . . . . . . . . . . . . . 29 16 package outline. . . . . . . . . . . . . . . . . . . . . . . . 30 17 handling information . . . . . . . . . . . . . . . . . . . 31 18 soldering of smd packages . . . . . . . . . . . . . . 31 18.1 introduction to soldering. . . . . . . . . . . . . . . . . 31 18.2 wave and reflow soldering. . . . . . . . . . . . . . . 31 18.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 31 18.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 32 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 33 20 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 34 22 legal information . . . . . . . . . . . . . . . . . . . . . . 35 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 35 22.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 35 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 36 23 contact information . . . . . . . . . . . . . . . . . . . . 36 24 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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