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| 8 bit microcontroller tlcs-870/c series TMP86FH92DMG
? 2009 toshiba corporation all rights reserved precaution for using the emulation chip / difference among products (1) precaution for using the emulation chip (development tool) ? precaution for debugging the voltage detection circuit the functions of the voltage detection circuit vary between the TMP86FH92DMG and the emulation chip tmp86c993xb. therefore, please ensure that the final verification of software operation related to the voltage detection circuit is conducted with the TMP86FH92DMG. for details, refer to the chapter on the voltage detection circuit. ? precaution for debugging the power-on reset circuit the power-on reset circuit cannot be emulated with the tmp86c993xb. therefore, when using the de- velopment tool for debugging, ensure that operation is performed within the operating voltage range of the TMP86FH92DMG. for the operating voltage range, refer to the chapter on electrical characteristics. ? precaution for debugging the flash control register although the TMP86FH92DMG contains the flash control register (flscr) at 0fffh in the dbr area, the tmp86c993xb do not contain the flscr register. therefore, when using the development tool for debugging, a program that accesses the flscr register cannot function properly (executes differently as in the case of TMP86FH92DMG). TMP86FH92DMG (2) difference among products ? differences in functions producrs TMP86FH92DMG tmp86fh93ng cpucore tlcs-870/c rom 16k bytes (flash) ram 512 bytes interrrupt 22 interrupts (external:5 internal:17) i/o 24 pins 26 pins port 0 8pins(large current output/sink open-drain or c-mos output/with programmable pull-up resistance) port 1 5 pins 7pins (sink-opendrain or c-mos output/with programmable pull-up resistance) port 2 3 pins (p20 is addition programmable pull-up resistance) port 3 8 pins watchdog timer 1 channel timer/counter 16 bit: 1 channel 8 bit: 2 channels uart 2 channels (1 channel is shared with i 2 c bus) 2 channels serial bus interface (i 2 c bus) 1 channel (shared with uart) sda(p13) and scl(p14) are fixed 1 channel sda(p13) and scl(p14) or sda(p15) and scl(p16) are selectable sei 1 channel 10 bit adconverter 6 channels key-on wake-up 4 channels clock oscillation circuit 2 circuits (single / dual clock modes are selectable) low power consumption operating 9 modes (stop/slow1/slow2/idle0/idle1/idle2/sleep0/sleep1/sleep2) otehr functions power on reset circuit low voltage detector circuit operating voltage(vdd) 4.0v to 5.5v (at 16mhz / 32.768khz) 2.7v to 5.5v (at 8mhz / 32.768khz) package 30pin (ssop30-p-56-0.65) 32pin (sdip32-p-400-1.78) ? difference in electrical characteristics TMP86FH92DMG tmp86fh93ng operating condition (mcu mode) read/fetch 3.0v to 5.5v (-40 to 85c) 2.7v to 3.0v (-20 to 85c) erase/ program 4.5v to 5.5v (-10 to 40c) operating condition (serial prom mode) 4.5v to 5.5v (-10 to 40c) TMP86FH92DMG revision history date revision 2007/4/19 1 first release 2007/5/17 2 contents revised 2007/6/26 3 contents revised 2008/1/31 4 contents revised 2008/2/27 5 contents revised 2008/9/26 6 contents revised 2009/8/24 7 contents revised table of contents precaution for using the emulation chip / difference among products TMP86FH92DMG 1.1 features...................................................................................................................................... 1 1.2 pin assignment.......................................................................................................................... 3 1.3 block diagram........................................................................................................................... 4 1.4 pin names and functions.......................................................................................................... 5 2. operational description 2.1 cpu core functions ................................................................................................................. 7 2.1.1 memory address map ........................................................................................................................................................ 7 2.1.2 program memory (flash) .................................................................................................................................................... 7 2.1.3 data memory (ram) ......................................................................................................................................................... 7 2.2 system clock controller ........................................................................................................... 8 2.2.1 clock generator .................................................................................................................................................................. 8 2.2.2 timing generator ................................................................................................................................................................9 2.2.2.1 configuration of timing generator 2.2.2.2 machine cycle 2.2.3 operation mode control circuit ....................................................................................................................................... 11 2.2.3.1 single-clock mode 2.2.3.2 dual-clock mode 2.2.3.3 stop mode 2.2.3.4 operating mode transition 2.2.4 operating mode control ................................................................................................................................................... 16 2.2.4.1 stop mode 2.2.4.2 idle1/2 mode and sleep1/2 mode 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) 2.2.4.4 slow mode 2.3 reset circuit ........................................................................................................................... 30 2.3.1 external reset input .......................................................................................................................................................... 30 2.3.2 address trap reset .............................................................................................................................................................. 31 2.3.3 watchdog timer reset ........................................................................................................................................................ 31 2.3.4 system clock reset ............................................................................................................................................................ 31 2.3.5 power-on reset.................................................................................................................................................................. 32 2.3.6 voltage detection reset....................................................................................................................................................... 32 2.3.7 trimming data reset........................................................................................................................................................... 32 2.4 internal reset detection flags................................................................................................. 33 3. interrupt control circuit 3.1 interrupt latches (il21 to il2) ................................................................................................ 36 3.2 interrupt enable register (eir) ................................................................................................ 36 3.2.1 interrupt master enable flag (imf) ................................................................................................................................... 36 3.2.2 individual interrupt enable flags (ef21 to ef4) ............................................................................................................... 37 3.3 interrupt sequence ................................................................................................................. 38 3.3.1 interrupt acceptance processing is packaged as follows. .................................................................................................. 38 i 3.3.2 saving/restoring general-purpose registers ....................................................................................................................... 39 3.3.2.1 using push and pop instructions 3.3.2.2 using data transfer instructions 3.3.3 interrupt return .................................................................................................................................................................. 42 3.4 software interrupt (intsw) ................................................................................................... 42 3.4.1 address error detection ..................................................................................................................................................... 42 3.4.2 debugging .........................................................................................................................................................................43 3.5 undefined instruction interrupt (intundef) ...................................................................... 43 3.6 address trap interrupt (intatrap) .................................................................................... 43 3.7 external interrupts .................................................................................................................. 44 4. special function register (sfr) 4.1 sfr.......................................................................................................................................... 47 4.2 dbr......................................................................................................................................... 49 5. i/o ports 5.1 p0 (p07 to p00) port (high current) ...................................................................................... 52 5.2 p1 (p14 to p10) port ............................................................................................................... 54 5.3 p2 (p22 to p20) port ............................................................................................................... 56 5.4 p3 (p37 to p30) port................................................................................................................ 58 6. power-on reset circuit 6.1 power-on reset circuit ............................................................................................................. 61 6.1.1 configuration .................................................................................................................................................................... 61 6.1.2 function.............................................................................................................................................................................. 61 7. voltage detection circuit (vltd) 7.1 configuration........................................................................................................................... 63 7.2 control..................................................................................................................................... 64 7.3 function................................................................................................................................... 66 7.3.1 enabling/disabling voltage detection operation............................................................................................................. 66 7.3.2 selecting the voltage detect operating mode.................................................................................................................. 66 7.3.3 detection voltage level section.......................................................................................................................................... 67 7.3.4 voltage detection flag and voltage detection status flag................................................................................................... 67 7.4 setting of register.....................................................................................................................68 7.4.1 setting procedure for generate an interrupt...................................................................................................................... 68 7.4.2 setting procedure to generate a reset ................................................................................................................................ 69 8. watchdog timer (wdt) 8.1 watchdog timer configuration ..............................................................................................71 8.2 watchdog timer control ........................................................................................................ 72 8.2.1 malfunction detection methods using the watchdog timer .......................................................................................... 72 8.2.2 watchdog timer enable ................................................................................................................................................... 73 8.2.3 watchdog timer disable .................................................................................................................................................. 74 8.2.4 watchdog timer interrupt (intwdt) ............................................................................................................................. 74 ii 8.2.5 watchdog timer reset ..................................................................................................................................................... 75 8.3 address trap ...........................................................................................................................76 8.3.1 selection of address trap in internal ram (atas) ....................................................................................................... 76 8.3.2 selection of operation at address trap (atout) .......................................................................................................... 76 8.3.3 address trap interrupt (intatrap)............................................................................................................................... 76 8.3.4 address trap reset............................................................................................................................................................ 77 9. time base timer (tbt) 9.1 time base timer..................................................................................................................... 79 9.1.1 configuration..................................................................................................................................................................... 79 9.1.2 control............................................................................................................................................................................... 79 9.1.3 function............................................................................................................................................................................. 80 9.2 divider output (dvo).............................................................................................................81 9.2.1 configuration..................................................................................................................................................................... 81 9.2.2 control............................................................................................................................................................................... 81 10. 16-bit timer/counter 1 (tc1) 10.1 configuration......................................................................................................................... 83 10.2 timer/counter control.......................................................................................................... 84 10.3 function................................................................................................................................. 86 10.3.1 timer mode......................................................................................................................................................................86 10.3.2 external trigger timer mode.......................................................................................................................................... 88 10.3.3 event counter mode........................................................................................................................................................ 90 10.3.4 window mode................................................................................................................................................................. 91 10.3.5 pulse width measurement mode.....................................................................................................................................92 10.3.6 programmable pulse generate (ppg) output mode....................................................................................................... 95 11. 8-bit timercounter (tc3, tc4) 11.1 configuration ........................................................................................................................ 99 11.2 timercounter control......................................................................................................... 100 11.3 function............................................................................................................................... 105 11.3.1 8-bit timer mode (tc3 and 4)...................................................................................................................................... 105 11.3.2 8-bit event counter mode (tc3, 4).............................................................................................................................. 106 11.3.3 8-bit programmable divider output (pdo) mode (tc3, 4)......................................................................................... 106 11.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4).................................................................................... 109 11.3.5 16-bit timer mode (tc3 and 4).................................................................................................................................... 111 11.3.6 16-bit event counter mode (tc3 and 4)...................................................................................................................... 112 11.3.7 16-bit pulse width modulation (pwm) output mode (tc3 and 4)............................................................................. 112 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4)...................................................................... 115 11.3.9 warm-up counter mode............................................................................................................................................... 117 11.3.9.1 low-frequency warm-up counter mode (normal1 normal2 slow2 slow1) 11.3.9.2 high-frequency warm-up counter mode (slow1 slow2 normal2 normal1) 12. asynchronous serial interface (uart1) 12.1 configuration ...................................................................................................................... 119 12.2 control ................................................................................................................................ 120 12.3 transfer data format...........................................................................................................123 12.4 transfer rate....................................................................................................................... 124 iii 12.5 data sampling method........................................................................................................ 124 12.6 stop bit length................................................................................................................. 125 12.7 parity.................................................................................................................................... 125 12.8 transmit/receive operation................................................................................................ 125 12.8.1 data transmit operation............................................................................................................................................... 125 12.8.2 data receive operation................................................................................................................................................. 125 12.9 status flag........................................................................................................................... 126 12.9.1 parity error.................................................................................................................................................................... 126 12.9.2 framing error................................................................................................................................................................ 126 12.9.3 overrun error................................................................................................................................................................. 126 12.9.4 receive data buffer full............................................................................................................................................... 127 12.9.5 transmit data buffer empty......................................................................................................................................... 127 12.9.6 transmit end flag......................................................................................................................................................... 128 13. asynchronous serial interface (uart2) 13.1 configuration ...................................................................................................................... 129 13.2 control ................................................................................................................................ 130 13.3 transfer data format........................................................................................................... 133 13.4 transfer rate....................................................................................................................... 134 13.5 data sampling method........................................................................................................ 134 13.6 stop bit length................................................................................................................. 135 13.7 parity.................................................................................................................................... 135 13.8 transmit/receive operation................................................................................................ 135 13.8.1 data transmit operation............................................................................................................................................... 135 13.8.2 data receive operation................................................................................................................................................. 135 13.9 status flag........................................................................................................................... 136 13.9.1 parity error.................................................................................................................................................................... 136 13.9.2 framing error................................................................................................................................................................ 136 13.9.3 overrun error................................................................................................................................................................. 136 13.9.4 receive data buffer full............................................................................................................................................... 137 13.9.5 transmit data buffer empty......................................................................................................................................... 137 13.9.6 transmit end flag......................................................................................................................................................... 138 14. serial expansion interface (sei) 14.1 features ............................................................................................................................... 139 14.2 sei registers ...................................................................................................................... 140 14.2.1 sei control register (secr)........................................................................................................................................ 140 14.2.1.1 transfer rate 14.2.2 sei status register (sesr)........................................................................................................................................... 141 14.2.3 sei data register (sedr)............................................................................................................................................. 141 14.3 sei operation ..................................................................................................................... 142 14.3.1 controlling sei clock polarity and phase ..................................................................................................................... 142 14.3.2 sei data and clock timing ............................................................................................................................................. 142 14.4 sei pin functions ............................................................................................................... 143 14.4.1 sclk pin ...................................................................................................................................................................... 143 14.4.2 miso/mosi pins .......................................................................................................................................................... 143 14.4.3 ss pin ............................................................................................................................................................................ 143 14.5 sei transfer formats .......................................................................................................... 144 14.5.1 cpha (secr register bit 2) = 0 format ....................................................................................................................... 144 14.5.2 cpha = 1 format .......................................................................................................................................................... 145 14.6 functional description......................................................................................................... 146 14.7 interrupt generation ............................................................................................................ 147 14.8 sei system errors ............................................................................................................... 147 iv 14.8.1 write collision error....................................................................................................................................................... 147 14.8.2 overflow error .............................................................................................................................................................. 147 14.8.3 mode fault error ............................................................................................................................................................ 148 14.9 bus driver protection ......................................................................................................... 148 15. serial bus interface(i 2 c bus) ver.-d (sbi) 15.1 configuration ...................................................................................................................... 149 15.2 control ................................................................................................................................ 149 15.3 software reset..................................................................................................................... 149 15.4 the data format in the i2c bus mode .............................................................................. 150 15.5 i2c bus control................................................................................................................... 151 15.5.1 acknowledgement mode specification ......................................................................................................................... 153 15.5.1.1 acknowledgment mode (ack = 1) 15.5.1.2 non-acknowledgment mode (ack = 0) 15.5.2 number of transfer bits.................................................................................................................................................. 154 15.5.3 serial clock ................................................................................................................................................................... 154 15.5.3.1 clock source 15.5.3.2 clock synchronization 15.5.4 slave address and address recognition mode specification........................................................................................... 155 15.5.5 master/slave selection....................................................................................................................................................155 15.5.6 transmitter/receiver selection........................................................................................................................................ 155 15.5.7 start/stop condition generation...................................................................................................................................... 156 15.5.8 interrupt service request and cancel............................................................................................................................... 157 15.5.9 setting of i2c bus mode................................................................................................................................................ 157 15.5.10 arbitration lost detection monitor................................................................................................................................ 157 15.5.11 slave address match detection monitor....................................................................................................................... 158 15.5.12 general call detection monitor.......................................................................................................................... 159 15.5.13 last received bit monitor............................................................................................................................................. 159 15.6 data transfer of i2c bus.....................................................................................................159 15.6.1 device initialization....................................................................................................................................................... 159 15.6.2 start condition and slave address generation................................................................................................................. 159 15.6.3 1-word data transfer....................................................................................................................................................... 160 15.6.3.1 when the mst is 1 (master mode) 15.6.3.2 when the mst is 0 (slave mode) 15.6.4 stop condition generation.............................................................................................................................................. 163 15.6.5 restart............................................................................................................................................................................ 163 16. 10-bit ad converter (adc) 16.1 configuration ...................................................................................................................... 165 16.2 register configuration......................................................................................................... 166 16.3 function.............................................................................................................................. 169 16.3.1 software start mode...................................................................................................................................................... 169 16.3.2 repeat mode.................................................................................................................................................................. 169 16.3.3 register setting.............................................................................................................................................................170 16.4 stop/slow modes during ad conversion...................................................................... 171 16.5 analog input voltage and ad conversion result.............................................................. 172 16.6 precautions about ad converter......................................................................................... 173 16.6.1 analog input pin voltage range......................................................................................................................................173 16.6.2 analog input shared pins............................................................................................................................................... 173 16.6.3 noise countermeasure................................................................................................................................................... 173 17. key-on wakeup (kwu) 17.1 configuration....................................................................................................................... 175 v 17.2 control................................................................................................................................. 176 18. flash memory 18.1 flash memory control......................................................................................................... 178 18.1.1 flash memory command sequence execution control (flscr 20. input/output circuitry 20.1 control pins......................................................................................................................... 217 20.2 input/output ports............................................................................................................... 218 21. electrical characteristics 21.1 absolute maximum ratings................................................................................................ 221 21.2 operating conditions........................................................................................................... 222 21.2.1 mcu mode (flash programming or erasing) ............................................................................................................... 222 21.2.2 mcu mode (except flash programming or erasing) ................................................................................................... 222 21.2.3 serial prom mode........................................................................................................................................................ 223 21.3 dc characteristics .............................................................................................................. 224 21.4 ad conversion characteristics........................................................................................... 226 21.5 power-on reset circuit characteristics................................................................................. 226 21.6 voltage detection circuit characteristics.............................................................................. 227 21.7 ac characteristics............................................................................................................... 228 21.8 flash characteristics............................................................................................................ 228 21.8.1 write/erase characteristics............................................................................................................................................ 228 21.9 oscillating conditions......................................................................................................... 229 21.10 handling precaution.......................................................................................................... 230 22. package dimensions vii viii cmos 8-bit microcontroller TMP86FH92DMG product no. rom (flash) ram package emulation chip TMP86FH92DMG 16384 bytes 512 bytes ssop30-p-56-0.65 tmp86c993xb 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 22interrupt sources (external : 5 internal : 17) 3. input / output ports (24 pins) large current output: 8pins (typ. 20ma), led direct drive 4. power-on reset circuit 5. voltage detection circuit 6. watchdog timer 7. prescaler - time base timer - divider output function 8. 16-bit timer counter: 1 ch - timer, external trigger, window, pulse width measurement, event counter, programmable pulse generate (ppg) modes 9. 8-bit timer counter : 2 ch - timer, event counter, programmable divider output (pdo), pulse width modulation (pwm) output, programmable pulse generation (ppg), 16bit mode (8bit timer 2ch combination) modes 10. 8-bit uart : 2 ch 11. 8bit serial expansion interface (sei): 1 channel (msb/lsb selectable and max. 4mbps at 16mhz) 12. serial bus interface(i 2 c bus): 1ch 13. 10-bit successive approximation type ad converter - analog input: 6 ch 14. key-on wakeup : 4 channels 15. clock operation single clock mode dual clock mode 16. low power consumption operation this product uses the super flash? technology under the licence of silicon storage technology, inc. super flash? is registered trademark of silicon storage technology, inc. TMP86FH92DMG page 1 stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation using low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation using low-frequency clock.(high-frequency clock os- cillate.) idle0 mode: cpu stops, and only the time-based-timer(tbt) on peripherals operate using high fre- quency clock. release by falling edge of the source clock which is set by tbtcr 1.2 pin assignment vss p37 (ain5/stop5) xin p36 (ain4/stop4) xout p35 (ain3/stop3) test p34 (ain2/stop2) vdd p33 (ain1) (xtin) p21 p32 (ain0) (xtout) p22 p31 (tc4/ pdo4/pwm4/ppg4) reset p30 (tc3/ pdo3/pwm3) ( int5/ stop) p20 p12 ( dvo) (txd1) p00 p11 (int1) (boot/rxd1) p01 p10 ( int0) (sclk) p02 p07 (tc1/int4) (mosi) p03 p06 (int3/ ppg) (miso) p04 p14 (scl/txd2) ( ss) p05 p13 (sda/rxd2) figure 1-1 pin assignment TMP86FH92DMG page 3 1.3 block diagram figure 1-2 block diagram TMP86FH92DMG 1.3 block diagram page 4 1.4 pin names and functions the TMP86FH92DMG has mcu mode, parallel prom mode, and serial prom mode. table 1-1 shows the pin functions in mcu mode. the serial prom mode is explained later in a separate chapter. table 1-1 pin names and functions(1/2) pin name pin number input/output functions p07 tc1 int4 19 io i i port07 tc1 input external interrupt 4 input p06 int3 ppg 18 io i o port06 external interrupt 3 input ppg output p05 ss 15 io i port05 sei master/slave select input p04 miso 14 io io port04 sei master input, slave output p03 mosi 13 io io port03 sei master input, slave output p02 sclk 12 io io port02 sei serial clock input/output pin p01 rxd1 boot 11 io i i port01 uart data input 1 serial prom mode control input p00 txd1 10 io o port00 uart data output 1 p14 scl txd2 17 io io o port14 i2c bus clock uart data output 2 p13 sda rxd2 16 io io i port13 i2c bus data uart data input 2 p12 dvo 22 io o port12 divider output p11 int1 21 io i port11 external interrupt 1 input p10 int0 20 io i port10 external interrupt 0 input p22 xtout 7 io o port22 resonator connecting pins(32.768khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768khz) for inputting external clock p20 stop int5 9 io i i port20 stop mode release signal input external interrupt 5 input TMP86FH92DMG page 5 table 1-1 pin names and functions(2/2) pin name pin number input/output functions p37 ain5 stop5 30 io i i port37 analog input5 stop5 p36 ain4 stop4 29 io i i port36 analog input4 stop4 p35 ain3 stop3 28 io i i port35 analog input3 stop3 p34 ain2 stop2 27 io i i port34 analog input2 stop2 p33 ain1 26 io i port33 analog input1 p32 ain0 25 io i port32 analog input0 p31 tc4 pdo4/pwm4/ppg4 24 io i o port31 tc4 input pdo4/pwm4/ppg4 output p30 tc3 pdo3/pwm3 23 io i o port30 tc3 input pdo3/pwm3 output xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal test 4 i test pin for out-going test. normally, be fixed to low. vdd 5 i +5v vss 1 i 0(gnd) TMP86FH92DMG 1.4 pin names and functions page 6 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system clock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FH92DMG memory is composed flash, ram, dbr(data buffer register) and sfr(special func- tion register). they are all mapped in 64-kbyte address space. figure 2-1 shows the TMP86FH92DMG memory address map. sfr 0000 h 64 bytes sfr: ram: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word random access memory includes: data memory stack 003f h ram 0040 h 512 bytes 023f h dbr 0f80 h 128 bytes dbr: data buffer register includes: peripheral control registers peripheral status registers 0fff h c000 h flash: program memory flash 16384 bytes ffb0 h vector table for interrupts (16 bytes) ffbf h ffc0 h vector table for vector call instructions (32 bytes) ffdf h ffe0 h vector table for interrupts (32 bytes) ffff h figure 2-1 memory address map 2.1.2 program memory (flash) the TMP86FH92DMG has a 16384 bytes (address c000h to ffffh) of program memory (flash). 2.1.3 data memory (ram) the TMP86FH92DMG has 512bytes (address 0040h to 023fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are located in the direct area; instructions with shorten operations are available against such an area. TMP86FH92DMG page 7 the data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. example :clears ram to 00h. (TMP86FH92DMG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 01ffh sramclr: ld (hl), a inc hl dec bc jrs f, sramclr 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 system clock control 2.2.1 clock generator the clock generator generates the basic clock which provides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation circuits: one for the high-frequency clock and one for the low- frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the xin/xout and xtin/xtout pins respectively. clock input from an external oscillator is also possible. in this case, external clock is applied to xin/xtin pin with xout/xtout pin not connected. TMP86FH92DMG 2. operational description 2.2 system clock controller page 8 tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. 2.2.2 timing generator the timing generator generates the various system clocks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, syscr2 figure 2-4 configuration of timing generator TMP86FH92DMG 2. operational description 2.2 system clock controller page 10 multi- plexer high-frequency clock fc low-frequency clock fs divider sysck fc/4 fc or fs machine cycle counters main system clock generator 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 dv7ck multiplexer warm-up controller watchdog timer a s b y s b0 a0 y0 b1 a1 y1 5 6 17 18 19 20 21 timer counter, serial interface, time-base-timer, divider output, etc. (peripheral functions) timing generator control register tbtcr (0036h) 7 6 5 4 3 2 1 0 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w note 1: in single clock mode, do not set dv7ck to 1. note 2: do not set 1 on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operation are synchronized with the main system clock. the minimum instruction execution unit is called an machine cycle. there are a total of 10 different types of instructions for the tlcs-870/c series: ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are three operating modes: single clock mode, dual clock mode and stop mode. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequency clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports. the main-system clock is obtained from the high-frequency clock. in the single- clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip peripherals operate using the high-frequency clock. the TMP86FH92DMG is placed in this mode after reset. TMP86FH92DMG page 11 main system clock state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 1/fc or 1/fs [s] (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2 switching back and forth between slow1 and slow2 modes are performed by syscr2 2.2.3.4 operating mode transition note 1: normal1 and normal2 modes are generically called normal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2: the mode is released by falling edge of tbtcr table 2-1 operating mode and conditions operating mode oscillator cpu core wdt tbt ad converter power-on rest voltage detect reset other peripherals machine cycle time high frequency low frequency single clock reset oscillation stop reset reset reset reset operate reset 4/fc [s] normal1 operate operate operate operate operate idle1 halt halt idle0 halt halt stop stop halt - dual clock normal2 oscillation oscillation operate with high-freq. operate with high or low- freq. operate operate operate operate 4/fs [s] idle2 halt halt slow2 operate with low-freq. operate with low-freq. halt 4/fs [s] sleep2 halt halt slow1 stop operate with low-freq. operate with low-freq. sleep1 halt halt sleep0 halt stop stop halt halt - TMP86FH92DMG page 15 2.2.4 operating mode control system control register 1 syscr1 7 6 5 4 3 2 1 0 (0038h) stop relm retm outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release r/w retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode r/w outen port output during stop mode 0: high impedance 1: output kept r/w wut warm-up time at releasing stop mode return to normal mode return to slow mode r/w 00 01 10 11 3 x 2 16 /fc 2 16 /fc 3 x 2 14 /fc 2 14 /fc 3 x 2 13 /fs 2 13 /fs 3 x 2 6 /fs 2 6 /fs note 1: always set retm to 0 when transiting from normal mode to stop mode. always set retm to 1 when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *; dont care note 4: bits 0 and 1 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = 0, input value is fixed to 0; therefore it may cause external interrupt request on account of falling edge. note 6: when the key-on wakeup is used, relm should be set to "1". note 7: in case of setting as stop mode is released by a rising edge of stop pin input, the release setting by stop5 to stop2 on stopcr register is prohibited. note 8: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 9: the warming-up time should be set correctly for using oscillator. system control register 2 syscr2 (0039h) 7 6 5 4 3 2 1 0 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/ main system clock monitor (read) 0: high-frequency clock (normal1/normal2/idle1/idle2) 1: low-frequency clock (slow1/slow2/sleep1/sleep2) idle cpu and watchdog timer control (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1 /2 and sleep1/2 modes) r/w tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0 and sleep0 modes) note 1: a reset is applied if both xen and xten are cleared to 0, xen is cleared to 0 when sysck = 0, or xten is cleared to 0 when sysck = 1. note 2: *: dont care, tg: timing generator. note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. TMP86FH92DMG 2. operational description 2.2 system clock controller page 16 note 4: do not set idle and tghalt to 1 simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti figure 2-7 level-sensitive release mode note 1: even if the stop pin input is low or the stop5 to stop2 pin inputs are high after warm-up start, the stop mode is not restarted. note 2: in this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = 0) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short program is executed repeatedly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge- sensitive release mode, stop mode is started even when the stop pin input is high level. do not use any stop5 to stop2 pin inputs for releasing stop mode in edge-sensitive release mode. example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode figure 2-8 edge-sensitive release mode TMP86FH92DMG 2. operational description 2.2 system clock controller page 18 normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four different warm-up times can be selected with the syscr1 figure 2-9 stop mode start/release TMP86FH92DMG 2. operational description 2.2 system clock controller page 20 instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts these modes. figure 2-10 idle1/2 and sleep1/2 modes TMP86FH92DMG page 21 reset reset input ?0? ?1? (interrupt release mode) yes no no cpu and wdt are halted interrupt request imf interrupt processing normal release mode yes starting idle1/2 and sleep1/2 modes by instruction execution of the instruc- tion which follows the idle1/2 and sleep1/2 modes start instruction ? start the idle1/2 and sleep1/2 modes after imf is set to "0", set the individual interrupt enable flag (ef) which releases idle1/2 and sleep1/2 modes. to start idle1/2 and sleep1/2 modes, set syscr2 figure 2-11 idle1/2 and sleep1/2 modes start/release TMP86FH92DMG page 23 halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 operate operate operate acceptance of interrupt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer (a) idle1/2 and sleep1/2 modes start (example: star ting with the set instruction located at address a) (b) idle1/2 and sleep1/2 modes release 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following status is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instruction which starts idle0 and sleep0 modes. note:before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle0 and sleep0 modes TMP86FH92DMG 2. operational description 2.2 system clock controller page 24 yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted reset tbt source clock falling edge tbtcr ? start the idle0 and sleep0 mode s stop (disable) peripherals such as a timer counter. to start idle0 and sleep0 mode s, set syscr2 figure 2-13 idle0 and sleep0 modes start/release TMP86FH92DMG 2. operational description 2.2 system clock controller page 26 halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt ?r:w normal release mode ?s:w interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a (b) idle and sleep0 modes release 2.2.4.4 slow mode slow mode is controlled by the system control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter. (1) switching from normal2 mode to slow1 mode first, set syscr2 (2) switching from slow1 mode to normal2 mode first, set syscr2 figure 2-14 switching between the normal2 and slow modes TMP86FH92DMG page 29 set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode 2.3 reset circuit the TMP86FH92DMG has types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset, voltage detect reset 1,voltage detection 2,power on reset, trimming data reset.of these reset, the address trap reset, the watchdog timer and the system clock reset, voltage detect reset 1,voltage detection 2 are a malfunction reset. when the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. the power-on reset signal and trimming data reset signal are input to the power-on warming-up reset circuit, which causes the device to enter a reset state. after the power-on warming-up time (tpowup) has elapsed, the reset is released. for details, refer to the section on the power-on reset circuit. table 2-3 shows on-chip hardware initialization by reset action. table 2-3 on-chip hardware initialization by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized watchdog timer enable jump status flag (jf) not initialized voltage detection circuit disable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 control registers refer to each of control register interrupt individual enable flags (ef) 0 interrupt latches (il) 0 ram not initialized 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at l level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. when the reset pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses fffeh to ffffh. TMP86FH92DMG 2. operational description 2.3 reset circuit page 30 figure 2-15 reset circuit 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 2.3.5 power-on reset a power-on reset is generated internally when the supply voltage (vdd) is turned on. refer to section power on reset. 2.3.6 voltage detection reset a voltage detection reset is generated internally when the supply voltage (vdd) falls below the predefined threshold voltage. refer to section voltage detection circuit. 2.3.7 trimming data reset trimming data bits are provided for adjusting the ladder resistor used to generate the reference voltages for the power-on reset signal and voltage detecting signal. these bits are read from the flash memory and latched internally during the power-on warming up period (tpowup). the trimming data reset is generated if the trim- ming data is corrupted due to noise or other causes.a supply voltage reset is generated internally when the supply voltage (vdd) falls below the predefined threshold voltage. TMP86FH92DMG 2. operational description 2.3 reset circuit page 32 2.4 internal reset detection flags after an internal reset is released, the cause of this internal reset can be identified by reading the internal reset detection flag register (irscr). irscr TMP86FH92DMG 2. operational description 2.4 internal reset detection flags page 34 3. interrupt control circuit the TMP86FH92DMG has a total of 22 interrupt sources excluding reset. interrupts can be nested with priorities. four of the internal interrupt sources are non-maskable while the rest are maskable. interrupt sources are provided with interrupt latches (il), which hold interrupt requests, and independent vectors. the interrupt latch is set to 1 by the generation of its interrupt request which requests the cpu to accept its interrupts. interrupts are enabled or disabled by software using the interrupt master enable flag (imf) and interrupt enable flag (ef). if more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. however, there are no prioritized interrupt factors among non-maskable interrupts. interrupt factors enable condition interrupt latch vector ad- dress priority internal/external (reset) non-maskable - fffe 1 internal intswi (software interrupt) non-maskable - fffc 2 internal intundef (executed the undefined instruction in- terrupt) non-maskable - fffc 2 internal intatrap (address trap interrupt) non-maskable il2 fffa 3 internal intwdt (watchdog timer interrupt) non-maskable il3 fff8 4 internal intvltd imf? ef4 = 1 il4 fff6 5 external int0 imf? ef5 = 1, int0en =1 il5 fff4 6 external int1 imf? ef6 = 1 il6 fff2 7 internal inttbt imf? ef7 = 1 il7 fff0 8 internal intsbi imf? ef8 = 1 il8 ffee 9 internal intrxd1 imf? ef9 = 1 il9 ffec 10 internal inttxd1 imf? ef10 = 1 il10 ffea 11 internal inttc1 imf? ef11 = 1 il11 ffe8 12 internal intrxd2 imf? ef12 = 1 il12 ffe6 13 internal inttxd2 imf? ef13 = 1 il13 ffe4 14 internal inttc3 imf? ef14 = 1 il14 ffe2 15 internal inttc4 imf? ef15 = 1 il15 ffe0 16 external int3 imf? ef16 = 1 il16 ffbe 17 internal intadc imf? ef17 = 1 il17 ffbc 18 internal intsei0 imf? ef18 = 1 il18 ffba 19 internal intsei1 imf? ef19 = 1 il19 ffb8 20 external int4 imf? ef20 = 1 il20 ffb6 21 external int5 imf? ef21 = 1 il21 ffb4 22 - reserved imf? ef22 = 1 il22 ffb2 23 - reserved imf? ef23 = 1 il23 ffb0 24 note 1: to use the address trap interrupt (intatrap), clear wdtcr1 3.1 interrupt latches (il21 to il2) an interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. when interrupt request is generated, the latch is set to 1, and the cpu is requested to accept the interrupt if its interrupt is enabled. the interrupt latch is cleared to "0" immediately after accepting interrupt. all interrupt latches are initialized to 0 during reset. the interrupt latches are located on address 003ch, 003dh, and 003eh in sfr area. each latch can be cleared to "0" individually by instruction. however, il2 and il3 should not be cleared to "0" by software. for clearing the interrupt latch, load instruction should be used and then il2 and il3 should be set to "1". if the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. interrupt latches are not set to 1 by an instruction. since interrupt latches can be read, the status for interrupt requests can be monitored by software. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :clears interrupt latches di ; imf 0 ldw (ill), 1110100000111111b ; il12, il10 to il6 0 ei ; imf 1 example 2 :reads interrupt latches ld wa, (ill) ; w ilh, a ill example 3 :tests interrupt latches test (ill). 7 ; if il7 = 1 then jump jr f, sset 3.2 interrupt enable register (eir) the interrupt enable register (eir) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). non- maskable interrupt is accepted regardless of the contents of the eir. the eir consists of an interrupt master enable flag (imf) and the individual interrupt enable flags (ef). these registers are located on address 003ah, 003bh, and 0032h in sfr area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 interrupt master enable flag (imf) the interrupt enable register (imf) enables and disables the acceptance of the whole maskable interrupt. while imf = 0, all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (ef). by setting imf to 1, the interrupt becomes acceptable if the individuals are enabled. when an interrupt is accepted, imf is cleared to 0 after the latest status on imf is stacked. thus the maskable interrupts which follow are disabled. by executing return interrupt instruction [reti/retn], the stacked data, which was the status before interrupt acceptance, is loaded on imf again. TMP86FH92DMG 3. interrupt control circuit 3.1 interrupt latches (il21 to il2) page 36 the imf is located on bit0 in eirl (address: 003ah in sfr), and can be read and written by an instruction. the imf is normally set and cleared by [ei] and [di] instruction respectively. during reset, the imf is initialized to 0. 3.2.2 individual interrupt enable flags (ef21 to ef4) each of these flags enables and disables the acceptance of its maskable interrupt. setting the corresponding bit of an individual interrupt enable flag to 1 enables acceptance of its interrupt, and setting the bit to 0 disables acceptance. during reset, all the individual interrupt enable flags (ef21 to ef4) are initialized to 0 and all maskable interrupts are not accepted until they are set to 1. note:in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". example 1 :enables interrupts individually and sets imf di ; imf 0 ldw (eirl), 1110100010100000b ; ef15 to ef13, ef11, ef7, ef5 1 : note: imf should not be set. : ei ; imf 1 example 2 :c compiler description example unsigned int _io (3ah) eirl; /* 3ah shows eirl address */ _di(); eirl = 10100000b; : _ei(); interrupt latches (initial value: 00000000 000000**) ilh,ill (003dh, 003ch) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 il15 il14 il13 il12 il11 il10 il9 il8 il7 il6 il5 il4 il3 il2 ilh (003dh) ill (003ch) (initial value: **000000) ile (003eh) 7 6 5 4 3 2 1 0 ? ? il21 il20 il19 il18 il17 il16 ile (003eh) il21 to il2 interrupt latches at rd 0: no interrupt request 1: interrupt request at wr 0: clears the interrupt request 1: (interrupt latch is not set.) r/w note 1: to clear any one of bits il7 to il4, be sure to write "1" into il2 and il3. TMP86FH92DMG page 37 note 2: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". note 3: do not clear il with read-modify-write instructions such as bit operations. interrupt enable registers (initial value: 00000000 0000***0) eirh,eirl (003bh, 003ah) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ef15 ef14 ef13 ef12 ef11 ef10 ef9 ef8 ef7 ef6 ef5 ef4 imf eirh (003bh) eirl (003ah) (initial value: **000000) eire (0032h) 7 6 5 4 3 2 1 0 ? ? ef21 ef20 ef19 ef18 ef17 ef16 eire (0032h) ef21 to ef4 individual-interrupt enable flag (specified for each bit) 0: 1: disables the acceptance of each maskable interrupt. enables the acceptance of each maskable interrupt. r/w imf interrupt master enable flag 0: 1: disables the acceptance of all maskable interrupts enables the acceptance of all maskable interrupts note 1: *: dont care note 2: do not set imf and the interrupt enable flag (ef15 to ef4) to 1 at the same time. note 3: in main program, before manipulating the interrupt enable flag (ef) or the interrupt latch (il), be sure to clear imf to "0" (disable interrupt by di instruction). then set imf newly again as required after operating on the ef or il (enable interrupt by ei instruction) in interrupt service routine, because the imf becomes "0" automatically, clearing imf need not execute normally on interrupt service routine. however, if using multiple interrupt on interrupt service routine, manipulating ef or il should be executed before setting imf="1". 3.3 interrupt sequence an interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to 0 by resetting or an instruction. interrupt acceptance sequence requires 8 machine cycles (2 s @16 mhz) after the completion of the current instruction. the interrupt service task terminates upon execution of an interrupt return instruction [reti] (for maskable interrupts) or [retn] (for non-maskable interrupts). figure 3-1 shows the timing chart of interrupt acceptance processing. 3.3.1 interrupt acceptance processing is packaged as follows. a. the interrupt master enable flag (imf) is cleared to 0 in order to disable the acceptance of any following interrupt. b. the interrupt latch (il) for the interrupt source accepted is cleared to 0. c. the contents of the program counter (pc) and the program status word, including the interrupt master enable flag (imf), are saved (pushed) on the stack in sequence of psw + imf, pch, pcl. meanwhile, the stack pointer (sp) is decremented by 3. d. the entry address (interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. the instruction stored at the entry address of the interrupt service program is executed. note:when the contents of psw are saved on the stack, the contents of imf are also saved. TMP86FH92DMG 3. interrupt control circuit 3.3 interrupt sequence page 38 note 1: a: return address, b: entry address, c: address which reti instruction is stored note 2: on condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (if the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. figure 3-1 timing chart of interrupt acceptance/return interrupt instruction example: correspondence between vector table address for inttbt and the entry address of the interrupt service program figure 3-2 vector table address and entry address a maskable interrupt is not accepted until the imf is set to 1 even if the maskable interrupt higher than the level of current servicing interrupt is requested. in order to utilize nested interrupt service, the imf is set to 1 in the interrupt service program. in this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. to avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting imf to 1. as for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.3.2 saving/restoring general-purpose registers during interrupt acceptance processing, the program counter (pc) and the program status word (psw, includes imf) are automatically saved on the stack, but the accumulator and others are not. these registers are saved by software if necessary. when multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. the following methods are used to save/restore the general-purpose reg- isters. TMP86FH92DMG page 39 d2h 03h d203h d204h 06h vector table address entry address 0fh vector interrupt service program fff0h fff1h a b a c + 1 execute instruction sp pc execute instruction n n ? 2 n - 3 n ? 2n ? 1 n ? 1 n a + 2 a + 1 c + 2 b + 3 b + 2 b + 1 a + 1 a a ? 1 execute reti instruction interrupt acceptance execute instruction interrupt service task 1-machine cycle interrupt request interrupt latch (il) imf 3.3.2.1 using push and pop instructions if only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the push/pop instructions. example :save/store register using push and pop instructions pintxx: push wa ; save wa register (interrupt processing) pop wa ; restore wa register reti ; return figure 3-3 saving/restoring general-purpose registers under push and pop instructions 3.3.2.2 using data transfer instructions to save only a specific register without nested interrupts, data transfer instructions are available. example :save/store register using data transfer instructions pintxx: ld (gsava), a ; save a register (interrupt processing) ld a, (gsava) ; restore a register reti ; return TMP86FH92DMG 3. interrupt control circuit 3.3 interrupt sequence page 40 pcl pch psw at acceptance of an interrupt at execution of push instruction at execution of reti instruction at execution of pop instruction b-4 b-3 b-2 b-1 b pcl pch psw pcl pch psw sp address (example) sp sp sp a w b-5 figure 3-4 saving/restoring general-purpose registers under interrupt processing TMP86FH92DMG page 41 interrupt acceptance interrupt service task restoring registers saving registers interrupt return saving/restoring general-purpose registers using push/pop data transfer instruction main task 3.3.3 interrupt return interrupt return instructions [reti]/[retn] perform as follows. [reti]/[retn] interrupt return 1. program counter (pc) and program status word (psw, includes imf) are restored from the stack. 2. stack pointer (sp) is incremented by 3. as for address trap interrupt (intatrap), it is required to alter stacked data for program counter (pc) to restarting address, during interrupt service program. note:if [retn] is executed with the above data unaltered, the program returns to the address trap area and intatrap occurs again. when interrupt acceptance processing has completed, stacked data for pcl and pch are located on address (sp + 1) and (sp + 2) respectively. example 1 :returning from address trap interrupt (intatrap) service program pintxx: pop wa ; recover sp by 2 ld wa, return address ; push wa ; alter stacked data (interrupt processing) retn ; return example 2 :restarting without returning interrupt (in this case, psw (includes imf) before interrupt acceptance is discarded.) pintxx: inc sp ; recover sp by 3 inc sp ; inc sp ; (interrupt processing) ld eirl, data ; set imf to 1 or clear it to 0 jp restart address ; jump into restarting address interrupt requests are sampled during the final cycle of the instruction being executed. thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. note 1: it is recommended that stack pointer be return to rate before intatrap (increment 3 times), if return interrupt instruction [retn] is not utilized during interrupt service program under intatrap (such as example 2). note 2: when the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.4 software interrupt (intsw) executing the swi instruction generates a software interrupt and immediately starts interrupt processing (intsw is highest prioritized interrupt). use the swi instruction only for detection of the address error or for debugging. 3.4.1 address error detection ffh is read if for some cause such as noise the cpu attempts to fetch an instruction from a non-existent memory address during single chip mode. code ffh is the swi instruction, so a software interrupt is generated TMP86FH92DMG 3. interrupt control circuit 3.4 software interrupt (intsw) page 42 and an address error is detected. the address error detection range can be further expanded by writing ffh to unused areas of the program memory. address trap reset is generated in case that an instruction is fetched from ram, dbr or sfr areas. 3.4.2 debugging debugging efficiency can be increased by placing the swi instruction at the software break point setting address. 3.5 undefined instruction interrupt (intundef) taking code which is not defined as authorized instruction for instruction causes intundef. intundef is generated when the cpu fetches such a code and tries to execute it. intundef is accepted even if non-maskable interrupt is in process. contemporary process is broken and intundef interrupt process starts, soon after it is requested. note:the undefined instruction interrupt (intundef) forces cpu to jump into vector address, as software interrupt (swi) does. 3.6 address trap interrupt (intatrap) fetching instruction from unauthorized area for instructions (address trapped area) causes reset output or address trap interrupt (intatrap). intatrap is accepted even if non-maskable interrupt is in process. contemporary process is broken and intatrap interrupt process starts, soon after it is requested. note:the operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (wdtcr). TMP86FH92DMG page 43 3.7 external interrupts the TMP86FH92DMG has 5 external interrupt inputs. these inputs are equipped with digital noise reject circuits (pulse inputs of less than a certain time are eliminated as noise). edge selection is also possible with int1,int3,int4. the int0/p10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. edge selection, noise reject control and int0/p10 pin function selection are performed by the external interrupt control register (eintcr). source pin enable conditions release edge (level) digital noise reject int0 int0 imf ef5 int0en=1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int1 int1 imf ef6 = 1 falling edge or rising edge pulses of less than 15/fc or 63/fc [s] are elimina- ted as noise. pulses of 49/fc or 193/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int3 int3 imf ef16 = 1 falling edge rising edge falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int4 int4 imf ef20 = 1 falling edge rising edge falling and rising edge or h level pulses of less than 7/fc [s] are eliminated as noise. pulses of 25/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. int5 int5 imf ef21 = 1 falling edge pulses of less than 2/fc [s] are eliminated as noise. pulses of 7/fc [s] or more are considered to be signals. in the slow or the sleep mode, pulses of less than 1/fs [s] are eliminated as noise. pulses of 3.5/fs [s] or more are considered to be signals. note 1: in normal1/2 or idle1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. note 2: when int0en = "0", il5 is not set even if a falling edge is detected on the int0 pin input. note 3: when a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. in this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. TMP86FH92DMG 3. interrupt control circuit 3.7 external interrupts page 44 external interrupt control register eintcr 7 6 5 4 3 2 1 0 (0037h) int1nc int0en int3es int4es int1es (initial value: 0000 000*) int1nc noise reject time select 0: pulses of less than 63/fc [s] are eliminated as noise 1: pulses of less than 15/fc [s] are eliminated as noise r/w int0en p10/ int0 pin configuration 0: p10 input/output port 1: int0 pin (port p10 should be set to an input mode) r/w int4 es int4 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: "h" level r/w int3 es int3 edge select 00: rising edge 01: falling edge 10: rising edge and falling edge 11: "h" level r/w int1 es int1 edge select 0: rising edge 1: falling edge r/w note 1: fc: high-frequency clock [hz], *: dont care note 2: when the system clock frequency is switched between high and low or when the external interrupt control register (eintcr) is overwritten, the noise canceller may not operate normally. it is recommended that external interrupts are disabled using the interrupt enable register (eir). note 3: the maximum time from modifying int1nc until a noise reject time is changed is 2 6 /fc. note 4: in case reset pin is released while the state of int4 pin keeps "h" level, the external interrupt 4 request is not generated even if the int4 edge select is specified as "h" level. the rising edge is needed after reset pin is released. TMP86FH92DMG page 45 TMP86FH92DMG 3. interrupt control circuit 3.7 external interrupts page 46 4. special function register (sfr) the TMP86FH92DMG adopts the memory mapped i/o system, and all peripheral control and data transfers are performed through the special function register (sfr) or the data buffer register (dbr). the sfr is mapped on address 0000h to 003fh, dbr is mapped on address 0f80h to 0fffh. this chapter shows the arrangement of the special function register (sfr) and data buffer register (dbr) for TMP86FH92DMG. 4.1 sfr address read write 0000h p0dr 0001h p1dr 0002h p2dr 0003h p3dr 0004h p0pucr 0005h p1pucr 0006h p2pucr 0007h reserved 0008h p3cr1 0009h p1outcr 000ah p3cr2 000bh p0outcr 000ch p0prd - 000dh p2prd - 000eh adccr1 000fh adccr2 0010h tc1dral 0011h tc1drah 0012h tc1drbl 0013h tc1drbh 0014h tc1cr 0015h sbisra sbicra 0016h sbidbr 0017h - i2car 0018h sbisrb sbicrb 0019h irstsr 001ah tc3cr 001bh tc4cr 001ch ttreg3 001dh ttreg4 001eh pwreg3 001fh pwreg4 0020h adcdr2 - 0021h adcdr1 - 0022h uart2sr uart2cr1 0023h - uart2cr2 0024h rd2buf td2buf 0025h uart1sr uart1cr1 TMP86FH92DMG page 47 address read write 0026h - uart1cr2 0027h rd1buf td1buf 0028h sesr - 0029h sedr 002ah secr 002bh vdcr1 002ch vdcr2 002dh p1prd - 002eh reserved 002fh reserved 0030h reserved 0031h - stopcr 0032h eire 0033h reserved 0034h - wdtcr1 0035h - wdtcr2 0036h tbtcr 0037h eintcr 0038h syscr1 0039h syscr2 003ah eirl 003bh eirh 003ch ill 003dh ilh 003eh ile 003fh psw note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH92DMG 4. special function register (sfr) 4.1 sfr page 48 4.2 dbr address read write 0f80h reserved : : : : 0f9fh reserved address read write 0fa0h reserved : : : : 0fbfh reserved address read write 0fc0h reserved : : : : 0fdfh reserved address read write 0fe0h reserved 0fe1h reserved 0fe2h reserved 0fe3h reserved 0fe4h reserved 0fe5h reserved 0fe6h reserved 0fe7h reserved 0fe8h reserved 0fe9h - flsstb 0feah spcr 0febh reserved 0fech reserved 0fedh reserved 0feeh reserved 0fefh reserved 0ff0h reserved 0ff1h reserved 0ff2h reserved 0ff3h reserved 0ff4h reserved 0ff5h reserved 0ff6h reserved 0ff7h reserved 0ff8h reserved 0ff9h reserved 0ffah reserved 0ffbh reserved 0ffch reserved 0ffdh reserved 0ffeh reserved TMP86FH92DMG page 49 address read write 0fffh flscr note 1: do not access reserved areas by the program. note 2: ? ; cannot be accessed. note 3: write-only registers and interrupt latches cannot use the read-modify-write instructions (bit manipulation instructions such as set, clr, etc. and logical operation instructions such as and, or, etc.). TMP86FH92DMG 4. special function register (sfr) 4.2 dbr page 50 5. i/o ports the TMP86FH92DMG have 4 parallel input/output ports as follows. primary function secondary functions port p0 8-bit i/o port external interrupt input, timer/counter input/output, uart input/output, serial expansion interface input/output and serial prom mode control input. port p1 5-bit i/o port external interrupt input, divider output, uart input/output and serial bus interface input/output port p2 3-bit i/o port external interrupt input, stop mode release signal input and low frequency res- onator connection port p3 8-bit i/o port analog input, stop mode release signal input and timer/counter input/output each output port contains a latch, which holds the output data. all input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. figure 5-1 shows input/output timing examples. external data is read from an i/o port in the s1 state of the read cycle during execution of the read instruction. this timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. output data changes in the s2 state of the write cycle during execution of the instruction which writes to an i/o port. note:the positions of the read and write cycles may vary, depending on the instruction. figure 5-1 input/output timing (example) TMP86FH92DMG page 51 ! " ! " ! " # # $ ! " ! " ! " %& # %& # ' ( 5.1 p0 (p07 to p00) port (high current) the p0 port is an 8-bit input/output port shared with external interrupt input, serial expansion interface input/output, uart1 input/output, timer counter input/output and serial prom mode control input. when using this port as serial expansion interface output or uart1 output, set the output latch to 1. when using this port as a port output, the output latch data (p0dr) is output to the p0 port. when reset, the output latch (p0dr) and the push-pull control register (p0outcr) are initialized to 1 and 0, respectively. the p0 port allows its output circuit to be selected between n-channel open-drain output or push-pull output by the p0outcr register. the p0 port has programmable internal pull-up resistance to be controlled by p0pucr registers. when using this port as a port input, external interrupt input, serial expansion interface input, uart1 input and timer counter input, set the p0outcr register's corresponding bit to 0 after setting the p0dr to 1. the p0 port has independent data input registers. to inspect the output latch status, read the p0dr register. to inspect the pin status, read the p0prd register. in the serial prom mode, p01 pin used as a boot/rxd1 pin, p00 pin used as a txd1 pin. for details, see "serial prom mode setting". figure 5-2 p0 port TMP86FH92DMG 5. i/o ports 5.1 p0 (p07 to p00) port (high current) page 52 output latch data input (p0prd) data output (p0dr) control output outen p0outcri p0outcri input data input (p0dr) control input p0i note: i = 7 to 0 stop dq dq p0pucri vdd p0dr (0000h) r/w 7 6 5 4 3 2 1 0 p07 tc1 int4 p06 int3 ppg p05 ss p04 miso p03 mosi p02 sclk p01 rxd1 boot p00 txd1 (initial value: 1111 1111) p0outcr (000bh) r/w 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p0outcr p0 port input/output control (specified bitwise) 0: nch open-drain output 1: push-pull output r/w p0pucr (0004h) r/w 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p0pucr p0 port pull-up resistance con- trol (specified bitwise) 0: no pull-up resistance 1: pull-up resistance r/w p0prd (000ch) read only 7 6 5 4 3 2 1 0 p07 p06 p05 p04 p03 p02 p01 p00 TMP86FH92DMG page 53 5.2 p1 (p14 to p10) port the p1 port is a 5-bit input/output port shared with external interrupt input, divider output, uart2 input/output and serial bus interface input/output. when using this port as divider output, uart2 output and serial bus interface output, set the output latch to 1. when using this port as a port output, the output latch data(p1dr) is output to the p1 port. when reset, the output latch (p1dr) and the push-pull control register(p1outcr) are initialized to 1 and 0,re- spectively. the p1 allows its output circuit to be selected between n-channel open-drain or push-pull output by the p1outcr register. the p1 port has programmable internal pull-up resistance to be controlled by p1pucr. when using this port as a port input, external interrupt input, uart2 input and serial bus interface input, set the p1outcr registers corresponding bit to 0 after setting the p1dr to 1. the p1 port has independent data input registers.to inspect the output latch status, read the p1dr register.to inspect the pin status, read the p1prd register. figure 5-3 p1 port TMP86FH92DMG 5. i/o ports 5.2 p1 (p14 to p10) port page 54 output latch data input (p1prd) data output (p1dr) control output outen p1outcri p1pucri p1outcri input data input (p1dr) control input p1i stop note: i = to 0 dq dq vdd 4 p1dr (0001h) r/w 7 6 5 4 3 2 1 0 p14 txd2 scl p13 rxd2 sda p12 dvo p11 int1 p10 int0 (initial value: ***1 1111) p1outcr (0009h) r/w 7 6 5 4 3 2 1 0 (initial value: ***0 0000) p1outcr p1port input/output control (specified bitwise) 0: nch open-drain output 1: push-pull output r/w p1pucr (0005h) r/w 7 6 5 4 3 2 1 0 (initial value: ***0 0000) p1pucr p1 port pull-up resistance control (specified bitwise) 0: no pull-up resistance 1: pull-up resistance r/w p1prd (002dh) read only 7 6 5 4 3 2 1 0 p14 p13 p12 p11 p10 note:p13 and p14 can be used as the input/output for either uart2 or i 2 c bus control signals. therefore, uart2 and serial bus interface cannot be used at the same time. these functions can be enabled and disabled in their respective function registers. uart2 and i 2 c bus cannot be enabled at the same time. TMP86FH92DMG page 55 5.3 p2 (p22 to p20) port the p2 port is a 3-bit input/output port shared with external interrupt input, stop mode release signal input, and low-frequency resonator connecting pin. when using this port as a port input or function pin, set the output latch to 1. the output latch is initialized to 1 when reset. when operating in dual-clock mode, connect a low-frequency reso- nator (32.768 khz) to the p21 (xtin) and p22 (xtout) pins. when operating in single-clock mode, the p21 and p22 pins can be used as ordinary input/output ports. we recommend using the p20 pin for external interrupt input or stop mode release signal input or as a port input. (when used as a port output, the interrupt latch is set by a falling edge.) the p2 port has independent data input registers. to inspect the output latch status, read the p2dr register. to inspect the pin status, read the p2prd register. when the p2dr or p2prd read instruction is executed for the p2 port, the values read from bits 7 to 3 are indeterminate. the p20 port has programmable internal pull-up resistance to be controlled by p2pucr. figure 5-4 p2 port TMP86FH92DMG 5. i/o ports 5.3 p2 (p22 to p20) port page 56 output latch data input (p20prd) data input (p21) data output (p21) data input (p20) data output (p20) control input data input (p21prd) data input (p22) data output (p22) data input (p22prd) stop outen xten fs p22 (xtout) p21 (xtin) p20 (int5, stop) osc.enable d q q d q d q d q d q q d q p2pucr<0> vdd output latch output latch p2dr (0002h) r/w 7 6 5 4 3 2 1 0 p22 xtout p21 xtin p20 int5 stop (initial value: **** *111) p2pucr (0006h) r/w 7 6 5 4 3 2 1 0 (initial value: **** ***0) p2pucr p2 port pull-up resistance con- trol (specified bitwise) 0: no pull-up resistance 1: pull-up resistance r/w p2prd (000dh) read only 7 6 5 4 3 2 1 0 p22 p21 p20 note:the p20 pin is shared with the stop pin, so that when in stop mode, its output goes to a high-z state regardless of the outen status. TMP86FH92DMG page 57 5.4 p3 (p37 to p30) port the p3 port is an 8-bit input/output port that can be specified for input or output bitwise, and is shared with analog input and key-on wakeup input (kwi). the p3 port input/output control registers p3cr1 and p3cr2 are used to specify the function of each pin. after reset, the p3cr1 and p3cr2 are initialized to 0 and 1, respectively, so the p3 port is configured for input mode. the p3 port output latches are initialized to 0. to use each pin as a port output, set the corresponding bit in the p3cr1 to 1. to use each pin as a port input, set the corresponding bit in the p3cr1 to 0 and then set the corresponding bit in the p3cr2 to 1. to use each pin as a key-on wakeup input, set the corresponding bit in the p3cr1 to 0 and then set the corresponding bit in the stopcr to 1. to use each pin as an analog input, set the corresponding bit in the p3cr1 to 0 and then set the corresponding bit in the p3cr2 to 0. when p3cr1=1, reading the p3dr returns the values of the respective output latches. any pins of the p3 port which are not used for analog input can be used as input/output ports. during ad conversion, however, avoid executing output instructions on these pins to ensure the accuracy of conversion. also note that, during ad conversion, rapidly changing signals should not be input on any pins near analog input pins. table 5-1 setting of register according to each function value function set value p3dr p3cr1 p3cr2 stopcr port input - 0 1 - key-on wakeup input - 0 - 1 analog input - 0 0 - port 0 output 0 1 - - port 1 output 1 1 - - table 5-2 setting of register according to each function value condition reading value of p3dr p3cr1 p3cr2 0 0 0 0 1 state of terminal 1 0 contents of output latch 1 TMP86FH92DMG 5. i/o ports 5.4 p3 (p37 to p30) port page 58 figure 5-5 p3 port TMP86FH92DMG page 59 output latch data input (p3drj) data output (p3drj) e ) equivalent circuit of p34 v q p37 p3cr1j d q d q d q d q p3cr1j k p r w v p3cr2j k p r w v ainds sain analog input st op outen key-on wakeup p3cr2j stopk d q d q p 3i p3j note1 note 9y9? stop = bit 7 of syscr1 note 9t9? sain = ad input select signal note 9?9? stopk = bit 7 to bit 4 of stopcr ) j = 7 to 4 note2 ) k = 5 to output latch data input (p3dri) data output (p3dri) b) equivalent circuit of p32, p33 p3cr1i p3 i p3i note ) i = 2,3 d q d q d q d q p3cr1i k p r w v p3cr2i input ainds sain analog input st op outen p3cr2i d q d q output latch data input (p3drk) data output (p3drk) a) equivalent circuit of p30, p31 control output st op outen p3cr1k p3cr1k k p r w v p3 i p3k note ) k = 0,1 d q d q d q d q control input p3dr (0003h) r/w 7 6 5 4 3 2 1 0 p37 ain5 stop5 p36 ain4 stop4 p35 ain3 stop3 p34 ain2 stop2 p33 ain1 p32 ain0 p31 tc4 pdo4 pwm4 ppg4 p30 tc3 pdo3 pwm3 (initial value: 0000 0000) p3cr1 (0008h) 7 6 5 4 3 2 1 0 (initial value: 0000 0000) p3cr1 controls p3 port input/output (specified bitwise) 0: input mode (port input, or analog input or key on wake up input) 1: output mode r/w p3cr2 (000ah) 7 6 5 4 3 2 1 0 (initial value: 1111 11**) p3cr2 controls p3 port input (specified bitwise) 0: analog input 1: port input r/w note 1: the port placed in input mode reads the pin input state.therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. note 2: as for the analog input pin because of penetration electric current measure, please be sure to clear the bit to which p3cr2 corresponds in "0". note 3: do not set the output mode (p3cr1="1") for the pin used as an analog input, due to avoid external short-circuits. note 4: pins not used for analog input can be used as i/o ports.during ad conversion, output instructions should not be executed to keep a precision. in addition, a variable signal should not be input to a port adjacent to the analog input during ad conversion. TMP86FH92DMG 5. i/o ports 5.4 p3 (p37 to p30) port page 60 6. power-on reset circuit 6.1 power-on reset circuit the power-on reset circuit generates a reset when the TMP86FH92DMG is powered on. it also generates a power- on reset signal if the supply voltage drops below the threshold voltage of the power-on reset circuit. note:the power-on reset circuit cannot be emulated with the tmp86c993xb (emulation chip). therefore, when using the development tool for debugging, ensure that operation is performed within the operating voltage range of the TMP86FH92DMG. for the operating voltage range, refer to the chapter on electrical characteristics. 6.1.1 configuration the power-on reset circuit is comprised of a reference voltage generator and a comparator. the comparator compares the supply voltage divided by a resistor ladder with the reference voltage generated by the reference voltage generator. figure 6-1 power-on reset circuit 6.1.2 function when the TMP86FH92DMG is powered on, the power-on reset circuit generates a power-on reset signal while the supply voltage is below the power-on reset release voltage. the power-on reset signal is released when the supply voltage rises above the power-on reset release voltage. when the TMP86FH92DMG is shut off, the power-on reset circuit generates a power-on reset signal when the supply voltage drops below the power-on reset threshold voltage. while the power-on reset signal is generated, the warm-up counter circuit, cpu and peripheral circuits are reset. upon release of the power-on reset signal, the warm-up counter circuit starts operating. after the warm-up time has elapsed, the cpu and peripheral circuits are released from the reset state. after the supply voltage reaches the power-on reset release voltage level, it must be raised to the operating range before the power-on warm-up time expires. if the supply voltage is not in the operating range at the com- pletion of the power-on warm-up time, the TMP86FH92DMG cannot operate properly. TMP86FH92DMG page 61 vdd reference detection voltage power on reset signal ? + note 1: the power-on reset circuit may not operate properly depending on transitions in supply voltage (vdd). when de- signing your application system, careful consideration must be given to ensure proper operation of the power-on reset circuit by referring to the device's electrical characteristics. note 2: the input clock to the warm-up counter is derived from the oscillation circuit. because the oscillation frequency is unstable until the oscillation circuit stabilizes, the warm-up time includes error. note 3: the supply voltage must be raised to satisfy the condition t vdd < t pwup . figure 6-2 operation of the power on reset circuit TMP86FH92DMG 6. power-on reset circuit 6.1 power-on reset circuit page 62 warm-up counter start t pwup t vdd t proff t pron t prw v proff supply operating voltage v dd v pron power-on reset signal warm-up counter clock ? cpu/peripheral circuits reset signal 7. voltage detection circuit (vltd) the voltage detecting circuit monitors the supply voltage level and generates an interrupt or reset upon detection of a low-voltage condition. note:the voltage detecting circuit may not operate properly depending on transitions in supply voltage (vdd). when designing your application system, careful consideration must be given to ensure proper operation of the voltage detecting circuit by referring to the device's electrical characteristics. 7.1 configuration the voltage detecting circuit is comprised of a reference voltage generator, two detection voltage select circuits, two comparators and control registers. the supply voltage (vdd) is divided by the ladder resistor and input to the detection voltage select circuit. the detection voltage select circuit selects a voltage according to the specified detection voltage (vdxlvl) (x = 1 or 2), and the comparator compares it with the reference voltage. when the comparator detects the selected voltage, a voltage detection reset signal or an intvltd interrupt request signal can be generated. whether to generate a voltage detection reset signal or an intvltd interrupt request signal can be programmed by software. in the former case, a voltage detection reset signal is generated when the supply voltage (vdd) becomes lower than the detection voltage (vdxlvl). in the latter case, an intvltd interrupt request signal is generated when the supply voltage (vdd) falls to the detection voltage level. note:since the comparators used for voltage detection do not have a hysteresis structure, intvltd interrupt request signals may be generated frequently if the supply voltage (vdd) is close to the detection voltage (vdxlvl). intvltd interrupt request signals may be generated not only when the supply voltage falls to the detection voltage but also when it rises to the detection voltage. figure 7-1 voltage detection circuit diagram TMP86FH92DMG page 63 vdd reference voltage ? + ? + vd1en vd1mod vd2en vd2mod vd2lvl vd1lvl vd1sf vd1f vd2sf vd2f vdcr2 detection voltage 1 select circuit detection voltage 2 select circuit vdcr1 voltage detection 1 reset signal voltage detection 2 reset signal intvltd interrupt request signal f/f f/f interrupt request signal internal bus 7.2 control the voltage detection circuit is controlled by the voltage detection control register 1 (vdcr1) and voltage detection control register 2 (vdcr2). the functions of the vdcr1 and vdcr2 vary between the TMP86FH92DMG and the emulation chip tmp86c993xb. for details, refer to the register descriptions below. the tmp86c993xb does not allow an interrupt or a reset to be generated by voltage detection. instead, the vd1s and vd2s bits are provided in the vdcr2 to support the emulation of voltage detection operation. setting vdcr2 note 4: each flag cannot be set to 1 by writing a 1 to it. voltage detection control register 2 vdcr2 7 6 5 4 3 2 1 0 (002ch) vd2s vd1s vd2mod vd2en vd1mod vd1en initial value: **** 0000) TMP86FH92DMG tmp86c993xb vd2s voltage detection 2 set no function 0: 1: generate a reset or an inter- rupt by vd2 - write only vd1s voltage detection 1 set no function 0: 1: generate a reset or an inter- rupt by vd1 - write only vd2mod voltage detection 2 operation mode select 0: 1: intvltd interrupt voltage detection 2 reset signal occurrence r/w vd2en voltage detection 2 operation enable/disa- ble 0: 1: voltage detection 2 disable voltage detection 2 enable r/w vd1mod voltage detection 1 operation mode select 0: 1: intvltd interrupt voltage detection 1 reset signal occurrence r/w vd1en voltage detection 1 operation enable/disa- ble 0: 1: voltage detection 1 disable voltage detection 1 enable r/w note 1: the vdcr2 is only initialized by a power-on reset or an external reset input. note 2: in the TMP86FH92DMG, the vd2s and vd1s bits are not available. setting a value to these bits has no effect. TMP86FH92DMG page 65 7.3 function the voltage detecting circuit allows two detection voltage levels (vdxlvl, x = 1, 2) to be specified. for each detection voltage, whether to enable or disable voltage detect operation and the action to be taken when the supply voltage (vdd) falls to or below the detection voltage (vdxlvl) can be programmed by software. 7.3.1 enabling/disabling voltage detection operation setting the vdcr2 figure 7-3 voltage detection reset signal 7.3.3 detection voltage level section the detection voltage level is selected by programming the vdcr1 7.4 setting of register 7.4.1 setting procedure for generate an interrupt the following shows the setting procedure for generating an intvltd interrupt upon detection of a low- voltage condition. 1. clear the intvltd interrupt enable flag 7.4.2 setting procedure to generate a reset the following shows the setting procedure for generating a voltage detect x reset signal upon detection of a low-voltage condition. 1. clear the intvltd interrupt enable flag TMP86FH92DMG 7. voltage detection circuit (vltd) 7.4 setting of register page 70 8. watchdog timer (wdt) the watchdog timer is a fail-safe system to detect rapidly the cpu malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the cpu to a system recovery routine. the watchdog timer signal for detecting malfunctions can be programmed only once as reset request or interrupt request. upon the reset release, this signal is initialized to reset request. when the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. note:care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 8.1 watchdog timer configuration figure 8-1 watchdog timer configuration TMP86FH92DMG page 71 0034 h overflow wdt output internal reset binary counters wdtout writing clear code writing disable code wdten wdtt 2 0035 h watchdog timer control registers wdtcr1 wdtcr2 intwdt interrupt request interrupt request reset request reset release clock clear 1 2 controller q sr s r q selector fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 19 or fs/2 11 fc/2 17 or fs/2 9 8.2 watchdog timer control the watchdog timer is controlled by the watchdog timer control registers (wdtcr1 and wdtcr2). the watchdog timer is automatically enabled after the reset release. 8.2.1 malfunction detection methods using the watchdog timer the cpu malfunction is detected, as shown below. 1. set the detection time, select the output, and clear the binary counter. 2. clear the binary counter repeatedly within the specified detection time. if the cpu malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. when wdtcr1 watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 (atas) (atout) wdten wdtt wdtout (initial value: **11 1001) wdten watchdog timer enable/disable 0: disable (writing the disable code to wdtcr2 is required.) 1: enable write only wdtt watchdog timer detection time [s] normal1/2 mode slow1/2 mode write only dv7ck = 0 dv7ck = 1 00 2 25 /fc 2 17 /fs 2 17 /fs 01 2 23 /fc 2 15 /fs 2 15 fs 10 2 21 fc 2 13 /fs 2 13 fs 11 2 19 /fc 2 11 /fs 2 11 /fs wdtout watchdog timer output select 0: interrupt request 1: reset request write only note 1: after clearing wdtout to 0, the program cannot set it to 1. note 2: fc: high-frequency clock [hz], fs: low-frequency clock [hz], *: dont care note 3: wdtcr1 is a write-only register and must not be used with any of read-modify-write instructions. if wdtcr1 is read, a dont care is read. note 4: to activate the stop mode, disable the watchdog timer or clear the counter immediately before entering the stop mode. after clearing the counter, clear the counter again immediately after the stop mode is inactivated. note 5: to clear wdten, set the register in accordance with the procedures shown in 8.2.3 watchdog timer disable. watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code 4eh: clear the watchdog timer binary counter (clear code) b1h: disable the watchdog timer (disable code) d2h: enable assigning address trap area others: invalid write only note 1: the disable code is valid only when wdtcr1 8.2.3 watchdog timer disable to disable the watchdog timer, set the register in accordance with the following procedures. setting the register in other procedures causes a malfunction of the micro controller. 1. set the interrupt master flag (imf) to 0. 2. set wdtcr2 to the clear code (4eh). 3. set wdtcr1 8.2.5 watchdog timer reset when a binary-counter overflow occurs while wdtcr1 8.3 address trap the watchdog timer control register 1 and 2 share the addresses with the control registers to generate address traps. watchdog timer control register 1 wdtcr1 (0034h) 7 6 5 4 3 2 1 0 atas atout (wdten) (wdtt) (wdtout) (initial value: **11 1001) atas select address trap generation in the internal ram area 0: generate no address trap 1: generate address traps (after setting atas to 1, writing the control code d2h to wdtcr2 is required) write only atout select operation at address trap 0: interrupt request 1: reset request watchdog timer control register 2 wdtcr2 (0035h) 7 6 5 4 3 2 1 0 (initial value: **** ****) wdtcr2 write watchdog timer control code and address trap area control code d2h: enable address trap area selection (atrap control code) 4eh: clear the watchdog timer binary counter (wdt clear code) b1h: disable the watchdog timer (wdt disable code) others: invalid write only 8.3.1 selection of address trap in internal ram (atas) wdtcr1 8.3.4 address trap reset while wdtcr1 TMP86FH92DMG 8. watchdog timer (wdt) 8.3 address trap page 78 9. time base timer (tbt) the time base timer generates time base for key scanning, dynamic displaying, etc. it also provides a time base timer interrupt (inttbt). 9.1 time base timer 9.1.1 configuration figure 9-1 time base timer configuration 9.1.2 control time base timer is controlled by time base timer control register (tbtcr). time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) (dvoen) (dvock) (dv7ck) tbten tbtck (initial value: 0000 0000) tbten time base timer enable / disable 0: disable 1: enable tbtck time base timer interrupt frequency select : [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 23 fs/2 15 fs/2 15 001 fc/2 21 fs/2 13 fs/2 13 010 fc/2 16 fs/2 8 - 011 fc/2 14 fs/2 6 - 100 fc/2 13 fs/2 5 - 101 fc/2 12 fs/2 4 - 110 fc/2 11 fs/2 3 - 111 fc/2 9 fs/2 - note 1: fc; high-frequency clock [hz], fs; low-frequency clock [hz], *; don't care TMP86FH92DMG page 79 fc/2 23 or fs/2 15 fc/2 21 or fs/2 13 fc/2 16 or fs/2 8 fc/2 14 or fs/2 6 fc/2 13 or fs/2 5 fc/2 12 or fs/2 4 fc/2 11 or fs/2 3 fc/2 9 or fs/2 tbtcr tbten tbtck 3 mpx source clock falling edge detector time base timer control register inttbt interrupt request idle0, sleep0 release request note 2: the interrupt frequency (tbtck) must be selected with the time base timer disabled (tbten = "0"). (the interrupt fre- quency must not be changed with the disable from the enable state.) both frequency selection and enabling can be performed simultaneously. example :set the time base timer frequency to fc/2 16 [hz] and enable an inttbt interrupt. ld (tbtcr) , 00000010b ; tbtck 010 ld (tbtcr) , 00001010b ; tbten 1 di ; imf 0 set (eirl) . 7 table 9-1 time base timer interrupt frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) tbtck time base timer interrupt frequency [hz] normal1/2, idle1/2 mode normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 000 1.91 1 1 001 7.63 4 4 010 244.14 128 - 011 976.56 512 - 100 1953.13 1024 - 101 3906.25 2048 - 110 7812.5 4096 - 111 31250 16384 - 9.1.3 function an inttbt ( time base timer interrupt ) is generated on the first falling edge of source clock ( the divider output of the timing generator which is selected by tbtck. ) after time base timer has been enabled. the divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( figure 9-2 ). figure 9-2 time base timer interrupt TMP86FH92DMG 9. time base timer (tbt) 9.1 time base timer page 80 source clock enable tbt interrupt period tbtcr 9.2 divider output ( dvo) approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. divider output is from dvo pin. 9.2.1 configuration figure 9-3 divider output 9.2.2 control the divider output is controlled by the time base timer control register. time base timer control register 7 6 5 4 3 2 1 0 tbtcr (0036h) dvoen dvock (dv7ck) (tbten) (tbtck) (initial value: 0000 0000) dvoen divider output enable / disable 0: disable 1: enable r/w dvock divider output ( dvo) frequency selection: [hz] normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 13 fs/2 5 fs/2 5 01 fc/2 12 fs/2 4 fs/2 4 10 fc/2 11 fs/2 3 fs/2 3 11 fc/2 10 fs/2 2 fs/2 2 note:selection of divider output frequency (dvock) must be made while divider output is disabled (dvoen="0"). also, in other words, when changing the state of the divider output frequency from enabled (dvoen="1") to disable(dvoen="0"), do not change the setting of the divider output frequency. TMP86FH92DMG page 81 tbtcr output latch port output latch mpx dvoen tbtcr example :1.95 khz pulse output (fc = 16.0 mhz) setting port ld (tbtcr) , 00000000b ; dvock "00" ld (tbtcr) , 10000000b ; dvoen "1" table 9-2 divider output frequency ( example : fc = 16.0 mhz, fs = 32.768 khz ) dvock divider output frequency [hz] normal1/2, idle1/2 mode slow1/2, sleep1/2 mode dv7ck = 0 dv7ck = 1 00 1.953 k 1.024 k 1.024 k 01 3.906 k 2.048 k 2.048 k 10 7.813 k 4.096 k 4.096 k 11 15.625 k 8.192 k 8.192 k TMP86FH92DMG 9. time base timer (tbt) 9.2 divider output ( dvo) page 82 10. 16-bit timer/counter 1 (tc1) 10.1 configuration figure 10-1 timercounter 1 (tc1) TMP86FH92DMG page 83 :::? pin tc1 :w:?::? mett1 start capture clear source clock ppg output mode write to tc1cr 16-bit up-counter clear tc1drb selector tc1dra tc1cr tc1 control register match inttc1 interript tff1 acap1 tc1ck window mode set toggle q 2 toggle set clear q y a d b c s b a y s tc1s clear mppg1 ppg output mode internal reset s enable mcap1 s y a b tc1s 2 set clear command start decoder external trigger start edge detector note: function i/o may not operate depending on i/o port setting. for more details, see the chapter "i/o port". port (note) q pulse width measurement mode falling rising trigger external cmp 16-bit timer register a, b pulse width measurement mode port (note) fc/2 11, fs/2 3 fc/2 7 fc/2 3 10.2 timer/counter control the timercounter 1 is controlled by the timercounter 1 control register (tc1cr) and two 16-bit timer registers (tc1dra and tc1drb). timer register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tc1dra (0011h, 0010h) tc1drah (0011h) tc1dral (0010h) (initial value: 1111 1111 1111 1111) read/write tc1drb (0013h, 0012h) tc1drbh (0013h) tc1drbl (0012h) (initial value: 1111 1111 1111 1111) read/write (write enabled only in the ppg output mode) timercounter 1 control register tc1cr (0014h) 7 6 5 4 3 2 1 0 tff1 acap1 mcap1 mett1 mppg1 tc1s tc1ck tc1m read/write (initial value: 0000 0000) tff1 timer f/f1 control 0: clear 1: set r/w acap1 auto capture control 0 : auto-capture disable 1 : auto-capture enable r/w mcap1 pulse width measurement mode control 0 :double edge capture 1 : single edge capture mett1 external trigger timer mode control 0 : trigger start 1 : trigger start and stop mppg1 ppg output control 0 : continuous pulse generation 1 : one-shot tc1s tc1 start control timer extrig- ger event win- dow pulse ppg r/w 00: stop and counter clear o o o o o o 01: command start o - - - - o 10: rising edge start (ex-trigger/pulse/ppg) rising edge count (event) positive logic count (window) - o o o o o 11: falling edge start (ex-trigger/pulse/ppg) falling edge count (event) negative logic count (window) - o o o o o tc1ck tc1 source clock select [hz] normal1/2, idle1/2 mode divider slow, sleep mode r/w dv7ck = 0 dv7ck = 1 00 fc/2 11 fs/2 3 dv9 fs/2 3 01 fc/2 7 fc/2 7 dv5 - 10 fc/2 3 fc/2 3 dv1 - 11 external clock (tc1 pin input) tc1m tc1 operating mode se- lect 00: timer/external trigger timer/event counter mode 01: window mode 10: pulse width measurement mode 11: ppg (programmable pulse generate) output mode r/w note 1: fc: high-frequency clock [hz], fs: low-frequency clock [hz] note 2: the timer register consists of two shift registers. a value set in the timer register becomes valid at the rising edge of the first source clock pulse that occurs after the upper byte (tc1drah and tc1drbh) is written. therefore, write the lower byte and the upper byte in this order (it is recommended to write the register with a 16-bit access instruction). writing only the lower byte (tc1dral and tc1drbl) does not enable the setting of the timer register. TMP86FH92DMG 10. 16-bit timer/counter 1 (tc1) 10.2 timer/counter control page 84 note 3: to set the mode, source clock, ppg output control and timer f/f control, write to tc1cr during tc1s=00. set the timer f/f1 control until the first timer start after setting the ppg mode. note 4: auto-capture can be used only in the timer, event counter, and window modes. note 5: to set the timer registers, the following relationship must be satisfied. tc1dra > tc1drb > 1 (ppg output mode), tc1dra > 1 (other modes) note 6: set tff1 to 0 in the mode except ppg output mode. note 7: set tc1drb after setting tc1m to the ppg output mode. note 8: when the stop mode is entered, the start control (tc1s) is cleared to 00 automatically, and the timer stops. after the stop mode is exited, set the tc1s to use the timer counter again. note 9: use the auto-capture function in the operative condition of tc1. a captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. read the capture value in a capture enabled condition. note 10: since the up-counter value is captured into tc1drb by the source clock of up-counter after setting tc1cr 10.3 function timercounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 10.3.1 timer mode in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register 1a (tc1dra) value is detected, an inttc1 interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. setting tc1cr figure 10-2 timer mode timing chart TMP86FH92DMG page 87 match detect acap1 tc1drb tc1dra inttc1 interruput request source clock counter source clock counter ? (a) timer mode (b) auto-capture ? 7 6 345 0 timer start 12 3 2 1 4 0 counter clear capture n + 1 n n n m + 2 m + 1 m m capture m + 2 m + 1 n + 1 n m ? 1 m ? 1 m ? 2 n ? 1 n ? 1 n ? 1 10.3.2 external trigger timer mode in the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. for the trigger edge used to start counting, either the rising or falling edge is defined in tc1cr figure 10-3 external trigger timer mode timing chart TMP86FH92DMG page 89 inttc1 interrupt request source clock up-counter tc1dra tc1 pin input inttc1 interrupt request source clock up-counter tc1dra tc1 pin input 0 at the rising edge (tc1s = 10) at the rising edge (tc1s = 10) (a) trigger start (mett1 = 0) count start match detect count start 0 1 2 3 4 2 3 n (b) trigger start and stop (mett1 = 1) count start count start 0 1 2 3 m 0 n n 0 count clear note: m < n count clear 1 2 3 1 n m ? 1 n ? 1 match detect count clear 10.3.3 event counter mode in the event counter mode, the up-counter counts up at the edge of the input pulse to the tc1 pin. either the rising or falling edge of the input pulse is selected as the count up edge in tc1cr 10.3.4 window mode in the window mode, the up-counter counts up at the rising edge of the pulse that is logical anded product of the input pulse to the tc1 pin (window pulse) and the internal source clock. either the positive logic (count up during high-going pulse) or negative logic (count up during low-going pulse) can be selected. when a match between the up-counter and the tc1dra value is detected, an inttc1 interrupt is generated and the up-counter is cleared. define the window pulse to the frequency which is sufficiently lower than the internal source clock programmed with tc1cr 10.3.5 pulse width measurement mode in the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the tc1 pin, and counts up at the edge of the internal clock. either the rising or falling edge of the internal clock is selected as the trigger edge in tc1cr example :duty measurement (resolution fc/2 7 [hz]) clr (inttc1sw). 0 ; inttc1 service switch initial setting address set to convert inttc1sw at each inttc1 ld (tc1cr), 00000110b ; sets the tc1 mode and source clock di ; imf= 0 set (eirh). 3 ; enables inttc1 ei ; imf= 1 ld (tc1cr), 00100110b ; starts tc1 with an external trigger at mcap1 = 0 : pinttc1: cpl (inttc1sw). 0 ; inttc1 interrupt, inverts and tests inttc1 service switch jrs f, sinttc1 ld a, (tc1drbl) ; reads tc1drb (high-level pulse width) ld w,(tc1drbh) ld (hpulse), wa ; stores high-level pulse width in ram reti sinttc1: ld a, (tc1drbl) ; reads tc1drb (cycle) ld w,(tc1drbh) ld (width), wa ; stores cycle in ram : reti ; duty calculation : vinttc1: dw pinttc1 ; inttc1 interrupt vector TMP86FH92DMG page 93 width hpulse tc1 pin inttc1 interrupt request inttc1sw figure 10-6 pulse width measurement mode TMP86FH92DMG 10. 16-bit timer/counter 1 (tc1) 10.3 function page 94 tc1drb inttc1 interrupt request interrupt request tc1 pin input counter internal clock (mcap1 = "1") 23 n count start count start trigger (tc1s = "10") 1 3 2 1 4 0 n 0 capture n - 1 tc1drb inttc1 tc1 pin input counter internal clock (mcap1 = "0") 12 n count start count start (tc1s = "10") 3 2 1 4 0 n capture capture n + 1 m - 2 n + 3 n + 2 n + 1 m - 1 m0 m [application] high-or low-level pulse width measurement [application] (1) cycle/frequency measurement (2) duty measurement (a) single-edge capture (b) double-edge capture 10.3.6 programmable pulse generate (ppg) output mode in the programmable pulse generation (ppg) mode, an arbitrary duty pulse is generated by counting performed in the internal clock. to start the timer, tc1cr example :after stopping ppg, setting the ppg pin to a high-level to restart ppg (fc = 16 mhz) setting port ld (tc1cr), 10000111b ; sets the ppg mode, selects the source clock ldw (tc1dra), 007dh ; sets the cycle (1 ms 2 7 /fc s = 007dh) ldw (tc1drb), 0019h ; sets the low-level pulse width (200 s 2 7 /fc = 0019h) ld (tc1cr), 10010111b ; starts the timer : : ld (tc1cr), 10000111b ; stops the timer ld (tc1cr), 10000100b ; sets the timer mode ld (tc1cr), 00000111b ; sets the ppg mode, tff1 = 0 ld (tc1cr), 00010111b ; starts the timer figure 10-7 ppg output TMP86FH92DMG 10. 16-bit timer/counter 1 (tc1) 10.3 function page 96 q r d ppg pin function output port output enable i/o port output latch shared with ppg output data output toggle set clear q tc1cr figure 10-8 ppg mode timing chart TMP86FH92DMG page 97 inttc1 tc1dra internal clock counter tc1drb tc1dra ppg pin output 0 inttc1 interrupt request interrupt request 12 m01 2 n m01 n 2 n n + 1 n + 1 m (a) continuous pulse generation (tc1s = 01) tc1drb trigger count start timer start counter internal clock tc1 pin input ppg pin output 0 1m n n n + 1 m 0 (b) one-shot pulse generation (tc1s = 10) match detect note: m > n note: m > n [application] one-shot pulse output TMP86FH92DMG 10. 16-bit timer/counter 1 (tc1) 10.3 function page 98 11. 8-bit timercounter (tc3, tc4) 11.1 configuration figure 11-1 8-bit timercounter 3, 4 TMP86FH92DMG page 99 8-bit up-counter decode en a y b s a b y c d e f g h s a y b s s a y b toggle q set clear 8-bit up-counter a b y c d e f g h s decode en toggle q set clear pwm mode pdo, ppg mode pdo mode pwm, ppg mode pwm mode pwm mode 16-bit mode 16-bit mode 16-bit mode 16-bit mode timer, event counter mode overflow overflow timer, event couter mode 16-bit mode clear clear fc/2 7 fc/2 5 fc/2 3 fc/2 fc fc/2 7 fc/2 5 fc/2 3 fc/2 fc pdo, pwm, ppg mode pdo, pwm mode 16-bit mode fc/2 11 or fs/2 3 fc/2 11 or fs/2 3 fs fs tc4cr tc3cr ttreg4 pwreg4 ttreg3 pwreg3 tc3 pin tc4 pin tc4s tc3s inttc3 interrupt request inttc4 interrupt request tff4 tff3 pdo 4 /pwm 4 / ppg 4 pin pdo 3 /pwm 3 / pin tc3ck tc4ck tc3m tc3s tff3 tc4m tc4s tff4 timer f/f4 timer f/f3 11.2 timercounter control the timercounter 3 is controlled by the timercounter 3 control register (tc3cr) and two 8-bit timer registers (ttreg3, pwreg3). timercounter 3 timer register ttreg3 (001ch) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg3 (001eh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg3) setting while the timer is running. note 2: do not change the timer register (pwreg3) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 3 control register tc3cr (001ah) 7 6 5 4 3 2 1 0 tff3 tc3ck tc3s tc3m (initial value: 0000 0000) tff3 time f/f3 control (note 2,3) 0: 1: clear set r/w tc3ck operating clock selection [hz] (note 2,3,6) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 8) fc (note 8) fc (note 8) 111 tc3 pin input tc3s tc3 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc3m tc3m operating mode select (note 2,3,7) 000: 001: 010: 011: 1**: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode 16-bit mode (note 4,5) (each mode is selectable with tc4m.) reserved r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock[hz] note 2: do not change the tc3m, tc3ck and tff3 settings while the timer is running. note 3: to stop the timer operation (tc3s= 1 0), do not change the tc3m, tc3ck and tff3 settings. to start the timer operation (tc3s= 0 1), tc3m, tc3ck and tff3 can be programmed. note 4: to use the timercounter in the 16-bit mode, set the operating mode by programming tc4cr note 8: the clock "fc" can be selected as the source clock only in 8/16 bit pwm mode and in warming-up counter mode in slow or sleep mode. TMP86FH92DMG page 101 the timercounter 4 is controlled by the timercounter 4 control register (tc4cr) and two 8-bit timer registers (ttreg4 and pwreg4). timercounter 4 timer register ttreg4 (001dh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) pwreg4 (001fh) r/w 7 6 5 4 3 2 1 0 (initial value: 1111 1111) note 1: do not change the timer register (ttreg4) setting while the timer is running. note 2: do not change the timer register (pwreg4) setting in the operating mode except the 8-bit and 16-bit pwm modes while the timer is running. timercounter 4 control register tc4cr (001bh) 7 6 5 4 3 2 1 0 tff4 tc4ck tc4s tc4m (initial value: 0000 0000) tff4 timer f/f4 control (note 2,3) 0: 1: clear set r/w tc4ck operating clock selection [hz] (note 2,3,7) normal1/2, idle1/2 mode slow1/2 sleep1/2 mode r/w dv7ck = 0 dv7ck = 1 000 fc/2 11 fs/2 3 fs/2 3 001 fc/2 7 fc/2 7 - 010 fc/2 5 fc/2 5 - 011 fc/2 3 fc/2 3 - 100 fs fs fs 101 fc/2 fc/2 - 110 fc (note 9) fc (note 9) - 111 tc4 pin input tc4s tc4 start control (note 3) 0: 1: operation stop and counter clear operation start r/w tc4m tc4m operating mode select (note 2,3,8) 000: 001: 010: 011: 100: 101: 110: 111: 8-bit timer/event counter mode 8-bit programmable divider output (pdo) mode 8-bit pulse width modulation (pwm) output mode reserved 16-bit timer/event counter mode warm-up counter mode 16-bit pulse width modulation (pwm) output mode 16-bit ppg mode r/w note 1: fc: high-frequency clock [hz] fs: low-frequency clock [hz] note 2: do not change the tc4m, tc4ck and tff4 settings while the timer is running. note 3: to stop the timer operation (tc4s= 1 0), do not change the tc4m, tc4ck and tff4 settings. to start the timer operation (tc4s= 0 1), tc4m, tc4ck and tff4 can be programmed. note 4: when tc4m= 1** (upper byte in the 16-bit mode), the source clock becomes the tc3 overflow signal regardless of the tc4ck setting. note 5: to use the timercounter in the 16-bit mode, select the operating mode by programming tc4m, where tc3cr note 7: the operating clock settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11-1 and table 11-2. note 8: the timer register settings are limited depending on the timer operating mode. for the detailed descriptions, see table 11-3. note 9: the clock "fc" can be selected as the source clock only in 8 bit pwm mode. table 11-1 operating mode and selectable source clock (normal1/2 and idle1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - 8-bit pwm - - 16-bit timer - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - 16-bit ppg - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock table 11-2 operating mode and selectable source clock (slow1/2 and sleep1/2 modes) operating mode fc/2 11 or fs/2 3 fc/2 7 fc/2 5 fc/2 3 fs fc/2 fc tc3 pin input tc4 pin input 8-bit timer - - - - - - - - 8-bit event counter - - - - - - - 8-bit pdo - - - - - - - - 8-bit pwm - - - - - - - 16-bit timer - - - - - - - - 16-bit event counter - - - - - - - - warm-up counter - - - - - - - - 16-bit pwm - - - - - - 16-bit ppg - - - - - - - note 1: for 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit pwm and 16-bit ppg), set its source clock on lower bit (tc3ck). note 2: : available source clock TMP86FH92DMG page 103 table 11-3 constraints on register values being compared operating mode register value 8-bit timer/event counter 1 (ttregn) 255 8-bit pdo 1 (ttregn) 255 8-bit pwm 2 (pwregn) 254 16-bit timer/event counter 1 (ttreg4, 3) 65535 warm-up counter 256 (ttreg4, 3) 65535 16-bit pwm 2 (pwreg4, 3) 65534 16-bit ppg 1 (pwreg4, 3) < (ttreg4, 3) 65535 and (pwreg4, 3) + 1 < (ttreg4, 3) note:n = 3 to 4 TMP86FH92DMG 11. 8-bit timercounter (tc3, tc4) 11.2 timercounter control page 104 11.3 function the timercounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (pdo), 8- bit pulse width modulation (pwm) output modes. the timercounter 3 and 4 (tc3, 4) are cascadable to form a 16- bit timer. the 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (pwm) output and 16-bit programmable pulse generation (ppg) modes. 11.3.1 8-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. when a match between the up-counter and the timer register j (ttregj) value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting. note 1: in the timer mode, fix tcjcr figure 11-2 8-bit timer mode timing chart (tc4) 11.3.2 8-bit event counter mode (tc3, 4) in the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the tcj pin. when a match between the up-counter and the ttregj value is detected, an inttcj interrupt is generated and the up-counter is cleared. after being cleared, the up-counter restarts counting at the falling edge of the input pulse to the tcj pin. two machine cycles are required for the low- or high-level pulse input to the tcj pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 hz in the slow1/2 or sleep1/2 mode. note 1: in the event counter mode, fix tcjcr example :generating 1024 hz pulse using tc4 (fc = 16.0 mhz) setting port ld (ttreg4), 3dh ; 1/1024 2 7 /fc 2 = 3dh ld (tc4cr), 00010001b ; sets the operating clock to fc/2 7 , and 8-bit pdo mode. ld (tc4cr), 00011001b ; starts tc4. note 1: in the programmable divider output mode, do not change the ttregj setting while the timer is running. since ttregj is not in the shift register configuration in the programmable divider output mode, the new value programmed in ttregj is in effect immediately after programming. therefore, if ttregj is changed while the timer is running, an expected operation may not be obtained. note 2: when the timer is stopped during pdo output, the pdoj pin holds the output status when the timer is stopped. to change the output status, program tcjcr figure 11-4 8-bit pdo mode timing chart (tc4) TMP86FH92DMG 11. 8-bit timercounter (tc3, tc4) 11.3 function page 108 12 0 n 0 n 0 n 0 n 0 1 2 2 1 2 1 2 3 1 0 n ? internal source clock counter match detect match detect match detect match detect held at the level when the timer is stopped set f/f write of "1" tc4cr 11.3.4 8-bit pulse width modulation (pwm) output mode (tc3, 4) this mode is used to generate a pulse-width modulated (pwm) signals with up to 8 bits of resolution. the up- counter counts up using the internal clock. when a match between the up-counter and the pwregj value is detected, the logic level output from the timer f/fj is switched to the opposite state. the counter continues counting. the logic level output from the timer f/ fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. the inttcj interrupt request is generated at this time. since the initial value can be set to the timer f/fj by tcjcr figure 11-5 8-bit pwm mode timing chart (tc4) TMP86FH92DMG 11. 8-bit timercounter (tc3, tc4) 11.3 function page 110 1 0 nn+1 ff 0 n n+1 ff 0 1 m m+1 ff 0 1 1 p n ? internal source clock counter m p m p n ? shift registar shift shift shift shift match detect match detect one cycle period match detect match detect n m p n tc4cr 11.3.5 16-bit timer mode (tc3 and 4) in the timer mode, the up-counter counts up using the internal clock. the timercounter 3 and 4 are cascadable to form a 16-bit timer. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr figure 11-6 16-bit timer mode timing chart (tc3 and tc4) 11.3.6 16-bit event counter mode (tc3 and 4) in the event counter mode, the up-counter counts up at the falling edge to the t c3 pin. the timercounter 3 and 4 are cascadable to form a 16-bit event counter. when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected after the timer is started by setting tc4cr since pwreg4 and 3 in the pwm mode are serially connected to the shift register, the values set to pwreg4 and 3 can be changed while the timer is running. the values set to pwreg4 and 3 during a run of the timer are shifted by the inttcj interrupt request and loaded into pwreg4 and 3. while the timer is stopped, the values are shifted immediately after the programming of pwreg4 and 3. set the lower byte (pwreg3) and upper byte (pwreg4) in this order to program pwreg4 and 3. (programming only the lower or upper byte of the register should not be attempted.) if executing the read instruction to pwreg4 and 3 during pwm output, the values set in the shift register is read, but not the values set in pwreg4 and 3. therefore, after writing to the pwreg4 and 3, reading data of pwreg4 and 3 is previous value until inttc4 is generated. for the pin used for pwm output, the output latch of the i/o port must be set to 1. note 1: in the pwm mode, program the timer register pwreg4 and 3 immediately after the inttc4 interrupt request is generated (normally in the inttc4 interrupt service routine.) if the programming of pwregj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next inttc4 interrupt request is generated. note 2: when the timer is stopped during pwm output, the pwm 4 pin holds the output status when the timer is stopped. to change the output status, program tc4cr figure 11-7 16-bit pwm mode timing chart (tc3 and tc4) TMP86FH92DMG 11. 8-bit timercounter (tc3, tc4) 11.3 function page 114 1 0 an an+1 ffff 0 an an+1 ffff 0 1 bm bm+1 ffff 0 bm cp b c 1 1 cp n a an ? ? ? internal source clock 16-bit shift register shift shift shift shift counter match detect match detect one cycle period match detect match detect an bm cp an m p tc4cr 11.3.8 16-bit programmable pulse generate (ppg) output mode (tc3 and 4) this mode is used to generate pulses with up to 16-bits of resolution. the timer counter 3 and 4 are cascadable to enter the 16-bit ppg mode. the counter counts up using the internal clock or external clock. when a match between the up-counter and the timer register (pwreg3, pwreg4) value is detected, the logic level output from the timer f/f4 is switched to the opposite state. the counter continues counting. the logic level output from the timer f/f4 is switched to the opposite state again when a match between the up-counter and the timer register (ttreg3, ttreg4) value is detected, and the counter is cleared. the inttc4 interrupt is generated at this time. two machine cycles are required for the high- or low-level pulse input to the tc3 pin. therefore, a maximum frequency to be supplied is fc/2 4 hz in the normal1/2 or idle1/2 mode, and fs/2 4 to in the slow1/2 or sleep1/2 mode. since the initial value can be set to the timer f/f4 by tc4cr figure 11-8 16-bit ppg mode timing chart (tc3 and tc4) TMP86FH92DMG 11. 8-bit timercounter (tc3, tc4) 11.3 function page 116 1 0 mn mn+1 qr-1 mn qr-1 1 mn mn+1 mn+1 0 qr 0 qr 1 0 internal source clock counter write of "0" match detect match detect match detect mn mn mn match detect match detect ? n m ? ? r q ? held at the level when the timer stops f/f clear tc4cr 11.3.9 warm-up counter mode in this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. the timer counter 3 and 4 are cascadable to form a 16- bit timercounter. the warm-up counter mode has two types of mode; switching from the high-frequency to low- frequency, and vice-versa. note 1: in the warm-up counter mode, fix tcicr |