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? vitesse semiconductor corporation p age 1 3/27/00 741 calle plano, camarillo, ca 93012 ? 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 features general description the vsc7186 is a quad gigabit ethernet transceiver ic. each of the four transmitters has a 10-bit wide bus, running at 125 mhz, which accepts 8b/10b encoded transmit characters and serializes the data onto high speed differential outputs at rates between 1.05 and 1.36 gb/s. the transmit data must be synchronous to the reference clock. each receiver samples serial receive data, recovers the clock and data, deserializes it into 10-bit receive characters, outputs a recovered clock and detects ?comma? characters. the vsc7186 contains on-chip pll circuitry for synthesis of the baud-rate transmit clock and extraction of the clocks from the received serial streams. vsc7186 block diagram (1 of 4 channels) four complete transceiver functions in one ic full gigabit ethernet (ieee 802.3z) compliance pin-compatible with agilent hdmp-1686a 5-volt tolerant ttl inputs uses reference clock to latch tx data 1/10 th or 1/20 th baud rate recovered clocks common local loopback control single comma detect enable cable equalization in receivers automatic lock-to-reference jtag access port 2kv esd protection on all pins 3.3v power supply, 2.67 w max dissipation 208 pin, 23 mm bga packaging si+ si- q d serial to parallel clock recovery 10/ comma rxi(0:9) clock parallel to serial so+ so- 20 10 10 q d qd detect d q d q multiply unit x10 1 0 rci1 rci0 syni txi(0:9) rfc1 rcm loop sync cap0 cap1 unit 10 sel
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 2 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 functional description notation in this document, each of the four channels are identified as channel 0, 1, 2 or 3. when discussing a signal on any specific channel, the signal will have the channel number embedded in the name, i.e. ? t 3 (0:9) ? . when referring to the common behavior of a signal which is used on each of the four channels, the notation ? i ? is used. differential signals, i.e. soi+ and soi-, may be referred to as a single signal, i.e. soi, by dropping reference to the ? + ? and ? - ? . clock synthesizer the vsc7186 clock multiplier unit (cmu) multiplies the reference frequency provided on the rfc1 input by 10 to achieve a baud rate clock between 1.05 and 1.36 ghz. the rfc1 input is ttl. the on-chip pll uses a single external 0.1uf capacitor, connected between cap0 and cap1, to control the loop filter. this capacitor should be a multilayer ceramic dielectric, or better, with at least a 5v working voltage rating and a good temperature coefficient, i.e., npo is preferred but x7r may be acceptable. these capacitors are used to minimize the impact of common mode noise on the clock multiplier unit, especially power supply noise. higher value capacitors provide better robustness in systems. npo is preferred because if an x7r capacitor is used, the power supply noise sensitivity will vary with temperature. for best noise immunity, the designer may use a three capacitor circuit with one differential capacitor between cap0 and cap1, c1, a capacitor from cap0 to ground, c2, and a capacitor from cap1 to ground, c3. larger values are better but 0.1uf is adequate. however, if the designer cannot use a three capacitor circuit, a single differential capacitor, c1, is adequate. these components should be isolated from noisy traces. figure 1: loop filter capacitors (best circuit) serializer the vsc7186 accepts ttl input data as four parallel 10 bit characters on the ti(0:9) buses which are latched into the input registers on the rising edge of rfc1. the 10-bit parallel transmission character will be serialized and transmitted on the soi+/- pecl differential outputs at the baud rate with bit ti0 (bit a) transmit- ted first. user data should be encoded using 8b/10b or an equivalent code. the mapping to 10b encoded bit nomenclature and transmission order is illustrated below, along with the recognized comma pattern. cap0 cap1 c1 c2 c3 vsc7186 c1=c2=c3= >0.1uf multilayer ceramic surface mount npo (prefered) or x7r 5v working voltage rating
? vitesse semiconductor corporation p age 3 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 table 1: transmission order and mapping of a 10b character clock recovery the vsc7186 accepts differential high speed serial input from the selected source (either the pecl sii+/- pins or the internal soi+/- data), extracts the clock and retimes the data. equalizers are included in the receiver to open the data eye and compensate for intersymbol interference (isi) which may be present in the incoming data. the serial bit stream should be encoded so as to provide dc balance and limited run length by an 8b/10b encoding scheme. the digital clock recovery unit (cru) is completely monolithic and requires no external components. for proper operation, the baud rate of the data stream to be recovered should be within + 200 ppm of ten times the ref frequency. for example, gigabit ethernet systems use 125 mhz oscillators with a +/- 100ppm accuracy resulting in +/-200 ppm between vsc7186 pairs. deserializer the recovered serial bit stream is converted into a 10-bit parallel output character. the vsc7186 provides complementary ttl recovered clocks, rci0 and rci1, at one-twentieth of the serial baud rate if rcm=low, or a single clock at one-tenth the serial baud rate, on rci1 only, if rcm=high. the clocks are generated by dividing down the high-speed recovered clock which is phase locked to the serial data. the serial data is retimed, deserialized and output on ri(0:9). if serial input data is not present, or does not meet the required baud rate, the vsc7186 will continue to produce a recovered clock so that downstream logic may continue to function. the rci0/rci1 output frequency under these circumstances will differ from its expected frequency by no more than + 1%. word alignment the vsc7186 provides 7-bit comma character recognition and data word alignment. word synchronization is enabled on all channels by asserting sync high. when synchronization is enabled, the receiver examines the recovered serial data for the presence of the ? comma ? pattern. this pattern is ? 0011111xxx ? , where the leading zero corresponds to the first bit received. the comma sequence is not contained in any normal 8b/10b coded data character or pair of adjacent characters. it occurs only within special characters, known as k28.1, k28.5 and k28.7, which are defined for synchronization purposes. improper comma alignment is defined as any of the following conditions: 1) the comma is not aligned within the 10-bit transmission character such that ri(0..6) = ? 0011111 ? . 2) the comma straddles the boundary between two 10-bit transmission characters. 3) the comma is properly aligned but occurs in the received character presented during the rising edge of rci0 rather than rci1. when an improperly aligned comma is encountered, the recovered clock is stretched, never slivered, so that the comma character and recovered clocks are aligned properly to ri(0:9). this results in proper character and word alignment. when the parallel data alignment changes in response to a improperly aligned comma pattern, data bit t9 t8 t7 t6 t5 t4 t3 t2 t1 t0 10b bit position j h g f i e d c b a comma character xxx1111100
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 4 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 data which would have been presented on the parallel output port prior to the comma character, and possibly the comma character itself, may be lost. possible loss of the comma character is data dependent, according to the relative change in alignment. data subsequent to the comma character will always be output correctly and prop- erly aligned. on encountering a comma character, syni is driven high. the syni pulse is presented simultaneously with the comma character and has a duration equal to the data. the syni signal is timed such that it can be cap- tured by the adjoining protocol logic on the rising edge of rci1. functional waveforms for synchronization are given in figure 1. the first k28.5 shows the case where the comma is detected, but it is misaligned so a change in the output data alignment is required. note that up to three characters prior to the comma character may be corrupted by the realignment process. the second k28.5 shows the case when a comma is detected and no phase adjustment is necessary. it illustrates the position of the syni pulse in relation to the comma character on ri(0:9). figure 2: misaligned and aligned k28.5 characters loopback operation loopback operation is controlled by the loop line. when this line is high, the outgoing high-speed serial data on each of the four channels is internally looped back into that channel ? s high-speed serial receiver section. this provides for in-circuit testing capability independent of the transmission medium. jtag access port a jtag access port is provided to assist in board-level testing. through this port most pins can be accessed or controlled and all ttl outputs can be tri-stated. a full description of the jtag functions on this device is available in ? vsc7186 jtag access port functionality ? . circuits designed exclusively for the hdmp-1686a will automatically disable the jtag port. the pinout table in this data sheet shows the proper connections for either hdmp-1686a emulation or for jtag functionality (in parentheses). corrupt corrupt corrupt k28.5 data1 data2 data3 k28.5 data rc i 0 rc i 1 rc i 0 rc i 1 syn i rx i (0:9) (rcm high) (rcm low) misaligned comma: stretched aligned comma
? vitesse semiconductor corporation p age 5 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 ac characteristics figure 3: transmit timing waveforms table 2: transmitter ac characteristics parameter description min typ max units conditions t 1 ti(0:9) setup time to the rising edge of rfc1 1.5 ?? ns. measured between the valid data level of ti(0:9) to the 1.4v point of rfc1 t 2 ti(0:9) hold time after the rising edge of rfc1 1.0 ?? ns. t sdr ,t sdf ti+/ti- rise and fall time ?? 300 ps. 20% to 80%, 75 ohm load to vdd/ 2, tested on a sample basis t lat latency from rising edge of rfc1 to ti0 appearing on so bit 0i 7bc + 0.66ns ? 7bc + 1.46ns note: bc = bit clocks ns = nanoseconds transmitter output jitter rj random jitter (rms) ? 58ps. measured at so+/-, 1 sigma deviation of 50% crossing pt dj serial data output deterministic jitter (pk-pk) ? 35 80 ps. ieee 802.3z clause 38.68, tested on a sample basis data valid txi(0:9) t 1 10 bit data t 2 rfc1 data valid data valid t lat +/-soi s0 s1 s2 rfc1
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 6 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 figure 4: receive timing waveforms table 3: receive ac characteristics ? parameters description min. max. units conditions t 1 ttl outputs valid prior to rci1/rci0 rise 3.0 ? ns. @ 1.25gb/s t 2 ttl outputs valid after rci1 or rci0 rise 2.0 ? ns. @ 1.25gb/s t 3 delay between rising edge of rci1 to rising edge of rci0 10 x t ri -500 10 x t ri +500 ps. t ri is the bit period of the incoming data on ri. t 4 period of rci1 and rci0 1.98 x t ref 2.02 x t ref ps. whether or not locked to serial data. t r , t f ttl output rise and fall time ? 2.4 ns. between v il(max) and v ih(min) , into 10 pf. load. t lock data acquisition lock time* ? 1400 bit times 8b/10b idle pattern. tested on a sample basis r lat latency from bit 0 of rxi0 appearing on si to rising edge of rci1 12bc + 2.77ns 13bc + 7.28 note: bc = bit clocks ns = nanoseconds. * note: probability of recovery for data acquisition is 95% per section 5.3 of fc-ph rev. 4.3 rci0 rxi(0:9) rci1 syni rcm=low rci0 rci1 rcm=high va l i d va l i d va l i d t 1 t 2 r lat +/-sii s0 s1 s2 rci1
? vitesse semiconductor corporation p age 7 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 figure 5: rfc1 waveform table 4: reference clock requirements parameters description min max units conditions fr frequency range 105 136 mhz range over which both transmit and receive reference clocks on any link may be centered fo frequency offset -200 200 ppm. maximum frequency offset between transmit and receive reference clocks on one link dc rfc1 duty cycle 35 65 % measured at 1.4v t rcr ,t rcf rfc1 rise and fall time ? 1.5 ns. between v il(max) and v ih(min) rfc1 v il(max) v ih(min) t l t h
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 8 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 dc characteristics note: (1) refer to application note, an-37, for differential measurement techniques. parameters description min. typ max. units conditions ttl outputs v oh ttl output high voltage 2.4 ?? vi oh = -1.0ma v ol ttl output low voltage ?? 0.5 v i ol = +1.0ma i oz ttl output leakage current ?? 50 a when set to high-impedance state through jtag. ttl inputs v ih ttl input high voltage 2.0 ? 5.5 v 5v tolerant inputs v il ttl input low voltage 0 ? 0.8 v i ih ttl input high current ? 50 500 a v in =2.4v i il ttl input low current ?? -500 a v in =0.5v high speed outputs ? v out75 (1) tx output differential peak- to-peak voltage swing 1200 ? 2200 mvp- p 75 ? to v dd ? 2.0 v (ti+) - (ti-) ? v out50 (1) ti output differential peak- to-peak voltage swing 1000 ? 2200 mvp- p 50 ? to v dd ? 2.0 v (ti+) - (ti-) high speed inputs ? v in (1) pecl differential peak-to-peak input voltage swing 200 ? 2600 mv ri+ - ri- miscellaneous v dd power supply voltage 3.14 ? 3.47 v 3.3v + 5% p d power dissipation ? 2.2 2.67 w maximum at 3.47v, outputs open, 25 o c, 136mhz ck, prbs 2 7 -1 parallel input pattern i dd supply current (all supplies) ?? 770 ma i dda supply current on v dda ? 100 ? ma
? vitesse semiconductor corporation p age 9 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 absolute maximum ratings (1) power supply voltage, (v dd ) ............................................................................................................-0.5v to +4v dc input voltage (pecl inputs)............................................................................................ -0.5v to v dd +0.5v dc input voltage (ttl inputs) .................................................................................................. ....... -0.5v to 5.5v dc output voltage (ttl outputs)........................................................................................ -0.5v to v dd + 0.5v output current (ttl outputs) ................................................................................................... .............. +/-50ma output current (pecl outputs).................................................................................................. ..............+/-50ma case temperature under bias .................................................................................................... .....-55 o to +125 o c storage temperature............................................................................................................ ......... -65 o c to +150 o c maximum input esd (human body model)........................................................................................... ... 2000 v recommended operating conditions power supply voltage, (v dd ) ................................................................................................................+3.3v+ 5% operating temperature range ........................................................... 0 o c ambient to +100 o c case temperature notes: (1) caution: stresses listed under ?absolute maximum ratings? may be applied to devices one at a time without causing per- manent damage. functionality at or above the values listed is not implied. exposure to these values for extended periods may affect device reliability.
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 10 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 table 5: pin table 17 gndt rc31 rx30 rx34 rx36 gnd vcct tx23 tx27 nc tx30 tx34 tx38 nc sync nc (tck) gnd 16 vcct rc30 gndt rx33 rx35 rx39 tx20 tx24 tx28 vcc tx31 tx35 tx39 nc vcctr gndtr gnd 15 gndt syn3 vcct rx32 gndt rx38 tx21 tx25 tx29 gnd tx32 tx36 vcc nc (tdi) gnd (trstn) gnd gnd 14 rx28 rx29 vcc rx31 vcct rx37 tx22 tx26 vcc gnd tx33 tx37 loop gnd vcc vcc si3+ 13 vcct rx25 rx26 rx27 not populated so3+ so3- vccp3 si3- 12 rx21 rx22 rx23 rx24 gnd gnd gnd gnd 11 gndt rx20 vcct gndt so2+ so2- vccp2 si2+ 10 vcc syn2 rc20 rc21 gnd gnd gnd si2- 9 vcct gnd nc nc (tms) cap0 cap1 vcca gnd 8 rx16 rx17 rx18 rx19 gnd gnda gnd gnd 7 rx14 vcct gndt rx15 so1- so1+ vccp1 si1+ 6 rx10 rx11 rx12 rx13 gnd gnd gnd si1- 5 rc10 rc11 vcct gnd so0- so0+ vccp0 vcc 4 syn1 gndt vcct gndt rx03 gndt vcc tx17 tx13 gnd vcc tx07 tx03 gnd vcc vcc si0+ 3 gndt rx09 rx06 vcct rx02 vcct gnd tx16 tx12 gnd gnd tx06 tx02 nc gnd vcc si0- 2 vcc rx08 rx05 rx01 rc01 syn0 tx19 tx15 tx11 nc (tdo) tx09 tx05 tx01 nc nc gnd gnd 1 gndt rx07 rx04 rx00 rc00 nc tx18 tx14 tx10 nc tx08 tx04 tx00 nc rfc1 rcm0 gnd a b c d e f g h j k l m n p r t u
? vitesse semiconductor corporation p age 11 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 table 6: pin description pin name description n1, n2, n3 n4, m1, m2, m3, m4, l1 l2 tx0-0, tx0-1, tx0-2 tx0-3, tx0-4, tx0-5, tx0-6, tx0-7, tx0-8 tx0-9 input - ttl: 10-bit transmit bus for channel 0. parallel data on this bus is latched on the rising edge of ref. tx0-0 is transmitted first. j1, j2, j3 j4, h1, h2 h3, h4, g1 g2 tx1-0, tx1-1, tx1-2 tx1-3, tx1-4, tx1-5, tx1-6, tx1-7, tx1-8, tx1-9 input - ttl: 10-bit transmit bus for channel 1. parallel data on this bus is latched on the rising edge of ref. tx1-0 is transmitted first. g16, g15, g14 h17, h16, h15 h14, j17, j16 j15 tx2-0, tx2-1, tx2-2 tx2-3, tx2-4, tx2-5, tx2-6, tx2-7, tx2-8, tx2-9 input - ttl: 10-bit transmit bus for channel 2. parallel data on this bus is latched on the rising edge of ref. tx2-0 is transmitted first. l17, l16, l15 l14, m17, m16 m15, m14, n17 n16 tx3-0, tx3-1, tx3-2, tx3-3, tx3-4, tx3-5, tx3-6, tx3-7, tx3-8, tx3-9 input - ttl: 10-bit transmit bus for channel 3. parallel data on this bus is latched on the rising edge of ref. tx3-0 is transmitted first. r1 rfc1 input - ttl: ttl reference clock. this rising edge of rfc1 provides the reference clock, at 1/10th of the baud rate to the clock multiplying pll. the rising edge of rfc1 will latch txi(0:9) on all four channels r5, p5 r7, p7 p11, r11 p13, r13 so0+, so0- so1+, so1- so2+, so2- so3+, so3- output - differential pecl (ac coupling recommended) these pins output the serialized transmit data for channels 0-3 when loop is low. when loop is high, soi+ is high and soi- is low. d1, d2, e3 e4, c1, c2 c3, b1, b2 b3 rx0-0, rx0-1, rx0-2, rx0-3, rx0-4, rx0-5, rx0-6, rx0-7, rx0-8, rx0-9 output - ttl: 10-bit receive bus for channel 0. parallel data on this bus is synchronous to rc0-0 and rc0-1. rx0-0 is the first bit received. a6, b6, c6 d6, a7, d7 a8, b8, c8 d8 rx1-0, rx1-1, rx1-2, rx1-3, rx1-4, rx1-5, rx1-6, rx1-7, rx1-8, rx1-9 output - ttl: 10-bit receive bus for channel 1. parallel data on this bus is synchronous to rc1-0 and rc1-1. rx1-0 is the first bit received. b11, a12, b12 c12, d12, b13 c13, d13, a14 b14 rx2-0, rx2-1, rx2-2, rx2-3, rx2-4, rx2-5, rx2-6, rx2-7, rx2-8, rx2-9 output - ttl: 10-bit receive bus for channel 2. parallel data on this bus is synchronous to rc2-0 and rc2-1. rx2-0 is the first bit received.
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 12 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 c17, d14, d15 d16, d17, e16 e17, f14, f15 f16 rx3-0, rx3-1, rx3-2, rx3-3, rx3-4, rx3-5, rx3-6, rx3-7, rx3-8, rx3-9 output - ttl: 10-bit receive bus for channel 3. parallel data on this bus is synchronous to rc3-0 and rc3-1. rx3-0 is the first bit received. t1 rcm0 input - ttl: recovered clock mode control. when low, rci0/rci1 is 1/20 th of the incoming baud rate. when high, rci0/rci1 is 1/10 th the incoming baud rate. e1 e2 rc00 rc01 output - complementary ttl: recovered complementary clocks for channel 0 at 1/10 th the incoming baud rate (rcm=high) or 1/20 th (rcm=low). synchronous to the rx0(0:9) bus and syn0. a5 b5 rc10 rc11 output - complementary ttl: recovered complementary clocks for channel 1 at 1/10 th the incoming baud rate (rcm=high) or 1/20 th (rcm=low). synchronous to the rx1(0:9) bus and syn1. c10 d10 rc20 rc21 output - complementary ttl: recovered complementary clocks for channel 2 at 1/10 th the incoming baud rate (rcm=high) or 1/20 th (rcm=low). synchronous to the rx20:9) bus and syn2. b16 b17 rc30 rc31 output - complementary ttl: recovered complementary clocks for channel 3 at 1/10 th the incoming baud rate (rcm=high) or 1/20 th (rcm=low). synchronous to the rx3(0:9) bus and syn3. u4, u3 u7, u6 u11, u10 u14, u13 si0+, si0- si1+, si1- si2+, si2- si3+, si3- input - differential pecl (ac coupling recommended): serial receive data inputs for channels 0-3 which are selected when loop is low. [internally biased to vdd/2] n14 loop input - ttl: parallel loopback enable input. sii is input to the cru for channel i (normal operation) when loop is low. when high, internal loopback paths from soi to sii are enabled. r17 sync input - ttl: enables syni and word alignment when high. when low, keeps current word alignment and disables syni (always low). f2 a4 b10 b15 syn0 syn1 syn2 syn3 output - ttl: comma detect for channel i. this output goes high for half of an rci1 period to indicate that rxi(0:9) contains a comma character ( ? 0011111xxx ? ). syni will go high only during a cycle when rci0 is rising. syni is enabled when sync is high. p9 r9 cap0 cap1 analog: loop filter capacitor for the clock multiply unit. typically 0.1 uf connected between cap0 and cap1. amplitude is less than 3.3v. t17 nc (tck) (input - ttl: jtag test clock) d9 nc (tms) (input - ttl: jtag test mode select) r15 gnd (trstn) (input - ttl: jtag test reset, active low) p15 nc (tdi) (input - ttl: jtag test data input) pin name description
? vitesse semiconductor corporation p age 13 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 k2 nc (tdo) (output - ttl: jtag test data output) t9 vcca analog power supply r8 gnda analog ground. tie to common ground plane with gnd. a2,a10,c14 g4,j14,k16 l4,n15,r4 r14,r16,t3 t4,t14,u5 vcc digital logic power supply c4, d3,f3 a9, b7, c5 a13, a16, c11 c15, e14, g17 vcct ttl output power supply. t5 t7 t11 t13 vccp0 vccp1 vccp2 vccp3 pecl i/o power supply for channel i. a1,a3,a11,a15 a17,b4,c7 c16,d4,d11 e15,f4 gndt ground for ttl outputs b9,f17,g3,k3, k14,k15,l3,p6, p8,p10,p12,p14 r6,r10,r12,t2 t6,t8,t10,t12 t15,t16,u1,u2, u8,u9,u12,u15 u16, u17 gnd ground pin name description
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 14 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 package thermal characteristics the vsc7186 is packaged in a 23 mm bga package with 1.27mm eutectic ball spacing. the construction of the package is shown below. figure 6: package cross section the vsc7186 is designed to operate with a case temperature up to 100 o c. in order to comply with this tar- get, the user must guarantee that the case temperature specification of 100 o c is not violated. with the thermal resistances shown below, the vsc7186 can operate in still air ambient temperatures of 40 o c [ 40 o c = 100 o c - 2.5w * 24 o c/w ]. if the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. table 7: thermal resistance moisture sensitivity level this device is rated at with a moisture sensitivity level 3 rating. refer to application note an-20 for appropriate handling procedures. symbol description va l u e units jc thermal resistance from junction to case 4.3 o c/w ca thermal resistance from case to ambient in still air including conduction through the leads. 24 o c/w ca-100 thermal resistance from case to ambient with 100 lfm airflow 21 o c/w ca-200 thermal resistance from case to ambient with200 lfm airflow 18.5 o c/w ca-400 thermal resistance from case to ambient with 400 lfm airflow 17 o c/w ca-600 thermal resistance from case to ambient with 600 lfm airflow 15 o c/w die adhesive copper heat spreader encapsulant eutectic solder balls wirebond polyimide dielectric die attach epoxy
? vitesse semiconductor corporation p age 15 3/27/00 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet g52306-0, rev. 2.0 package information a b c d e f g h j k l m n p r t u 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 23.0 23.0 1.27 typ 1.55 typ pin a1 indicator bottom view top view
vitesse semiconductor corporation advance product information vsc7186 quad transceiver for gigabit ethernet page 16 ? vitesse semiconductor corporation 741 calle plano, camarillo, ca 93012 805/388-3700 fax: 805/987-5896 3/27/00 g52306-0, rev. 2.0 ordering information the part number for this product is formed by a combination of the device number and the package style: VSC7186TW device type: vsc7186: quad gigabit transceiver package style tw: 208 pin, 23 mm bga marking information the package is marked with three lines of text as shown below. figure 7: package marking information notice this document contains information about a product during its fabrication or early sampling phase of development. the information contained in this document is based on design targets, simulation results or early prototype test results. characteristic data and other specifications are subject to change without notice. therefore the reader is cautioned to confirm that this data sheet is current prior to design or order placement. warning vitesse semiconductor corporation ? s product are not intended for use in life support appliances, devices or systems. use of a vitesse product in such applications without written consent is prohibited. vitesse VSC7186TW ####aaaa part number datecode package suffix lot tracking code pin a1 identifier

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