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? semiconductor component s industries, llc, 2017 1 publication order number : june 2017 - rev. 1 lc75809pt/d www.onsemi.com ordering information see detailed ordering and shipping info rmation on page 43 of this data sheet. * computer control bus (ccb) is an on semiconductor?s original bus format and the bus addresses are controlled by on semiconductor. lc75809pt 1/4 and 1/3-duty general-purpose lcd driver overview the lc75809pt is the 1/4 duty and 1/3 duty general-purpose microprocessor-controlled lcd driver that can be used in applications such as frequency display in products with electronic tuning. in addition to being able to drive up to 352 segments directly, the lc75809pt can also control up to 12 general-purpose out put ports. because it has the pwm output of a maximum of 6 ch, the brightness control of the led backlight of rgb ? 2 can be done. incorporation of an oscillation circuit helps to reduce the number of external resistors and capacitors required. features ? support for 1/4-duty 1/3-bias or 1/3-duty 1/3-bias drive techniques under serial data control. when 1/4-duty : capable of driving up to 352 segments when 1/3-duty : capable of driving up to 267 segments ? serial data input supports ccb* format communication with the system controller. (support 3.3 v and 5 v operation) ? serial data control of the power-saving mode based backup function and the all segments forced off function. ? serial data control of switching between the segment output port and general-purpose output port function. (support for up to 12 general-purpose output ports) ? support for the pwm output function of a maximum of 6 ch. (it can output from the general-purpose output port). ? support for clock output function of 1 ch. (it can output from the general-purpose output port). ? serial data control of the frame frequency of the common and segment output waveforms. ? serial data control of switching be tween the internal oscillator operating mode and external clock operating mode. ? high generality, since display data is displayed directly without the intervention of a decoder circuit. ? built-in display contrast adjustment circuit. ? the inh pin allows the display to be forced to the off state. ? incorporation of an oscillator circuit. (incorporation of resistor and capacitor for an oscillation) tqfp100 14x14 / tqfp100
lc75809pt www.onsemi.com 2 specifications absolute maximum ratings at ta = 25 ? c, v ss = 0 v parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ? 0.3 to +6.8 v input voltage v in 1 ce, cl, di, inh ? 0.3 to +6.8 v v in 2 osci, v dd 1, v dd 2 ? 0.3 to v dd +0.3 output voltage v out s1 to s89, com1 to com4, p1 to p12 ? 0.3 to v dd +0.3 v output current i out 1 s1 to s88 300 ? a i out 2 com1 to com4, s89 3 ma i out 3 p1 to p12 5 allowable power dissipation pd max ta = 85 ? c 200 mw operating temperature topr ? 40 to +85 ? c storage temperature tstg ? 55 to +125 ? c allowable operating ranges at ta = ? 40 to +85 ? c, v ss = 0 v parameter symbol conditions ratings unit min typ max supply voltage v dd v dd 4.5 6.3 v input voltage *1 v dd 1 v dd 1 2/3v dd 0 v dd 0 v v dd 2 v dd 2 1/3v dd 0 v dd 0 input high level voltage v ih 1 ce, cl, di, inh 0.4v dd 6.3 v v ih 2 osci: external clock operating mode 0.4v dd v dd input low level voltage v il 1 ce, cl, di, inh 0 0.2v dd v v il 2 osci: external clock operating mode 0 0.2v dd external clock operating frequency f ck osci: external clock operating mode [figure4] 10 300 600 khz external clock duty cycle d ck osci: external clock operating mode [figure4] 30 50 70 % data setup time tds cl, di [figure2], [figure3] 160 ns data hold time tdh cl, di [figure2], [figure3] 160 ns ce wait time tcp ce, cl [figure2], [figure3] 160 ns ce setup time tcs ce, cl [figure2], [figure3] 160 ns ce hold time tch ce, cl [figure2], [figure3] 160 ns high level clock pulse width t ? h cl [figure2], [figure3] 160 ns low level clock pulse width t ? l cl [figure2], [figure3] 160 ns rise time tr ce, cl, di [figure2], [figure3] 160 ns fall time tf ce, cl, di [figure2], [figure3] 160 ns inh switching time tc inh , ce [figure5], [figure6] [figure7], [figure8] 10 ? s note : *1. v dd 0 = 0.70v dd to v dd stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc75809pt www.onsemi.com 3 electrical characteristics for the allowable operating ranges parameter symbol pin conditions ratings unit min typ max hysteresis v h ce, cl, di, inh 0.03v dd v input high level current i ih 1 ce, cl, di, inh v i = 6.3 v 5.0 ? a i ih 2 osci v i = v dd : external clock operating mode 5.0 input low level current i il 1 ce, cl, di, inh v i = 0 v ? 5.0 ? a i il 2 osci v i = 0 v: external clock operating mode ? 5.0 output high level voltage *1 v oh 1 s1 to s89 i o = ? 20 ? a v dd 0 ? 0.9 v v oh 2 com1 to com4 i o = ? 100 ? a v dd 0 ? 0.9 v oh 3 p1 to p12 i o = ? 1 ma v dd ? 0.9 output low level voltage v ol 1 s1 to s89 i o = 20 ? a 0.9 v v ol 2 com1 to com4 i o = 100 ? a 0.9 v ol 3 p1 to p12 i o = 1 ma 0.9 output middle level voltage *1 *2 v mid 1 s1 to s89 1/3 bias i o = 20 ? a 2/3v dd 0 ? 0.9 2/3v dd 0 +0.9 v v mid 2 s1 to s89 1/3 bias i o = 20 ? a 1/3v dd 0 ? 0.9 1/3v dd 0 +0.9 v mid 3 com1 to com4 1/3 bias i o = 100 ? a 2/3v dd 0 ? 0.9 2/3v dd 0 +0.9 v mid 4 com1 to com4 1/3 bias i o = 100 ? a 1/3v dd 0 ? 0.9 1/3v dd 0 +0.9 oscillator frequency fosc internal oscillator circuit internal oscillator operating mode 240 300 360 khz current drain i dd 1 v dd power-saving mode 100 ? a i dd 2 v dd v dd = 6.3 v output open internal oscillator operating mode 1000 2000 i dd 3 v dd v dd = 6.3 v output open external clock operating mode f ck = 300 khz v ih 2 = 0.5v dd v il 2 = 0.1v dd 1000 2000 note: *1. v dd 0 = 0.70v dd to v dd note: *2. excluding the bias voltage gener ation divider resistors built in the v dd 1 and v dd 2. (see figure 1.) to the common and segment drivers [figure 1] v dd 2 v dd 1 except these resistors. contrast adjuster v dd v ss v dd 0 product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc75809pt www.onsemi.com 4 1. when cl is stopped at the low level [figure 2] 2. when cl is stopped at the high level [figure 3] 3. osci pin clock timing in external clock operating mode [figure 4] osci t ck l t ck h f ck = 1 t ck h + t ck l [khz] d ck = t ck h t ck h + t ck l ? 100[%] v il 2 50% v ih 2 tds v il 1 v il 1 v il 1 v ih 1 50% v ih 1 v ih 1 tch tcs tcp tdh tr tf t ? l t ? h ce cl di ? ? ? ? ? ? ? ? tds v il 1 v il 1 v il 1 v ih 1 v ih 1 50% v ih 1 tch tcs tcp tdh tr tf t ? h t ? l ce cl di ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 5 package dimensions unit : mm tqfp100 14x14 / tqfp100 case 932ay issue a xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxx ymddd 14.0 ? 0.1 12 0.5 (1.0) 0.10 14.0 ? 0.1 16.0 ? 0.2 16.0 ? 0.2 100 0.2 0.10 1.2 max (1.0) 0.1 ? 0.1 0 to 10 ? 0.125 0.5 ? 0.2 (unit: mm) 15.40 15.40 0.28 0.50 1.00 soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
lc75809pt www.onsemi.com 6 pin assignment block diagram top view s55 s51 s52 s53 s54 s56 s57 s58 s59 s60 s61 s62 s63 s64 s65 s66 s67 s68 s69 s70 s71 s72 s73 s74 s75 p5/s5 p11/s11 p4/s4 p3/s3 p2/s2 p1/s1 s77 s79 s78 s80 s76 lc75809pt (tqfp100) s81 s82 s83 s85 s84 s87/com4 s86 com3 com1 com2 v dd s88 v dd 1 v ss v dd 2 s89/osci ce inh cl s35 s34 s33 s32 s31 s29 s30 s27 s28 s26 di 51 75 50 76 26 100 25 1 p10/s10 p9/s9 p8/s8 p7/s7 p6/s6 s16 s22 s15 s14 s13 p12/s12 s21 s20 s19 s18 s17 s25 s24 s23 s40 s39 s38 s37 s36 s45 s44 s43 s42 s41 s50 s49 s48 s47 s46 s1/p1 s2/p2 s12/p12 s13 ce cl di com4/s87 com3 com2 com1 v ss v dd 2 v dd 1 v dd inh s89/osci shift register segment driver & latch ccb interface clock generator common driver s88 control register s86 contrast adjuster v dd 0
lc75809pt www.onsemi.com 7 pin functions pin pin no. function active i/o handling when unused s1/p1 to s12/p12 s13 to s86 s88 1 to 12 13 to 86 91 segment outputs for displaying the display data transferred by serial data input. the s1/p1 to s12/p12 pins can be used as general-purpose output ports under serial data control. - o open com1 to com3 com4/s87 90 to 88 87 common driver outputs the frame frequency is fo[hz]. the com4/s87 pin can be used as a segment output in 1/3 duty. - o open s89/osci 96 segment output. this pin can also be us ed as the external clock input pin when the external clock operating mode is selected by control data. - i/o open ce cl di 98 99 100 serial data transfer inputs. must be connected to the controller. ce : chip enable cl : synchronization clock di : transfer data h - i i i gnd inh 97 display off control input ? inh =low(v ss )?.display forced off s1/p1 to s12/p12=low (v ss ) (these pins are forcibly set to the general-purpose output port function and held at the v ss level.) s13 to s86, s88=low(v ss ) com1 to com3=low(v ss ) com4/s87=low(v ss ) s89/osci=low(v ss ) (this pin is forcibly set to the segment output port function and held at the v ss level.) stops the internal oscillator. inhibits external clock input. display contrast adjustment circuit stopped. ? inh =high(v dd )?display on enables the internal oscillator circuit. (internal oscillator operating mode) enables external clock input. (external clock operating mode) display contrast adjustment circuit operation is enabled. however, serial data transfer is possible when the display is forced off. l i gnd v dd 1 93 used to apply the lcd drive 2/3 bias voltage externally. - i open v dd 2 94 used to apply the lcd drive 1/3 bias voltage externally. - i open v dd 92 power supply pin. a power voltage of 4.5 to 6.3v must be applied to this pin. - - - v ss 95 ground pin. must be connected to ground. - - -
lc75809pt www.onsemi.com 8 serial data input 1. 1/4 duty (1) when cl is stopped at the low level ? when the display data is transferred b1 b0 d1 0 0 dd 3 bits display data 88 bits ccb address 8 bits ? ? ? ? di cl ce 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 0 d73 d72 d74 d75 d77 d76 d78 d79 fixed data 5 bits d81 d80 d82 d83 d85 d84 d86 d87 d88 0 b1 b0 d89 0 0 ? ? ? ? 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 1 0 0 d161 d160 d162 d163 d165 d164 d166 d167 d169 d168 d170 d171 d173 d172 d174 d175 d176 0 b1 b0 d261 0 0 display data 92 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 d352 d351 d350 1 1 0 d333 d332 d334 d335 d337 d336 d338 d339 fixed data 1 bits d341 d340 d342 d343 d345 d344 d346 d347 d348 d349 b1 b0 d177 0 0 display data 84 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 0 d249 d248 d250 d251 d253 d252 d254 d255 d257 d256 d258 d259 0 d260 0 0 0 0 ? ? ? ? display data 88 bits fixed data 5 bits dd 3 bits ccb address 8 bits fixed data 9 bits dd 3 bits ccb address 8 bits dd 3 bits ccb address 8 bits ? ? ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 9 ? when the control data is transferred note: dd is the direction data. b1 b0 w10 0 0 control data 45 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 w14 w13 w15 w20 w22 w21 w23 w24 w30 w25 w31 w32 w34 w33 w35 w11 w12 0 0 0 0 1 0 1 w50 w45 w51 w52 w54 w53 w55 w60 w62 w61 w63 w64 0 w65 0 0 0 0 w42 w41 w43 w44 w40 di cl ce b1 b0 p1a 0 0 control data 61 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 p8c p8b p8a p7c p9a p2a p1d p2b p2c p3b p3a p3c p4a p4c p4b p5a p5b p6a p5c p6b p6c p7a p7b p1b p1c dd 3 bits 0 0 0 0 0 0 1 pf3 pf2 fc0 fc1 oc fc2 ct0 ct1 p0 ct2 p1 p2 dt p3 dn exf sc bu p12c p12b pf0 pf1 p10a p9b p9c p10b p10c p11a p11b p11c p12a ccb address 8 bits ccb address 8 bits dd 3 bits ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 10 (2) when cl is stopped at the high level ? when the display data is transferred ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? b1 b0 d89 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 1 0 0 d161 d160 d162 d163 d165 d164 d166 d167 d169 d168 d170 d171 d173 d172 d174 d175 d176 0 b1 b0 d1 0 0 dd 3 bits display data 88 bits di cl ce 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 0 d73 d72 d74 d75 d77 d76 d78 d79 fixed data 5 bits d81 d80 d82 d83 d85 d84 d86 d87 d88 0 b1 b0 d177 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 1 0 d249 d248 d250 d251 d253 d252 d254 d255 d257 d256 d258 d259 0 d260 0 0 0 0 b1 b0 d261 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 d352 d351 d350 1 1 0 d333 d332 d334 d335 d337 d336 d338 d339 d341 d340 d342 d343 d345 d344 d346 d347 d348 d349 ccb address 8 bits display data 88 bits fixed data 5 bits dd 3 bits ccb address 8 bits ccb address 8 bits display data 84 bits fixed data 9 bits dd 3 bits dd 3 bits fixed data 1 bits display data 92 bits ccb address 8 bits ? ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 11 ? when the control data is transferred note: dd is the direction data ? ccb address ......................... ?40h? ? d1 to d352 ........................... display data ? p1a, p1b, p1c, p1d ............ ge neral-purpose output port (p1) function setting control data ? p2a, p2b, p2c to p12a, ....... gene ral-purpose output port (p2 to p12) function setting control data p12b, p12c ? pf0 to pf3 ............................ pwm output wa veform frame frequency setting control data ? fc0 to fc2 ........................... common/segm ent output waveform frame frequency setting control data ? oc ........................................ in ternal oscillator operating mode/externa l clock operating mode switching cont rol data ? ct0 to ct2 .......................... display contrast setting control data ? p0 to p3 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data ? dn ........................................ s88 pin an d s89/osci pin state setting control data ? exf ...................................... external clock operatin g frequency setting control data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? w10 to w15, w20 to w25, ... pwm data of the pwm output w30 to w35, w40 to w45, w50 to w55, w60 to w65 ? di cl ce b1 b0 p1a 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 p8c p8b p8a p7c p9a p2a p1d p2b p2c p3b p3a p3c p4a p4c p4b p5a p5b p6a p5c p6b p6c p7a p7b p1b p1c 0 0 0 0 0 0 1 pf3 pf2 fc0 fc1 oc fc2 ct0 ct1 p0 ct2 p1 p2 dt p3 dn exf sc bu p12c p12b pf0 pf1 p10a p9b p9c p10b p10c p11a p11b p11c p12a ccb address 8 bits control data 61 bits dd 3 bits b1 b0 w10 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 w14 w13 w15 w20 w22 w21 w23 w24 w30 w25 w31 w32 w34 w33 w35 w11 w12 0 0 0 0 1 0 1 w50 w45 w51 w52 w54 w53 w55 w60 w62 w61 w63 w64 0 w65 0 0 0 0 w42 w41 w43 w44 w40 ccb address 8 bits control data 45 bits dd 3 bits ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 12 2. 1/3 duty (1) when cl is stopped at the low level ? when the display data is transferred ? ? ? ? ? ? ? ? b1 b0 d1 0 0 di cl ce 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 0 d73 d72 d74 d75 d77 d76 d78 d79 d81 d80 d82 d83 d85 d84 d86 d87 0 0 b1 b0 d88 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 d177 1 0 0 d160 d159 d161 d162 d164 d163 d165 d166 d168 d167 d169 d170 d172 d171 d173 d174 d175 d176 b1 b0 d178 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 d267 0 1 0 d250 d249 d251 d252 d254 d253 d255 d256 d258 d257 d259 d260 d262 d261 d263 d264 d265 d266 ccb address 8 bits display data 87 bits fixed data 6 bits dd 3 bits ccb address 8 bits display data 90 bits fixed data 3 bits dd 3 bits ccb address 8 bits display data 90 bits fixed data 3 bits dd 3 bits ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 13 ? when the control data is transferred note: dd is the direction data. ? ? b1 b0 w10 0 0 control data 45 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 w14 w13 w15 w20 w22 w21 w23 w24 w30 w25 w31 w32 w34 w33 w35 w11 w12 0 0 0 0 1 0 1 w50 w45 w51 w52 w54 w53 w55 w60 w62 w61 w63 w64 0 w65 0 0 0 0 w42 w41 w43 w44 w40 di cl ce b1 b0 p1a 0 0 control data 61 bits 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 p8c p8b p8a p7c p9a p2a p1d p2b p2c p3b p3a p3c p4a p4c p4b p5a p5b p6a p5c p6b p6c p7a p7b p1b p1c dd 3 bits 0 0 0 0 0 0 1 pf3 pf2 fc0 fc1 oc fc2 ct0 ct1 p0 ct2 p1 p2 dt p3 dn exf sc bu p12c p12b pf0 pf1 p10a p9b p9c p10b p10c p11a p11b p11c p12a ccb address 8 bits ccb address 8 bits dd 3 bits ? ? ? ? ? ?
lc75809pt www.onsemi.com 14 (2) when cl is stopped at the high level ? when the display data is transferred ? ? ? ? ? ? ccb address 8 bits display data 87 bits fixed data 6 bits dd 3 bits ccb address 8 bits display data 90 bits fixed data 3 bits dd 3 bits ccb address 8 bits display data 90 bits fixed data 3 bits dd 3 bits b1 b0 d1 0 0 di cl ce 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 0 0 0 0 d73 d72 d74 d75 d77 d76 d78 d79 d81 d80 d82 d83 d85 d84 d86 d87 0 0 b1 b0 d88 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 d177 1 0 0 d160 d159 d161 d162 d164 d163 d165 d166 d168 d167 d169 d170 d172 d171 d173 d174 d175 d176 b1 b0 d178 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 0 0 0 d267 0 1 0 d250 d249 d251 d252 d254 d253 d255 d256 d258 d257 d259 d260 d262 d261 d263 d264 d265 d266 ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 15 ? when the control data is transferred note: dd is the direction data ? ccb address ......................... ?40h? ? d1 to d267 ........................... display data ? p1a, p1b, p1c, p1d ............ ge neral-purpose output port (p1) function setting control data ? p2a, p2b, p2c to p12a, ....... gene ral-purpose output port (p2 to p12) function setting control data p12b, p12c ? pf0 to pf3 ............................ pwm output wa veform frame frequency setting control data ? fc0 to fc2 ........................... common/segm ent output waveform frame frequency setting control data ? oc ........................................ in ternal oscillator operating mode/externa l clock operating mode switching cont rol data ? ct0 to ct2 .......................... display contrast setting control data ? p0 to p3 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data ? dn ........................................ s88 pin an d s89/osci pin state setting control data ? exf ...................................... external clock operatin g frequency setting control data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? w10 to w15, w20 to w25, ... pwm data of the pwm output w30 to w35, w40 to w45, w50 to w55, w60 to w65 ? di cl ce b1 b0 p1a 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 p8c p8b p8a p7c p9a p2a p1d p2b p2c p3b p3a p3c p4a p4c p4b p5a p5b p6a p5c p6b p6c p7a p7b p1b p1c 0 0 0 0 0 0 1 pf3 pf2 fc0 fc1 oc fc2 ct0 ct1 p0 ct2 p1 p2 dt p3 dn exf sc bu p12c p12b pf0 pf1 p10a p9b p9c p10b p10c p11a p11b p11c p12a ccb address 8 bits control data 61 bits dd 3 bits b1 b0 w10 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 w14 w13 w15 w20 w22 w21 w23 w24 w30 w25 w31 w32 w34 w33 w35 w11 w12 0 0 0 0 1 0 1 w50 w45 w51 w52 w54 w53 w55 w60 w62 w61 w63 w64 0 w65 0 0 0 0 w42 w41 w43 w44 w40 ccb address 8 bits control data 45 bits dd 3 bits ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 16 3. 1/4 duty (simple mode transfer) (1) when cl is stopped at the low level note: dd is the direction data. b1 b0 d2 d1 0 0 d82 ct2 ct1 di cl ce 0 0 0 d85 1 0 0 b3 b2 a1 a0 a3 a2 d83 d87 d86 d88 ct0 0 sc fc p2 p1 0 0 bu p0 oc p3 dt dn d84 d79 d80 d81 b1 b0 0 0 d90 d89 0 0 0 0 d176 1 0 0 b3 b2 a1 a0 a3 a2 d172 d171 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 d173 d175 d174 d169 d170 d167 d168 0 b1 b0 0 0 d178 d177 0 0 0 0 0 1 0 0 b3 b2 a1 a0 a3 a2 d256 d255 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 d257 d258 d259 d260 0 d343 b1 b0 0 0 d262 d261 0 0 0 0 d349 1 0 0 b3 b2 a1 a0 a3 a2 d344 d351 d350 d352 0 0 1 0 1 0 0 0 0 0 d348 d347 d346 d345 d342 d341 d340 d339 ccb address 8 bits display data 88 bits control data 14 bits dd 2 bits ccb address 8 bits display data 88 bits fixed data 14 bits dd 2 bits display data 84 bits ccb address 8 bits fixed data 18 bits dd 2 bits ccb address 8 bits display data 92 bits fixed data 10 bits dd 2 bits ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 17 (2) when cl is stopped at the high level note: dd is the direction data ? ccb address ......................... ?40h? ? d1 to d352 ........................... display data ? oc ........................................ in ternal oscillator operating mode/externa l clock operating mode switching cont rol data ? ct0 to ct2 .......................... display contrast setting control data ? p0 to p3 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data ? dn ........................................ s88 pin an d s89/osci pin state setting control data ? fc ......................................... co mmon/segment output waveform frame frequency setting control data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? ? ? ? ? ? ? ? ? p3 sc b1 b0 d2 d1 0 0 0 0 0 d85 d80 d79 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d82 d81 d84 d83 d87 d86 d88 ct2 ct1 ct0 oc p1 p0 p2 bu 0 0 0 fc dt dn 0 b1 b0 0 0 0 0 0 d173 d168 d90 d89 b3 b2 a1 a0 a3 a2 1 0 0 d175 d174 0 0 0 1 0 d172 d171 d170 d169 0 0 0 0 0 0 0 d176 0 0 0 d167 0 b1 b0 0 0 0 0 0 0 d256 d178 d177 d255 b3 b2 a1 a0 a3 a2 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 d257 d258 d259 d260 0 b1 b0 0 0 0 0 0 d349 d344 d262 d261 d343 b3 b2 a1 a0 a3 a2 1 0 0 d351 d350 d352 0 0 1 1 0 0 0 0 0 0 0 d348 d347 d346 d345 d342 d341 d340 d339 ccb address 8 bits display data 88 bits control data 14 bits dd 2 bits ccb address 8 bits display data 88 bits fixed data 14 bits dd 2 bits ccb address 8 bits display data 84 bits fixed data 18 bits dd 2 bits ccb address 8 bits display data 92 bits fixed data 10 bits dd 2 bits ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 18 4. 1/3 duty (simple mode transfer) (1) when cl is stopped at the low level note: dd is the direction data. b1 b0 d2 d1 0 0 d82 ct2 ct1 di cl ce 0 0 0 d85 1 0 0 b3 b2 a1 a0 a3 a2 d83 d87 d86 0 ct0 0 sc fc p2 p1 0 0 bu p0 oc p3 dt dn d84 d79 d80 d81 b1 b0 0 0 d89 d88 0 0 0 0 d175 1 0 0 b3 b2 a1 a0 a3 a2 d171 d170 d177 d176 0 0 0 1 0 0 0 0 0 0 0 0 0 d172 d174 d173 d168 d169 d166 d167 0 b1 b0 0 0 d179 d178 0 0 0 0 d266 1 0 0 b3 b2 a1 a0 a3 a2 d257 d256 0 d267 0 0 0 0 0 1 0 0 0 0 0 d265 d263 d262 d264 d258 d259 d260 d261 ccb address 8 bits display data 87 bits control data 15 bits dd 2 bits ccb address 8 bits display data 90 bits fixed data 12 bits dd 2 bits ccb address 8 bits display data 90 bits fixed data 12 bits dd 2 bits ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
lc75809pt www.onsemi.com 19 (2) when cl is stopped at the high level note: dd is the direction data ? ccb address ......................... ?40h? ? d1 to d267 ........................... display data ? oc ........................................ in ternal oscillator operating mode/externa l clock operating mode switching cont rol data ? ct0 to ct2 .......................... display contrast setting control data ? p0 to p3 ................................ segment output port/general -purpose output port switching control data ? dt ........................................ 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data ? dn ........................................ s88 pin an d s89/osci pin state setting control data ? fc ......................................... co mmon/segment output waveform frame frequency setting control data ? sc ......................................... segment on/off control data ? bu ........................................ normal mode/powe r-saving mode control data ? ? ? ? ? ? ? ? ? ? ? ? p3 sc b1 b0 d2 d1 0 0 0 0 0 d85 d80 d79 di cl ce b3 b2 a1 a0 a3 a2 1 0 0 d82 d81 d84 d83 d87 d86 0 ct2 ct1 ct0 oc p1 p0 p2 bu 0 0 0 fc dt dn 0 b1 b0 0 0 0 0 0 d172 d167 d89 d88 b3 b2 a1 a0 a3 a2 1 0 0 d174 d173 0 0 0 1 0 d171 d170 d169 d168 0 0 0 0 0 0 0 d175 d177 d176 0 d166 0 b1 b0 0 0 0 0 0 d262 d257 d179 d178 d256 b3 b2 a1 a0 a3 a2 1 0 0 0 d267 0 0 0 0 1 0 0 0 0 0 0 0 d266 d265 d263 d264 d258 d259 d260 d261 ccb address 8 bits display data 87 bits control data 15 bits dd 2 bits ccb address 8 bits display data 90 bits fixed data 12 bits dd 2 bits ccb address 8 bits display data 90 bits fixed data 12 bits dd 2 bits ? ? ? ?
lc75809pt www.onsemi.com 20 serial data transfer example 1. 1/4 duty ? when 261 or more segments are used all 496 bits of serial data must be sent. ? when fewer than 261 segments are used the serial data shown below (the control data) must always be sent. 96 bits 8 bits d2 d1 d69 d177 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d70 d71 d72 d73 d75 d76 d77 d78 d80 d87 d81 d82 d83 d84 d85 d86 d88 0 0 0 0 0 0 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d89 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d178 d90 d157 d158 d159 d160 d245 d246 d163 d164 d165 d166 d167 d168 d169 d170 d171 d172 d173 d174 d175 d176 0 0 0 0 0 d79 0 d251 d252 d253 d254 d255 d256 d257 d258 d259 d260 0 0 0 0 0 0 0 0 0 0 d74 d161 d162 d261 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d262 d329 d334 d339 d340 d341 d342 d343 d344 d345 d346 d347 d348 d349 d350 d351 d352 0 0 d247 d248 d249 d250 d338 d337 d336 d335 d333 d332 d331 d330 0 0 d68 d156 d244 d328 1 0 0 1 1 1 48 bits 8 bits w11 w10 w14 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 w15 w20 w21 w22 w24 w25 w30 w31 w33 w44 w34 w35 w40 w41 w42 w43 w45 w32 w23 w13 w12 w51 w50 w54 w55 w60 w61 w62 w64 w65 0 0 0 0 0 0 0 0 0 1 1 0 w63 w53 w52 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 p1b p1a p2a p2b p2c p3a p3b p4a p4b p4c p5a p5c p8a p6a p6b p6c p7a p7b p7c p8b p8c p9c p10a p10b p10c p11a p5b p3c p9b p9a p1d p1c 64 bits p11c p11b p12c pf0 pf1 pf2 pf3 fc1 fc2 oc ct0 ct2 ext p0 p1 p2 p3 dt dn sc bu 0 0 1 0 0 ct1 fc0 0 0 p12b p12a 8 bits 48 bits 8 bits w11 w10 w14 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 w15 w20 w21 w22 w24 w25 w30 w31 w33 w44 w34 w35 w40 w41 w42 w43 w45 w32 w23 w13 w12 w51 w50 w54 w55 w60 w61 w62 w64 w65 0 0 0 0 0 0 0 0 0 1 1 0 w63 w53 w52 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 p1b p1a p2a p2b p2c p3a p3b p4a p4b p4c p5a p5c p8a p6a p6b p6c p7a p7b p7c p8b p8c p9c p10a p10b p10c p11a p5b p3c p9b p9a p1d p1c 64 bits p11c p11b p12c pf0 pf1 pf2 pf3 fc1 fc2 oc ct0 ct2 ext p0 p1 p2 p3 dt dn sc bu 0 0 1 0 0 ct1 fc0 0 0 p12b p12a 8 bits
lc75809pt www.onsemi.com 21 2. 1/3 duty ? when 178 or more segments are used all 400 bits of serial data must be sent. ? when fewer than 178 segments are used the serial data shown below (the control data) must always be sent. 96 bits 8 bits d2 d1 d69 d178 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d70 d71 d72 d73 d75 d76 d77 d78 d80 d87 d81 d82 d83 d84 d85 d86 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d88 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d179 d89 d156 d157 d158 d159 d246 d247 d162 d163 d164 d165 d166 d167 d168 d169 d170 d171 d172 d173 d174 d175 d176 d177 0 0 0 d79 0 d252 d253 d254 d255 d256 d257 d258 d259 d260 d261 d262 d263 d264 d265 d266 d267 0 0 0 0 d74 d160 d161 d248 d249 d250 d251 0 0 d68 d155 d245 1 0 0 1 48 bits 8 bits w11 w10 w14 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 w15 w20 w21 w22 w24 w25 w30 w31 w33 w44 w34 w35 w40 w41 w42 w43 w45 w32 w23 w13 w12 w51 w50 w54 w55 w60 w61 w62 w64 w65 0 0 0 0 0 0 0 0 0 1 1 0 w63 w53 w52 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 p1b p1a p2a p2b p2c p3a p3b p4a p4b p4c p5a p5c p8a p6a p6b p6c p7a p7b p7c p8b p8c p9c p10a p10b p10c p11a p5b p3c p9b p9a p1d p1c 64 bits p11c p11b p12c pf0 pf1 pf2 pf3 fc1 fc2 oc ct0 ct2 ext p0 p1 p2 p3 dt dn sc bu 0 0 1 0 0 ct1 fc0 0 0 p12b p12a 8 bits 48 bits 8 bits w11 w10 w14 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 w15 w20 w21 w22 w24 w25 w30 w31 w33 w44 w34 w35 w40 w41 w42 w43 w45 w32 w23 w13 w12 w51 w50 w54 w55 w60 w61 w62 w64 w65 0 0 0 0 0 0 0 0 0 1 1 0 w63 w53 w52 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 p1b p1a p2a p2b p2c p3a p3b p4a p4b p4c p5a p5c p8a p6a p6b p6c p7a p7b p7c p8b p8c p9c p10a p10b p10c p11a p5b p3c p9b p9a p1d p1c 64 bits p11c p11b p12c pf0 pf1 pf2 pf3 fc1 fc2 oc ct0 ct2 ext p0 p1 p2 p3 dt dn sc bu 0 0 1 0 0 ct1 fc0 0 0 p12b p12a 8 bits
lc75809pt www.onsemi.com 22 3. 1/4 duty (simple mode transfer) ? when 261 or more segments are used all 416 bits of serial data must be sent. ? when fewer than 261 segments are used either 104, 208 or 312 bits of serial data must be sent, depending on the number of segments to be used. however, the serial data shown below (the d1 to d88 di splay data and the control data) must always be sent. 4. 1/3duty (simple mode transfer) ? when 178 or more segments are used all 312 bits of serial data must be sent. ? when fewer than 178 segments are used either 104 or 208 bits of serial data must be sent, depending on the number of segments to be used. however, the serial data shown below (the d1 to d87 di splay data and the control data) must always be sent. 104 bits 8 bits d2 d1 d77 d177 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d78 d79 d80 d81 d83 d84 d85 d86 d88 p1 0 oc ct0 ct1 ct2 p0 p2 p3 fc sc bu 0 0 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d89 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d178 d90 d165 d166 d167 d168 d253 d254 d171 d172 d173 d174 d175 d176 0 0 0 0 0 0 0 0 0 0 0 0 0 d87 0 d259 d260 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 d82 d169 d170 d261 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d262 d337 d342 d347 d348 d349 d350 d351 d352 0 0 0 0 0 0 0 0 0 0 d255 d256 d257 d258 d346 d345 d344 d343 d341 d340 d339 d338 dn dt d76 d164 d252 d336 1 0 0 1 1 1 104 bits 8 bits d2 d1 d77 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d78 d79 d80 d81 d83 d84 d85 d86 d88 p1 0 oc ct0 ct1 ct2 p0 p2 p3 fc sc bu 0 0 d87 d82 dn dt d76 104 bits 8 bits d2 d1 d77 d178 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d78 d79 d80 d81 d83 d84 d85 d86 0 p1 0 oc ct0 ct1 ct2 p0 p2 p3 fc sc bu 0 0 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d88 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d179 d89 d164 d165 d166 d167 d254 d255 d170 d171 d172 d173 d174 d175 d176 d177 0 0 0 0 0 0 0 0 0 0 0 d87 0 d260 d261 d262 d263 d264 d265 d266 d267 0 0 0 0 0 0 0 0 0 0 0 0 d82 d168 d169 d256 d257 d258 d259 dn dt d76 d163 d253 1 0 0 1 104 bits 8 bits d2 d1 d77 0 0 0 0 0 0 1 0 b0 b1 b2 b3 a0 a1 a2 a3 d78 d79 d80 d81 d83 d84 d85 d86 0 p1 0 oc ct0 ct1 ct2 p0 p2 p3 fc sc bu 0 0 d87 d82 dn dt d76
lc75809pt www.onsemi.com 23 control data functions (1) p1a,p1b,p1c,p1d ?? ?????. general-purpose ou tput port (p1) functio n setting control data p2a,p2b,p2c to p12a,p12b,p12c ? general-purpose output port (p2 to p12) function setting control data these control data bits set the general-purpose output fu nction (high or low level output), pwm output function or clock output function of the p1 output pin, and the general-purpose output function (high or low level output) or pwm output function of the p2 to p12 output pins. however, be careful of being unable to set a pwm output function when the external clock operating frequency is set the f ck 2=38[khz]typ (exf="1") in external clock operating mode (oc= "1"). in addition, be careful of setting of the general-purpose output function (high or low level output) in the case of the simple mode transfer forcibly. p1a p1b p1c p1d general-purpose output port (p1) function 0 0 0 0 general-purpose output function (high or low level output) 1 0 0 0 pwm output function (ch1) (support for pwm data w10 to w15) 0 1 0 0 pwm output function (ch2) (support for pwm data w20 to w25) 1 1 0 0 pwm output function (ch3) (support for pwm data w30 to w35) 0 0 1 0 pwm output function (ch4) (support for pwm data w40 to w45) 1 0 1 0 pwm output function (ch5) (support for pwm data w50 to w55) 0 1 1 0 pwm output function (ch6) (support for pwm data w60 to w65) 1 1 1 0 clock output function (clock frequency : fosc/2, f ck /2) 0 0 0 1 clock output function (clock frequency : fosc/8, f ck /8) note : when are setting (p1a,p1b,p1c,p1d)=(1,x,x,1), (x,1,x,1), and (x,x,1,1), the function of general-purpose output ports p1 is set the general-purpose output function (high or low level output). x: don?t care pna pnb pnc general-purpose output port (p2 to p12) function 0 0 0 general-purpose output function (high or low level output) 1 0 0 pwm output function (ch1) (support for pwm data w10 to w15) 0 1 0 pwm output function (ch2) (support for pwm data w20 to w25) 1 1 0 pwm output function (ch3) (support for pwm data w30 to w35) 0 0 1 pwm output function (ch4) (support for pwm data w40 to w45) 1 0 1 pwm output function (ch5) (support for pwm data w50 to w55) 0 1 1 pwm output function (ch6) (support for pwm data w60 to w65) note1 : the data pna, pnb and pnc (note : n=2 to 12) are the control data switching the general-purpose output function or pwm output function of the general-purpose output ports pn (note : n=2 to 12). for example, if the s10/p10 output pin is set the general-purpose output port, the general-purpose output port p10 pin is selected the pwm output function (ch1) when (p10a,p10b,p10c)=(1,0,0). note2 : when are setting (pna,pnb,pnc)=(1,1,1) / (note : n= 2 to 12), the function of general-purpose output ports pn (note : n=2 to 12) is set the general-purpose output function (high or low level output).
lc75809pt www.onsemi.com 24 (2) pf0 to pf3 ? pwm output waveform frame frequency setting control data these control data bits set the frame frequency of the pwm output waveforms. however, when the pwm output function isn?t used, these control data bits become invalid . in addition, when the external clock operating frequency is set the f ck 2=38[khz]typ (exf="1") in external clock operating mode (oc= "1") or when the serial data transfer is the simple mode transfer, these control data bits become invalid. control data pwm output waveform frame frequency fp[hz] pf0 pf1 pf2 pf3 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) 0 0 0 0 fosc/1536 f ck 1/1536 1 0 0 0 fosc/1408 f ck 1/1408 0 1 0 0 fosc/1280 f ck 1/1280 1 1 0 0 fosc/1152 f ck 1/1152 0 0 1 0 fosc/1024 f ck 1/1024 1 0 1 0 fosc/896 f ck 1/896 0 1 1 0 fosc/768 f ck 1/768 1 1 1 0 fosc/640 f ck 1/640 0 0 0 1 fosc/512 f ck 1/512 1 0 0 1 fosc/384 f ck 1/384 0 1 0 1 fosc/256 f ck 1/256 note : when is setting (pf0,pf1,pf2,pf3)=(1,1,0,1) and (x,x,1,1), the frame frequency is same as frame frequency at the time of the (pf0,pf1,pf2,pf3)=(1,0,1,0) setting (fosc/896, f ck 1/896). x: don?t care (3) fc0 to fc2 ? common/segment output waveform fram frequency control data these control data bits set the frame frequency of the common and segment output waveforms. control data common/segment output wa veform frame fr equency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz] typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96 note : when is setting (fc0,f c1,fc2)=(1,1,1), the frame frequency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). however, in the case of the simple mode transfer, the frame frequency of the common and segment output waveforms is set as following by the control data fc. control data common/segment output wa veform frame fr equency fo[hz] fc internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 f ck 1=300[khz] typ) 0 fosc/3072 f ck 1/3072 1 fosc/1536 f ck 1/1536
lc75809pt www.onsemi.com 25 (4) oc ? internal oscillator operating mode/external clock operating mode switching control data this control data bit selects either the internal oscillator operating mode or external clock operating mode. oc fundamental clock operating m ode i/o pin (s89/osci) state 0 internal oscillator operating mode s89 1 external clock operating mode osci note : s89 : segment output osci : external clock input (5) ct0 to ct2 ? display c ontrast setting control data these control data bits set display contrast. ct0 to ct2 : sets the display contrast (7 steps) ct0 ct1 ct2 lcd drive 3/3 bias voltage v dd 0 level 0 0 0 1.00v dd =v dd -(0.05v dd 0) 1 0 0 0.95v dd =v dd -(0.05v dd 1) 0 1 0 0.90v dd =v dd -(0.05v dd 2) 1 1 0 0.85v dd =v dd -(0.05v dd 3) 0 0 1 0.80v dd =v dd -(0.05v dd 4) 1 0 1 0.75v dd =v dd -(0.05v dd 5) 0 1 1 0.70v dd =v dd -(0.05v dd 6) note : when is setting (ct0,ct1,ct2)=(1,1,1), the lcd drive 3/3 bias voltage v dd 0 level is 1.00v dd . note that although the display contrast can be ad justed by operating the built-in display contrast adjustment circuit, it can also be adjusted by modifying the supply pin v dd voltage level. (6) p0 to p3 ? segment output port/general-purpose output port switching control data these control data bits switch the segment output port/general-purpose output port functions of the s1/p1 to s12/p12 output pins. control data output pin state p0 p1 p2 p3 s1/p1 s2/p2 s3/p3 s4/p4 s5/p5 s6 /p6 s7/p7 s8/p8 s9/p9 s10/p10 s11/p11 s12/p12 0 0 0 0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 0 0 0 1 p1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 0 0 1 0 p1 p2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 0 0 1 1 p1 p2 p3 s4 s5 s6 s7 s8 s9 s10 s11 s12 0 1 0 0 p1 p2 p3 p4 s5 s6 s7 s8 s9 s10 s11 s12 0 1 0 1 p1 p2 p3 p4 p5 s6 s7 s8 s9 s10 s11 s12 0 1 1 0 p1 p2 p3 p4 p5 p6 s7 s8 s9 s10 s11 s12 0 1 1 1 p1 p2 p3 p4 p5 p6 p7 s8 s9 s10 s11 s12 1 0 0 0 p1 p2 p3 p4 p5 p6 p7 p8 s9 s10 s11 s12 1 0 0 1 p1 p2 p3 p4 p5 p6 p7 p8 p9 s10 s11 s12 1 0 1 0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 s11 s12 1 0 1 1 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 s12 1 1 0 0 p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 note1 : sn(n=1 to 12) : segment output ports pn(n=1 to 12) : general-purpose output ports note2 : when are setting (p0,p1,p2,p3)=(1,1,0,1), (1,1,1,0 ), and (1,1,1,1), the all p1/s1 to p12/s12 output pins selects the segment output port.
lc75809pt www.onsemi.com 26 the table below lists the correspondence between the display data and the output pins when these pins are selected to be general-purpose output ports (general-purpose output function). output pin correspondence display data 1/4 duty 1/3 duty s1/p1 d1 d1 s2/p2 d5 d4 s3/p3 d9 d7 s4/p4 d13 d10 s5/p5 d17 d13 s6/p6 d21 d16 s7/p7 d25 d19 s8/p8 d29 d22 s9/p9 d33 d25 s10/p10 d37 d28 s11/p11 d41 d31 s12/p12 d45 d34 for example, if the circuit is operated in 1/4 duty and the s4/p4 output pin is selected to be a general-purpose output port and is set general-purpose output function, the s4/p4 output pin will output a high (v dd ) level when the display data d13 is 1, and will output a low (v ss ) level when d13 is 0. (7) dt ? 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive switching control data this control data bit selects either 1/4-duty 1/3-bias drive or 1/3-duty 1/3-bias drive. dt drive scheme the com4/s87 pin state 0 1/4-duty 1/3-bias drive com4 1 1/3-duty 1/3-bias drive s87 note : com4 : common output s87 : segment output (8) dn ? s88 pin and s89/osci pin state setting control data this control data bit sets state of the s88 pin and the s89/osci pin. dn number of display segments pin state 1/4 duty 1/3 duty s88 s89/osci 0 up to 344 segments up to 261 segments ?l?(v ss ) ?l?(v ss )/osci 1 up to 352 segments up to 267 segments s88 s89/osci note : "l" (v ss ) : low (v ss ) level output s88 : segment output "l" (v ss )/osci : low (v ss ) level output in internal oscillator operating mode (oc=0) external clock input in external clock operating mode (oc=1) s89/osci : segment output in internal oscillator operating mode (oc=0) external clock input in external clock operating mode (oc=1) (9) exf ? external clock operating frequency setting control data this control data bit sets the operating frequency of the external clock which input into the osci pin, when the external clock operating mode (oc="1") is set. however, be careful of setting the f ck 1=300[khz]typ when the external clock operating mode (oc="1") is set in the case of the simple mode transfer forcibly. in addition, this data is effective only when external clock operating mode (oc= "1") is set. exf external clock operating frequency f ck [khz] 0 f ck 1=300[khz] typ 1 f ck 2=38[khz] typ
lc75809pt www.onsemi.com 27 (10) sc ? segment on/off control data this control data bit controls the on/off state of the segments. sc display state 0 on 1 off note that when the segments are turned off by setting sc to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. (11) bu ? normal mode/power-saving mode control data this control data bit selects either normal mode or power-saving mode. bu mode 0 normal mode 1 power saving mode in this mode, the internal oscillator circuit stops oscillation (the s89/osci pin is configured fo r segment output) if the ic i s in the internal oscillator operating mode (oc=0) and the ic stops receiving external clock signals (the s89/osci pin is configured for external clock input) if the ic is in the external clock operating mode (oc=1). the common and segment output pins go to the v ss level. however, the s1/p1 to s12/p12 output pins can be used as general-purpose output ports under the control of the data bits p0 to p3. (the general-purpose output port p1 to p12 can not be used as pwm output or clock output).
lc75809pt www.onsemi.com 28 (12) w10 to w15, w20 to w25, w30 to w35 , w40 to w45, w50 to w55, w60 to w65 ? pwm data of the pwm output these control data bits set the pulse width of the pwm output p1 to p12. however, when the pwm output function isn?t used, these control data bits become invalid . in addition, when the external clock operating frequency is set the f ck 2=38[khz]typ (exf="1") in external clock operating mode (oc= "1") or when the serial data transfer is the simple m ode transfer, these control data bits become invalid. wn0 wn1 wn2 wn3 wn4 wn5 pulse width of pwm output wn0 wn1 wn2 wn3 wn4 wn5 pulse width of pwm output 0 0 0 0 0 0 (1/64)tp 0 0 0 0 0 1 (33/64)tp 1 0 0 0 0 0 (2/64)tp 1 0 0 0 0 1 (34/64)tp 0 1 0 0 0 0 (3/64)tp 0 1 0 0 0 1 (35/64)tp 1 1 0 0 0 0 (4/64)tp 1 1 0 0 0 1 (36/64)tp 0 0 1 0 0 0 (5/64)tp 0 0 1 0 0 1 (37/64)tp 1 0 1 0 0 0 (6/64)tp 1 0 1 0 0 1 (38/64)tp 0 1 1 0 0 0 (7/64)tp 0 1 1 0 0 1 (39/64)tp 1 1 1 0 0 0 (8/64)tp 1 1 1 0 0 1 (40/64)tp 0 0 0 1 0 0 (9/64)tp 0 0 0 1 0 1 (41/64)tp 1 0 0 1 0 0 (10/64)tp 1 0 0 1 0 1 (42/64)tp 0 1 0 1 0 0 (11/64)tp 0 1 0 1 0 1 (43/64)tp 1 1 0 1 0 0 (12/64)tp 1 1 0 1 0 1 (44/64)tp 0 0 1 1 0 0 (13/64)tp 0 0 1 1 0 1 (45/64)tp 1 0 1 1 0 0 (14/64)tp 1 0 1 1 0 1 (46/64)tp 0 1 1 1 0 0 (15/64)tp 0 1 1 1 0 1 (47/64)tp 1 1 1 1 0 0 (16/64)tp 1 1 1 1 0 1 (48/64)tp 0 0 0 0 1 0 (17/64)tp 0 0 0 0 1 1 (49/64)tp 1 0 0 0 1 0 (18/64)tp 1 0 0 0 1 1 (50/64)tp 0 1 0 0 1 0 (19/64)tp 0 1 0 0 1 1 (51/64)tp 1 1 0 0 1 0 (20/64)tp 1 1 0 0 1 1 (52/64)tp 0 0 1 0 1 0 (21/64)tp 0 0 1 0 1 1 (53/64)tp 1 0 1 0 1 0 (22/64)tp 1 0 1 0 1 1 (54/64)tp 0 1 1 0 1 0 (23/64)tp 0 1 1 0 1 1 (55/64)tp 1 1 1 0 1 0 (24/64)tp 1 1 1 0 1 1 (56/64)tp 0 0 0 1 1 0 (25/64)tp 0 0 0 1 1 1 (57/64)tp 1 0 0 1 1 0 (26/64)tp 1 0 0 1 1 1 (58/64)tp 0 1 0 1 1 0 (27/64)tp 0 1 0 1 1 1 (59/64)tp 1 1 0 1 1 0 (28/64)tp 1 1 0 1 1 1 (60/64)tp 0 0 1 1 1 0 (29/64)tp 0 0 1 1 1 1 (61/64)tp 1 0 1 1 1 0 (30/64)tp 1 0 1 1 1 1 (62/64)tp 0 1 1 1 1 0 (31/64)tp 0 1 1 1 1 1 (63/64)tp 1 1 1 1 1 0 (32/64)tp 1 1 1 1 1 1 (64/64)tp note : w10 to w15 ? pwm data of the pwm output (ch1) w20 to w25 ? pwm data of the pwm output (ch2) w30 to w35 ? pwm data of the pwm output (ch3) w40 to w45 ? pwm data of the pwm output (ch4) w50 to w55 ? pwm data of the pwm output (ch5) w60 to w65 ? pwm data of the pwm output (ch6) 1 fp tp= n=1 to 6
lc75809pt www.onsemi.com 29 display data and output pin correspondence (1/4 duty) output pin com1 com2 com3 com4 output pin com1 com2 com3 com4 s1/p1 d1 d2 d3 d4 s45 d177 d178 d179 d180 s2/p2 d5 d6 d7 d8 s46 d181 d182 d183 d184 s3/p3 d9 d10 d11 d12 s47 d185 d186 d187 d188 s4/p4 d13 d14 d15 d16 s48 d189 d190 d191 d192 s5/p5 d17 d18 d19 d20 s49 d193 d194 d195 d196 s6/p6 d21 d22 d23 d24 s50 d197 d198 d199 d200 s7/p7 d25 d26 d27 d28 s51 d201 d202 d203 d204 s8/p8 d29 d30 d31 d32 s52 d205 d206 d207 d208 s9/p9 d33 d34 d35 d36 s53 d209 d210 d211 d212 s10/p10 d37 d38 d39 d 40 s54 d213 d214 d215 d216 s11/p11 d41 d42 d43 d 44 s55 d217 d218 d219 d220 s12/p12 d45 d46 d47 d 48 s56 d221 d222 d223 d224 s13 d49 d50 d51 d52 s57 d225 d226 d227 d228 s14 d53 d54 d55 d56 s58 d229 d230 d231 d232 s15 d57 d58 d59 d60 s59 d233 d234 d235 d236 s16 d61 d62 d63 d64 s60 d237 d238 d239 d240 s17 d65 d66 d67 d68 s61 d241 d242 d243 d244 s18 d69 d70 d71 d72 s62 d245 d246 d247 d248 s19 d73 d74 d75 d76 s63 d249 d250 d251 d252 s20 d77 d78 d79 d80 s64 d253 d254 d255 d256 s21 d81 d82 d83 d84 s65 d257 d258 d259 d260 s22 d85 d86 d87 d88 s66 d261 d262 d263 d264 s23 d89 d90 d91 d92 s67 d265 d266 d267 d268 s24 d93 d94 d95 d96 s68 d269 d270 d271 d272 s25 d97 d98 d99 d100 s69 d273 d274 d275 d276 s26 d101 d102 d103 d104 s70 d277 d278 d279 d280 s27 d105 d106 d107 d108 s71 d281 d282 d283 d284 s28 d109 d110 d111 d112 s72 d285 d286 d287 d288 s29 d113 d114 d115 d116 s73 d289 d290 d291 d292 s30 d117 d118 d119 d120 s74 d293 d294 d295 d296 s31 d121 d122 d123 d124 s75 d297 d298 d299 d300 s32 d125 d126 d127 d128 s76 d301 d302 d303 d304 s33 d129 d130 d131 d132 s77 d305 d306 d307 d308 s34 d133 d134 d135 d136 s78 d309 d310 d311 d312 s35 d137 d138 d139 d140 s79 d313 d314 d315 d316 s36 d141 d142 d143 d144 s80 d317 d318 d319 d320 s37 d145 d146 d147 d148 s81 d321 d322 d323 d324 s38 d149 d150 d151 d152 s82 d325 d326 d327 d328 s39 d153 d154 d155 d156 s83 d329 d330 d331 d332 s40 d157 d158 d159 d160 s84 d333 d334 d335 d336 s41 d161 d162 d163 d164 s85 d337 d338 d339 d340 s42 d165 d166 d167 d168 s86 d341 d342 d343 d344 s43 d169 d170 d171 d172 s88 d345 d346 d347 d348 s44 d173 d174 d175 d176 s89/ osci d349 d350 d351 d352 note : this table assumes that pins s1/p1 to s12/p12 and s89/osci are configured for segment output.
lc75809pt www.onsemi.com 30 for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d81 d82 d83 d84 0 0 0 0 the lcd segments corresponding to com1, com2, com3, and com4 are off. 0 0 0 1 the lcd segment corresponding to com4 is on. 0 0 1 0 the lcd segment corresponding to com3 is on. 0 0 1 1 the lcd segment corresponding to com3 and com4 are on. 0 1 0 0 the lcd segment corresponding to com2 is on. 0 1 0 1 the lcd segment corresponding to com2 and com4 are on. 0 1 1 0 the lcd segment corresponding to com2 and com3 are on. 0 1 1 1 the lcd segments corresponding to com2, com3, and com4 are on. 1 0 0 0 the lcd segment corresponding to com1 is on. 1 0 0 1 the lcd segment corresponding to com1 and com4 are on. 1 0 1 0 the lcd segment corresponding to com1 and com3 are on. 1 0 1 1 the lcd segments corresponding to com1, com3, and com4 are on. 1 1 0 0 the lcd segment corresponding to com1 and com2 are on. 1 1 0 1 the lcd segments corresponding to com1, com2, and com4 are on. 1 1 1 0 the lcd segments corresponding to com1, com2, and com3 are on. 1 1 1 1 the lcd segments corresponding to com1, com2, com3, and com4 are on.
lc75809pt www.onsemi.com 31 display data and output pin correspondence (1/3 duty) output pin com1 com2 com3 output pin com1 com2 com3 s1/p1 d1 d2 d3 s46 d136 d137 d138 s2/p2 d4 d5 d6 s47 d139 d140 d141 s3/p3 d7 d8 d9 s48 d142 d143 d144 s4/p4 d10 d11 d12 s49 d145 d146 d147 s5/p5 d13 d14 d15 s50 d148 d149 d150 s6/p6 d16 d17 d18 s51 d151 d152 d153 s7/p7 d19 d20 d21 s52 d154 d155 d156 s8/p8 d22 d23 d24 s53 d157 d158 d159 s9/p9 d25 d26 d27 s54 d160 d161 d162 s10/p10 d28 d29 d30 s55 d163 d164 d165 s11/p11 d31 d32 d33 s56 d166 d167 d168 s12/p12 d34 d35 d36 s57 d169 d170 d171 s13 d37 d38 d39 s58 d172 d173 d174 s14 d40 d41 d42 s59 d175 d176 d177 s15 d43 d44 d45 s60 d178 d179 d180 s16 d46 d47 d48 s61 d181 d182 d183 s17 d49 d50 d51 s62 d184 d185 d186 s18 d52 d53 d54 s63 d187 d188 d189 s19 d55 d56 d57 s64 d190 d191 d192 s20 d58 d59 d60 s65 d193 d194 d195 s21 d61 d62 d63 s66 d196 d197 d198 s22 d64 d65 d66 s67 d199 d200 d201 s23 d67 d68 d69 s68 d202 d203 d204 s24 d70 d71 d72 s69 d205 d206 d207 s25 d73 d74 d75 s70 d208 d209 d210 s26 d76 d77 d78 s71 d211 d212 d213 s27 d79 d80 d81 s72 d214 d215 d216 s28 d82 d83 d84 s73 d217 d218 d219 s29 d85 d86 d87 s74 d220 d221 d222 s30 d88 d89 d90 s75 d223 d224 d225 s31 d91 d92 d93 s76 d226 d227 d228 s32 d94 d95 d96 s77 d229 d230 d231 s33 d97 d98 d99 s78 d232 d233 d234 s34 d100 d101 d102 s79 d235 d236 d237 s35 d103 d104 d105 s80 d238 d239 d240 s36 d106 d107 d108 s81 d241 d242 d243 s37 d109 d110 d111 s82 d244 d245 d246 s38 d112 d113 d114 s83 d247 d248 d249 s39 d115 d116 d117 s84 d250 d251 d252 s40 d118 d119 d120 s85 d253 d254 d255 s41 d121 d122 d123 s86 d256 d257 d258 s42 d124 d125 d126 s87/com4 d259 d260 d261 s43 d127 d128 d129 s88 d262 d263 d264 s44 d130 d131 d132 s89/osci d265 d266 d267 s45 d133 d134 d135 note : this table assumes that pins s1/p1 to s12/p12, s87/com4 and s89/osci are configured for segment output.
lc75809pt www.onsemi.com 32 for example, the table below lists the output states for the s21 output pin. display data output pin (s21) state d61 d62 d63 0 0 0 the lcd segments corresponding to com1, com2, and com3 are off. 0 0 1 the lcd segment corresponding to com3 is on. 0 1 0 the lcd segment corresponding to com2 is on. 0 1 1 the lcd segment corresponding to com2 and com3 are on. 1 0 0 the lcd segment corresponding to com1 is on. 1 0 1 the lcd segment corresponding to com1 and com3 are on. 1 1 0 the lcd segment corresponding to com1 and com2 are on. 1 1 1 the lcd segments corresponding to com1, com2, and com3 are on.
lc75809pt www.onsemi.com 33 output waveforms (1/4-duty 1/3-bias drive scheme) v dd 1 v dd 2 fo[hz] v dd 0 com3 com2 com1 com4 lcd driver output when all lcd segments corresponding to com1, com2, com3, and co m4 a r e o n. lcd driver output when lcd segments corresponding to com2 and com4 are on. lcd driver output when only lcd segments corresponding to com4 are on. lcd driver output when lcd segments corresponding to com1, com2, and com3 a r e o n. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when all lcd segments corresponding to com1, com2, com3, and co m4 a r e o ff. 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v v dd 1 v dd 2 v dd 0 0v
lc75809pt www.onsemi.com 34 note : when is setting (fc0,fc1,fc2)= (1,1,1), the frame frequency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). in addition, if the serial data transfer is the simple mode transfer, the frame frequency is set the fosc/3072 or f ck 1/3072 when the control data fc is 0, and is set the fosc/1536 or f ck 1/1536 when fc is 1. control data common/segment output wa veform frame fr equency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz] typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96
lc75809pt www.onsemi.com 35 output waveforms (1/3-duty 1/3-bias drive scheme) com3 com2 com1 lcd driver output when all lcd segments corresponding to com1, com2,and com3 are on. lcd driver output when lcd segments corresponding to com2 and com3 are on. lcd driver output when lcd segments corresponding to com1 and com3 are on. lcd driver output when all lcd segments corresponding to com1, com2, and com3 are off. lcd driver output when only lcd segments corresponding to com1 are on. lcd driver output when only lcd segments corresponding to com2 are on. lcd driver output when only lcd segments corresponding to com3 are on. lcd driver output when lcd segments corresponding to com1 and com2 are on. fo[hz] v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v v dd 2 v dd 1 v dd 0 0v
lc75809pt www.onsemi.com 36 control data common/segment output wa veform frame fr equency fo[hz] fc0 fc1 fc2 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 1, f ck 2=38[khz] typ) 0 0 0 fosc/6144 f ck 1/6144 f ck 2/768 0 0 1 fosc/4608 f ck 1/4608 f ck 2/576 0 1 0 fosc/3072 f ck 1/3072 f ck 2/384 0 1 1 fosc/2304 f ck 1/2304 f ck 2/288 1 0 0 fosc/1536 f ck 1/1536 f ck 2/192 1 0 1 fosc/1152 f ck 1/1152 f ck 2/144 1 1 0 fosc/768 f ck 1/768 f ck 2/96 note : when is setting (fc0,fc1,fc2)= (1,1,1), the frame frequency is same as frame frequency at the time of the (fc0,fc1,fc2)=(0,1,0) setting (fosc/3072, f ck 1/3072, f ck 2/384). in addition, if the serial data transfer is the simple mode transfer, the frame frequency is set the fosc/3072 or f ck 1/3072 when the control data fc is 0, and is set the fosc/1536 or f ck 1/1536 when fc is 1.
lc75809pt www.onsemi.com 37 pwm output waveforms control data pwm output waveforms pwm output ch1 pwm output ch2 pwm output ch3 w10 w11 w12 w13 w14 w15 w20 w21 w22 w23 w24 w25 w30 w31 w32 w33 w34 w35 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 0 0 1 (1) 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 1 0 1 (2) control data pwm output waveforms pwm output ch4 pwm output ch5 pwm output ch6 w40 w41 w42 w43 w44 w45 w50 w51 w52 w53 w54 w55 w60 w61 w62 w63 w64 w65 1 1 1 1 1 0 1 1 1 0 1 0 1 1 1 1 0 0 (1) 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 0 0 1 (2) continued on next page. 1 fp tp= (56/64) ? tp v dd v ss (48/64) ? tp v ss v dd (40/64) ? tp v ss v dd (32/64) ? tp v dd v ss (8/64) ? tp (8/64) ? tp v dd v ss (16/64) ? tp v ss v dd (24/64) ? tp v ss v dd (16/64) ? tp (24/64) ? tp (32/64) ? tp tp tp (56/64) ? tp (48/64) ? tp (40/64) ? tp (16/64) ? tp v ss v dd (16/64) ? tp (24/64) ? tp v ss v dd (24/64) ? tp (48/64) ? tp v ss v dd (48/64) ? tp (32/64) ? tp v dd v ss (32/64) ? tp (40/64) ? tp v ss v dd (40/64) ? tp (1) (2) p1 to p12 (pwm output ch1) p1 to p12 (pwm output ch3) p1 to p12 (pwm output ch3) p1 to p12 (pwm output ch1) p1 to p12 (pwm output ch6) p1 to p12 (pwm output ch5) p1 to p12 (pwm output ch4) p1 to p12 (pwm output ch4) p1 to p12 (pwm output ch2) p1 to p12 (pwm output ch2) p1 to p12 (pwm output ch5) p1 to p12 (pwm output ch6)
lc75809pt www.onsemi.com 38 continued from preceding page. note: when is setting (pf0,pf1,pf2,pf3)=(1,1,0,1) and (x,x,1,1 ), the frame frequency is same as frame frequency at the time of the (pf0,pf1,pf2,pf3)=(1,0,1,0) setting (fosc/896, f ck 1/896). x: don?t care clock output waveforms control data clock frequency of clock output p1 fc(=1/tc)[hz] p1a p1b p1c p1d 1 1 1 0 clock output function (fosc/2, f ck /2) 0 0 0 1 clock output function (fosc/8, f ck /8) control data pwm output waveform frame frequency fp[hz] pf0 pf1 pf2 pf3 internal oscillator operating mode (the control data oc is 0, fosc=300[khz] typ) external clock operating mode (the control data oc is 1 and exf is 0, f ck 1=300[khz] typ) 0 0 0 0 fosc/1536 f ck 1/1536 1 0 0 0 fosc/1408 f ck 1/1408 0 1 0 0 fosc/1280 f ck 1/1280 1 1 0 0 fosc/1152 f ck 1/1152 0 0 1 0 fosc/1024 f ck 1/1024 1 0 1 0 fosc/896 f ck 1/896 0 1 1 0 fosc/768 f ck 1/768 1 1 1 0 fosc/640 f ck 1/640 0 0 0 1 fosc/512 f ck 1/512 1 0 0 1 fosc/384 f ck 1/384 0 1 0 1 fosc/256 f ck 1/256 p1 tc tc/2 1 fc tc=
lc75809pt www.onsemi.com 39 display control and the inh pin since the lsi internal data (1/4 duty : the display data d1 to d352 and the control data, 1/3 duty : the display data d1 to d267 and the control data) is undefined when power is first applied, applications should set the inh pin low at the same time as power is applied to turn off the display (this sets the s1/p1 to s12/p12, s13 to s86, com1 to com3, com4/s87, s88, and s89/osci pins to the v ss level.) and during this period send serial data from the controller. the controller should then set the inh pin high after the data transfer has comp leted. this procedure prevents meaningless display at power on. (see figure 5, figure 6, figure 7 and figure 8.) (1)1/4 duty [figure 5] (2)1/3 duty [figure 6] display data and control data transferred t2 undefined undefined undefined defined defined defined defined undefined undefined undefined undefined v il 1 tc v il 1 internal data (d261 to d352) t1 undefined undefined defined defined undefined undefined v dd ce inh internal data (d1 to d88) internal data (d177 to d260) internal data (d89 to d176) internal data w10 to w15,w20 to w25,w30 to w3 5 w40 to w45,w50 to w55,w60 to w6 5 internal data p1a,p1b,p1c,p1d, p2a,p2b,p2c to p12a,p12b,p12c pf0 to pf3,fc0 to fc2,oc,ct0 to ct2 p0 to p3,dt,dn,ext,sc,bu undefined display data and control data transferred t2 undefined undefined undefined defined defined defined undefined undefined undefined v il 1 tc v il 1 t1 undefined undefined defined defined undefined undefined v dd ce inh internal data (d1 to d87) internal data (d178 to d267) internal data (d88 to d177) internal data w10 to w15,w20 to w25,w30 to w3 5 w40 to w45,w50 to w55,w60 to w6 5 internal data p1a,p1b,p1c,p1d, p2a,p2b,p2c to p12a,p12b,p12c pf0 to pf3,fc0 to fc2,oc,ct0 to ct2 p0 to p3,dt,dn,ext,sc,bu ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? note : t1>1ms t2>0 tc ? 10 ? s min note : t1>1ms t2>0 tc ? 10 ? s min
lc75809pt www.onsemi.com 40 (3)1/4 duty (simple mode transfer) [figure 7] (4)1/3 duty (simple mode transfer) [figure 8] internal data (d261 to d352) internal data (d89 to d176) v dd internal data (d177 to d260) ce inh internal data d1 to d88,oc ct0 to ct2,p0 to p3, dt,dn,fc,sc,bu t2 undefined undefined undefined undefined defined defined defined defined undefined undefined undefined undefined v il 1 tc v il 1 t1 display data and control data transferred ? ? ? ? ? ? ? ? ? ? ? note : t1>1ms t2>0 tc ? 10 ? s min t2 undefined undefined undefined defined defined defined undefined undefined undefined v il 1 tc v il 1 t1 internal data (d88 to d177) v dd internal data (d178 to d267) ce inh internal data d1 to d87,oc ct0 to ct2,p0 to p3, dt,dn,fc,sc,bu display data and control data transferred ? ? ? ? ? ? ? ? ? note : t1>1ms t2>0 tc ? 10 ? s min
lc75809pt www.onsemi.com 41 notes on controller transfer of display data when using the lc75809pt in 1/4 duty, applications transfer the display data (d1 to d352) in four operations, and in 1/3 duty, they transfer the display data (d1 to d267) in three operations. in either case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image. s89/osci pin peripheral circuit (1) internal oscillator operating mode (control data oc=0) connect the s89/osci pin to the lcd panel when the internal oscillator operating mode is selected. (2) external clock operating mode (control data oc=1) when the external clock operating m ode is selected, insert a current pr otection resistor rg (2.2 to 22k ? ) between the s89/osci pin and external clock output pin (external oscillator). determine the value of the resistance according to the allowable current value at the ex ternal clock output pin. also make sure that the waveform of the external clock is not heavily distorted. (3) unused pin treatment when the s89/osci pin is not to be used, select the intern al oscillator operating mode (setting control data oc to 0) to keep the pin open. p1 to p12 pin peripheral circuit it is recommended the circuit shown below be used to adjust the brightness of the led backlight using the pwm output p1 to p12 osci/s89 external clock output pin rg external oscillato r note : allowable current value at external clock output pin > v dd rg osci/s89 to lcd panel osci/s89 open p1 to p12 led +5v
lc75809pt www.onsemi.com 42 sample application circuit 1 1/4 duty, 1/3bias * 3 the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3 v or 5 v. * 4 connect the s89/osci pin to the lcd panel in the internal oscillator operating mode and insert a current protection resistor rg (2.2 to 22 k ? ) between the s89/osci pin and external clock output pin (external oscillator) in the external clock operating mode (see ?s 89/osci pin peripheral circuit?) sample application circuit 2 1/3 duty, 1/3 bias * 3 the pins to be connected to the controller (ce, cl, di, inh ) can handle 3.3 v or 5 v. * 4 connect the s89/osci pin to the lcd panel in the internal oscillator operating mode and insert a current protection resistor rg (2.2 to 22 k ? ) between the s89/osci pin and external clock output pin (external oscillator) in the external clock operating mode (see ?s 89/osci pin peripheral circuit?) general-purpose output ports used for functions such as backlight control (p12) (p2) (p1) lcd panel (up to 352 segments) di cl ce inh v dd 1 osci/s89 s87/com4 s88 s13 p12/s12 p2/s2 p1/s1 com3 com2 com1 *3 v dd v dd 2 v ss c from the controller c ? 0.047 ? f +5v c s86 *4 general-purpose output ports used for functions such as backlight control (p12) (p2) (p1) lcd panel (up to 267 segments) di cl ce inh v dd 1 *3 v dd v dd 2 v ss c from the controller c ? 0.047 ? f +5v c osci/s89 com4/s87 s88 s13 p12/s12 p2/s2 p1/s1 com3 com2 com1 s86 *4
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