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| this is information on a product in full production. april 2015 docid025540 rev 4 1/134 STM32F358XC arm ? -based cortex ? -m4 32b mcu+fpu, up to 256kb flash+ 48kb sram, 4 adcs, 2 dac ch., 7 comp., 4 pga, timers, 1.8 v datasheet - production data features ? core: arm ? cortex ? -m4 32-bit cpu with fpu (72 mhz max), single-cycle multiplication and hw division, 90 dmips (from ccm), dsp instruction and mpu (memory protection unit). ? operating conditions: ? vdd: 1.8v +/- 8% ? vdda voltage range: 1.65 to 3.6 v ? memories ? 256 kbytes of flash memory ? up to 40 kbytes of sram, with hw parity check implemented on the first 16 kbytes. ? routine bootster: 8 kbytes of sram on instruction and data bus, with hw parity check (ccm: core coupled memory) ? crc calculation unit ? reset and supply management ? low-power modes: sleep, and stop ? vbat supply for rtc and backup registers ? clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x 16 pll option ? internal 40 khz oscillator ? up to 86 fast i/os ? all mappable on external interrupt vectors ? several 5 v-tolerant ? interconnect matrix ? 12-channel dma controller ? up to four adc 0.20 s (up to 38 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 v conversion range, separate analog supply from 1.8 to 3.6 v ? up to two 12-bit dac channels with analog supply from 2.4 to 3.6 v ? seven fast rail-to-rail an alog comparators with analog supply from 1.65 to 3.6 v ? up to four operational amplifiers that can be used in pga mode, all terminal accessible with analog supply from 2.4 to 3.6 v ? up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors ? up to 13 timers ? one 32-bit timer and two 16-bit timers with up to 4 ic/oc/pwm or pulse counter and quadrature (incremental) encoder input ? up to two 16-bit 6-channel advanced- control timers, with up to 6 pwm channels, deadtime generation and emergency stop ? one 16-bit timer with 2 ic/ocs, 1 ocn/pwm, deadtime generation and emergency stop ? two 16-bit timers with ic/oc/ocn/pwm, deadtime generation and emergency stop ? 2 watchdog timers (independent, window) ? systick timer: 24-bit downcounter ? up to two 16-bit basic timers to drive the dac ? calendar rtc with alar m, periodic wakeup from stop ? communication interfaces ? can interface (2.0b active) ? two i2c fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, wakeup from stop ? up to five usart/uarts (iso 7816 interface, lin, irda, modem control) ? up to three spis, two with multiplexed i2s interface, 4 to 16 programmable bit frames ? infrared transmitter ? cortex ? -m4 with fpu etm, serial wire debug, jtag ? 96-bit unique id table 1. device summary reference part number STM32F358XC stm32f358cc, stm32f358rc, stm32f358vc lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp48 (7 7 mm) www.st.com
contents STM32F358XC 2/134 docid025540 rev 4 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 arm ? cortex ? -m4 core with fpu with embedded flash and sram . . . 12 3.2 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 embedded sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.5 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.6 cyclic redundancy check (crc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.7 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.2 power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.7.3 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.8 interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.9 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.10 general-purpose input/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.11 direct memory access (dma) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12 interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.12.1 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . 18 3.13 fast analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13.2 internal voltage reference (v refint ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.13.3 vbat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.13.4 opamp reference voltage (vopamp) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.14 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.15 operational amplifier (opamp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.16 fast comparators (comp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.17 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.17.1 advanced timers (tim1, tim8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) . . 22 docid025540 rev 4 3/134 STM32F358XC contents 4 3.17.3 basic timers (tim6, tim7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.17.4 independent watchdog (iwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.5 window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.18 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23 3.19 inter-integrated circuit interface (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.20 universal synchronous/asynchronous re ceiver transmitter (usart) . . . 25 3.21 universal asynchronous receiver transmitter (uart) . . . . . . . . . . . . . . . 25 3.22 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) . 25 3.23 controller area network (can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.24 infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.25 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.26 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26.1 serial wire jtag debug port (swj-dp) . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.26.2 embedded trace macrocell? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 6.1.6 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.1.7 current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 6.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 6.3.2 operating conditions at power-up / powe r-down . . . . . . . . . . . . . . . . . . 57 6.3.3 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 6.3.4 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.3.5 wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 contents STM32F358XC 4/134 docid025540 rev 4 6.3.6 external clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3.7 internal clock source charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.8 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.9 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 6.3.10 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.3.11 electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 6.3.12 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.3.13 i/o port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.14 nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.15 npor pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.16 timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.17 communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.3.18 adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3.19 dac electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.3.20 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.3.21 operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.22 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.23 v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7.1 lqfp100 ? 14 x 14 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 7.2 lqfp64 ? 10 x 10 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.3 lqfp48 ? 7 x 7 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.4 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.4.1 reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 7.4.2 selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 129 8 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 docid025540 rev 4 5/134 STM32F358XC list of tables 6 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. STM32F358XC family device feat ures and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10 table 3. external analog supply values for analog peripheral s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. STM32F358XC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 5. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. STM32F358XC i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 8. usart features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. STM32F358XC spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 10. capacitive sensing gpios available on stm32f35 8xc devices . . . . . . . . . . . . . . . . . . . . 28 table 11. no. of capacitive sensing channels available on STM32F358XC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. STM32F358XC pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 14. alternate functions for port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. alternate functions for port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. alternate functions for port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 17. alternate functions for port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. alternate functions for port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 19. alternate functions for port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 20. STM32F358XC memory map and peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 21. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 22. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 24. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26. embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 table 27. internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 28. typical and maximum current consumption from v dd supply at v dd = 1.8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 29. typical and maximum current consumption from the v dda supply . . . . . . . . . . . . . . . . . . 60 table 30. typical and maximum v dd consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 31. typical and maximum v dda consumption in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 32. typical and maximum current consumption from v bat supply. . . . . . . . . . . . . . . . . . . . . . 61 table 33. typical current consumption in run mode, code with data processing running from flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 34. typical current consumption in sleep mode, code running from flash or ram . . . . . . . . . 64 table 35. switching output i/o current cons umption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 36. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 37. low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38. high-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 39. low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 41. lse oscillator characteristics (f lse = 32.768 khz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 42. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 43. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 44. pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 list of tables STM32F358XC 6/134 docid025540 rev 4 table 45. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 46. flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 47. ems characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 48. emi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 49. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 50. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 51. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 52. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 53. output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 54. i/o ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 55. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 56. npor pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 57. timx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 58. iwdg min/max timeout period at 40 khz (lsi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 59. wwdg min-max timeout value @72 mhz (pclk). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 60. i2c timings specification (see i2c specification, rev.03, june 2007) . . . . . . . . . . . . . . . . . 91 table 61. i2c analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 62. spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 63. i 2 s characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 64. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 65. maximum adc rain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 66. adc accuracy - limited test conditions 100-pin pack ages . . . . . . . . . . . . . . . . . . . . . . . . 102 table 67. adc accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 68. adc accuracy - limited te st conditions 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 69. adc accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 8 table 70. adc accuracy at 1msps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 71. dac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 72. comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 73. operational amplifier characteristic s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 74. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 75. temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 76. v bat monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 77. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 119 table 78. lqfp64 ? 10 x 10 mm, low-profile quad flat pa ckage mechanical data. . . . . . . . . . . . . . 122 table 79. lqfp48 ? 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 125 table 80. package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 table 81. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 table 82. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 docid025540 rev 4 7/134 STM32F358XC list of figures 7 list of figures figure 1. STM32F358XC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 3. infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 4. STM32F358XC lqfp48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 5. STM32F358XC lqfp64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 6. STM32F358XC lqfp100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7. STM32F358XC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 figure 8. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 9. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 10. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 11. current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 12. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) . . . . . . . . . . . 62 figure 13. high-speed external clock source ac timing diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 14. low-speed external clock source ac timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 15. typical application with an 8 mhz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 16. typical application with a 32.768 khz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 17. hsi oscillator accuracy char acterization results for soldered parts . . . . . . . . . . . . . . . . . . 76 figure 18. tc and tta i/o input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 19. five volt tolerant (ft and ftf) i/o input characte ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 20. i/o ac characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 21. recommended nrst pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 22. i 2 c bus ac waveforms and measurement ci rcuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 23. spi timing diagram - slave mode and cpha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 24. spi timing diagram - slave mode and cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 25. spi timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 26. i 2 s slave timing diagram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 27. i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 28. adc typical current consumption on vdda pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 29. adc typical current consumption on vref+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 30. adc accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 31. typical connection diagram using the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 32. 12-bit buffered /non-buffered dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 33. maximum vrefint scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 34. opamp voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 figure 35. lqfp100 ? 14 x 14 mm, low-profile quad flat pa ckage outline . . . . . . . . . . . . . . . . . . . . 119 figure 36. lqfp100 ? 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 120 figure 37. lqfp100 ? 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 121 figure 38. lqfp64 ? 10 x 10 mm, low-profile quad flat pack age outline . . . . . . . . . . . . . . . . . . . . . 122 figure 39. lqfp64 ? 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 123 figure 40. lqfp64 ? 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 124 figure 41. lqfp48 ? 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 125 figure 42. lqfp48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 126 figure 43. lqfp48 - 7 x 7 mm, low-profile quad flat packa ge top view example . . . . . . . . . . . . . . . 127 introduction STM32F358XC 8/134 docid025540 rev 4 1 introduction this datasheet provides the ordering informat ion and mechanical devic e characteristics of the STM32F358XC microcontrollers. this STM32F358XC datasheet should be read in conjunction with the stm32f303xx, STM32F358XC and stm32f328x4/6/8 (rm0316) reference manual. the reference manual is available from the stmicroelectronics website www.st.com . for information on the cortex ? -m4 core with fpu please refer to: ? cortex ? -m4 with fpu technical reference manual , available from arm website www.arm.com. ? stm32f3xxx and stm32f4xxx cortex ? -m4 programming manual (pm0214) available from our website www.st.com . docid025540 rev 4 9/134 STM32F358XC description 51 2 description the STM32F358XC family is bas ed on the high-performance arm ? cortex ? -m4 32-bit risc core with fpu operating at a frequency of up to 72 mhz, and embedding a floating point unit (fpu), a memory protection unit (mpu) and an embedded trace macrocell (etm). the family incorporates high-speed embedded memories (up to 256 kbytes of flash memory, up to 48 kbytes of sram) and an extens ive range of enhanced i/os and peripherals connected to two apb buses. the devices offer up to fo ur fast 12-bit adcs (5 msps), up to seven comparators, up to four operational amplifiers, up to two dac channels, a low-power rtc, up to five general- purpose 16-bit timers, one general-purpose 32-bi t timer, and two timers dedicated to motor control. they also feature standard and advanced communication interfaces: up to two i 2 cs, up to three spis (two spis are with multiplexed full-duplex i2 ss on STM32F358XC devices), three usarts, up to two uarts, and can. to achieve audio class accuracy, the i2s peripherals can be clocked via an external pll. the STM32F358XC family operates in the -40 to +85 c and -40 to +105 c temperature ranges. a comprehensive set of power-saving mode allows the design of low-power applications. the STM32F358XC family offers devices in three packages ranging from 48 pins to 100 pins. the set of included peripherals changes with the device chosen. description STM32F358XC 10/134 docid025540 rev 4 table 2. STM32F358XC family device features and peripheral counts peripheral stm32f 358cx stm32f 358rx stm32f 358vx flash (kbytes) 256 256 256 sram (kbytes) on data bus 40 40 40 ccm (core coupled memory) ram (kbytes) 8 timers advanced control 2 (16-bit) general purpose 5 (16-bit) 1 (32-bit) basic 2 (16-bit) pwm channels (all) (1) 1. this total number considers also the pw ms generated on the complementary output channels. 31 33 pwm channels (except complementary) 22 24 comm. interfaces spi(i2s) (2) 2. the spi interfaces can work in an exclusive way in either the spi mode or the i 2 s audio mode. 3(2) i 2 c 2 usart 3 uart 2 can 1 gpios normal i/os (tc, tta) 19 26 44 5 volts to l e r a n t i/os (ft, ftf) 17 25 42 dma channels 12 12-bit adcs number of channels 4 14 21 38 12-bit dac channels 2 analog comparator 7 operational amplifiers 4 cpu frequency 72 mhz operating voltage v dd = 1.8 v +/- 8%, v dda = 1.65 v to 3.6 v operating temperature ambient operating temperature: - 40 to 85 c / - 40 to 105 c junction temperature: - 40 to 125 c packages lqfp48 lqfp64 lqfp100 docid025540 rev 4 11/134 STM32F358XC description 51 figure 1. STM32F358XC block diagram 1. af: alternate function on i/o pins. 0 6 y 9 7 r x f k 6 h q v l q j & r q w u r o o h u $ + % 7 , 0 ( 5 & k d q q h o v & r p s & k d q q h o % 5 . d v $ ) 7 , 0 ( 5 7 , 0 ( 5 3 : 0 7 , 0 ( 5 3 : 0 & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) 6 3 , 0 2 6 , 0 , 6 2 6 & . 1 6 6 d v $ ) 8 6 $ 5 7 5 ; 7 ; & 7 6 5 7 6 6 p d u w & d u g d v $ ) : l q : $ 7 & + ' 2 * % x v 0 d w u l [ 0 3 8 ) 3 8 & r u w h [ 0 & 3 8 ) p d [ 0 + ] 1 9 , & * 3 ' 0 $ f k d q q h o v & & 0 5 $ 0 . % ) o d v k l q w h u i d f h 2 % / ) / $ 6 + . % e l w v - 7 5 6 7 - 7 ' , - 7 & . 6 : & / . - 7 0 6 6 : ' $ 7 - 7 ' 2 $ v $ ) 3 r z h u 9 ' ' 9 ' ' , 2 9 6 6 , q g : ' * . 3 / / # 9 ' ' , 2 # 9 ' ' $ ; 7 $ / 2 6 & 0 + ] 5 h v h w f o r f n f r q w u r o $ + % 3 & / . $ 3 % 3 & / . $ 3 % 3 & / . $ + % $ 3 % $ + % $ 3 % & 5 & $ 3 % ) p d [ 0 + ] $ 3 % i p d [ 0 + ] * 3 , 2 3 2 5 7 $ * 3 , 2 3 2 5 7 % * 3 , 2 3 2 5 7 & * 3 , 2 3 2 5 7 ' * 3 , 2 3 2 5 7 ( 2 6 & b , 1 2 6 & b 2 8 7 6 3 , , 6 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 6 & / 6 ' $ 6 0 % $ d v $ ) 8 6 $ 5 7 5 & / 6 7 , 0 ( 5 7 , 0 ( 5 6 3 , , 6 e l w ' $ & , ) # 9 ' ' $ 7 , 0 ( 5 e l w 3 : 0 3 $ > @ 3 % > @ 3 & > @ 0 2 6 , 6 ' 0 , 6 2 h [ w b 6 ' 6 & . & . 1 6 6 : 6 0 & / . d v $ ) & k d q q h o v ( 7 5 d v $ ) ' $ & b & + d v $ ) + & / . ) & / . 8 6 $ 5 7 & / . 5 & + 6 0 + ] 6 5 $ 0 . % ( 7 0 7 u d f h 7 u l j 6 : - 7 $ * 7 3 , 8 , e x v 7 5 $ ' ( & / . 7 5 $ & ( ' > @ d v $ ) ' e x v 6 \ v w h p * 3 ' 0 $ f k d q q h o v e l w $ ' & e l w $ ' & , ) 7 h p s v h q v r u 9 5 ( ) 9 5 ( ) 7 , 0 ( 5 ( ; 7 , 7 : . 8 3 ; ; $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o & r p s & k d q q h o % 5 . d v $ ) & k d q q h o v & r p s f k d q q h o v ( 7 5 % 5 . d v $ ) * 3 , 2 3 2 5 7 ) 3 ' > @ 3 ( > @ 7 , 0 ( 5 3 ) > @ e l w $ ' & , ) e l w $ ' & , & & / . $ ' & 6 $ 5 & / . # 9 ' ' , 2 # 9 6 : ; 7 $ / n + ] 2 6 & b , 1 2 6 & b 2 8 7 9 ' ' 5 7 & $ : 8 % d f n x s 5 h j % \ w h % d f n x s l q w h u i d f h $ 1 7 , 7 $ 0 3 7 , 0 ( 5 8 $ 5 7 8 $ 5 7 , & , & e [ & $ 1 % 6 5 $ 0 ' $ & b & + d v $ ) 2 s $ p s 2 s $ p s 2 s $ p s 2 s $ p s # 9 ' ' $ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 [ [ 2 8 7 [ [ , 1 7 ( 5 ) $ & ( 6 < 6 & ) * & 7 / * 3 & r p s d u d w r u s * 3 & r p s d u d w r u * 3 & r p s d u d w r u & $ 1 7 ; & $ 1 5 ; & k d q q h o v ( 7 5 d v $ ) & k d q q h o v ( 7 5 d v $ ) 0 2 6 , 6 ' 0 , 6 2 h [ w b 6 ' 6 & . & . 1 6 6 : 6 0 & / . d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; & 7 6 5 7 6 d v $ ) 5 ; 7 ; d v $ ) 5 ; 7 ; d v $ ) # 9 ' ' $ ; [ , q v 2 8 7 v d v $ ) ; ; * u r x s v r i f k d q q h o v d v $ ) 6 x s s o \ 6 x s h u y l v l r q 5 h v h w 1 5 ( 6 ( 7 9 ' ' $ 9 6 6 $ 1 3 2 5 # 9 ' ' $ $ + % functional overview STM32F358XC 12/134 docid025540 rev 4 3 functional overview 3.1 arm ? cortex ? -m4 core with fpu with embedded flash and sram the arm ? cortex ? -m4 processor with fpu is the latest generation of arm processors for embedded systems. it was developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. the arm ? cortex ? -m4 32-bit risc processor with fpu features exceptional code- efficiency, delivering the high-performance expect ed from an arm core in the memory size usually associated with 8- and 16-bit devices. the processor supports a set of dsp instructions which allow efficient signal processing and complex algorithm execution. its single precision fpu speeds up software development by using metalanguage development tools, while avoiding saturation. with its embedded arm core, the STM32F358XC family is compatible with all arm tools and software. figure 1 shows the general block diagram of the STM32F358XC family devices. 3.2 memory protection unit (mpu) the memory protection unit (mpu) is used to se parate the processing of tasks from the data protection. the mpu can manage up to 8 protection areas that can all be further divided up into 8 subareas. the protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. the memory protection unit is especially help ful for applications w here some critical or certified code has to be protected against th e misbehavior of other tasks. it is usually managed by an rtos (real-time operating system). if a program accesses a memory location that is prohibited by the mpu, the rt os can detect it and take action. in an rtos environment, the kernel can dynamically update the mpu area setting, based on the process to be executed. the mpu is optional and can be bypassed for applications that do not need it. 3.3 embedded flash memory all STM32F358XC devices feature up to 256 kbytes of embedded flash memory available for storing programs and data. the flash memory access time is adjusted to the cpu clock frequency (0 wait state from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states above). 3.4 embedded sram STM32F358XC devices feature up to 48 kbytes of embedded sram with hardware parity docid025540 rev 4 13/134 STM32F358XC functional overview 51 check. the memory can be acce ssed in read/write at cpu clock speed with 0 wait states, allowing the cpu to achieve 90 dhrystone mips at 72 mhz (when running code from the ccm (core coupled memory) ram). ? 8 kbytes of ccm ram on stm32f303xx devices mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of ccm ram). ? 40 kbytes of sram mapped on the data bus (p arity check on first 16 kbytes of sram). 3.5 boot modes at startup, boot0 pin and boot1 option bit are used to select one of three boot options: ? boot from user flash ? boot from system memory ? boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1 (pa9/pa10) or usar t2 (pd5/pd6) or i2c1 (pb6/pb7). 3.6 cyclic redund ancy check (crc) the crc (cyclic redundancy check) calculati on unit is used to get a crc code using a configurable generator polynomial value and size. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc calculation unit helps compute a signature of the software during runtime, to be compar ed with a reference signature generated at linktime and stored at a given memory location. functional overview STM32F358XC 14/134 docid025540 rev 4 3.7 power management 3.7.1 power supply schemes ? v ss , v dd = 1.8 v+/- 8% : external power supply for i/os and core. it is provided externally through v dd pins. ? v ssa , v dda = 1.65 to 3.6 v: external analog powe r supply for adc, dacs, comparators operational amplifiers, reset blocks, rcs an d pll. the minimum voltage to be applied to v dda differs from one analog peripheral to another. table 3 provides the summary of the v dda ranges for analog peripherals. the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. ? v bat = 1.65 to 3.6 v: power supply for rtc, ex ternal clock 32 khz oscillator and backup registers (through power swit ch which is guaranteed in the full range of vdd) when vdd is not present. 3.7.2 power supply supervision the device power on reset is controlled through the external npor pin. the device remains in reset state when npor pin is held low. to guarantee a proper power-on reset, the npor pin must be held low when vdda is applied. then, when vdd is stable, the reset state can be exited by: ? either putting the npor pin in high impedance. npor pin has an internal pull up. ? or forcing the pin to high level by connecting it to v dda . 3.7.3 low-power modes the STM32F358XC devices support two low-power modes to achieve the best compromise between low-power consumption, short st artup time and available wakeup sources: ? sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. ? stop mode stop mode achieves the lowest power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal osc illators are disabled. the device can be woken up from stop mode by any of the exti line. the exti line source can be one of the 16 external lines , the rtc alarm, compx, i2cx or u(s)artx. note: the rtc, the iwdg and the corresponding clock sources are not stopped by entering stop mode. table 3. external analog supply values for analog peripherals analog peripheral minimum v dda supply maximum v dda supply adc 1.8 v 3.6 v comp 1.65 v 3.6 v dac / opamp 2.4 v 3.6v docid025540 rev 4 15/134 STM32F358XC functional overview 51 3.8 interconnect matrix several peripherals have direct connecti ons between them. this allows autonomous communication between peripherals, savi ng cpu resources thus power supply consumption. in addition, these hardware co nnections allow fast and predictable latency. note: for more details about the interconnect action s, please refer to the corresponding sections in the reference manual rm0316. table 4. STM32F358XC peripheral interconnect matrix interconnect source interconnect destination interconnect action timx timx timers synchronization or chaining adcx dac1 conversion triggers dma memory to memory transfer trigger compx comparator output blanking compx timx timer input: ocref_clr input, input capture adcx timx timer triggered by analog watchdog gpio rtcclk hse/32 mc0 tim16 clock source used as input channel for hsi and lsi calibration css cpu (hard fault) compx pvd gpio tim1, tim8, tim15, 16, 17 timer break gpio timx external trigger, timer break adcx dac1 conversion external trigger dac1 compx comparator inverting input functional overview STM32F358XC 16/134 docid025540 rev 4 3.9 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an external 4-32 mhz clock can be selected, in which case it is monitored for fa ilure. if failure is detected, th e system automatically switches back to the internal rc oscillator. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example with failure of an indirectly used external oscillator). several prescalers allow to configure the ahb frequency, the high speed apb (apb2) and the low speed apb (apb1) domain s. the maximum fr equency of the ah b and the high speed apb domains is 72 mhz, while the maximum allowe d frequency of the low speed apb domain is 36 mhz. docid025540 rev 4 17/134 STM32F358XC functional overview 51 figure 2. clock tree 0 6 9 ?} &o?z ??}p?uu]vp ]v? ?( w r 8 6 $ 5 7 [ [ ?} }?? ? ^??? u ?]u ? l?? er?? d , , ^ k ^ k ^ z / e k ^ z k h d k ^ ??z / e k ^ ??z k h d ? d , , ^ / z / t ' > < ?} / t ' w > > ??u??uxx ? w > > d h > , w ?? ?o ? lu?ueu?u , > < w > > > < ?} , ?u }? u u u}?? v d > ^ > ^ / , ^ / , ^ / , ^ ?} z d w > > ^ z ^ t l? ^ z ^ > < z d > < z d ^ >?w? w r 7 , 0 /( ~ w ?? ?o ? a ? o? ?? & > / d & > < ?} /? ? ~? a u? > ^ , ^ / ^ z ^ > < l? w > < ^ z ^ > < , ^ / w > < ?} /? ^? ~? a ?u? h ^ > < ?} h ^ ]v? ?( & , > < }?? ? (? ?vv]vp o}l ?} w ? ?]?z ?o? , ?? ?o ? lu?uxx?? ^ ^ l?ul?uxxx l > ^ k ^ ??x?l , > ^ / z el , h ^ ?? ?o ? lux? w ? ?? ?o ? lu?ueu?u w r 7 , 0 /( ~ w ? ?? ?o ? a ? o? ?? w r 8 6 $ 5 7 > ^ , ^ / ^ z ^ > < w > <? w > <? w r $ 3 % s h u l s k h u d o v d / dl? w? ?o ? lu?ue ?} ?? ~?? a ?u ?e w? ?o ? lu?ueuu?uu?uu ??ueu??u?? /? ^ ^ z ^ z ^ > < ??x o}l /? ^z < / e ?? d k d]v o}l }??? l? w > > > < , ^ / , ^ d k ^ z ^ > < > ^ / > ^ functional overview STM32F358XC 18/134 docid025540 rev 4 3.10 general-purpose in put/outputs (gpios) each of the gpio pins can be configured by so ftware as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. all gpios are high current capable except for analog inputs. the i/os alternate function configuration c an be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. fast i/o handling allows i/o toggling up to 36 mhz. 3.11 direct memo ry access (dma) the flexible general-purpose dma is able to manage memory-to-memory, peripheral-to- memory and memory-to-peripheral transfers. the dma controller supports circular buffer management, avoiding the generation of interrup ts when the controller reaches the end of the buffer. each of the 12 dma channels is connected to dedicated hardware dma requests, with software trigger support for each channel. configuration is done by software and transfer sizes between source and destination are independent. the dma can be used with the main peripherals: spi, i 2 c, usart, general-purpose timers, dac and adc. 3.12 interrupts and events 3.12.1 nested vectored inte rrupt controller (nvic) the STM32F358XC devices embed a nested vect ored interrupt controller (nvic) able to handle up to 66 maskable interrupt channels and 16 priority levels. the nvic benefits are the following: ? closely coupled nvic gives lo w latency interrupt processing ? interrupt entry vector table address passed directly to the core ? closely coupled nvic core interface ? allows early processing of interrupts ? processing of late arriving higher priority interrupts ? support for tail chaining ? processor state automatically saved ? interrupt entry restored on interrupt exit with no instruction overhead the nvic hardware block provides flexible interrupt management features with minimal interrupt latency. docid025540 rev 4 19/134 STM32F358XC functional overview 51 3.13 fast analog-to-digital converter (adc) up to four fast analog-to-dig ital converters 5 msps, with se lectable resolution between 12 and 6 bit, are embedded in the STM32F358XC family devices. the adcs have up to 38 external channels. some of the external channels are shared between adc1&2 and between adc3&4, performing conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adcs have also internal channels: temp erature sensor connected to adc1 channel 16, vbat/2 connected to adc1 channel 17, voltage reference v refint connected to the 4 adcs channel 18, vopamp1 connected to adc1 channel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. additional logic functions embedded in the adc interface allow: ? simultaneous sample and hold ? interleaved sample and hold ? single-shunt phase current reading techniques. the adc can be served by the dma controller. an analog watchdog feature allows very precis e monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. the events generated by the general-purpose timers and the advanc ed-control timers can be internally connected to the adc start trigger and injection trigger, respectively, to allow the application to synchroniz e a/d conversion and timers. 3.13.1 temperature sensor the temperature sensor (ts) generates a voltage v sense that varies linearly with temperature. the temperature sensor is internally connec ted to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. the sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. as the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. to improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by st. the te mperature sensor factory calibration data are stored by st in the system memory area, accessible in read-only mode. 3.13.2 internal voltage reference (v refint ) the internal voltage reference (v refint ) provides a stable (bandgap) voltage output for the adc and comparators. v refint is internally connected to th e adc_in18 input channel. the precise voltage of v refint is individually measured for each part by st during production test and stored in the syste m memory area. it is accessible in read-only mode. functional overview STM32F358XC 20/134 docid025540 rev 4 3.13.3 vbat battery voltage monitoring this embedded hardware feature allows the application to measure the vbat battery voltage using the internal adc channel adc_in17. as the vbat voltage may be higher than vdda, and thus outside the adc input range , the vbat pin is internally connected to a bridge divider by 2. as a cons equence, the converted digital value is half the vbat voltage. 3.13.4 opamp reference voltage (vopamp) every opamp reference voltage can be measured using a corresponding adc internal channel: vopamp1 connected to adc1 ch annel 15, vopamp2 connected to adc2 channel 17, vopamp3 connected to adc3 channel 17, vopamp4 connected to adc4 channel 17. 3.14 digital-to-analog converter (dac) up to two 12-bit buffered dac channels can be used to convert digital signals into analog voltage signal outputs. the chosen design st ructure is composed of integrated resistor strings and an amplifier in inverting configuration. this digital interface supp orts the following features: ? up to two dac output channels on STM32F358XC devices ? 8-bit or 10-bit monotonic output ? left or right data alignment in 12-bit mode ? synchronized update capab ility on STM32F358XC devices ? noise-wave generation ? triangular-wave generation ? dual dac channel independent or simu ltaneous conversions on STM32F358XC devices ? dma capability (for each chann el on STM32F358XC devices) ? external triggers for conversion 3.15 operational amplifier (opamp) the STM32F358XC devices embed up to four operational amplifiers with external or internal follower routing and pga capab ility (or even amplifier and f ilter capability with external components). when an operational amplifier is selected, an external adc channel is used to enable output measurement. the operational amplifier features: ? 8.2 mhz bandwidth ? 0.5 ma output capability ? rail-to-rail input/output ? in pga mode, the gain can be programmed to be 2, 4, 8 or 16. docid025540 rev 4 21/134 STM32F358XC functional overview 51 3.16 fast comparators (comp) the STM32F358XC devices embed seven fast rail-to-rail comparators with programmable reference voltage (internal or external), hyster esis and speed (low speed for low-power) and with selectable output polarity. the reference voltage can be one of the following: ? external i/o ? dac output pin ? internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 26: embedded internal reference voltage on page 57 for the value and precision of the internal reference voltage. all comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator 3.17 timers and watchdogs the STM32F358XC devices include up to two advanced control timers, up to 6 general- purpose timers, two basic timers, two watchdog timers and a systick timer. the table below compares the features of the advanced co ntrol, general purpose and basic timers. note: tim1/8 can have pll as clock source, and therefore can be clocked at 144 mhz. table 5. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/ compare channels complementary outputs advanced tim1, tim8 16-bit up, down, up/down any integer between 1 and 65536 yes 4 yes general- purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim3, tim4 16-bit up, down, up/down any integer between 1 and 65536 yes 4 no general- purpose tim15 16-bit up any integer between 1 and 65536 yes 2 1 general- purpose tim16, tim17 16-bit up any integer between 1 and 65536 yes 1 1 basic tim6, tim7 16-bit up any integer between 1 and 65536 yes 0 no functional overview STM32F358XC 22/134 docid025540 rev 4 3.17.1 advanced time rs (tim1, tim8) the advanced-control timers (tim1 on all de vices and tim8 on STM32F358XC devices) can each be seen as a three-phase pwm multiple xed on 6 channels. they have complementary pwm outputs with programmable inserted dead-times. they can also be seen as complete general-purpose timers. the 4 independent channels can be used for: ? input capture ? output compare ? pwm generation (edge or cent er-aligned modes) with full modulation capability (0- 100%) ? one-pulse mode output in debug mode, the advanced-control timer counter can be frozen and the pwm outputs disabled to turn off any power switches driven by these outputs. many features are shared with those of the general-purpose tim timers (described in section 3.17.2 using the same architecture, so t he advanced-control timers can work together with the tim timers via the timer link feature for synchronization or event chaining. 3.17.2 general-purpose timers (tim2, tim3, tim4, tim15, tim16, tim17) there are up to six synchronizable general-purpose timers embedded in the STM32F358XC devices (see table 5 for differences). each general-purpose timer can be used to generate pwm outputs, or act as a simple time base. ? tim2, 3, and tim4 these are full-featured general-purpose timers: ? tim2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler ? tim3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. these timers all feature 4 independent chan nels for input capture/output compare, pwm or one-pulse mode output. they can work together, or with the other general- purpose timers via the timer link featur e for synchronization or event chaining. the counters can be frozen in debug mode. all have independent dma request generat ion and support quadrature encoders. ? tim15, 16 and 17 these three timers general-purpose timers with mid-range features: they have 16-bit auto-reload upcounters and 16-bit prescalers. ? tim15 has 2 channels and 1 complementary channel ? tim16 and tim17 have 1 channel and 1 complementary channel all channels can be used for input capture/output compare, pwm or one-pulse mode output. the timers can work together via the timer link feature for synchronization or event chaining. the timers have independent dma request generation. the counters can be frozen in debug mode. 3.17.3 basic timers (tim6, tim7) these timers are mainly used for dac trigge r generation. they can also be used as a generic 16-bit time base. docid025540 rev 4 23/134 STM32F358XC functional overview 51 3.17.4 independent watchdog (iwdg) the independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop mode. it can be used either as a watchdog to reset the device when a problem occurs, or as a fr ee running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.17.5 window watchdog (wwdg) the window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the main clock. it has an early warning interrupt capab ility and the counter can be frozen in debug mode. 3.17.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: ? a 24-bit down counter ? autoreload capability ? maskable system interrupt generation when the counter reaches 0. ? programmable clock source 3.18 real-time clock (rtc ) and backup registers the rtc and the 16 backup registers are supplied through v dd a switch that takes power from either the vdd supply when present or the vbat pin. the backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when v dd power is not present. they are not reset by a system or power reset. the rtc is an independent bcd timer/count er. it supports the following features: ? calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. ? reference clock detection: a more precise se cond source clock (50 or 60 hz) can be used to enhance the calendar precision. ? automatic correction for 28, 29 (leap year), 30 and 31 days of the month. ? two programmable alarms with wake up from stop mode capability. ? on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. ? digital calibration circuit with 1 ppm resolu tion, to compensate for quartz crystal inaccuracy. ? three anti-tamper detection pins with programmable filter. the mcu can be woken up from stop mode on tamper event detection. ? timestamp feature which can be used to save the calendar content. this function can be triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop mode on timestamp event detection. functional overview STM32F358XC 24/134 docid025540 rev 4 ? 17-bit auto-reload counter fo r periodic interrupt with wa keup from stop capability. the rtc clock sources can be: ? a 32.768 khz external crystal ? a resonator or oscillator ? the internal low-power rc oscillator (typical frequency of 40 khz) ? the high-speed external clock divided by 32. 3.19 inter-integrated circuit interface (i 2 c) up to two i 2 c bus interfaces can operate in multim aster and slave modes. they can support standard (up to 100 khz), fast (up to 400 khz) and fast mode + (up to 1 mhz) modes. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. in addition, they provide hard ware support for sm bus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) gener ation/verification, timeouts verifications and alert protocol management. they also have a clock domain independent from the cpu clock, allowing the i2cx (x=1,2) to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to table 7 for the features available in i2c1 and i2c2. table 6. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process wakeup from stop on address match is not available when digital filter is enabled. table 7. STM32F358XC i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode xx 10-bit addressing mode xx standard mode (up to 100 kbit/s) xx fast mode (up to 400 kbit/s) xx fast mode plus with 20ma output drive i/os (up to 1 mbit/s) xx independent clock xx smbus xx wakeup from stop xx docid025540 rev 4 25/134 STM32F358XC functional overview 51 3.20 universal synchronous/asynch ronous receiver transmitter (usart) the STM32F358XC devices have three embedded universal synchronous/asynchronous receiver transmitters (usart1, usart2 and usart3). the usart interfaces are able to communicate at speeds of up to 9 mbits/s. they provide hardware management of the ct s and rts signals, they support irda sir endec, the multiprocessor communication mode, the single-wire half-duplex communication mode and have li n master/slave capability. the usart interfaces can be served by the dma controller. 3.21 universal asynchronous receiver transmitter (uart) the STM32F358XC devices have 2 embedde d universal asynchronous receiver transmitters (uart4, and uart5). the uart interfaces suppor t irda sir endec, multiprocessor communication mode and single-wire half-duplex communication mode. the uart4 interface can be served by the dma controller. refer to table 8 for the features available in all u(s)arts interfaces. 3.22 serial peripheral interface (spi)/inter-integrated sound interfaces (i2s) up to three spis are able to communicate up to 18 mbits/s in slave and master modes in full-duplex and half-duplex communication mo des. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. table 8. usart features usart modes/features (1) usart1 usart2 usart3 uart4 uart5 hardware flow control for modem x x x - - continuous communication using dma x x x x - multiprocessor communication x x x x x synchronous mode x x x - - smartcard mode x x x - - single-wire half-dupl ex communication x x x x x irda sir endec block x x x x x lin mode x x x x x dual clock domain and wakeup from stop mode x x x x x receiver timeout interrupt x x x x x modbus communication x x x x x auto baud rate detection x x x - - driver enable x x x - - 1. x = supported. functional overview STM32F358XC 26/134 docid025540 rev 4 two standard i2s interfaces (multiplexed with spi2 and spi3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. they can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clo ck for an external audio component at 256 times the sampling frequency. refer to table 9 for the features available in spi1, spi2 and spi3. 3.23 controller area network (can) the can is compliant with specif ications 2.0a and b (active) wit h a bit rate up to 1 mbit/s. it can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. it has three transmit mailboxes, two receive fifos with 3 stages and 14 scalable filter banks. 3.24 infrared transmitter the STM32F358XC devices provide an infrared transmitter solution. the solution is based on internal connections between tim16 and tim 17 as shown in the figure below. tim17 is used to provide the carrier frequency and tim1 6 provides the main signal to be sent. the infrared output signal is available on pb9 or pa13. to generate the infrared remote control sign als, tim16 channel 1 and tim17 channel 1 must be properly configured to generate correct waveforms. all standard ir pulse modulation modes can be obtained by programming t he two timers output compare channels. table 9. STM32F358XC spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 spi3 hardware crc calculation x x x rx/tx fifo x x x nss pulse mode x x x i2s mode - x x ti mode xxx docid025540 rev 4 27/134 STM32F358XC functional overview 51 figure 3. infrared transmitter 3.25 touch sensing controller (tsc) the STM32F358XC devices provide a simple solution for adding capacitive sensing functionality to any application. these device s offer up to 24 capacitive sensing channels distributed over 8 analog i/o groups. capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). the capacitive variation introduced by the finger (or any conduct ive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. it consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor unt il the voltage across this capa citor has reached a specific threshold. to limit the cpu bandwidth usage th is acquisition is dire ctly managed by the hardware touch sensing controller and only r equires few external components to operate. the touch sensing controller is fully supported by the stmtouch touch sensing firmware library which is free to use and allows touch se nsing functionality to be implemented reliably in the end application. 7 , 0 ( 5 i r u h q y h o r s 7 , 0 ( 5 i r u f d u u l h u 2 & 2 & 3 % 3 $ 0 6 9 functional overview STM32F358XC 28/134 docid025540 rev 4 table 10. capacitive sensing gpios available on STM32F358XC devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 5 tsc_g5_io1 pb3 tsc_g1_io2 pa1 tsc_g5_io2 pb4 tsc_g1_io3 pa2 tsc_g5_io3 pb6 tsc_g1_io4 pa3 tsc_g5_io4 pb7 2 tsc_g2_io1 pa4 6 tsc_g6_io1 pb11 tsc_g2_io2 pa5 tsc_g6_io2 pb12 tsc_g2_io3 pa6 tsc_g6_io3 pb13 tsc_g2_io4 pa7 tsc_g6_io4 pb14 3 tsc_g3_io1 pc5 7 tsc_g7_io1 pe2 tsc_g3_io2 pb0 tsc_g7_io2 pe3 tsc_g3_io3 pb1 tsc_g7_io3 pe4 4 tsc_g4_io1 pa9 tsc_g7_io4 pe5 tsc_g4_io2 pa10 8 tsc_g8_io1 pd12 tsc_g4_io3 pa13 tsc_g8_io2 pd13 tsc_g4_io4 pa14 tsc_g8_io3 pd14 tsc_g8_io4 pd15 table 11. no. of capacitive se nsing channels available on STM32F358XC devices analog i/o group number of capacitive sensing channels stm32f358xvx stm32f358xrx STM32F358XCx g1 3 3 3 g2 3 3 3 g3 2 2 1 g4 3 3 3 g5 3 3 3 g6 3 3 3 g7 3 0 0 g8 3 0 0 number of capacitive sensing channels 23 17 16 docid025540 rev 4 29/134 STM32F358XC functional overview 51 3.26 development support 3.26.1 serial wire jt ag debug port (swj-dp) the arm swj-dp interface is embedded, and is a combined jtag and serial wire debug port that enables either a serial wire debug or a jtag probe to be connected to the target. the jtag tms and tck pins are shared re spectively with swdio and swclk and a specific sequence on the tms pin is us ed to switch between jtag-dp and sw-dp. 3.26.2 embedded trace macrocell? the arm embedded trace ma crocell provides a greater visib ility of the instruction and data flow inside the cpu core by streaming compressed data at a very high rate from the STM32F358XC through a small number of etm pi ns to an external hardware trace port analyzer (tpa) device. the tpa is connected to a host computer using a high-speed channel. real-time instruction and data flow ac tivity can be recorded and then formatted for display on the host computer running debugger software. tpa hardware is commercially available from common development tool vendors. it operates with third party debugger software tools. pinouts and pin description STM32F358XC 30/134 docid025540 rev 4 4 pinouts and pin description figure 4. STM32F358XC lqfp48 pinout 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' b 9 6 6 b 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 $ 3 $ 9 ' ' b 9 6 6 b 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 $ 3 $ 3 $ 3 $ 3 $ 3 % 3 % 1 3 2 5 3 % 9 6 6 b 3 % 9 ' ' b 3 ) 2 6 & b , 1 3 ) 2 6 & b 2 8 7 3 & . 4 7 , 1 & 0 docid025540 rev 4 31/134 STM32F358XC pinouts and pin description 51 figure 5. STM32F358XC lqfp64 pinout 9 % $ 7 3 & 2 6 & b , 1 3 & 2 6 & b 2 8 7 1 5 6 7 3 & 3 & 3 & 3 & 9 6 6 $ 9 5 ( ) 9 ' ' $ 9 5 ( ) 3 $ 3 $ 3 $ 9 ' ' b 3 % 3 % % 2 2 7 3 % 3 % 3 % 3 % 3 % 3 ' 3 & 3 & 3 & 3 $ 3 $ 9 ' ' b 9 6 6 b 3 $ 3 $ 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 & 3 & 3 % 3 % 3 % 3 % 3 ) 3 $ 9 ' ' b 3 $ 3 $ 3 $ 3 $ 3 & 3 & 3 % 3 % 1 3 2 5 3 % 3 ) 2 6 & b 2 8 7 3 ) 2 6 & b , 1 3 & 9 6 6 b 3 % 9 6 6 b 9 ' ' b , 1 & 0 - 3 6 pinouts and pin description STM32F358XC 32/134 docid025540 rev 4 figure 6. STM32F358XC lqfp100 pinout 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 0 & 0 & 0 & / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 0 & 6 3 3 ! 6 2 % & 6 2 % & 6 $ $ ! 0 ! 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 & 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 0 & 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " . 0 / 2 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 6 3 3 ? 6 $ $ ? 6 $ $ ? 6 3 3 ? 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! - 3 6 , 1 & 0 0 # 0 & / 3 # ? / 5 4 0 " docid025540 rev 4 33/134 STM32F358XC pinouts and pin description 51 table 12. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor por external power on reset pin with embedded weak pull-up resistor, powered from vdda notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabl ed through peripheral registers pinouts and pin description STM32F358XC 34/134 docid025540 rev 4 table 13. STM32F358XC pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions 1 - - pe2 i/o ft (1) traceck, tim3_ch1, tsc_g7_io1, eventout - 2 - - pe3 i/o ft (1) traced0, tim3_ch2, tsc_g7_io2, eventout - 3 - - pe4 i/o ft (1) traced1, tim3_ch3, tsc_g7_io3, eventout - 4 - - pe5 i/o ft (1) traced2, tim3_ch4, tsc_g7_io4, eventout - 5 - - pe6 i/o ft (1) traced3, eventout wkup3, rtc_tamp3 611 v bat s - - backup power supply 722pc13 (2) i/o tc - tim1_ch1n wkup2, rtc_tamp1, rtc_ts, rtc_out 833 pc14 (2) osc32_in (pc14) i/o tc - - osc32_in 944 pc15 (2) osc32_ out (pc15) i/o tc - - osc32_out 10 - - pf9 i/o ft (1) tim15_ch1, spi2_sck, eventout - 11 - - pf10 i/o ft (1) tim15_ch2, spi2_sck, eventout - 12 5 5 pf0- osc_in (pf0) i/o ftf - tim1_ch3n, i2c2_sda, osc_in 13 6 6 pf1- osc_out (pf1) i/o ftf - i2c2_scl osc_out 14 7 7 nrst i/o rst - device reset input / internal reset output (active low) 15 8 - pc0 i/o tta (1) eventout adc12_in6, comp7_inm 16 9 - pc1 i/o tta (1) eventout adc12_in7, comp7_inp 17 10 - pc2 i/o tta (1) comp7_out, eventout adc12_in8 18 11 - pc3 i/o tta (1) tim1_bkin2, eventout adc12_in9 19 - - pf2 i/o tta (1) eventout adc12_in10 20 12 8 vssa/ vref- s - - analog ground/negative reference voltage docid025540 rev 4 35/134 STM32F358XC pinouts and pin description 51 21 - - vref+ s - - positive refe rence voltage 22 - vdda s - - analog power supply -139 vdda/ vref+ s - - analog power supply/positive reference voltage 23 14 10 pa0 i/o tta - usart2_cts, tim2_ch1_etr, tim8_bkin, tim8_etr, tsc_g1_io1, comp1_out, eventout adc1_in1, comp1_inm, rtc_ tamp2, wkup1, comp7_inp 24 15 11 pa1 i/o tta - usart2_rts_de, tim2_ch2, tsc_g1_io2, tim15_ch1n, rtc_refin, eventout adc1_in2, comp1_inp, opamp1_vinp, opamp3_vinp 25 16 12 pa2 i/o tta (3) usart2_tx, tim2_ch3, tim15_ch1, tsc_g1_io3, comp2_out, eventout adc1_in3, comp2_inm, opamp1_vout 26 17 13 pa3 i/o tta - usart2_rx, tim2_ch4, tim15_ch2, tsc_g1_io4, eventout adc1_in4, opamp1_vinp, comp2_inp, opamp1_vinm 27 18 - pf4 i/o tta (1) comp1_out, eventout adc1_in5 28 19 - vdd_4 s - - -- 29 20 14 pa4 i/o tta (3) spi1_nss, spi3_nss, i2s3_ws, usart2_ck, tsc_g2_io1, tim3_ch2, eventout adc2_in1, dac1_out1, opamp4_vinp, comp1_inm, comp2_inm, comp3_inm, comp4_inm, comp5_inm, comp6_inm,comp7_inm 30 21 15 pa5 i/o tta (3) spi1_sck, tim2_ch1_etr, tsc_g2_io2, eventout adc2_in2, dac1_out2 opamp1_vinp, opamp2_vinm, opamp3_vinp, comp1_inm, comp2_inm, comp3_inm, comp4_inm,comp5_inm, comp6_inm, comp7_inm 31 22 16 pa6 i/o tta (3) spi1_miso, tim3_ch1, tim8_bkin, tim1_bkin, tim16_ch1, comp1_out, tsc_g2_io3, eventout adc2_in3, opamp2_vout table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions pinouts and pin description STM32F358XC 36/134 docid025540 rev 4 32 23 17 pa7 i/o tta - spi1_mosi, tim3_ch2, tim17_ch1, tim1_ch1n, tim8_ch1n, tsc_g2_io4, comp2_out, eventout adc2_in4, comp2_inp, opamp2_vinp, opamp1_vinp 33 24 - pc4 i/o tta (1) usart1_tx, eventout adc2_in5 34 25 - pc5 i/o tta (1) usart1_rx, tsc_g3_io1, eventout adc2_in11, opamp2_vinm, opamp1_vinm 35 26 18 pb0 i/o tta - tim3_ch3, tim1_ch2n, tim8_ch2n, tsc_g3_io2, eventout adc3_in12, comp4_inp, opamp3_vinp, opamp2_vinp 36 27 19 pb1 i/o tta (3) tim3_ch4, tim1_ch3n, tim8_ch3n, comp4_out, tsc_g3_io3, eventout adc3_in1, opamp3_vout 37 28 20 npor i por (4) device power-on reset input 38 - - pe7 i/o tta (1) tim1_etr, eventout a dc3_in13, comp4_inp 39 - - pe8 i/o tta (1) tim1_ch1n, eventout co mp4_inm, adc34_in6 40 - - pe9 i/o tta (1) tim1_ch1, eventout adc3_in2 41 - - pe10 i/o tta (1) tim1_ch2n, eventout adc3_in14 42 - - pe11 i/o tta (1) tim1_ch2, eventout adc3_in15 43 - pe12 i/o tta (1) tim1_ch3n, eventout adc3_in16 44 - - pe13 i/o tta (1) tim1_ch3, eventout adc3_in3 45 - - pe14 i/o tta (1) tim1_ch4, tim1_bkin2, eventout adc4_in1 46 - - pe15 i/o tta (1) usart3_rx, tim1_bkin, eventout adc4_in2 47 29 21 pb10 i/o tta - usart3_tx, tim2_ch3, tsc_sync, eventout comp5_inm, opamp4_vinm, opamp3_vinm 48 30 22 pb11 i/o tta - usart3_rx, tim2_ch4, tsc_g6_io1, eventout comp6_inp, opamp4_vinp 49 31 23 vss_2 s - - digital ground 50 32 24 vdd_2 s - - digital power supply 51 33 25 pb12 i/o tta (3) spi2_nss, i2s2_ws, i2c2_smba, usart3_ck, tim1_bkin, tsc_g6_io2, eventout adc4_in3, comp3_inm, opamp4_vout, table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions docid025540 rev 4 37/134 STM32F358XC pinouts and pin description 51 52 34 26 pb13 i/o tta - spi2_sck, i2s2_ck, usart3_cts, tim1_ch1n, tsc_g6_io3, eventout adc3_in5, comp5_inp, opamp4_vinp, opamp3_vinp 53 35 27 pb14 i/o tta - spi2_miso, i2s2ext_sd, usart3_rts_de, tim1_ch2n, tim15_ch1, tsc_g6_io4, eventout comp3_inp, adc4_in4, opamp2_vinp 54 36 28 pb15 i/o tta - spi2_mosi, i2s2_sd, tim1_ch3n, rtc_refin, tim15_ch1n, tim15_ch2, eventout adc4_in5, comp6_inm 55 - - pd8 i/o tta (1) usart3_tx, eventout adc4 _in12, opamp4_vinm 56 - - pd9 i/o tta (1) usart3_rx, eventout adc4_in13 57 - - pd10 i/o tta (1) usart3_ck, eventout adc34_in7, comp6_inm 58 - - pd11 i/o tta (1) usart3_cts, eventout adc34_in8, comp6_inp, opamp4_vinp 59 - - pd12 i/o tta (1) usart3_rts_de, tim4_ch1, tsc_g8_io1, eventout adc34_in9, comp5_inp 60 - - pd13 i/o tta (1) tim4_ch2, tsc_g8_io2, eventout adc34_in10, comp5_inm 61 - - pd14 i/o tta (1) tim4_ch3, tsc_g8_io3, eventout comp3_inp, adc34_in11, opamp2_vinp 62 - - pd15 i/o tta (1) spi2_nss, tim4_ch4, tsc_g8_io4, eventout comp3_inm 63 37 - pc6 i/o ft (1) i2s2_mck, comp6_out, tim8_ch1, tim3_ch1, eventout - 64 38 - pc7 i/o ft (1) i2s3_mck, tim8_ch2, tim3_ch2, comp5_out, eventout - 65 39 - pc8 i/o ft (1) tim8_ch3, tim3_ch3, comp3_out, eventout - 66 40 - pc9 i/o ft (1) tim8_ch4, tim8_bkin2, tim3_ch4, i2s_ckin, eventout - table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions pinouts and pin description STM32F358XC 38/134 docid025540 rev 4 67 41 29 pa8 i/o ft - i2c2_smba, i2s2_mck, usart1_ck, tim1_ch1, tim4_etr, mco, comp3_out, eventout - 68 42 30 pa9 i/o ftf - i2c2_scl, i2s3_mck, usart1_tx, tim1_ch2, tim2_ch3, tim15_bkin, tsc_g4_io1, comp5_out, eventout - 69 43 31 pa10 i/o ftf - i2c2_sda, usart1_rx, tim1_ch3, tim2_ch4, tim8_bkin, tim17_bkin, tsc_g4_io2, comp6_out, eventout - 70 44 32 pa11 i/o ft - usart1_cts, can_rx, tim1_ch1n, tim1_ch4, tim1_bkin2, tim4_ch1, comp1_out, eventout - 71 45 33 pa12 i/o ft - usart1_rts_de, can_tx, tim1_ch2n, tim1_etr, tim4_ch2, tim16_ch1, comp2_out, eventout - 72 46 34 pa13 i/o ft - usart3_cts, tim4_ch3, tim16_ch1n, tsc_g4_io3, ir_out, swdio-jtms, eventout - 73 - - pf6 i/o ftf (1) i2c2_scl, usart3_rts_de, tim4_ch4, eventout - 74 47 35 vss_3 s - -ground 75 48 36 vdd_3 s - - digital power supply 76 49 37 pa14 i/o ftf - i2c1_sda, usart2_tx, tim8_ch2, tim1_bkin, tsc_g4_io4, swclk-jtck, eventout - 77 50 38 pa15 i/o ftf - i2c1_scl, spi1_nss, spi3_nss, i2s 3_ws, jtdi, usart2_rx, tim1_bkin, tim2_ch1_etr, tim8_ch1, eventout - table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions docid025540 rev 4 39/134 STM32F358XC pinouts and pin description 51 78 51 - pc10 i/o ft (1) spi3_sck, i2s3_ck, usart3_tx, uart4_tx, tim8_ch1n, eventout - 79 52 - pc11 i/o ft (1) spi3_miso, i2s3ext_sd, usart3_rx, uart4_rx, tim8_ch2n, eventout - 80 53 - pc12 i/o ft (1) spi3_mosi, i2s3_sd, usart3_ck, uart5_tx, tim8_ch3n, eventout - 81 - - pd0 i/o ft (1) can_rx, eventout - 82 - - pd1 i/o ft (1) can_tx, tim8_ch4, tim8_bkin2, eventout - 83 54 - pd2 i/o ft (1) uart5_rx, tim3_etr, tim8_bkin, eventout - 84 - - pd3 i/o ft (1) usart2_cts, tim2_ch1_etr, eventout - 85 - - pd4 i/o ft (1) usart2_rts_de, tim2_ch2, eventout - 86 - - pd5 i/o ft (1) usart2_tx, eventout - 87 - - pd6 i/o ft (1) usart2_rx, tim2_ch4, eventout - 88 - - pd7 i/o ft (1) usart2_ck, tim2_ch3, eventout - 89 55 39 pb3 i/o ft - spi3_sck, i2s3_ck, spi1_sck, usart2_tx, tim2_ch2, tim3_etr, tim4_etr, tim8_ch1n, tsc_g5_io1, jtdo- traceswo, eventout - 90 56 40 pb4 i/o ft - spi3_miso, i2s3ext_sd, spi1_miso, usart2_rx, tim3_ch1, tim16_ch1, tim17_bkin, tim8_ch2n, tsc_g5_io2, njtrst, eventout - 91 57 41 pb5 i/o ft - spi3_mosi, spi1_mosi, i2s3_sd, i2c1_smba, usart2_ck, tim16_bkin, tim3_ch2, tim8_ch3n, tim17_ch1, eventout - table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions pinouts and pin description STM32F358XC 40/134 docid025540 rev 4 92 58 42 pb6 i/o ftf - i2c1_scl, usart1_tx, tim16_ch1n, tim4_ch1, tim8_ch1, tsc_g5_io3, tim8_etr, tim8_bkin2, eventout - 93 59 43 pb7 i/o ftf - i2c1_sda, usart1_rx, tim3_ch4, tim4_ch2, tim17_ch1n, tim8_bkin, tsc_g5_io4, eventout - 94 60 44 boot0 i b - boot memory selection 95 61 45 pb8 i/o ftf - i2c1_scl, can_rx, tim16_ch1, tim4_ch3, tim8_ch2, tim1_bkin, tsc_sync, comp1_out, eventout - 96 62 46 pb9 i/o ftf - i2c1_sda, can_tx, tim17_ch1, tim4_ch4, tim8_ch3, ir_out, comp2_out, eventout - 97 - - pe0 i/o ft (1) usart1_tx, tim4_etr, tim16_ch1, eventout - 98 - - pe1 i/o ft (1) usart1_rx, tim17_ch1, eventout - 99 63 47 vss_1 s - -ground 100 64 48 vdd_1 s - - digital power supply 1. function availability depends on the chosen device. when using the small packages (48 and 64 pin packages), the gp io pins which are not present on these packages, must not be configured in analog mode. 2. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch sinks only a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as current sources (e.g. to drive an led). after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the ma in reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register des cription sections in the reference manual. 3. these gpios offer a reduced touch sensing sensitivity. it is thus recommended to use them as sampling capacitor i/o 4. this pin is powered by vdda. table 13. STM32F358XC pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp100 lqfp64 lqfp48 alternate functions a dditional functions STM32F358XC pinouts and pin description docid025540 rev 4 41/134 table 14. alternate functions for port a port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af14 af15 pa0 - tim2_ ch1_ etr - tsc_ g1_io1 -- - usart2_ cts comp1 _out tim8_ bkin tim8_ etr --- event out pa1 rtc_ refin tim2_ ch2 - tsc_ g1_io2 -- - usart2_ rts_de - tim15_ ch1n ---- event out pa2 - tim2_ ch3 - tsc_ g1_io3 -- - usart2_ tx comp2 _out tim15_ ch1 ---- event out pa3 - tim2_ ch4 - tsc_ g1_io4 -- - usart2_ rx - tim15_ ch2 ---- event out pa4 - tim3_ ch2 tsc_ g2_io1 - spi1_ nss spi3_nss, i2s3_ws usart2_ ck --- - -- event out pa5 - tim2_ ch1_ etr - tsc_ g2_io2 - spi1_ sck -------- event out pa6 - tim16_ ch1 tim3_ ch1 tsc_ g2_io3 tim8_ bkin spi1_ miso tim1_bkin - comp1 _out -- - -- event out pa7 - tim17_ ch1 tim3_ ch2 tsc_ g2_io4 tim8_ ch1n spi1_ mosi tim1_ch1n - comp2 _out -- - -- event out pa8 mco - - - i2c2_ smba i2s2_ mck tim1_ch1 usart1_ ck comp3 _out - tim4_ etr --- event out pa9 - - - tsc_ g4_io1 i2c2_ scl i2s3_ mck tim1_ch2 usart1_ tx comp5 _out tim15_ bkin tim2_ ch3 --- event out pa10 - tim17_ bkin - tsc_ g4_io2 i2c2_ sda - tim1_ch3 usart1_ rx comp6 _out - tim2_ ch4 tim8_ bkin -- event out pa11 - - - - - - tim1_ch1n usart1_ cts comp1 _out can_rx tim4_ ch1 tim1_ch4 tim1_ bkin2 - event out pinouts and pin description STM32F358XC 42/134 docid025540 rev 4 pa12 - tim16_ ch1 - - - - tim1_ch2n usart1_ rts_de comp2 _out can_tx tim4_ ch2 tim1_etr - - event out pa13 swdio -jtms tim16_ ch1n - tsc_ g4_io3 - ir_ out - usart3_ cts -- tim4_ ch3 --- event out pa14 swclk -jtck -- tsc_ g4_io4 i2c1_ sda tim8_ ch2 tim1_bkin usart2_ tx --- - -- event out pa15 jtdi tim2_ ch1_ etr tim8_ ch1 - i2c1_ scl spi1_ nss spi3_nss, i2s3_ws usart2_ rx - tim1_ bkin ---- event out table 14. alternate functions for port a (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af11 af12 af14 af15 STM32F358XC pinouts and pin description docid025540 rev 4 43/134 table 15. alternate functions for port b port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af12 af15 pb0 - - tim3_ ch3 tsc_ g3_io2 tim8_ ch2n - tim1_ch2n - - - - - event out pb1 - - tim3_ ch4 tsc_ g3_io3 tim8_ ch3n - tim1_ch3n - comp4_ out - - - event out pb3 jtdo- traces wo tim2_ ch2 tim4_ etr tsc_ g5_io1 tim8_ ch1n spi1_ sck spi3_sck, i2s3_ck usart2_ tx - - tim3_ etr - event out pb4 njtrst tim16_ ch1 tim3_ ch1 tsc_ g5_io2 tim8_ ch2n spi1_ miso spi3_miso, i2s3ext_sd usart2_ rx - - tim17_ bkin - event out pb5 - tim16_ bkin tim3_ ch2 tim8_ ch3n i2c1_ smba spi1_ mosi spi3_mosi, i2s3_sd usart2_ ck - - tim17_ ch1 - event out pb6 - tim16_ ch1n tim4_ ch1 tsc_ g5_io3 i2c1_scl tim8_ch1 tim8_ etr usart1_ tx - - tim8_ bkin2 - event out pb7 - tim17_ ch1n tim4_ ch2 tsc_ g5_io4 i2c1_ sda tim8_ bkin - usart1_ rx - - tim3_ ch4 - event out pb8 - tim16_ ch1 tim4_ ch3 tsc_ sync i2c1_scl - - - comp1_ out can_rx tim8_ ch2 tim1_ bkin event out pb9 - tim17_ ch1 tim4_ ch4 i2c1_ sda - ir_out - comp2_ out can_tx tim8_ ch3 - event out pb10 - tim2_ ch3 - tsc_ sync - - - usart3_ tx - - - - event out pb11 - tim2_ ch4 - tsc_ g6_io1 - - - usart3_ rx - - - - event out pb12 - - - tsc_ g6_io2 i2c2_ smba spi2_nss, i2s2_ws tim1_ bkin usart3_ ck - - - - event out pb13 - - - tsc_ g6_io3 - spi2_sck, i2s2_ck tim1_ ch1n usart3_ cts - - - - event out pinouts and pin description STM32F358XC 44/134 docid025540 rev 4 pb14 - tim15_ ch1 - tsc_ g6_io4 - spi2_miso, i2s2ext_sd tim1_ ch2n usart3_ rts_de - - - - event out pb15 rtc_ refin tim15_ ch2 tim15_ ch1n - tim1_ ch3n spi2_mosi, i2s2_sd - - - - - - event out table 15. alternate functions for port b (continued) port & pin name af0 af1 af2 af3 af4 af5 af6 af7 af8 af9 af10 af12 af15 STM32F358XC pinouts and pin description docid025540 rev 4 45/134 table 16. alternate functions for port c port & pin name af1 af2 af3 af4 af5 af6 af7 pc0 eventout - - - - - - pc1 eventout - - - - - - pc2 eventout - comp7_out - - - - pc3 eventout - - - - tim1_bkin2 - pc4 eventout - - - - - usart1_tx pc5 eventout tsc_g3_io1 - - - usart1_rx pc6 eventout tim3_ch1 - tim8_ch1 - i2s2_mck comp6_out pc7 eventout tim3_ch2 - tim8_ch2 - i2s3_mck comp5_out pc8 eventout tim3_ch3 - tim8_ch3 - - comp3_out pc9 eventout tim3_ch4 - tim8_ch4 i2s_ckin tim8_bkin2 - pc10 eventout - - tim8_ch1n uart4_tx spi3_sck, i2s3_ck usart3_tx pc11 eventout - - tim8_ch2n uart4_rx spi3_miso, i2s3ext_sd usart3_rx pc12 eventout - - tim8_ch3n uart5_tx spi3_mosi, i2s3_sd usart3_ck pc13 - - - tim1_ch1n - - - pc14 - - - - - - - pc15 - - - - - - - pinouts and pin description STM32F358XC 46/134 docid025540 rev 4 table 17. alternate functions for port d port & pin name af1 af2 af3 af4 af5 af6 af7 pd0 eventout - - - - - can_rx pd1 eventout - tim8_ch4 - tim8_bkin2 - pd2 eventout tim3_etr - tim8_bkin uart5_rx - - pd3 eventout tim2_ch1_etr - - - - usart2_cts pd4 eventout tim2_ch2 - - - - usart2_rts_de pd5 eventout - - - - - usart2_tx pd6 eventout tim2_ch4 - - - - usart2_rx pd7 eventout tim2_ch3 - - - - usart2_ck pd8 eventout - - - - usart3_tx pd9 eventout - - - - - usart3_rx pd10 eventout - - - - - usart3_ck pd11 eventout - - - - - usart3_cts pd12 eventout tim4_ch1 tsc_g8_io1 - - - usart3_rts_de pd13 eventout tim4_ch2 tsc_g8_io2 - - - - pd14 eventout tim4_ch3 tsc_g8_io3 - - - - pd15 eventout tim4_ch4 tsc_g8_io4 - - spi2_nss - STM32F358XC pinouts and pin description docid025540 rev 4 47/134 table 18. alternate functions for port e port & pin name af0 af1 af2 af3 af4 af6 af7 pe0 - eventout tim4_etr - tim16_ch1 - usart1_tx pe1 - eventout - - tim17_ch1 - usart1_rx pe2 traceck eventout tim3_ch1 tsc_g7_io1 - - - pe3 traced0 eventout tim3_ch2 tsc_g7_io2 - - - pe4 traced1 eventout tim3_ch3 tsc_g7_io3 - - - pe5 traced2 eventout tim3_ch4 tsc_g7_io4 - - - pe6 traced3 eventout - - - - - pe7 - eventout tim1_etr - - - - pe8 - eventout tim1_ch1n - - - - pe9 - eventout tim1_ch1 - - - - pe10 - eventout tim1_ch2n - - - - pe11 - eventout tim1_ch2 - - - - pe12 - eventout tim1_ch3n - - - - pe13 - eventout tim1_ch3 - - - - pe14 - eventout tim1_ch4 - - tim1_bkin2 - pe15 - eventout tim1_bkin - - - usart3_rx pinouts and pin description STM32F358XC 48/134 docid025540 rev 4 table 19. alternate functions for port f port & pin name af1 af2 af3 af4 af5 af6 af7 pf0 - - - i2c2_sda - tim1_ch3n - pf1 - - - i2c2_scl - - - pf2 eventout - - - - - - pf4 eventout comp1_out - - - - pf6 eventout tim4_ch4 i2c2_scl - - usart3_rts_de pf9 eventout - tim15_ch1 - spi2_sck - - pf10 eventout - tim15_ch2 - spi2_sck - - docid025540 rev 4 49/134 STM32F358XC memory mapping 51 5 memory mapping figure 7. STM32F358XC memory map [ ) ) ) ) ) ) ) ) [ ( [ & [ $ [ [ [ [ [ & r u w h [ 0 z l w k ) 3 8 , q w h u q d o 3 h u l s k h u d o v 3 h u l s k h u d o v 6 5 $ 0 & 2 ' ( 2 s w l r q e \ w h v 6 \ v w h p p h p r u \ & & 0 5 $ 0 ) o d v k p h p r u \ ) o d v k v \ v w h p p h p r u \ r u 6 5 $ 0 g h s h q g l q j r q % 2 2 7 f r q i l j x u d w l r q $ + % $ + % $ 3 % $ 3 % [ [ [ [ ) ) [ [ & [ [ $ [ [ ) ) ) ) ) ) ) [ ) ) ) ) [ ) ) ) ' [ [ [ [ [ [ 5 h v h u y h g 0 6 y 9 $ + % [ ) ) 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g 5 h v h u y h g memory mapping STM32F358XC 50/134 docid025540 rev 4 table 20. STM32F358XC memory map and peripheral register boundary addresses bus boundary address size (bytes) peripheral ahb3 0x5000 0400 - 0x5000 07ff 1 k adc3 - adc4 0x5000 0000 - 0x5000 03ff 1 k adc1 - adc2 0x4800 1800 - 0x4fff ffff ~132 m reserved ahb2 0x4800 1400 - 0x4800 17ff 1 k gpiof 0x4800 1000 - 0x4800 13ff 1 k gpioe 0x4800 0c00 - 0x4800 0fff 1 k gpiod 0x4800 0800 - 0x4800 0bff 1 k gpioc 0x4800 0400 - 0x4800 07ff 1 k gpiob 0x4800 0000 - 0x4800 03ff 1 k gpioa 0x4002 4400 - 0x47ff ffff ~128 m reserved ahb1 0x4002 4000 - 0x4002 43ff 1 k tsc 0x4002 3400 - 0x4002 3fff 3 k reserved 0x4002 3000 - 0x4002 33ff 1 k crc 0x4002 2400 - 0x4002 2fff 3 k reserved 0x4002 2000 - 0x4002 23ff 1 k flash interface 0x4002 1400 - 0x4002 1fff 3 k reserved 0x4002 1000 - 0x4002 13ff 1 k rcc 0x4002 0800 - 0x4002 0fff 2 k reserved 0x4002 0400 - 0x4002 07ff 1 k dma2 0x4002 0000 - 0x4002 03ff 1 k dma1 0x4001 8000 - 0x4001 ffff 32 k reserved apb2 0x4001 4c00 - 0x4001 7fff 13 k reserved 0x4001 4800 - 0x4001 4bff 1 k tim17 0x4001 4400 - 0x4001 47ff 1 k tim16 0x4001 4000 - 0x4001 43ff 1 k tim15 0x4001 3c00 - 0x4001 3fff 1 k reserved 0x4001 3800 - 0x4001 3bff 1 k usart1 0x4001 3400 - 0x4001 37ff 1 k tim8 0x4001 3000 - 0x4001 33ff 1 k spi1 0x4001 2c00 - 0x4001 2fff 1 k tim1 0x4001 0800 - 0x4001 2bff 9 k reserved 0x4001 0400 - 0x4001 07ff 1 k exti 0x4001 0000 - 0x4001 03ff 1 k syscfg + comp + opamp docid025540 rev 4 51/134 STM32F358XC memory mapping 51 0x4000 8000 - 0x4000 ffff 32 k reserved apb1 0x4000 7800 - 0x4000 7fff 2 k reserved 0x4000 7400 - 0x4000 77ff 1 k dac (dual) 0x4000 7000 - 0x4000 73ff 1 k pwr 0x4000 6c00 - 0x4000 6fff 1 k reserved 0x4000 6800 - 0x4000 6bff 1 k reserved 0x4000 6400 - 0x4000 67ff 1 k bxcan 0x4000 5c00 - 0x4000 63ff 2 k reserved 0x4000 5800 - 0x4000 5bff 1 k i2c2 0x4000 5400 - 0x4000 57ff 1 k i2c1 0x4000 5000 - 0x4000 53ff 1 k uart5 0x4000 4c00 - 0x4000 4fff 1 k uart4 0x4000 4800 - 0x4000 4bff 1 k usart3 0x4000 4400 - 0x4000 47ff 1 k usart2 0x4000 4000 - 0x4000 43ff 1 k i2s3ext 0x4000 3c00 - 0x4000 3fff 1 k spi3/i2s3 0x4000 3800 - 0x4000 3bff 1 k spi2/i2s2 0x4000 3400 - 0x4000 37ff 1 k i2s2ext 0x4000 3000 - 0x4000 33ff 1 k iwdg 0x4000 2c00 - 0x4000 2fff 1 k wwdg 0x4000 2800 - 0x4000 2bff 1 k rtc 0x4000 1800 - 0x4000 27ff 4 k reserved 0x4000 1400 - 0x4000 17ff 1 k tim7 0x4000 1000 - 0x4000 13ff 1 k tim6 0x4000 0c00 - 0x4000 0fff 1 k reserved 0x4000 0800 - 0x4000 0bff 1 k tim4 0x4000 0400 - 0x4000 07ff 1 k tim3 0x4000 0000 - 0x4000 03ff 1 k tim2 table 20. STM32F358XC memory map and peripheral register boundary addresses (continued) bus boundary address size (bytes) peripheral electrical characteristics STM32F358XC 52/134 docid025540 rev 4 6 electrical characteristics 6.1 parameter conditions unless otherwise specified, all voltages are referenced to v ss . 6.1.1 minimum and maximum values unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 6.1.2 typical values unless otherwise specified, typical data are based on t a = 25 c, v dd = 1.8 v, v dda = 3.3 v. they are given only as design guidelines and are not tested. typical adc accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 6.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 8 . 6.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 9 . figure 8. pin loading conditions figure 9. pin input voltage 0 6 9 0 & 8 s l q & s ) 0 6 9 0 & 8 s l q 9 , 1 docid025540 rev 4 53/134 STM32F358XC electrical characteristics 118 6.1.6 power supply scheme figure 10. power supply scheme 1. dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins. caution: each power supply pair (v dd /v ss , v dda /v ssa etc..) must be decoupled with filtering ceramic capacitors as shown above. these capa citors must be placed as close as possible to, or below the appropriate pins on the underside of the pcb to ensure the good functionality of the device. 6.1.7 current consumption measurement figure 11. current consumption measurement scheme 0 6 9 3 r z h u v z l w f k 9 % $ 7 * 3 , 2 v 2 8 7 , 1 . h u q h o o r j l f & 3 8 ' l j l w d o 0 h p r u l h v % d f n x s f l u f x l w u \ / 6 ( 5 7 & % d f n x s u h j l v w h u v : d n h x s o r j l f q ) ? ? ) 9 5 h j x o d w r u 9 ' ' $ 9 6 6 $ $ ' & ' $ & / h y h o v k l i w h u , 2 / r j l f 9 ' ' q ) ? ) 9 ' ' $ 9 5 ( ) 9 5 ( ) 9 ' ' 9 6 6 ? ? 9 5 ( ) q ) ? ) ? ! n a l o g 2 # s 0 , , c o m p a r a t o r s / 0 ! - 0 - 3 6 6 $ $ 6 $ $ ! ) $ $ ) $ $ ! electrical characteristics STM32F358XC 54/134 docid025540 rev 4 6.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 21: voltage characteristics , table 22: current characteristics , and table 23: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. table 21. voltage characteristics (1) symbol ratings min max unit v dd ? v ss external digital supply voltage (including v dd and v bat ) -0.3 1.95 v v dda ? v ss external analog supply voltage -0.3 4.0 v dd ? v dda allowed voltage difference for v dd > v dda -0.4 v ref+ ?v dda (2) allowed voltage difference for v ref+ > v dda -0.4 v in (3) input voltage on ft and ftf pins v ss ? 0.3 v dd + 4.0 input voltage on tta pins v ss ? 0.3 4.0 input voltage on any other pin v ss ? 0.3 4.0 input voltage on por pin v ss ? 0.3 v dda + 4.0 input voltage on b pin 0 9 | v ddx | variations between different v dd power pins - 50 mv |v ssx ? v ss | variations between all the different ground pins - 50 v esd(hbm) electrostatic discharge voltage (human body model) see section 6.3.11: electrical sensitivity characteristics - 1. all main power (v dd , v dda ) and ground (v ss , v ssa ) pins must always be connected to the external power supply, in the permitted range. the following relationship must be respected between v dda and v dd : v dda must power on before or at the same time as v dd in the power up sequence. v dda must be greater than or equal to v dd . 2. v ref+ must be always lower or equal than v dda (v ref+ v dda) . if unused then it must be connected to v dda . 3. v in maximum must always be respected. refer to table 22: current characteristics for the maximum allowed injected current values. docid025540 rev 4 55/134 STM32F358XC electrical characteristics 118 table 22. current characteristics symbol ratings max. unit i vdd total current into sum of all vdd_x power lines (source) 160 ma i vss total current out of sum of all vss_x ground lines (sink) ? 160 i vdd maximum current into each v dd_x power line (source) (1) 100 i vss maximum current out of each v ss _x ground line (sink) (1) ? 100 i io(pin) output current sunk by any i/o and control pin 25 output current source by any i/o and control pin ? 25 i io(pin) total output current sunk by sum of all ios and control pins (2) 80 total output current sourced by sum of all ios and control pins (2) ? 80 i inj(pin) injected current on ft, ftf, por and b pins (3) -5/+0 injected current on tc and rst pin (4) 5 injected current on tta pins (5) 5 i inj(pin) total injected current (sum of all i/o and control pins) (6) 25 1. all main power (v dd , v dda ) and ground (v ss and v ssa ) pins must always be connected to the external power supply, in the permitted range. 2. this current consumption must be correctly distributed over all i/os and control pins.the total output current must not be sunk/sourced between two c onsecutive power supply pins referrin g to high pin count lqfp packages. 3. positive injection is not possible on these i/os and does not occur for input voltages lower than the specified maximum value. 4. a positive injection is induced by v in > v dd while a negative injection is induced by v in < v ss . i inj(pin) must never be exceeded. refer to table 21: voltage characteristics for the maximum allowed input voltage values. 5. a positive injection is induced by v in > v dda while a negative injection is induced by v in < v ss . i inj (pin) must never be exceeded. refer also to table 21: voltage characteristics for the maximum allowed input voltage values. negative injection disturbs the analog performance of the device. see note (2) below table 66 . 6. when several inputs are submitted to a current injection, the maximum i inj(pin) is the absolute sum of the positive and negative injected currents (instantaneous values). table 23. thermal characteristics symbol ratings value unit t stg storage temperature range ?65 to +150 c t j maximum junction temperature 150 c electrical characteristics STM32F358XC 56/134 docid025540 rev 4 6.3 operating conditions 6.3.1 general operating conditions table 24. general operating conditions symbol parameter conditions min max unit f hclk internal ahb clock frequency 0 72 mhz f pclk1 internal apb1 clock frequency 0 36 f pclk2 internal apb2 clock frequency 0 72 v dd standard operating voltage 1.65 1.95 v v dda analog operating voltage (opamp and dac not used) must have a potential equal to or higher than v dd 1.65 3.6 v analog operating voltage (opamp and dac used) 2.4 3.6 analog operating voltage (adc used) 1.8 v 3.6 v v bat backup operating voltage 1.65 3.6 v v in i/o input voltage tc i/o ?0.3 v dd +0.3 v tta i/o and por i/o pins ?0.3 v dda +0.3 ft, ftf i/o pins ?0.3 5.2 boot0 0 5.2 p d power dissipation at t a = 85 c for suffix 6 or t a = 105 c for suffix 7 (1) 1. if t a is lower, higher p d values are allowed as long as t j does not exceed t jmax (see table 23: thermal characteristics ). lqfp100 - 488 mw lqfp64 - 444 lqfp48 - 364 t a ambient temperature for 6 suffix version maximum power dissipation ?40 85 c low-power dissipation (2) 2. in low-power dissipation state, t a can be extended to this range as long as t j does not exceed t jmax (see table 23: thermal characteristics ). ?40 105 ambient temperature for 7 suffix version maximum power dissipation ?40 105 c low-power dissipation (2) ?40 125 t j junction temperature range 6 suffix version ?40 105 c 7 suffix version ?40 125 docid025540 rev 4 57/134 STM32F358XC electrical characteristics 118 6.3.2 operating conditions at power-up / power-down the parameters given in table 25 are derived from tests performed under the ambient temperature condition summarized in table 24 . 6.3.3 embedded reference voltage the parameters given in table 26 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 24 . table 25. operating conditions at power-up / power-down symbol parameter conditions min max unit t vdd v dd rise time rate - 0 s/v v dd fall time rate 20 t vdda v dda rise time rate - 0 v dda fall time rate 20 table 26. embedded internal reference voltage symbol parameter conditions min typ max unit v refint internal reference voltage ?40 c < t a < +105 c 1.16 1.2 1.25 v ?40 c < t a < +85 c 1.16 1.2 1.24 (1) 1. data based on characterization results, not tested in production. v t s_vrefint adc sampling time when reading the internal reference voltage -2.2--s v rerint internal reference voltage spread over the temperature range v dd = 1.8 v 10 mv - - 10 (2) 2. guaranteed by design, not tested in production. mv t coeff temperature coefficient - - - 100 (2) ppm/c t refint_rdy (3) 3. guaranteed by design, not tested in production. lat ency between the time when pin npor is set to 1 by the application and the time when v refintrdyf is set to 1 by the hardware. internal reference voltage temporization -1.52.54.5ms table 27. internal reference voltage calibration values calibration value name description memory address v refint_cal raw data acquired at temperature of 30 c v dda = 3.3 v 0x1fff f7ba - 0x1fff f7bb electrical characteristics STM32F358XC 58/134 docid025540 rev 4 6.3.4 supply current characteristics the current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, i/o pi n loading, device software configuration, operating frequencies, i/o pin switching rate, program location in memory and executed binary code. the current consumption is measured as described in figure 11: current consumption measurement scheme . all run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to coremark code. typical and maximum current consumption the mcu is placed under the following conditions: ? all i/o pins are in input mode with a static value at v dd or v ss (no load) ? all peripherals are disabled ex cept when explicitly mentioned ? the flash memory access time is adjusted to the f hclk frequency (0 wait state from 0 to 24 mhz,1 wait state from 24 to 48 mhz and 2 wait states from 48 to 72 mhz) ? prefetch in on (reminder: this bit must be set before clock setting and bus prescaling) ? when the peripherals are enabled f pclk2 = f hclk and f pclk1 = f hclk/2 ? when f hclk > 8 mhz, the pll is on and the pll input is equal to hsi/2 (4 mhz) or hse (8 mhz) in bypass mode. the parameters given in table 28 to table 37 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24 . docid025540 rev 4 59/134 STM32F358XC electrical characteristics 118 table 28. typical and maximum current consumption from v dd supply at v dd = 1.8 v symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c i dd supply current in run mode, executing from flash external clock (hse bypass) 72 mhz 60.4 65.4 66.6 67.8 27.3 29.6 30.3 31.0 ma 64 mhz 54.1 58.6 59.8 60.9 24.5 26.5 27.3 27.9 48 mhz 41.5 45.0 46.1 47.0 18.8 20.4 21.0 21.7 32 mhz 28.2 30.6 31.6 32.4 12.9 14.0 14.5 15.1 24 mhz 21.5 23.4 24.2 24.9 9.8 10.8 11.3 11.8 8 mhz 7.2 8.0 8.6 9.1 3.3 3.8 4.1 4.8 1 mhz 1.1 1.4 1.6 2.4 0.6 0.8 1.1 1.9 internal clock (hsi) 64 mhz 49.4 53.6 54.6 55.7 24.3 26.3 27.0 27.6 48 mhz 37.9 41.2 42.1 43.0 18.6 20.3 20.8 21.4 32 mhz 25.8 28.1 29.0 29.7 12.7 13.9 14.4 14.9 24 mhz 19.7 21.4 22.3 22.9 6.6 7.3 7.8 8.3 8 mhz 6.8 7.5 8.0 8.6 3.3 3.7 4.1 4.8 supply current in run mode, executing from ram external clock (hse bypass) 72 mhz 61.3 66,5 (2) 67.6 68,9 (2) 28.3 30,6 (2) 31.5 32,2 (2) 64 mhz 54.9 59.5 60.6 61.9 25.3 27.4 28.1 28.8 48 mhz 41.7 45.3 46.4 47.3 19.1 20.7 21.3 22.0 32 mhz 28.2 30.7 31.7 32.4 12.8 14.0 14.6 15.1 24 mhz 21.3 23.2 24.0 24.7 9.7 10.6 11.1 11.6 8 mhz 7.0 7.8 8.3 8.9 3.1 3.4 4.0 4.6 1 mhz 0.7 0.9 1.3 2.1 0.2 0.4 0.8 1.5 internal clock (hsi) 64 mhz 50.0 54.2 55.4 56.5 24.9 27.0 27.7 28.3 48 mhz 38.0 41.3 42.3 43.2 18.7 20.4 21.0 21.6 32 mhz 25.7 27.9 28.8 29.6 12.6 13.7 14.2 14.8 24 mhz 19.4 21.1 22.0 22.6 6.3 7.0 7.4 8.0 8 mhz 6.4 7.2 7.7 8.2 3.0 3.3 3.9 4.4 electrical characteristics STM32F358XC 60/134 docid025540 rev 4 i dd supply current in sleep mode, executing from flash or ram external clock (hse bypass) 72 mhz 44.2 48.2 49.4 50.5 6.6 7.2 7.8 8.4 ma 64 mhz 39.5 43.1 44.3 45.2 5.8 6.5 7.0 7.6 48 mhz 29.9 32.7 33.8 34.6 4.4 4.9 5.5 6.0 32 mhz 20.2 22.1 23.0 23.7 3.0 3.3 3.9 4.5 24 mhz 15.2 16.7 17.5 18.2 2.3 2.5 3.0 3.7 8 mhz 4.9 5.6 6.1 6.7 0.6 0.8 1.2 2.0 1 mhz 0.5 0.7 1.0 1.8 0.1 0.0 0.4 1.2 internal clock (hsi) 64 mhz 34.5 37.7 38.9 39.7 5.5 6.2 6.6 7.2 48 mhz 26.1 28.6 29.7 30.4 4.1 4.6 5.1 5.7 32 mhz 17.6 19.3 20.2 20.8 2.7 3.0 3.5 4.2 24 mhz 13.3 14.7 15.4 16.0 1.3 1.6 2.0 2.7 8 mhz 4.4 4.9 5.5 6.1 0.5 0.7 1.0 1.9 1. data based on characterization results, not tested in production unless otherwise specified . 2. data based on characterization results and te sted in production with code executing from ram. table 28. typical and maximum current consumption from v dd supply at v dd = 1.8 v (continued) symbol parameter conditions f hclk all peripherals enabled all peripherals disabled unit typ max @ t a (1) typ max @ t a (1) 25 c 85 c 105 c 25 c 85 c 105 c table 29. typical and maximum current consumption from the v dda supply symbol parameter conditions (1) f hclk v dda = 2.4 v v dda = 3.6 v unit typ max @ t a (2) typ max @ t a (2) 25 c 85 c 105 c 25 c 85 c 105 c i dda supply current in run/sleep mode, code executing from flash or ram hse bypass 72 mhz 225 276 289 297 245 302 319 329 a 64 mhz 198 249 261 268 216 270 284 293 48 mhz 149 195 204 211 159 209 222 230 32 mhz 102 145 152 157 110 154 162 169 24 mhz 80 119 124 128 86 126 131 135 8 mhz 2 3 4 6 3 4 5 9 1 mhz 2 3 5 7 3 4 6 9 hsi clock 64 mhz 270 323 337 344 299 354 371 381 48 mhz 220 269 280 286 244 293 309 318 32 mhz 173 218 228 233 193 239 251 257 24 mhz 151 194 200 204 169 211 219 225 8 mhz 73 97 99 103 88 105 110 116 1. current consumption from the v dda supply is independent of whether the peripherals are on or off. furthermore when the pll is off, i dda is independent from the frequency. docid025540 rev 4 61/134 STM32F358XC electrical characteristics 118 2. data based on characterization results, not tested in production. table 30. typical and maximum v dd consumption in stop mode symbol parameter conditions typ@v dd (v dd =v dda =1.8v) max (1) unit t a =25 c t a =85 c t a =105 c i dd supply current in stop mode all oscillators off 6.6 31.1 (2) 560.5 1225.8 (2) a 1. data based on characterization results, not te sted in production unless otherwise specified. 2. data based on characterization results and tested in production. table 31. typical and maximum v dda consumption in stop mode symbol parameter conditions typ@v dda (v dd = 1.8v) max (1) unit 1.8 v 2.0 v 2.4 v 2.7 v 3.0 v 3.3 v 3.6 v t a = 25 c t a = 85 c t a = 105 c i dda supply current in stop mode all oscillators off 0.76 0.78 0.80 0.83 0.87 0.94 1.01 3.2 5.3 7.9 a 1. data based on characterization results and tested in production. note: the total current consumpt ion is the sum of idd and idda table 32. typical and maximum current consumption from v bat supply symbol para meter conditions (1) typ @v bat max @v bat = 3.6 v (2) unit 1.65v 1.8v 2v 2.4v 2.7v 3v 3.3v 3.6v t a = 25c t a = 85c t a = 105c i dd_vbat backup domain supply current lse & rtc on; "xtal mode" lower driving capability; lsedrv[1: 0] = '00' 0.48 0.50 0.52 0.58 0.65 0. 72 0.80 0.90 1.1 1.5 2.0 a lse & rtc on; "xtal mode" higher driving capability; lsedrv[1: 0] = '11' 0.83 0.86 0.90 0.98 1.03 1. 10 1.20 1.30 1.5 2.2 2.9 1. crystal used: abracon abs07-120-32.768 khz-t with a cl of 6 pf for typical values. 2. data based on characterization re sults, not tested in production. electrical characteristics STM32F358XC 62/134 docid025540 rev 4 figure 12. typical v bat current consumption (lse and rtc on/lsedrv[1:0] = ?00?) typical current consumption the mcu is placed under the following conditions: ? v dd = 1.8 v, v dda = 3.3 v ? all i/o pins available on each packag e are in analog input configuration ? the flash access time is adjusted to f hclk frequency (0 wait states from 0 to 24 mhz, 1 wait state from 24 to 48 mhz and 2 wait states from 48 mhz to 72 mhz), and flash prefetch is on ? when the peripherals are enabled, f apb1 = f ahb/2 , f apb2 = f ahb ? pll is used for frequencies greater than 8 mhz ? ahb prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 mhz, 2 mhz, 1 mhz, 500 khz and 125 khz respectively. ? # ? # ? # ? # 6 6 6 6 6 6 6 6 4 ! ? # ? ! ) 6 " ! 4 - 3 6 docid025540 rev 4 63/134 STM32F358XC electrical characteristics 118 table 33. typical current consumption in run mode, code with data processing running from flash symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in run mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash 72 mhz 58.6 26.5 ma 64 mhz 52.6 23.7 48 mhz 40.6 18.5 32 mhz 27.6 12.7 24 mhz 21.1 9.9 16 mhz 14.3 6.8 8 mhz 7.2 3.5 4 mhz 4.1 2.1 2 mhz 2.3 1.3 1 mhz 1.5 0.9 500 khz 1.0 0.7 125 khz 0.7 0.5 i dda (1) (2) supply current in run mode from v dda supply 72 mhz 239.0 a 64 mhz 210.3 48 mhz 157.0 32 mhz 108.1 24 mhz 84.4 16 mhz 60.8 8 mhz 1.0 4 mhz 1.0 2 mhz 1.0 1 mhz 1.0 500 khz 1.0 125 khz 1.0 1. v dda monitoring is on. 2. when peripherals are enabled, the power consumption of the analog part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tabl es of characteristics in the subsequent sections. electrical characteristics STM32F358XC 64/134 docid025540 rev 4 table 34. typical current consumption in sleep mode, code running from flash or ram symbol parameter conditions f hclk typ unit peripherals enabled peripherals disabled i dd supply current in sleep mode from v dd supply running from hse crystal clock 8 mhz, code executing from flash or ram 72 mhz 42.5 6.5 ma 64 mhz 38.0 5.8 48 mhz 28.8 4.4 32 mhz 19.4 3.0 24 mhz 14.6 2.3 16 mhz 9.8 1.6 8 mhz 4.8 0.8 4 mhz 2.9 0.6 2 mhz 1.7 0.5 1 mhz 1.2 0.5 500 khz 0.9 0.5 125 khz 0.7 0.5 i dda (1) (2) supply current in sleep mode from v dda supply 72 mhz 239.0 a 64 mhz 210.3 48 mhz 157.0 32 mhz 108.1 24 mhz 84.4 16 mhz 60.8 8 mhz 1.0 4 mhz 1.0 2 mhz 1.0 1 mhz 1.0 500 khz 1.0 125 khz 1.0 1. v dda monitoring is on 2. when peripherals are enabled, the power consumption of the analog part of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tabl es of characteristics in the subsequent sections. docid025540 rev 4 65/134 STM32F358XC electrical characteristics 118 i/o system current consumption the current consumption of the i/o system has two components: static and dynamic. i/o static current consumption all the i/os used as inputs with pull-up ge nerate current consumpt ion when the pin is externally held low. the value of this current consumption can be simply computed by using the pull-up/pull-down resi stors values given in table 52: i/o static characteristics . for the output pins, any external pull-down or external load must also be considered to estimate the current consumption. additional i/o current consumption is due to i/os configured as inputs if an intermediate voltage level is externally applie d. this current consumption is caused by the input schmitt trigger circuits used to discriminate the input va lue. unless this spec ific configuration is required by the application, this supply curr ent consumption can be avoided by configuring these i/os in analog mode. this is notably the case of adc input pins which should be configured as analog inputs. caution: any floating input pin can also settle to an in termediate voltage level or switch inadvertently, as a result of external electromagnetic nois e. to avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. this can be done either by usin g pull-up/down resistors or by configuring the pins in output mode. i/o dynamic current consumption in addition to the internal peripheral current consumption (see table 36: peripheral current consumption ), the i/os used by an application also contribute to the current consumption. when an i/o pin switches, it uses the current from the mcu supply voltage to supply the i/o pin circuitry and to charge/discharge the capaci tive load (internal or external) connected to the pin: where i sw is the current sunk by a switching i/ o to charge/discharge the capacitive load v dd is the mcu supply voltage f sw is the i/o switching frequency c is the total capacitance seen by the i/o pin: c = c int + c ext +c s the test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. i sw v dd f sw c = electrical characteristics STM32F358XC 66/134 docid025540 rev 4 table 35. switching output i/o current consumption symbol parameter conditions (1) 1. cs = 5 pf (estimated value). i/o toggling frequency (f sw ) typ unit i sw i/o current consumption v dd = 1.8 v c ext = 0 pf c = c int + c ext + c s 2 mhz 0.10 ma 4 mhz 0.17 8 mhz 0.40 18 mhz 0.78 36 mhz 1.51 48 mhz 2.06 v dd = 1.8 v c ext = 10 pf c = c int + c ext +c s 2 mhz 0.14 4 mhz 0.25 8 mhz 0.57 18 mhz 1.16 36 mhz 2.45 48 mhz 3.03 v dd = 1.8 v c ext = 22 pf c = c int + c ext +c s 2 mhz 0.19 4 mhz 0.36 8 mhz 0.75 18 mhz 1.59 36 mhz 3.25 v dd = 1.8 v c ext = 33 pf c = c int + c ext + c s 2 mhz 0.23 4 mhz 0.45 8 mhz 0.94 18 mhz 1.97 36 mhz 3.62 v dd = 1.8 v c ext = 47 pf c = c int + c ext + c s 2 mhz 0.28 4 mhz 0.55 8 mhz 1.15 18 mhz 2.42 docid025540 rev 4 67/134 STM32F358XC electrical characteristics 118 on-chip peripheral current consumption the mcu is placed under the following conditions: ? all i/o pins are in analog input configuration ? all peripherals are disabled unless otherwise mentioned ? the given value is calculated by measuring the current consumption ? with all peripherals clocked off ? with only one peripheral clocked on ? ambient operating temperature at 25c and v dd = 1.8 v, v dda = 3.3 v. table 36. peripheral current consumption peripheral typical consumption (1) unit i dd busmatrix (2) 12.6 a/mhz dma1 7.6 dma2 6.1 crc 2.1 gpioa 10.0 gpiob 10.3 gpioc 2.2 gpiod 8.8 gpioe 3.3 gpiof 3.0 tsc 5.5 adc1&2 17.3 adc3&4 18.8 apb2-bridge (3) 3.6 syscfg 7.3 tim1 40.0 spi1 8.8 tim8 36.4 usart1 23.3 tim15 17.1 tim16 10.1 tim17 11.0 apb1-bridge (3) 6.1 tim2 49.1 tim3 38.8 tim4 38.3 electrical characteristics STM32F358XC 68/134 docid025540 rev 4 tim6 9.7 a/mhz tim7 12.1 wwdg 6.4 spi2 40.4 spi3 40.0 usart2 41.9 usart3 40.2 uart4 36.5 uart5 30.8 i2c1 10.5 i2c2 10.4 can 33.4 pwr 5.7 dac 15.4 1. the power consumption of the analog part (i dda ) of peripherals such as adc, dac, comparators, opamp etc. is not included. refer to the tables of characteristics in the subsequent sections. 2. busmatrix is automatically active when at least one master is on (cpu, dma1 or dma2). 3. the apbx bridge is automatically active when at least one peripheral is on on the same bus. table 36. peripheral current consumption (continued) peripheral typical consumption (1) unit i dd docid025540 rev 4 69/134 STM32F358XC electrical characteristics 118 6.3.5 wakeup time from low-power mode the wakeup times given in table 37 are measured starting from the wakeup event trigger up to the first instruction executed by the cpu: ? for stop or sleep mode: the wakeup event is wfe. ? wkup1 (pa0) pin is used to wakeup from stop and sleep modes. all timings are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 24 . table 37. low-power mode wakeup timings symbol parameter typ @v dd = 1.8 v, v dda = 3.3v max unit t wustop wakeup from stop mode 3.8 5.3 s t wusleep wakeup from sleep mode 6 - cpu clock cycles t wupor wakeup from power off state 69.2 100 s electrical characteristics STM32F358XC 70/134 docid025540 rev 4 6.3.6 external clock source characteristics high-speed external user clock generated from an external source in bypass mode the hse oscillato r is switched off and the inpu t pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.13 . however, the recommended clock input waveform is shown in figure 13 . figure 13. high-speed external clock source ac timing diagram table 38. high-speed external user clock characteristics symbol parameter condi tions min typ max unit f hse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - 1832mhz v hseh osc_in input pin high level voltage 0.7v dd -v dd v v hsel osc_in input pin low level voltage v ss -0.3v dd t w(hseh) t w(hsel) osc_in high or low time (1) 15 - - ns t r(hse) t f(hse) osc_in rise or fall time (1) --20 0 6 9 9 + 6 ( + w i + 6 ( 7 + 6 ( w w u + 6 ( 9 + 6 ( / w z + 6 ( + w z + 6 ( / docid025540 rev 4 71/134 STM32F358XC electrical characteristics 118 low-speed external user clock generated from an external source in bypass mode the lse oscillator is switched off and the input pin is a standard gpio. the external clock signal has to re spect the i/o characteristics in section 6.3.13 . however, the recommended clock input waveform is shown in figure 14 figure 14. low-speed external clock source ac timing diagram table 39. low-speed external user clock characteristics symbol parameter conditions min typ max unit f lse_ext user external clock source frequency (1) 1. guaranteed by design, not tested in production. - - 32.768 1000 khz v lseh osc32_in input pin high level voltage 0.7v dd -v dd v v lsel osc32_in input pin low level voltage v ss -0.3v dd t w(lseh) t w(lsel) osc32_in high or low time (1) 450 - - ns t r(lse) t f(lse) osc32_in rise or fall time (1) --50 0 6 9 9 / 6 ( + w i / 6 ( 7 / 6 ( w w u / 6 ( 9 / 6 ( / w z / 6 ( + w z / 6 ( / electrical characteristics STM32F358XC 72/134 docid025540 rev 4 high-speed external clock generated from a crystal/ceramic resonator the high-speed external (hse) clock can be supplied with a 4 to 32 mhz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 40 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). table 40. hse oscillator characteristics symbol parameter conditions (1) 1. resonator characteristics given by the crystal/ceramic resonator manufacturer. min (2) 2. guaranteed by design, not tested in production. typ max (2) unit f osc_in oscillator frequency 4 8 32 mhz r f feedback resistor - 200 k i dd hse current consumption during startup (3) 3. this consumption level occurs during the first 2/3 of the t su(hse) startup time. --8.5 ma v dd =3.3 v, rm= 30 , cl=10 pf@8 mhz -0.4- v dd =3.3 v, rm= 45 , cl=10 pf@8 mhz -0.5- v dd =3.3 v, rm= 30 , cl=5 pf@32 mhz -0.8- v dd =3.3 v, rm= 30 , cl=10 pf@32 mhz -1- v dd =3.3 v, rm= 30 , cl=20 pf@32 mhz -1.5- g m oscillator transconductance startup 10 - - ma/v t su(hse) (4) 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a standard crystal res onator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 2 - ms docid025540 rev 4 73/134 STM32F358XC electrical characteristics 118 for c l1 and c l2 , it is recommended to use high-quality external ceramic capacitors in the 5 pf to 25 pf range (typ.), designed for high-freque ncy applications, and selected to match the requirements of the crystal or resonator (see figure 15 ). c l1 and c l2 are usually the same size. the crystal manufacturer typically specifies a load capacitance which is the series combination of c l1 and c l2 . pcb and mcu pin capacitance must be included (10 pf can be used as a rough estimate of the comb ined pin and board capacitance) when sizing c l1 and c l2 . note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . figure 15. typical application with an 8 mhz crystal 1. r ext value depends on the cr ystal characteristics. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 5 ) % l d v f r q w u r o o h g j d l q i + 6 ( 5 ( ; 7 0 + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics STM32F358XC 74/134 docid025540 rev 4 low-speed external clock generated from a crystal/ceramic resonator the low-speed external (lse) clock can be supplied with a 32.768 khz crystal/ceramic resonator oscillator. all the information given in this pa ragraph are bas ed on design simulation results obtained with typical external components specified in table 41 . in the application, the resonator and the load capacito rs have to be placed as close as possible to the oscillator pins in order to minimize outpu t distortion and startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, pack age, accuracy). note: for information on selecting the crystal, refer to the application note an2867 ?oscillator design guide for st microcontrollers? available from the st website www.st.com . table 41. lse oscillator characteristics (f lse = 32.768 khz) symbol parameter conditions (1) min (2) typ max (2) unit i dd lse current consumption lsedrv[1:0]=00 lower driving capability -0.50.9 a lsedrv[1:0]=01 medium low driving capability --1 lsedrv[1:0]=10 medium high driving capability --1.3 lsedrv[1:0]=11 higher driving capability --1.6 g m oscillator transconductance lsedrv[1:0]=00 lower driving capability 5- - a/v lsedrv[1:0]=01 medium low driving capability 8- - lsedrv[1:0]=10 medium high driving capability 15 - - lsedrv[1:0]=11 higher driving capability 25 - - t su(lse) (3) startup time v dd is stabilized - 2 - s 1. refer to the note and caution paragraphs below the table, and to the application note an2867 ?oscillator design guide for st microcontrollers?. 2. guaranteed by design, not tested in production. 3. t su(lse) is the startup time measured from the moment it is ena bled (by software) to a stabili zed 32.768 khz oscillation is reached. this value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. docid025540 rev 4 75/134 STM32F358XC electrical characteristics 118 figure 16. typical applicati on with a 32.768 khz crystal note: an external resistor is not required between osc32_in and osc32_out and it is forbidden to add one. 0 6 9 2 6 & b , 1 2 6 & b 2 8 7 ' u l y h s u r j u d p p d e o h d p s o l i l h u i + 6 ( n + ] u h v r q d w r u 5 h v r q d w r u z l w k l q w h j u d w h g f d s d f l w r u v & / & / electrical characteristics STM32F358XC 76/134 docid025540 rev 4 6.3.7 internal clock source characteristics the parameters given in table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24 . high-speed internal (hsi) rc oscillator figure 17. hsi oscillator accuracy characterization results for soldered parts table 42. hsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter conditions min typ max unit f hsi frequency - - 8 - mhz trim hsi user trimming step - - - 1 (2) 2. guaranteed by design, not tested in production. % ducy (hsi) duty cycle - 45 (2) -55 (2) % acc hsi accuracy of the hsi oscillator t a = -40 to 105c -2.8 (3) 3. data based on characterization results, not tested in production. -3.8 (3) % t a = -10 to 85c -1.9 (3) -2.3 (3) t a = 0 to 85c -1.9 (3) -2 (3) t a = 0 to 70c -1.3 (3) -2 (3) t a = 0 to 55c -1 (3) -2 (3) t a = 25c (4) 4. factory calibrated, parts not soldered. -1 - 1 t su(hsi) hsi oscillator startup time - 1 (2) -2 (2) s i dda(hsi) hsi oscillator power consumption - - 80 100 (2) a 0 6 9 5 < ? $ > " . " 9 . * / docid025540 rev 4 77/134 STM32F358XC electrical characteristics 118 low-speed internal (lsi) rc oscillator 6.3.8 pll characteristics the parameters given in table 44 are derived from tests performed under ambient temperature and supply voltage conditions summarized in table 24 . table 43. lsi oscillator characteristics (1) 1. v dda = 3.3 v, t a = ?40 to 105 c unless otherwise specified. symbol parameter min typ max unit f lsi frequency 30 40 50 khz t su(lsi) (2) 2. guaranteed by design, not tested in production. lsi oscillator startup time - - 85 s i dd(lsi) (2) lsi oscillator power consumption - 0.75 1.2 a table 44. pll characteristics symbol parameter value unit min typ max f pll_in pll input clock (1) 1. take care of using the appropriate multiplier factors so as to have pll input clock values compatible with the range defined by f pll_out . 1 (2) -24 (2) mhz pll input clock duty cycle 40 (2) -60 (2) % f pll_out pll multiplier output clock 16 (2) -72mhz t lock pll lock time - - 200 (2) s jitter cycle-to-cycle jitter - - 300 (2) 2. guaranteed by design, not tested in production. ps electrical characteristics STM32F358XC 78/134 docid025540 rev 4 6.3.9 memory characteristics flash memory the characteristics are given at t a = ?40 to 105 c unless otherwise specified. table 45. flash memory characteristics symbol parameter conditions min typ max (1) 1. guaranteed by design, not tested in production. unit t prog 16-bit programming time t a = ?40 to +105 c 40 53.5 60 s t erase page (2 kb) erase time t a = ?40 to +105 c 20 - 40 ms t me mass erase time t a = ?40 to +105 c 20 - 40 ms i dd supply current write mode - - 10 ma erase mode - - 12 ma table 46. flash memory endurance and data retention symbol parameter conditions value unit min (1) 1. data based on characterization results, not tested in production. n end endurance t a = ?40 to +85 c (6 suffix versions) t a = ?40 to +105 c (7 suffix versions) 10 kcycles t ret data retention 1 kcycle (2) at t a = 85 c 2. cycling performed over the whole temperature range. 30 years 1 kcycle (2) at t a = 105 c 10 10 kcycles (2) at t a = 55 c 20 docid025540 rev 4 79/134 STM32F358XC electrical characteristics 118 6.3.10 emc characteristics susceptibility tests are perf ormed on a sample basis duri ng device characterization. functional ems (electromagnetic susceptibility) while a simple application is executed on t he device (toggling 2 leds through i/o ports). the device is stressed by two electromagnetic events until a failure o ccurs. the failure is indicated by the leds: ? electrostatic discharge (esd) (positive and negative) is applied to all device pins until a functional disturbance occurs. this test is compliant with the iec 61000-4-2 standard. ? ftb : a burst of fast transient voltage (positive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a func tional disturbance occurs. this test is compliant with the iec 61000-4-4 standard. a device reset allows normal operations to be resumed. the test results are given in table 47 . they are based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. software recommendations the software flowchart must include the m anagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) table 47. ems characteristics symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 1.8 v, lqfp100, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-2 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 1.8 v, lqfp100, t a = +25c, f hclk = 72 mhz conforms to iec 61000-4-4 4a electrical characteristics STM32F358XC 80/134 docid025540 rev 4 prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) the electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 leds through the i/o por ts). this emission test is compliant with iec 61967-2 standard which specifies the test board and the pin loading. 6.3.11 electrical sens itivity characteristics based on three different tests (esd, lu) using specific measurement methods, the device is stressed in order to determ ine its performance in terms of electrical sensitivity. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts (n+1) supply pins). this test conforms to the jesd22-a114/c101 standard. table 48. emi characteristics symbol parameter conditions monitored frequency band max vs. [f hse /f hclk ] unit 8/72 mhz s emi peak level v dd = 1.8 v, t a = 25 c, lqfp100 package compliant with iec 61967-2 0.1 to 30 mhz 7 dbv 30 to 130 mhz 16 130 mhz to 1ghz 23 sae emi level 4 - table 49. esd absolute maximum ratings symbol ratings conditions class maximum value (1) 1. data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c, conforming to jesd22-a114 22000 v v esd(cdm) electrostatic discharge voltage (charge device model) t a = +25 c, conforming to jesd22-c101 ii 500 docid025540 rev 4 81/134 STM32F358XC electrical characteristics 118 static latch-up two complementary static te sts are required on six pa rts to assess the latch-up performance: ? a supply overvoltage is applied to each power supply pin ? a current injection is applied to each input, output and configurable i/o pin these tests are compliant with eia/jesd 78a ic latch-up standard. 6.3.12 i/o current in jection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard, 3 v-capable i/o pins) should be avoided during normal product operation. however, in order to give an indica tion of the robustness of the microcontroller in cases when abnormal injection ac cidentally happens, susceptib ility tests are pe rformed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc error above a certain limit (higher than 5 lsb tue), out of conventional limits of induced leakage current on adjacent pins (out of ?5 a/+0 a range), or other functional failu re (for example reset occurrence or oscillator frequency deviation). the test results are given in table 51 table 50. electrical sensitivities symbol parameter conditions class lu static latch-up class t a = +105 c conforming to jesd78a ii level a electrical characteristics STM32F358XC 82/134 docid025540 rev 4 note: it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative currents. table 51. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on boot0 ? 0 na ma injected current on pc0, pc1, pc2, pc3, pf2, pa0, pa1, pa2, pa3, pf4, pa4, pa5, pa6, pa7, pc4, pc5 with induced leakage current on other pins from this group less than -50 a ? 5 - injected current on pb0, pb1, pe7, pe8, pe9, pe10, pe11, pe12, pe13, pe14, pe15, pb12, pb13, pb14, pb15, pd8, pd9, pd10, pd11 , pd12, pd13, pd14 with induced leakage current on other pins from this group less than -50 a ? 5 - injected current on pc0, pc1, pc2, pc3, pf2, pa0, pa1, pa2, pa3, pf4, pa4, pa5, pa6, pa7, pc4, pc5, pb0, pb1, pe7, pe8, pe9, pe 10, pe11, pe12, pe13, pe14, pe15, pb12, pb13, pb14, pb15, pd8, pd9, pd10, pd11, pd12, pd13, pd14 with induced leakage current on other pins from this group less than 400 a -+5 injected current on npor pin and on any other ft and ftf pins ? 5 na injected current on any other pins ? 5 +5 docid025540 rev 4 83/134 STM32F358XC electrical characteristics 118 6.3.13 i/o port characteristics general input/output characteristics unless otherwise specified, the parameters given in table 52 are derived from tests performed under the conditions summarized in table 24 . all i/os are cmos and ttl compliant. table 52. i/o static characteristics symbol parameter conditions min typ max unit v il low level input voltage tc and tta i/o - - 0.3 v dd +0.07 (1) v ft and ftf i/o - - 0.475 v dd -0.2 (1) boot0 - - 0.3 v dd ?0.3 (1) all i/os except boot0 - - 0.3 v dd (2) v ih high level input voltage tc and tta i/o 0.445 v dd +0.398 (1) -- ft and ftf i/o 0.5 v dd +0.2 (1) -- boot0 0.2 v dd +0.95 (1) -- all i/os except boot0 0.7 v dd (2) -- v hys schmitt trigger hysteresis tc and tta i/o - 200 (1) - mv ft and ftf i/o - 100 (1) - boot0 - 300 (1) - i lkg input leakage current (3) tc, ft, ftf and por i/o tta i/o in digital mode v ss v in v dd --0.1 a tta i/o in digital mode v dd v in v dda --1 tta i/o in analog mode v ss v in v dda --0.2 ft and ftf i/o (4) v dd v in 5 v --10 por v dda v in 5 v --10 r pu weak pull-up equivalent resistor (5) v in = v ss 25 40 55 k r pd weak pull-down equivalent resistor (5) v in = v dd 25 40 55 k c io i/o pin capacitance - - 5 - pf 1. data based on design simulation. 2. tested in production. 3. leakage could be higher than the maximum value. if n egative current is injected on adjacent pins. refer to table 51: i/o current injection susceptibility . 4. to sustain a voltage higher than v dd +0.3 v, the internal pull-up/pull-down resistors must be disabled. electrical characteristics STM32F358XC 84/134 docid025540 rev 4 all i/os are cmos and ttl compliant (no software configuration required). their characteristics cover more than the strict cmos-technology or ttl parameters. figure 18. tc and tta i/o input characteristics figure 19. five volt tolerant (ft and ftf) i/o input characteristics 5. pull-up and pull-down resistors are designed with a true re sistance in series with a switchable pmos/nmos. this pmos/nmos contribution to the series resistance is minimum (~10% order). 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v 0 6 9 9 ' ' 9 9 , + p l q 9 , / p d [ 9 , / 9 , + 9 & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , + p l q 9 ' ' 9 , / p d [ 9 ' ' & 0 2 6 v w d q g d u g u h t x l u h p h q w v 9 , / p d [ 9 ' ' 9 , + p l q 9 ' ' $ u h d q r w g h w h u p l q h g 7 h v w h g l q s u r g x f w l r q 7 h v w h g l q s u r g x f w l r q % d v h g r q g h v l j q v l p x o d w l r q v % d v h g r q g h v l j q v l p x o d w l r q v docid025540 rev 4 85/134 STM32F358XC electrical characteristics 118 output driving current the gpios (general purpose input/outputs) can sink or source up to +/-8 ma, and sink or source up to +/- 20 ma (with a relaxed v ol/ v oh ). in the user application, the number of i/o pi ns which can drive curr ent must be limited to respect the absolute maximum rating specified in section 6.2 : ? the sum of the currents sourced by all the i/os on v dd, plus the maximum run consumption of the mcu sourced on v dd, cannot exceed the absolute maximum rating i vdd (see table 22 ). ? the sum of the currents sunk by all the i/os on v ss plus the maximum run consumption of the mcu sunk on v ss cannot exceed the absolute maximum rating i vss (see table 22 ). output voltage levels unless otherwise specified, the parameters given in table 53 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 24 . all i/os (ft, tta and tc unless otherwise specified) are cmos and ttl compliant. table 53. output voltage characteristics symbol parameter conditions min max unit v ol (1) output low level voltage for an i/o pin i io = +4 ma 1.65 v < v dd < 1.95 v -0.4 v v oh (2) output high level voltage for an i/o pin i io = -4 ma 1.65 v < v dd < 1.95 v v dd ? 0.4 - v olfm+ (1)(3) output low level voltage for an ftf i/o pin in fm+ mode i io = +10 ma v dd = 1.65 v to 1.95 v -0.4 1. the i io current sunk by the device must always res pect the absolute maximum rating specified in table 22 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 2. the i io current sourced by the device must always re spect the absolute maximu m rating specified in table 22 and the sum of i io (i/o ports and control pins) must not exceed i io(pin) . 3. guaranted by design, not tested in production. electrical characteristics STM32F358XC 86/134 docid025540 rev 4 input/output ac characteristics the definition and values of input/output ac characteristics are given in figure 20 and table 54 , respectively. unless otherwise specified, th e parameters given are derived from tests performed under ambient temperature and v dd supply voltage condit ions summarized in table 24 . table 54. i/o ac characteristics (1) ospeedry [1:0] value (1) symbol parameter conditions min max unit x0 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 1.65 v to 1.95 v -1mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.65 v to 1.95 v - 125 (3) ns t r(io)out output low to high level rise time - 125 (3) 01 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 1.65 v to 1.95 v -4 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.65 v to 1.95 v - 62.5 (3) ns t r(io)out output low to high level rise time - 62.5 (3) 11 f max(io)out maximum frequency (2) c l = 50 pf, v dd = 1.65 v to 1.95 v -10 (3) mhz t f(io)out output high to low level fall time c l = 50 pf, v dd = 1.65 v to 1.95 v -25 (3) ns t r(io)out output low to high level rise time c l = 50 pf, v dd = 1.65 v to 1.95 v -25 (3) fm+ configuration (4) f max(io)out maximum frequency (2) c l = 50 pf, v dd = 1.65 v to 1.95 v -0.5 (4)(3) mhz t f(io)out output high to low level fall time -16 (4)(3) ns t r(io)out output low to high level rise time -44 (4)(3) -t extipw pulse width of external signals detected by the exti controller - 10 - ns 1. the i/o speed is configured using the ospeedrx[1:0] bits. refer to the rm0316 reference manual for a description of gpio port configuration register. 2. the maximum frequency is defined in figure 20 . 3. guaranteed by design, not tested in production. 4. the i/o speed configuration is bypassed in fm+ i/o mode. refer to the rm0316 stm32f303xx, STM32F358XC and stm32f328x4/6/8 reference manual (rm0316) for a description of fm+ i/o mode configuration. docid025540 rev 4 87/134 STM32F358XC electrical characteristics 118 figure 20. i/o ac charac teristics definition 6.3.14 nrst pin characteristics the nrst pin input driver uses cmos technology. it is connected to a permanent pull-up resistor, r pu (see table 52 ). unless otherwise specified, the parameters given in table 55 are derived from tests performed under ambient temperature and v dd supply voltage conditions summarized in table 24 . a i c t r ) / o u t / 5 4 0 5 4 % 8 4 % 2 . ! , / . p & - a x i m u m f r e q u e n c y i s a c h i e v e d i f t r t f ? 4 a n d i f t h e d u t y c y c l e i s w h e n l o a d e d b y p & 4 t f ) / o u t table 55. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) (1) nrst input low level voltage - - - 0.3v dd + 0.07 (1) v v ih(nrst) (1) nrst input high level voltage - 0.445v dd + 0.398 (1) -- v hys(nrst) nrst schmitt trigger voltage hysteresis - - 200 - mv r pu weak pull-up equivalent resistor (2) v in = v ss 25 40 55 k v f(nrst) (1) nrst input filtered pulse - - - 100 (1) ns v nf(nrst) (1) nrst input not filtered pulse - 700 (1) --ns 1. guaranteed by design, not tested in production. 2. the pull-up is designed with a true resistance in se ries with a switchable pmos. this pmos contribution to the series resistance must be minimum (~10% order) . electrical characteristics STM32F358XC 88/134 docid025540 rev 4 figure 21. recommended nrst pin protection 1. the reset network protects t he device against par asitic resets. 2. the user must ensure that the level on the nrst pin can go below the v il(nrst) max level specified in table 55 . otherwise the reset will not be taken into account by the device. 6.3.15 npor pin characteristics the npor pin input driver uses cmos technol ogy. it is connected to a permanent pull-up resistor, rpu (see table 56 ) connected to v dda supply. unless otherwise specified, the parameters given in table 56 are derived from tests performed under ambient temperature and v dda supply voltage conditions summarized in table 24 . table 56. npor pin characteristics 6.3.16 timer characteristics the parameters given in table 57 are guaranteed by design. refer to section 6.3.13: i/o port characteristics for details on the input/output alternate function characteristics (output compare, i nput capture, external clock, pwm output). 0 6 9 ( [ w h u q d o u h v h w f l u f x l w u \ 1 5 6 7 ? ) 9 ' ' 5 3 8 ) l o w h u , q w h u q d o u h v h w symbol (1) 1. guaranteed by design, not tested in production. parameter conditions min typ max unit v il(npor) npor input low level voltage - - - 0.475v dda - 0.2 v v ih(npor) npor input high level voltage - 0.5v dda + 0.2 -- v hys(npor) npor schmitt trigger voltage hysteresis --100-mv r pu weak pull-up equivalent resistor (2) 2. the pull-up is designed with a true resistance in series with a switchable pmos. this pmos contribution to the series resistance is minimal (~10% order). v in = v ss 25 40 55 k docid025540 rev 4 89/134 STM32F358XC electrical characteristics 118 table 57. timx (1)(2) characteristics 1. timx is used as a general term to refer to the tim1, tim2, tim3, tim4, tim6, tim15, tim16 and tim17 timers. 2. guaranteed by design, not tested in production. symbol parameter conditions min max unit t res(tim) timer resolution time -1- t timxclk f timxclk = 72 mhz 13.9 - ns f timxclk = 144 mhz, x= 1.8 6.95 - ns f ext timer external clock frequency on ch1 to ch4 -0 f timxclk /2 mhz f timxclk = 72 mhz 0 36 mhz res tim timer resolution timx (except tim2) - 16 bit tim2 - 32 t counter 16-bit counter clock period - 1 65536 t timxclk f timxclk = 72 mhz 0.0139 910 s f timxclk = 144 mhz, x= 1.8 0.0069 455 s t max_count maximum possible count with 32-bit counter - - 65536 65536 t timxclk f timxclk = 72 mhz - 59.65 s f timxclk = 144 mhz, x= 1.8 - 29.825 s electrical characteristics STM32F358XC 90/134 docid025540 rev 4 table 58. iwdg min/max timeout period at 40 khz (lsi) (1) 1. these timings are given for a 40 kh z clock but the microcontroller?s in ternal rc frequency can vary from 30 to 60 khz. moreover, given an exact rc oscillator frequency, the exact timings still depend on the phasing of the apb interface clock versus the lsi clock so t hat there is always a full rc period of uncertainty. prescaler divider pr[2:0] bits min timeout (ms) rl[11:0]= 0x000 max timeout (ms) rl[11:0]= 0xfff /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 table 59. wwdg min-max timeout value @72 mhz (pclk) (1) 1. guaranteed by design, not tested in production. prescaler wdgtb min timeout value max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 docid025540 rev 4 91/134 STM32F358XC electrical characteristics 118 6.3.17 communications interfaces i 2 c interface characteristics the i 2 c interface meets the requirements of the standard i 2 c communication protocol with the following restrictions: the i/o pins sda and scl are mapped to are not ?true? open- drain. when configured as open-drain, the pmos connected between the i/o pin and v dd is disabled, but is still present. the i 2 c characteristics are described in table 60 . refer also to section 6.3.13: i/o port characteristics for more details on the input/output al ternate function characteristics (sda and scl) . table 60. i2c timings specification (see i2c specification, rev.03, june 2007) (1) symbol parameter standard mode fast mode fast mode plus unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t low low period of the scl clock 4.7 - 1.3 - 0.5 - s t high high period of the scl clock 4 0.6 0.26 - s t r rise time of both sda and scl signals - 1000 - 300 - 120 ns t f fall time of both sda and scl signals - 300 - 300 - 120 ns t hd;dat data hold time 0 - 0 - 0 - s t vd;dat data valid time - 3.45 (2) -0.9 (2) -0.45 (2) s t vd;ack data valid acknowledge time - 3.45 (2) -0.9 (2) -0.45 (2) s t su;dat data setup time 250 - 100 - 50 - ns t hd:sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - s t su:sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 s t su:sto set-up time for stop condition 4.0 - 0.6 - 0.26 - s t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - s c b capacitive load for each bus line - 400 - 400 - 550 pf 1. the i2c characteristics are the requirements from i2c bus specification rev03. th ey are guaranteed by design when i2cx_timing register is correctly programmed (refer to t he reference manual). these char acteristics are not tested in production. 2. the maximum thd;dat could be 3.45 s , 0.9 s and 0.45 s for standard mode, fast mode and fast mode plus, but must be less than the maximum of tvd;dat or tvd;ack by a transition time. electrical characteristics STM32F358XC 92/134 docid025540 rev 4 figure 22. i 2 c bus ac waveforms and measurement circuit 1. rs: series protection resistors, rp: pu ll-up resistors, vdd_i2c: i2c bus supply . table 61. i2c analog filter characteristics (1) 1. guaranteed by design, not tested in production. symbol parameter min max unit t sp pulse width of spikes that are suppressed by the analog filter 50 260 ns 0 6 9 5 v , & e x v 5 s 5 v 9 ' ' b , & 0 & 8 6 ' $ 6 & / 5 s 9 ' ' b , & d p o u j o v f e d p o u j o v f e 4 % " 4 $ - 4 % " 4 $ - u g u g u s u s u 4 6 % " 5 u ) % % " 5 u ) * ( ) u 7 % % " 5 u g 4 $ - u - 0 8 u i d m p d l t u d m p d l d z d m f u 4 6 4 5 " u ) % 4 5 " u 4 1 u 7 % " $ , u 4 6 4 5 0 u # 6 ' u i d m p d l 4 s 4 1 4 ) % 4 5 " docid025540 rev 4 93/134 STM32F358XC electrical characteristics 118 spi/i 2 s characteristics unless otherwise specified, the parameters given in table 62 for spi or in table 63 for i 2 s are derived from tests performed under ambient temperature, f pclkx frequency and v dd supply voltage conditions summarized in table 24 . refer to section 6.3.13: i/o port characteristics for more details on the input/output alternate function characteristics (n ss, sck, mosi, miso for spi and ws, ck, sd for i 2 s). table 62. spi characteristics (1) symbol parameter conditions min typ max unit f sck 1/t c(sck) spi clock frequency master mode,spi1/2/3 -- 18 mhz slave mode,spi1/2/3 18 slave mode transmitter/full duplex spi1/2/3 12.5 (2) duty(sck) spi slave input clock duty cycle slave mode 30 50 70 % t su (nss) nss setup time slave mode, spi presc = 2 4*tpclk - - ns t h (nss) nss hold time slave mode spi presc = 2 2*tpclk - - t w (sckh) t w (sckl) sck high and low time master mode, f pclk = 36 mhz, presc = 4 tpclk-2 tpclk tpclk+2 t su (mi) t su (si) data input setup time master mode 5.5 - - slave mode 6.5 - - t h (mi) data input hold time master mode 5 - - t h (si) slave mode 5 - - t a (so) data output access time slave mode, f pclk = 24 mhz 0 - 4*tpclk t dis (so ) data output disable time slave mode 0 - 24 t v (so) data output valid time slave mode (after enable edge) - 25 39 t v (mo) data output valid time master mode (after enable edge) - 1.5 3 t h (so) data output hold time slave mode (after enable edge) 11 - - t h (mo) master mode (after enable edge) 0 - - 1. data based on characterization results, not tested in production. 2. maximum frequency in slave transmitter mode is determined by the sum of tv(so) and tsu(mi) which has to fit into sck low or high phase preceding the sck sampling edge. this va lue can be achieved when the spi communicates with a master having t su (mi) = 0 while duty(sck) = 50%. electrical characteristics STM32F358XC 94/134 docid025540 rev 4 figure 23. spi timing diagram - slave mode and cpha = 0 figure 24. spi timing diagram - slave mode and cpha = 1 (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. d l f ^ < /v?? w , a d k ^ / / e w h d d / ^ k k h d w h d w , a d ^ k h d d ^ / e / d k h d > ^ / e > ^ k h d w k >a w k >a / d / e e ^ ^ ]v?? ? ^ h~ e ^ ^ ?~ ^ < ?z~ e ^ ^ ?~ ^ k ?~ ^ < , ?~ ^ < > ?~ ^ k ?z~ ^ k ??~ ^ < ?(~ ^ < ?]?~ ^ k ??~ ^ / ?z~ ^ / d l 6 & . , q s x w & 3 + $ 0 2 6 , , 1 3 8 7 0 , 6 2 2 8 7 3 8 7 & 3 + $ 0 6 % 2 8 7 0 6 % , 1 % , 7 2 8 7 / 6 % , 1 / 6 % 2 8 7 & 3 2 / & 3 2 / % , 7 , 1 w 6 8 1 6 6 w f 6 & . w k 1 6 6 w d 6 2 w z 6 & . + w z 6 & . / w y 6 2 w k 6 2 w u 6 & . w i 6 & . w g l v 6 2 w v x 6 , w k 6 , 1 6 6 l q s x w docid025540 rev 4 95/134 STM32F358XC electrical characteristics 118 figure 25. spi timing diagram - master mode (1) 1. measurement points are done at 0.5v dd and with external c l = 30 pf. a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / table 63. i 2 s characteristics (1) symbol parameter conditions min max unit f ck 1/t c(ck) i 2 s clock frequency master data: 16 bits, audio freq=48 khz 1.496 1.503 mhz slave 0 12.288 t r(ck) t f(ck) i 2 s clock rise and fall time capacitive load c l = 30 pf -8 ns t w(ckh) i 2 s clock high time master f pclk = 36 mhz, audio frequency = 48 khz 331 - t w(ckl) i 2 s clock low time 332 - t v(ws) ws valid time master mode 4 - t h(ws) ws hold time master mode 4 - t su(ws) ws setup time slave mode 4 - t h(ws) ws hold time slave mode 0 - duty cycle i 2 s slave input clock duty cycle slave mode 30 70 % electrical characteristics STM32F358XC 96/134 docid025540 rev 4 figure 26. i 2 s slave timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. t su(sd_mr) data input setup ti me master receiver 9 - ns t su(sd_sr) data input setup time slave receiver 2 - t h(sd_mr) data input hold time master receiver 0 - t h(sd_sr) slave receiver 0 - t v(sd_st) data output valid time slave transmitter (after enable edge) -29 t h(sd_st) data output hold time slave transmitter (after enable edge) 12 - t v(sd_mt) data output valid time master transmitter (after enable edge) -3 t h(sd_mt) data output hold time master transmitter (after enable edge) 2- 1. data based on characterization results, not tested in production. table 63. i 2 s characteristics (1) (continued) symbol parameter conditions min max unit & . , q s x w & 3 2 / & 3 2 / w f & . : 6 l q s x w 6 ' w u d q v p l w 6 ' u h f h l y h w z & . + w z & . / w v x : 6 w y 6 ' b 6 7 w k 6 ' b 6 7 w k : 6 w v x 6 ' b 6 5 w k 6 ' b 6 5 0 6 % u h f h l y h % l w q u h f h l y h / 6 % u h f h l y h 0 6 % w u d q v p l w % l w q w u d q v p l w / 6 % w u d q v p l w d l e / 6 % u h f h l y h / 6 % w u d q v p l w docid025540 rev 4 97/134 STM32F358XC electrical characteristics 118 figure 27. i 2 s master timing diagram (philips protocol) (1) 1. measurement points are done at 0.5v dd and with external c l =30 pf. 2. lsb transmit/receive of the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. can (controller area network) interface refer to section 6.3.13: i/o port characteristics for more details on the input/output alternate function characteristics (can_tx and can_rx). # + o u t p u t # 0 / , # 0 / , t c # + 7 3 o u t p u t 3 $ r e c e i v e 3 $ t r a n s m i t t w # + ( t w # + , t s u 3 $ ? - 2 t v 3 $ ? - 4 t h 3 $ ? - 4 t h 7 3 t h 3 $ ? - 2 - 3 " r e c e i v e " i t n r e c e i v e , 3 " r e c e i v e - 3 " t r a n s m i t " i t n t r a n s m i t , 3 " t r a n s m i t a i b t f # + t r # + t v 7 3 , 3 " r e c e i v e , 3 " t r a n s m i t electrical characteristics STM32F358XC 98/134 docid025540 rev 4 6.3.18 adc characteristics unless otherwise specified, the parameters given in table 64 to table 67 are guaranteed by design, with conditio ns summarized in table 24 . table 64. adc characteristics symbol parameter conditions min typ max unit v dda analog supply voltage for adc -1.8-3.6v i dda adc current consumption on vdda pin (see figure 28 ) single-ended mode, 5 msps - 907 1033.0 a single-ended mode, 1 msps - 194 285.5 single-ended mode, 200 ksps -51.570 differential mode, 5 msps - 887. 5 1009 differential mode, 1 msps -212285 differential mode, 200 ksps -5169.5 v ref+ positive reference voltage -2-v dda v i ref adc current consumption on vref+ pin (see figure 29 ) single-ended mode, 5 msps -104139 a single-ended mode, 1 msps -20.437 single-ended mode, 200 ksps - 3.3 11.3 differential mode, 5 msps -174235 differential mode, 1 msps -34.652.6 differential mode, 200 ksps -613.6 f adc adc clock frequency 0.14 - 72 mhz f s (1) sampling rate resolution = 12 bits, fast channel 0.01 - 5.14 msps resolution = 10 bits, fast channel 0.012 - 6 resolution = 8 bits, fast channel 0.014 - 7.2 resolution = 6 bits, fast channel 0.0175 - 9 docid025540 rev 4 99/134 STM32F358XC electrical characteristics 118 f trig (1) external trigger frequency f adc = 72 mhz resolution = 12 bits - - 5.14 mhz resolution = 12 bits - - 14 1/f adc v ain conversion voltage range (2) -0-v ref+ v r ain (1) external input impedance ---100k c adc (1) internal sample and hold capacitor --5-pf t cal (1) calibration time f adc = 72 mhz 1.56 s - 112 1/f adc t latr (1) trigger conversion latency regular and injected channels without conversion abort ckmode = 00 1.5 2 2.5 1/f adc ckmode = 01 - - 2 1/f adc ckmode = 10 - - 2.25 1/f adc ckmode = 11 - - 2.125 1/f adc t latrinj (1) trigger conversion latency injected channels aborting a regular conversion ckmode = 00 2.5 3 3.5 1/f adc ckmode = 01 - - 3 1/f adc ckmode = 10 - - 3.25 1/f adc ckmode = 11 - - 3.125 1/f adc t s (1) sampling time f adc = 72 mhz 0.021 - 8.35 s - 1.5 - 601.5 1/f adc tadcvre g_stup (1 ) adc voltage regulator start-up time ---10s t conv (1) total conversion time (including sampling time) f adc = 72 mhz resolution = 12 bits 0.19 - 8.52 s resolution = 12 bits 14 to 614 (t s for sampling + 12.5 for successive approximation) 1/f adc 1. data guaranteed by design, not tested in production. 2. v ref+ can be internally connected to v dda and v ref- can be internally connected to v ssa , depending on the package. refer to section 4: pinouts and pin description for further details. table 64. adc characteristics (continued) symbol parameter conditions min typ max unit electrical characteristics STM32F358XC 100/134 docid025540 rev 4 figure 28. adc typical current consumption on vdda pin figure 29. adc typical curren t consumption on vref+ pin & o r f n i u h t x h q f \ 0 6 3 6 $ ' & f x u u h q w f r q v x p s w l r q ? $ 0 6 9 ' l i i h u h q w l d o p r g h 6 l q j o h h q g h g p r g h & o r f n i u h t x h q f \ 0 6 3 6 $ ' & f x u u h q w f r q v x p s w l r q ? $ 0 6 9 6 l q j o h h q g h g p r g h ' l i i h u h q w l d o p r g h docid025540 rev 4 101/134 STM32F358XC electrical characteristics 118 table 65. maximum adc r ain (1) resolution sampling cycle @ 72 mhz sampling time [ns] @ 72 mhz r ain max (k ) fast channels (2) slow channels other channels (3) 12 bits 1.5 20.83 0.018 na na 2.5 34.72 0.150 na 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 10 bits 1.5 20.83 0.082 na na 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 8 bits 1.5 20.83 0.150 na 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 6 bits 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. data based on characterization results, not tested in production . 2. all fast channels, expect channels on pa2, pa6, pb1, pb12. electrical characteristics STM32F358XC 102/134 docid025540 rev 4 3. channels available on pa2, pa6, pb1 and pb12. table 66. adc accuracy - limited test conditions 100-pin packages (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. 72 mhz sampling freq. 5 msps v dda = v ref+ = 3.3 v 25c 100-pin package single ended fast channel 5.1 ms - 3.5 4.5 lsb slow channel 4.8 ms - 4 4.5 differential fast channel 5.1 ms - 3 3 slow channel 4.8 ms - 3 3 eo offset error single ended fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 2.5 differential fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 eg gain error single ended fast channel 5.1 ms - 3 4 slow channel 4.8 ms - 3.5 4 differential fast channel 5.1 ms - 1.5 2.5 slow channel 4.8 ms - 2 2.5 ed differential linearity error single ended fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 differential fast channel 5.1 ms - 1 1 slow channel 4.8 ms - 1 1 el integral linearity error single ended fast channel 5.1 ms - 1.5 2 slow channel 4.8 ms - 1.5 3 differential fast channel 5.1 ms - 1 1.5 slow channel 4.8 ms - 1 1.5 enob effective number of bits single ended fast channel 5.1 ms 10.7 10.8 - bits slow channel 4.8 ms 10.7 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.1 11.3 - sinad signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - docid025540 rev 4 103/134 STM32F358XC electrical characteristics 118 snr signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = v ref+ = 3.3 v 25c 100-pin package single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd to ta l harmonic distortion single ended fast channel 5.1 ms - -76 -76 slow channel 4.8 ms - -76 -76 differential fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -80 -80 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins wh ich may potentially inject negative current. any positive injection current wi thin the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. data based on characterization re sults, not tested in production. table 66. adc accuracy - limited test conditions 100-pin packages (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit electrical characteristics STM32F358XC 104/134 docid025540 rev 4 table 67. adc accuracy, 100-pin packages (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 1.8v v dda , v ref+ 3.6 v 100-pin package single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 2 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2 enob effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.2 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - docid025540 rev 4 105/134 STM32F358XC electrical characteristics 118 sinad signal-to- noise and distortion ratio adc clock freq. 72 mhz, sampling freq. 5 msps, 1.8v v dda , v ref+ 3.6 v 100-pin package single ended fast channel 5.1 ms - 64 db slow channel 4.8 ms - 63 differential fast channel 5.1 ms - 67 slow channel 4.8 ms - 67 snr signal-to- noise ratio single ended fast channel 5.1 ms 64 - slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd to ta l harmonic distortion single ended fast channel 5.1 ms - -74 slow channel 4.8 ms - -74 differential fast channel 5.1 ms - -78 slow channel 4.8 ms - -76 1. adc dc accuracy values are meas ured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. table 67. adc accuracy, 100-pin packages (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit electrical characteristics STM32F358XC 106/134 docid025540 rev 4 table 68. adc accuracy - limited test conditions 64-pin packages (1)(2) symbol parameter conditions min (3) typ max (3) unit et to ta l unadjusted error adc clock freq. 72 mhz sampling freq. 5 msps v dda = v ref+ = 3.3 v 25c 64-pin package single ended fast channel 5.1 ms - 4.0 4.5 lsb slow channel 4.8 ms - 5.5 6.0 differential fast channel 5.1 ms - 3.5 4.0 slow channel 4.8 ms - 3.5 4.0 eo offset error single ended fast channel 5.1 ms - 2.0 2.0 slow channel 4.8 ms - 1.5 2.0 differential fast channel 5.1 ms - 1.5 2.0 slow channel 4.8 ms - 1.5 2.0 eg gain error single ended fast channel 5.1 ms - 3.0 4 . 0 slow channel 4.8 ms - 5.0 5.5 differential fast channel 5.1 ms - 3.0 3.0 slow channel 4.8 ms - 3.0 3.0 ed differential linearity error single ended fast channel 5.1 ms - 1.0 1.0 slow channel 4.8 ms - 1.0 1.0 differential fast channel 5.1 ms - 1.0 1.0 slow channel 4.8 ms - 1.0 1.0 el integral linearity error single ended fast channel 5.1 ms - 1.5 2.0 slow channel 4.8 ms - 2.0 3.0 differential fast channel 5.1 ms - 1.5 1.5 slow channel 4.8 ms - 1.5 2.0 enob (4) effective number of bits single ended fast channel 5.1 ms 10.8 10.8 - bits slow channel 4.8 ms 10.8 10.8 - differential fast channel 5.1 ms 11.2 11.3 - slow channel 4.8 ms 11.2 11.3 - sinad (4) signal-to- noise and distortion ratio single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - docid025540 rev 4 107/134 STM32F358XC electrical characteristics 118 snr (4) signal-to- noise ratio adc clock freq. 72 mhz sampling freq 5 msps v dda = v ref+ = 3.3 v 25c 100-pin package single ended fast channel 5.1 ms 66 67 - db slow channel 4.8 ms 66 67 - differential fast channel 5.1 ms 69 70 - slow channel 4.8 ms 69 70 - thd (4) to ta l harmonic distortion single ended fast channel 5.1 ms - -80 -80 slow channel 4.8 ms - -78 -77 differential fast channel 5.1 ms - -83 -82 slow channel 4.8 ms - -81 -80 1. adc dc accuracy values are meas ured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negative current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion bei ng performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. data based on characterization results, not tested in production. 4. value measured with a ?0.5db full scale 50khz sine wave input signal. table 68. adc accuracy - limited test conditions 64-pin packages (1)(2) (continued) symbol parameter conditions min (3) typ max (3) unit electrical characteristics STM32F358XC 108/134 docid025540 rev 4 table 69. adc accuracy, 64-pin packages (1)(2)(3) symbol parameter conditions min (4) max (4) unit et to ta l unadjusted error adc clock freq. 72 mhz, sampling freq. 5 msps 1.8v v dda , v ref+ 3.6 v 64-pin package single ended fast channel 5.1 ms - 6.5 lsb slow channel 4.8 ms - 6.5 differential fast channel 5.1 ms - 4 slow channel 4.8 ms - 4.5 eo offset error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3 differential fast channel 5.1 ms - 2.5 slow channel 4.8 ms - 2.5 eg gain error single ended fast channel 5.1 ms - 6 slow channel 4.8 ms - 6 differential fast channel 5.1 ms - 3.5 slow channel 4.8 ms - 4 ed differential linearity error single ended fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 differential fast channel 5.1 ms - 1.5 slow channel 4.8 ms - 1.5 el integral linearity error single ended fast channel 5.1 ms - 3 slow channel 4.8 ms - 3.5 differential fast channel 5.1 ms - 2 slow channel 4.8 ms - 2.5 enob effective number of bits single ended fast channel 5.1 ms 10.4 - bits slow channel 4.8 ms 10.4 - differential fast channel 5.1 ms 10.8 - slow channel 4.8 ms 10.8 - docid025540 rev 4 109/134 STM32F358XC electrical characteristics 118 sinad signal-to- noise and distortion ratio adc clock freq. 72 mhz, sampling freq. 5 msps, 1.8v v dda , v ref+ 3.6 v 64-pin package single ended fast channel 5.1 ms 64 - db slow channel 4.8 ms 63 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - snr signal-to- noise ratio single ended fast channel 5.1 ms 64 - slow channel 4.8 ms 64 - differential fast channel 5.1 ms 67 - slow channel 4.8 ms 67 - thd to ta l harmonic distortion single ended fast channel 5.1 ms - -75 slow channel 4.8 ms - -75 differential fast channel 5.1 ms - -79 slow channel 4.8 ms - -78 1. adc dc accuracy values are meas ured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negativ e current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current within the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. better performance may be achieved in restricted v dda , frequency and temperature ranges. 4. data based on characterization results, not tested in production. table 69. adc accuracy, 64-pin packages (1)(2)(3) (continued) symbol parameter conditions min (4) max (4) unit table 70. adc accuracy at 1msps (1)(2) symbol parameter conditions typ max (3) unit et total unadjusted error adc clock freq. 72 mhz, sampling freq. 1 msps 2.4v v dda , v ref+ 3.6 v single-ended mode fast channel 2.5 5 lsb slow channel 3 . 5 5 eo offset error fast channel 1 2.5 slow channel 1 . 5 2.5 eg gain error fast channel 2 3 slow channel 3 4 ed differential linearity error fast channel 0 . 7 2 slow channel 0 . 7 2 el integral linearity error fast channel 1 3 slow channel 1 . 2 3 1. adc dc accuracy values are measured after internal calibration. 2. adc accuracy vs. negative injection current: injecting negat ive current on any analog input pi ns should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. it is recommended to add a schottky diode (pin to ground) to analog pins which may potentially inject negative current. any positive injection current with in the limits specified for i inj(pin) and i inj(pin) in section 6.3.13 does not affect the adc accuracy. 3. data based on characterization results, not tested in production. electrical characteristics STM32F358XC 110/134 docid025540 rev 4 figure 30. adc accuracy characteristics figure 31. typical connecti on diagram using the adc 1. refer to table 64 for the values of r ain . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc should be reduced. general pcb design guidelines power supply decoupling should be performed as shown in figure 10 . the 10 nf capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. ( [ d p s o h r i d q d f w x d o w u d q v i h u f x u y h 7 k h l g h d o w u d q v i h u f x u y h ( q g s r l q w f r u u h o d w l r q o l q h d l h ( 7 7 r w d o x q d g m x v w h g ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q w k h d f w x d o d q g w k h l g h d o w u d q v i h u f x u y h v ( 2 2 i i v h w ( u u r u g h y l d w l r q e h w z h h q w k h i l u v w d f w x d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( * * d l q ( u u r u g h y l d w l r q e h w z h h q w k h o d v w l g h d o w u d q v l w l r q d q g w k h o d v w d f w x d o r q h ( ' ' l i i h u h q w l d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d f w x d o v w h s v d q g w k h l g h d o r q h ( / , q w h j u d o / l q h d u l w \ ( u u r u p d [ l p x p g h y l d w l r q e h w z h h q d q \ d f w x d o w u d q v l w l r q d q g w k h h q g s r l q w f r u u h o d w l r q o l q h 9 6 6 $ 9 ' ' $ / 6 % , ' ( $ / ( ' ( / ( 2 ( 7 ( * > / 6 % , ' ( $ / 9 5 ( ) 9 ' ' $ r u g h s h q g l q j r q s d f n d j h 0 6 9 9 ' ' $ , 1 [ , / ? ? $ 9 9 7 5 $ , 1 & s d u d v l w l f 9 $ , 1 9 9 7 5 $ ' & & $ ' & c j u d p o w f s u f s 4 b n q m f b o e i p m e " % $ d p o w f s u f s docid025540 rev 4 111/134 STM32F358XC electrical characteristics 118 6.3.19 dac electri cal specifications table 71. dac characteristics symbol parameter min typ max unit comments v dda analog supply voltage for dac on 2.4 - 3.6 v - r load (1) resistive load with buffer on 5 - - k - r o (1) impedance output with buffer off -- 15 k when the buffer is off, the minimum resistive load between dac_out and v ss to have a 1% accuracy is 1.5 m c load (1) capacitive load - - 50 pf maximum capacitive load at dac_out pin (when the buffer is on). dac_out min (1) lower dac_out voltage with buffer on 0.2 - - v it gives the maximum output excursion of the dac. it corresponds to 12-bit input code (0x0e0) to (0xf1c) at v dda = 3.6 v and (0x155) and (0xeab) at v dda = 2.4 v dac_out max (1) higher dac_out voltage with buffer on --v dda ? 0.2 v dac_out min (1) lower dac_out voltage with buffer off -0.5 - mv it gives the maximum output excursion of the dac. dac_out max (1) higher dac_out voltage with buffer off --v dda ? 1lsb v i dda (3) dac dc current consumption in quiescent mode (2) - - 380 a with no load, middle code (0x800) on the input - - 480 a with no load, worst code (0xf1c) on the input dnl (3) differential non linearity difference between two consecutive code-1lsb) - - 0.5 lsb given for a 10-bit input code - - 2 lsb given for a 12-bit input code inl (3) integral non linearity (difference between measured value at code i and the value at code i on a line drawn between code 0 and last code 1023) - - 1 lsb given for a 10-bit input code - - 4 lsb given for a 12-bit input code offset (3) offset error (difference between measured value at code (0x800) and the ideal value = v dda /2) -- 10mv - -- 3lsb given for a 10-bit input code at v dda = 3.6 v -- 12lsb given for a 12-bit input code at v dda = 3.6 v gain error (3) gain error - - 0.5 % given for a 12-bit input code electrical characteristics STM32F358XC 112/134 docid025540 rev 4 figure 32. 12-bit buffered /non-buffered dac 1. the dac integrates an output buffer that can be used to r educe the output impedance and to dr ive external loads directly without the use of an external operational amplifier. the buffer can be bypassed by configuring the boffx bit in the dac_cr register. t settling (3) settling time (full scale: for a 10-bit input code transition between the lowest and the highest input codes when dac_out reaches final value 1lsb -3 4 sc load 50 pf, r load 5 k update rate (3) max frequency for a correct dac_out change when small variation in the input code (from code i to i+1lsb) -- 1 ms/sc load 50 pf, r load 5 k t wakeup (3) wakeup time from off state (setting the enx bit in the dac control register) -6.5 10 s c load 50 pf, r load 5 k input code between lowest and highest possible ones. psrr+ (1) power supply rejection ratio (to v dda ) (static dc measurement - ?67 ?40 db no r load , c load = 50 pf 1. guaranteed by design, not tested in production. 2. quiescent mode refers to the state of the dac a keepi ng steady value on the output, so no dynamic consumption is involved. 3. data based on characterization results, not tested in production. table 71. dac characteristics (continued) symbol parameter min typ max unit comments 5 / & / % x i i h u h g 1 r q e x i i h u h g ' $ & ' $ & b 2 8 7 [ % x i i h u e l w g l j l w d o w r d q d o r j f r q y h u w h u a i 6 docid025540 rev 4 113/134 STM32F358XC electrical characteristics 118 6.3.20 comparator characteristics table 72. comparator characteristics (1) symbol parameter conditions min typ max unit v dda analog supply voltage v refint scaler not in use 1.65 - 3.6 v v refint scaler in use 2 - 3.6 v in comparator input voltage range -0-v dda v bg scaler input voltage - - 1.2 - v sc scaler offset voltage - - 5 10 mv t s_sc v refint scaler startup time from power down first v refint scaler activation after device power on --1 (2) s next activations - - 0.2 ms t start comparator startup time startup time to reach propagation delay specification - - 60 s t d propagation delay for 200 mv step with 100 mv overdrive ultra-low-power mode - 2 4.5 s low-power mode - 0.7 1.5 medium power mode - 0.3 0.6 high speed mode v dda 2.7 v - 50 100 ns v dda < 2.7 v - 100 240 propagation delay for full range step with 100 mv overdrive ultra-low-power mode - 2 7 s low-power mode - 0.7 2.1 medium power mode - 0.3 1.2 high speed mode v dda 2.7 v - 90 180 ns v dda < 2.7 v - 110 300 v offset comparator offset error - - 4 10 mv dv offset /dt offset error temperature coefficient --18- v/ c i dd(comp) comp current consumption ultra-low-power mode - 1.2 1.5 a low-power mode - 3 5 medium power mode - 10 15 high speed mode - 75 100 electrical characteristics STM32F358XC 114/134 docid025540 rev 4 figure 33. maximum v refint scaler startup time from power down v hys comparator hysteresis no hysteresis (compxhyst[1:0]=00) --0- mv low hysteresis (compxhyst[1:0]=01) high speed mode 3 8 13 all other power modes 510 medium hysteresis (compxhyst[1:0]=10) high speed mode 7 15 26 all other power modes 919 high hysteresis (compxhyst[1:0]=11) high speed mode 18 31 49 all other power modes 19 40 1. data based on characterization re sults, not tested in production. 2. for more details and conditions, see figure 33 maximum v refint scaler startup time from power down. table 72. comparator characteristics (1) (continued) symbol parameter conditions min typ max unit 0 6 9 docid025540 rev 4 115/134 STM32F358XC electrical characteristics 118 6.3.21 operational am plifier char acteristics table 73. operational amplifier characteristics (1) symbol parameter condition min typ max unit v dda analog supply voltage - 2.4 - 3.6 v cmir common mode input range - 0 - v dda v vi offset input offset voltage maximum calibration range 25c, no load on output. --4 mv all voltage/temp. --6 after offset calibration 25c, no load on output. --1.6 all voltage/temp. --3 vi offset input offset voltage drift - - 5 - v/c i load drive current - - - 500 a iddopamp consumption no load, quiescent mode - 690 1450 a cmrr common mode rejection ratio - - 90 - db psrr power supply rejection ratio dc 73 117 - db gbw bandwidth - - 8.2 - mhz sr slew rate - - 4.7 - v/s r load resistive load - 4 - - k c load capacitive load - - - 50 pf voh sat high saturation voltage r load = min, input at v dda . - - 100 mv r load = 20k, input at v dda . --20 vol sat low saturation voltage rload = min, input at 0v - - 100 rload = 20k, input at 0v. --20 ? m phase margin - - 62 - t offtrim offset trim time: during calibration, minimum time needed between two steps to have 1 mv accuracy ---2ms t wakeup wake up time from off state. c load 50 pf, r load 4 k , follower configuration -2.85s electrical characteristics STM32F358XC 116/134 docid025540 rev 4 pga gain non inverting gain value - -2-- -4-- -8-- -16-- r network r2/r1 internal resistance values in pga mode (2) gain=2 - 5.4/5.4 - k gain=4 - 16.2/5.4 - gain=8 - 37.8/5.4 - gain=16 - 40.5/2.7 - pga gain error pga gain error - -1% - 1% i bias opamp input bias current - - - 0.2 (3) a pga bw pga bandwidth for different non inverting gain pga gain = 2, cload = 50pf, rload = 4 k -4- mhz pga gain = 4, cload = 50pf, rload = 4 k -2- pga gain = 8, cload = 50pf, rload = 4 k -1- pga gain = 16, cload = 50pf, rload = 4 k -0.5- en voltage noise density @ 1khz, output loaded with 4 k -109- @ 10khz, output loaded with 4 k -43- 1. guaranteed by design, not tested in production. 2. r2 is the internal resistance between opamp output and opamp inverting input. r1 is the internal resistance between opamp inverting input and ground. the pga gain =1+r2/r1 3. mostly tta i/o leakage, when used in analog mode. table 73. operational amplifier characteristics (1) (continued) symbol parameter condition min typ max unit nv hz ----------- docid025540 rev 4 117/134 STM32F358XC electrical characteristics 118 figure 34. opamp voltage noise versus frequency electrical characteristics STM32F358XC 118/134 docid025540 rev 4 6.3.22 temperature sensor characteristics 6.3.23 v bat monitoring characteristics table 74. ts characteristics symbol parameter min typ max unit t l (1) 1. guaranteed by design, not tested in production. v sense linearity with temperature - 1 2c avg_slope (1) average slope 4.0 4.3 4.6 mv/c v 25 voltage at 25 c 1.34 1.43 1.52 v t start (1) startup time 4 - 10 s t s_temp (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the temperature 2.2 - - s table 75. temperature sensor calibration values calibration value name description memory address ts_cal1 ts adc raw data acquired at temperature of 30 c, v dda = 3.3 v 0x1fff f7b8 - 0x1fff f7b9 ts_cal2 ts adc raw data acquired at temperature of 110 c v dda = 3.3 v 0x1fff f7c2 - 0x1fff f7c3 table 76. v bat monitoring characteristics symbol parameter min typ max unit r resistor bridge for v bat -50-k q ratio on v bat measurement -2- er (1) 1. guaranteed by design, not tested in production. error on q -1 - +1 % t s_vbat (1)(2) 2. shortest sampling time can be determined in the application by multiple iterations. adc sampling time when reading the v bat 1mv accuracy 2.2 - - s docid025540 rev 4 119/134 STM32F358XC package information 131 7 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. 7.1 lqfp100 ? 14 x 14 mm, lo w-profile quad flat package information figure 35. lqfp100 ? 14 x 14 mm, low-profile quad flat package outline 1. drawing is not to scale. e ) $ % . 4 ) & ) # ! 4 ) / . 0 ) . ' ! 5 ' % 0 , ! . % m m 3 % ! 4 ) . ' 0 , ! . % $ $ $ % % % + c c c # # , ? - % ? 6 ! ! ! , , c b ! table 77. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.60 - - 0.063 a1 0.05 - 0.15 0.002 - 0.0059 package information STM32F358XC 120/134 docid025540 rev 4 figure 36. lqfp100 ? 14 x 14 mm, low-profile quad flat package recommended footprint 1. dimensions are in millimeters. a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.2 0.0035 - 0.0079 d 15.80 16.00 16.2 0.622 0.6299 0.6378 d1 13.80 14.00 14.2 0.5433 0.5512 0.5591 d3 - 12.00 - - 0.4724 - e 15.80 16.00 16.2 0.622 0.6299 0.6378 e1 13.80 14.00 14.2 0.5433 0.5512 0.5591 e3 - 12.00 - - 0.4724 - e - 0.50 - - 0.0197 - l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 - 1.00 - - 0.0394 - k 03.57 03.57 ccc - - 0.08 - - 0.0031 1. values in inches are converted fr om mm and rounded to 4 decimal digits. table 77. lqpf100 ? 14 x 14 mm, low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c docid025540 rev 4 121/134 STM32F358XC package information 131 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 37. lqfp100 ? 14 x 14 mm, low-prof ile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 ' d w h f r g h 3 l q l g h q w l i l h u 4 5 . ' 7 $ 5 3 3 u r g x f w l g h q w l i l f d w l r q 6 7 o r j r 5 h y l v l r q f r g h : 8 8 package information STM32F358XC 122/134 docid025540 rev 4 7.2 lqfp64 ? 10 x 10 mm, low- profile quad flat package information figure 38. lqfp64 ? 10 x 10 mm, low-profile quad flat package outline 1. drawing is not to scale. table 78. lqfp64 ? 10 x 10 mm, low- profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.60 - - 0.0630 a1 0.05 - 0.15 0.0020 - 0.0059 a2 1.350 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 0.0079 d - 12.00 - - 0.4724 - d1 - 10.00 - - 0.3937 - d3 - 7.50 - - 0.2953 - e - 12.00 - - 0.4724 - : b 0 ( b 9 $ $ $ 6 ( $ 7 , 1 * 3 / $ 1 ( f f f & e & f $ / / . , ' ( 1 7 , ) , & $ 7 , 2 1 3 , 1 ' ' ' h ( ( ( * $ 8 * ( 3 / $ 1 ( p p docid025540 rev 4 123/134 STM32F358XC package information 131 figure 39. lqfp64 ? 10 x 10 mm, low-profile quad flat package recommended footprint 1. dimensions are in millimeters. e1 - 10.00 - - 0.3937 - e3 - 7.50 - - 0.2953 - e - 0.50 - - 0.0197 - k 03.57 03.57 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 - 1.00 - - 0.0394 - ccc - - 0.08 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 78. lqfp64 ? 10 x 10 mm, low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i c package information STM32F358XC 124/134 docid025540 rev 4 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 40. lqfp64 ? 10 x 10 mm, low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 y 9 5 h y l v l r q f r g h 6 7 0 3 u r g x f w l g h q w l i l f d w l r q ' d w h f r g h < : : % d o o l q g h q w l i l h u 5 & 7 5 docid025540 rev 4 125/134 STM32F358XC package information 131 7.3 lqfp48 ? 7 x 7 mm, low- profile quad flat package information figure 41. lqfp48 ? 7 x 7 mm, low-profile quad flat package outline 1. drawing is not to scale. table 79. lqfp48 ? 7 x 7 mm, low-prof ile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a - - 1.60 - - 0.0630 a1 0.05 - 0.15 0.0020 - 0.0059 a2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 - 0.0079 d 8.80 9.00 9.20 0.3465 0.3543 0.3622 d1 6.80 7.00 7.20 0.2677 0.2756 0.2835 d3 - 5.50 - - 0.2165 - e 8.80 9.00 9.20 0.3465 0.3543 0.3622 " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information STM32F358XC 126/134 docid025540 rev 4 figure 42. lqfp48 - 7 x 7 mm, low-profile quad flat package recommended footprint 1. dimensions are in millimeters. e1 6.80 7.00 7.20 0.2677 0.2756 0.2835 e3 - 5.50 - - 0.2165 - e - 0.50 - - 0.0197 - l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 - 1.00 - - 0.0394 - k 03.57 03.57 ccc - - 0.08 - - 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits. table 79. lqfp48 ? 7 x 7 mm, low-profile quad flat package mechanical data (continued) symbol millimeters inches (1) min typ max min typ max a i d docid025540 rev 4 127/134 STM32F358XC package information 131 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. figure 43. lqfp48 - 7 x 7 mm, low-profile quad flat package top view example 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 3 u r g x f w l g h q w l i l f d w l r q 4 5 . ' $ $ 5 3 : 8 8 3 l q l g h q w l i l f d w l r q 5 h y l v l r q f r g h ' d w h f r g h 0 6 9 package information STM32F358XC 128/134 docid025540 rev 4 7.4 thermal characteristics the maximum chip junction temperature (t j max) must never exceed the values given in table 24: general operating conditions on page 56 . the maximum chip-junction temperature, t j max, in degrees celsius, may be calculated using the following equation: t j max = t a max + (p d max x ja ) where: ? t a max is the maximum ambient temperature in c, ? ja is the package junction-to-ambient thermal resistance, in c/w, ? p d max is the sum of p int max and p i/o max (p d max = p int max + p i/o max), ? p int max is the product of i dd and v dd , expressed in watts. th is is the maximum chip internal power. p i/o max represents the maximum power dissipation on output pins where: p i/o max = (v ol i ol ) + ((v dd ? v oh ) i oh ), taking into account the actual v ol / i ol and v oh / i oh of the i/os at low and high level in the application. 7.4.1 reference document jesd51-2 integrated circuits thermal test method environment conditions - natural convection (still air). available from www.jedec.org table 80. package thermal characteristics symbol parameter value unit ja thermal resistance junction-ambient lqfp64 - 10 10 mm / 0.5 mm pitch 45 c/w thermal resistance junction-ambient lqfp48 - 7 7 mm 55 thermal resistance junction-ambient lqfp100 - 14 14 mm / 0.5 mm pitch 41 docid025540 rev 4 129/134 STM32F358XC package information 131 7.4.2 selecting the product temperature range when ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in section 8: part numbering . each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a spec ific maximum junction temperature. as applications do not commonly use the STM32F358XC devices at the maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temper ature range will be best su ited to the application. the following examples show how to calculat e the temperature range needed for a given application. example 1: high-performance application assuming the following ap plication conditions: maximum ambient temperature t amax = 82 c (measured according to jesd51-2), i ddmax = 50 ma, v dd = 3.5 v, maximum 3 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v and maximum 2 i/os used at the same time in output at low level with i ol = 20 ma, v ol = 1.3 v p intmax = 50 ma 3.5 v= 175 mw p iomax = 3 8 ma 0.4 v + 2 20 ma 1.3 v = 61.6 mw this gives: p intmax = 175 mw and p iomax = 61.6 mw: p dmax = 175 + 61.6 = 236.6 mw thus: p dmax = 236.6 mw using the values obtained in table 80 t jmax is calculated as follows: ? for lqfp64, 45c/w t jmax = 82 c + (45c/w 236.6 mw) = 82 c + 10.65 c = 92.65 c this is within the range of the suffix 6 version parts (?40 < t j < 105 c). in this case, parts must be ordered at leas t with the temperature range suffix 6 (see section 8: part numbering ). package information STM32F358XC 130/134 docid025540 rev 4 example 2: high-temperature application using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature t j remains within the specified range. assuming the following ap plication conditions: maximum ambient temperature t amax = 115 c (measured according to jesd51-2), i ddmax = 20 ma, v dd = 3.5 v, maximum 9 i/os used at the same time in output at low level with i ol = 8 ma, v ol = 0.4 v p intmax = 20 ma 3.5 v= 70 mw p iomax = 9 8 ma 0.4 v = 28.8 mw this gives: p intmax = 70 mw and p iomax = 28.8 mw: p dmax = 70 + 28.8 = 98.8 mw thus: p dmax = 98.8 mw using the values obtained in table 80 t jmax is calculated as follows: ? for lqfp100, 41c/w t jmax = 115 c + (41c/w 98.8 mw) = 115 c + 4.05 c = 119.05 c this is within the range of the suffix 7 version parts (?40 < t j < 125 c). in this case, parts must be ordered at leas t with the temperature range suffix 7 (see section 8: part numbering ). docid025540 rev 4 131/134 STM32F358XC part numbering 131 8 part numbering for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 81. ordering information scheme example: stm32 f 358 r c t 6 xxx device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose device subfamily 358 = stm32f358 pin count c = 48 pins r = 64 pins v = 100 pins flash memory size c = 256 kbytes of flash memory package t = lqfp temperature range 6 = industrial temperature range, ?40 to 85 c 7 = industrial temperature range, ?40 to 105 c options xxx = programmed parts tr = tape and reel revision history STM32F358XC 132/134 docid025540 rev 4 9 revision history table 82. document revision history date revision changes 17-apr-2014 1 initial release. 10-dec-2014 2 updated core description in cover page. updated figure 1: STM32F358XC block diagram . updated hsi characteristics table 42: hsi oscillator characteristics and figure 17: hsi oscillator accuracy characterization results for soldered parts . updated table 29: typical and maximum current consumption from the vdda supply . updated table 51: i/o current injection susceptibility adding ?on npor pin?. updated table 37: low-power mode wakeup timings . updated figure 18: tc and tta i/o input characteristics and figure 19: five volt tolerant (ft and ftf) i/o input characteristics . updated table 13: STM32F358XC pin definitions adding note for i/os featuring an analog output f unction (dac_out,opamp_out). updated table 64: adc characteristics adding idda & iref consumptions. added figure 28: adc typical current consumption on vdda pin and figure 29: adc typical current consumption on vref+ pin . added section 3.8: interconnect matrix . updated section 6.3.5: wakeup time from low-power mode removing standby mode. added note for table 31: typical and maximum vdda consumption in stop mode and table 30: typical and maximum vdd consumption in stop mode . updated section 7: package information with new lqfp100, lqfp64, lqfp48 package markings. updated table 13: STM32F358XC pin definitions and alternate functions tables replacing usart_rts by usart_rts_de. docid025540 rev 4 133/134 STM32F358XC revision history 133 30-jan-2015 3 updated section 6.3.20: comparator characteristics modifying ts_sc, v dda characteristics in table 76 and adding figure 36: maximum vrefint scaler startup time from power down . updated i dd data current consumption in table 40: hse oscillator characteristics . 17-apr-2015 4 updated table 36: peripheral current consumption with 12.6ua/mhz- busmatrix, 7.6ua/mhz-dma1, 6.1u a/mhz-dma2 new current values. updated section 7: package information : with new package information structure adding 1 sub paragraph for each package. updated figure 40: lqfp100 ? 14 x 14 mm, low-profile quad flat package top view example removing gate mark. added note for all package device markings: ?the following figure gives an example of topside marking ori entation versus pin 1 identifier location?. updated table 82: lqfp64 ? 10 x 10 mm, low-profile quad flat package mechanical data . table 82. document revision history (continued) date revision changes STM32F358XC 134/134 docid025540 rev 4 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics ? all rights reserved |
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