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0.1 ghz to 6.0 ghz, 0.5 db lsb , 6 - bit, silicon digital attenuator data sheet HMC1122 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed b y analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2016 analog devices, inc. al l rights reserved. technical support www.analog.com features attenuation range: 0.5 db lsb steps to 31.5 db low insertion loss 1.1 db at 1 ghz 1. 3 db at 2 ghz typical step error: less than 0.1 db excellent attenuation accuracy safe state transitions high linearity input 0.1db compression (p0.1db): 30 dbm typical input third - order intercept (ip3) : 55 dbm typical rf settling time (0.05 db final rf out put ) : 250 ns low phase shift error: 6 at 1 ghz single supply operation: 3.3 v to 5 v esd rating: class 2 (2 kv hbm) 24 - lead , 4 mm 4 mm lfcsp package: 16 mm 2 pin compatible to the hmc624a applications cellular infrastructure microwave radios and very small aperture terminals ( vsats) test equipment and sensors if and rf designs functional block dia gram figure 1. general description the HMC1122 is a 6 - bit digital attenuator opera ting from 0.1 g hz to 6 g hz with a 31.5 db attenuation control range in 0.5 db steps. the HMC1122 is implemented in a silicon process , offering very fast settling time, low power consumption, and high esd robustness . the device features safe state transitions and optimized for excellent step accuracy and high linearity over frequency and temper ature range. the rf input and output are internally matched to 50 and do not require any external matching components. the design is bidirectional; therefore, the rf input and output are interchangeable. the HMC1122 operates on a single supply ranging from 3.3 v to 5 v with no performance change due to an on - chip regulator. the device incorporate s a driver t hat provides both serial and parallel control of the attenuator . the device also featur es a user - selectable power - up state and a serial output port for cascading other serial controlled components. the HMC1122 comes in a rohs compliant, compact , 4 mm 4 mm lfcsp package , and is pin compatible to the hmc624a . a fully populated evaluation board is available. p ackage base gnd serial/ p aralle l inter f ace 6-bit/ digi t al a ttenu a t or 13719-001 24 23 22 21 20 19 7 8 9 10 1 1 12 1 2 3 4 5 6 18 17 16 15 14 13 serin clk p/s le a ttin gnd vdd pup1 pup2 serout a tt out gnd gnd gnd gnd gnd gnd gnd d0 d5 d4 d3 d2 d1
HMC1122 data sheet rev. 0 | page 2 of 15 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificat ions ..................................................................................... 3 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 interface schematics ..................................................................... 6 typical performanc e characteristics ............................................. 7 insertion loss, return loss, state error, step error, and relative phase ................................................................................ 7 input power compression and third - order intercept ............9 theory of operation ...................................................................... 10 power supply ............................................................................... 10 rf input and output ................................................................. 10 serial or parallel mode selection ............................................. 10 serial mode interface ................................................................. 10 parallel mode interface .............................................................. 11 power - up interface .................................................................... 11 applications information .............................................................. 12 eval uation printed circuit board ............................................. 12 evaluation board schematic and artwork ............................. 13 outline dimensions ....................................................................... 15 ordering guide .......................................................................... 15 revision history 4/16r evision 0: initial version
data sheet HMC1122 rev. 0 | page 3 of 15 specifications v dd = 3.3 v to 5 v, t a = 25c, 50 ? system , unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit frequency range 0.1 6.0 ghz insertion loss at 0.2 ghz to 1.0 ghz 1.1 1.8 db at 1.0 ghz to 2.0 ghz 1.3 2.0 db at 2.0 ghz to 4.0 ghz 1.7 2.4 db at 4.0 ghz to 6.0 ghz 2.0 2.8 db at tenuation at 0.2 ghz to 6 ghz range between min imum and max imum attenuation states 31.5 db step size between any successive attenuation states 0.5 db step error between any successive attenuation states < 0.1 db accuracy all attenuation states ; referenced to insertion loss state ? (0.1 + 4% of attenuation state) +(0.1 + 4% of attenuation state) db overshoot between all attenuation states <0.1 db return loss (at tin and at tout ) at 1.0 ghz , min imum attenuation (worst case) 24 db at 2.0 ghz, minimum attenuation (worst case) 22 db at 4.0 ghz, minimum attenuation (worst case) 22 db at 6.0 ghz, max imum attenuation (worst case) 21 db relative phase between min imum and max imum attenuation states at 1.0 ghz 6 degrees at 2.0 ghz 18 degrees at 4.0 ghz 38 degrees at 6.0 ghz 58 degrees switching characteristics between all attenuation states rise and fall time t rise , t fal l 10% to 90% of rf output 60 ns on and off time t on , t off 50% v ctl to 90% of rf output 150 ns 0.1 db settling time 50% v ctl to 0.1 db of f inal rf output 200 ns 0.05 db settling time 50% v ctl to 0.05 db of f inal rf output 250 ns input linearity all attenuation states , 0.2 ghz to 6 ghz input 0.1 db compression p0.1db 30 dbm input third - order intercept ip3 two - tone input power = 15 dbm each tone , f = 1 mhz 55 dbm supply current i dd v dd = 3.3 v 0. 3 ma v dd = 5.0 v 0.4 ma
HMC1122 data sheet rev. 0 | page 4 of 15 parameter symbol test conditions/comments min typ max unit digital control inputs p/s, clk, serin, le, d0 to d5, pup1, and pup2 pins input voltage low v inl v dd = 3.3 v 0 0.5 v v dd = 5.0 v 0 0.8 v high v inh v dd = 3.3 v 2.0 3.3 v v dd = 5.0 v 3 . 5 5.0 v low and high input current i inl , i inh v dd = 3.3 v to 5 v <1 a digital control output serout output voltage low v outl 0.1 v high v outh v dd 0.1 v low and high output current i outl , i outh 1 ma recommended operating conditons supply voltage v dd 3.0 5.4 v digital control voltage range v ctl 0 v dd v rf input power p in all attenuation states, t case = 85c 24 dbm case temperature t case ? 40 +85 c
data sheet HMC1122 rev. 0 | page 5 of 15 absolute maximum rat ings table 2 . parameter rating rf input power, p in (t case = 85c) 25 dbm supply voltage ?0.3 v to +5.5 v digital control input voltage ?0.3 v to v dd + 0.5 v continuous power dissipation, p diss 0.31 w junction to case thermal resistance, jc (at maximum power dissipation ) 156 c/w temperature junction, t j 135c storage ?65c to +150c reflow 260c (msl3 rating) esd sensitivity human body model ( hbm ) 2 k v (class 2) stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximu m operating conditions for extended periods may affect product reliability. only one absolute maximum rating can be applied at any one time. esd caution
HMC1122 data sheet rev. 0 | page 6 of 15 pin configuration an d function descripti ons figure 2. pin configuration (top view) table 3 . pin function descriptions pin no. mnemonic description 1 p/s parallel/serial mode select. for parallel mode operation, set this pin to lo w. f or serial mode operation, set this pin to h igh. 2 clk serial interface clock input. 3 serin serial interface data input. 4 le latch enable input. 5, 7 to 12, 14 gnd ground. these pins must be connected to ground. 6 at tin attenuator rf input . this pin can also be used as an output because the design is bidirec tional . at tin is dc - coupled and matched to 50 . an e xternal dc blocking capacitor is required. 13 at tout attenuator rf output. this pin can also be used as an input because the design is bidirectional. at tout is dc - coupled and matched to 50 . an e xternal dc blocking capacitor is required. 15 serout serial interface data output. serial input data is delayed by six clock cycles. 16 , 17 pup2 , pup1 power - up state selection bit s . these pins set the attenuation va lue at power - up (see table 7 ). there is n o internal pull - up or pull - down resistor on these pins ; therefore, they must always be kept at a valid logic level (v ih or v i l ) and not be left floating. 18 vdd power supply. 19 to 24 d5 to d0 parallel control voltage inputs . these pins select the required attenuation (see table 5 ). there is no internal pull - up or pull - down resistor on these pins ; therefore, they must always be kept at a valid logic level (v ih or v il ) and not be left floating. epad exposed pad. the e xposed pad must be connected to ground for proper operation. interface schematics figure 3. pup1, pup2, and d0 to d5 interface schematic figure 4. attin, attout interface schematic figur e 5. p/s, le, clk, and serin interface schematic figure 6 . gnd interface schematic 24 23 22 21 20 19 7 8 9 10 1 1 12 1 2 3 4 5 6 notes 1. the exposed p ad must be connected t o ground for proper oper a tion. hmc 1 122 t op view (not to scale) 18 17 16 15 14 13 serin clk p/s le a ttin gnd vdd pup1 pup2 serout a tt out gnd gnd gnd gnd gnd gnd gnd d0 d5 d4 d3 d2 d1 13719-002 v dd pup1, pup2, d0 t o d5 13719-021 a ttin, a tt out 13719-023 13719-024 v dd p/s, le, clk, sernin 100k gnd 13719-022
data sheet HMC1122 rev. 0 | page 7 of 15 typical performance characteri sti cs i nsertion l oss , r eturn l oss , s tate e rror , s tep e rror , and r elative p hase figure 7 . insertion loss vs. frequency over temperature figure 8 . input return loss vs. frequency o ver major attenuation states figure 9 . state error vs. attenuation state o ver frequency ( 100 mhz to 500 m hz) figure 10 . normalized attenuation vs. frequency o ver major attenuation states figure 11 . output return loss vs. frequency o ver major attenuation states figure 12 . state error vs. attenuation state over frequency (1 ghz to 6 ghz) ?4.0 ?3.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0 1 2 3 4 5 6 insertion loss (db) frequenc y (ghz) +85c +25c ?40c 13719-003 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 return loss (db) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-004 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 0 4 8 12 16 20 24 28 32 sta te error (db) a ttenu a tion s ta te (db) 100mhz 200mhz 400mhz 500mhz 13719-005 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 0 1 2 3 4 5 6 normalized a ttenu a tion (db) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-006 ?60 ?50 ?40 ?30 ?20 ?10 0 0 1 2 3 4 5 6 return loss (db) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-007 ?2.0 ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 2.0 0 4 8 12 16 20 24 28 32 sta te error (db) a ttenu a tion s ta te (db) 1ghz 3ghz 5ghz 2ghz 4ghz 6ghz 13719-008
HMC1122 data sheet rev. 0 | page 8 of 15 figure 13 . step error vs. attenuation state over frequency (100 mhz to 500 mhz) figure 14 . state error vs. frequency over major attenuation states figure 15 . relative phase vs. frequency over major attenuation states figure 16 . step error vs. attenuation state over frequency (1 ghz to 6 ghz) figure 17 . step error vs. frequency over major attenuation states figure 18 . relative phase vs. attenuation states over frequency ?1.0 ?0.8 0.8 ?0.4 0.4 0 ?0.6 ?0.2 0.2 0.6 1.0 0 4 8 12 16 20 24 28 32 ste p error (db) a ttenu a tion s ta te (db) 100mhz 200mhz 400mhz 500mhz 13719-009 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 0 1 2 3 4 5 6 s ta te error (db) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-010 ?80 ?60 ?40 ?20 0 20 40 60 80 0 1 2 3 4 5 6 rel a tive phase (degrees) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-0 1 1 ?1.0 ?0.8 0.8 ?0.4 0.4 0 ?0.6 ?0.2 0.2 0.6 1.0 0 4 8 12 16 20 24 28 32 ste p error (db) a ttenu a tion s ta te (db) 1ghz 3ghz 5ghz 2ghz 4ghz 6ghz 13719-012 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 6 ste p error (db) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-013 ?80 ?60 ?40 ?20 0 20 40 60 80 0 4 8 12 16 20 24 28 32 rel a tive phase (degrees) a ttenu a tion s ta te (db) 0.1ghz 1ghz 3ghz 5ghz 0.5ghz 2ghz 4ghz 6ghz 13719-014
data sheet HMC1122 rev. 0 | page 9 of 15 i nput p ower c ompression and t hird - order i ntercept figure 19 . input p0.1db vs. frequency (0.1 ghz to 1 ghz) at minimum attenuation state over temperature figure 20 . input ip3 vs. frequency (0.1 ghz to 1 ghz) at minimum atte nuation state over temperature figure 21 . input ip3 vs. frequency (0.1 ghz to 1 ghz) over major attenuation states figure 22 . input p0.1db vs. frequency (0.1 ghz to 6 ghz) at minimum attenuation state over temperature figure 23 . input ip3 vs. frequency (0.1 ghz to 6 ghz) at minimum attenuation state over temperature figure 24 . input ip3 vs. frequency (0.1 ghz to 6 ghz) over major attenuation states 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1.0 p0.1db (dbm) frequenc y (ghz) +85c +25c ?40c 13719-015 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 ip3 (dbm) frequenc y (ghz) +85c +25c ?40c 13719-016 30 40 50 60 70 0 0.2 0.4 0.6 0.8 1.0 ip3 (dbm) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-017 15 20 25 30 35 40 0 1 2 3 4 5 6 p0.1db (dbm) frequenc y (ghz) +85c +25c ?40c 13719-018 30 40 50 60 70 0 1 2 3 4 5 6 ip3 (dbm) frequenc y (ghz) +85c +25c ?40c 13719-019 30 40 50 60 70 0 1 2 3 4 5 6 ip3 (dbm) frequenc y (ghz) 0db 1db 4db 16db 0.5db 2db 8db 31.5db 13719-020
HMC1122 data sheet rev. 0 | page 10 of 15 theory of operation the HMC1122 incorporates a 6 - bit fixed attenuator array that offers an attenuation range of 31. 5 db in 0.5 db steps. an integrat ed driver e nables both serial and parallel mode control of the attenuator array (see figure 25). power supply the HMC1122 requires a single dc voltage applied to the vdd pin . the ideal power - up sequence is as follows : 1. connect the gnd pin to a ground reference. 2. apply a supply voltage to the vdd pin. 3. power up the digital control inputs . the relative order of the digital control inputs is not important . 4. apply an rf i nput signal to attin or attout . rf input and output the attenuator in the HMC1122 is bidi rectional; attin a nd att out pins are interchangeable as the rf input and output ports. the attenuator is internally matched to 50 at both the input and the output; therefore, no external matching compo - nents are required. rf pins are dc - coupled ; therefore, dc blocking capacitors are required on the rf lines. s erial or p arallel mode selection the HMC1122 can be controlled in either serial or parallel mode by setting the p/s pin to high or low, respectively (see table 4 ). table 4 . mode selection p/s control mode low parallel high serial serial mode interfac e the HMC1122 has a 3 - wire serial peripheral interface (spi): serial data input (serin), clock (clk), and latch enable (le). the serial control interface is activated when p/s is set to high. in serial mode, the 6 - bit serin data is clocked msb first on the rising clk edges into the shift register and then le must be toggled high to latch the new attenuation state into the device. le must be set to low to clock new 6 - bit data into the shift regi ster because clk is masked to prevent the attenuator value from changing if le is kept high. see figure 26 in conjunction with table 5 and table 6 . the HMC1122 also features a serial data output pin, serout, that outputs serial input data delayed by six clock cycles to control the cascaded attenuator using a single spi bus. in serial mode operat ion, the parallel control inputs must always be kept at a valid logic level (v ih or v il ) and not be left floating. i t is recommended to connect all parallel control inputs (d0 to d5) to ground. figure 25 . functional block diagram table 5 . d5 to d0 truth table digital control input 1 attenuation state (db) d5 d4 d3 d2 d1 d0 high high high high high high 0 (reference) high high high high high low 0.5 high high high high low high 1.0 high high high low high high 2.0 high high low high high high 4.0 high low high high high high 8.0 low high high high high high 16.0 low low low low low low 31.5 1 any combination of the control voltage input states shown in table 5 provides an attenuation equal to the sum of the bits selected . serin d0 d q d1 d2 d3 d4 d5 clk p/s select p/s le rf input rf output d q d q d q d q d q 6-bit l a tch 0.5db 1db 2db 4db 8db 16db 13719-028
data sheet HMC1122 rev. 0 | page 11 of 15 figure 26 . serial mode timing diagram table 6 . timing specifications parameter description min typ max unit t sck minimum serial period, see figure 26 70 ns t cs control setup time, see figure 26 15 ns t ch control hold time, see figure 26 20 ns t ln le setup time, see figure 26 15 ns t lew minimum le pulse width, see figure 26 and figure 27 10 ns t les minimum le pulse spacing, see figure 26 630 ns t ckn serial clock hold time from le, see figure 26 0 ns t ph hold time, see figure 27 10 ns t ps setup time, see figure 27 2 ns parallel mode interf ace the HMC1122 has six digital control inputs, d0 (lsb) to d5 (msb), to select the desired attenuation state in parallel mode, as shown in table 5 . the parallel con trol interface is activated when p/s is set to low . in parallel mode operation, the parallel control inputs (d0 to d5) must always be kept at a valid logic level (v ih or v il ). i t is recommended to use pull - down resistor s on all parallel control input lines if the device driving them goes to a high impedance state during hibernation . there are two modes of parallel operation: direct parallel and latched parallel. direct parallel mode he l i t e et hih he atteatio tate i chaed the cotrol oltae it d to d directl hi ode i ideal or aal cotrol o the atteator latched parallel mode he l i t e et lo he chai the cotrol oltae it d to d to et the atteatio tate he the deire d tate i et l t e toled hih to traer the it data to the a itche o the atteator arra ad the toled lo to latch the chae ito the deice til the et deired atteatio chae ee ire i coctio ith ale figure 27 . latched parallel mode timing diagram power - up interface the HMC1122 uses the pup1 and pup2 control voltage inputs to set the attenuation value to a known value at power - up before the initial control data word is provided in either serial or parallel mode. when the attenuator powers up with le low, the state of pup1 and pup2 determines the power - up state of the device per the truth table shown in table 7 . the attenuator latches in the desired power - up state approximately 200 ms after power - up. table 7 . pupx truth tab le 1 attenuation state le pup1 pup2 31. 5 db low low low 24.0 db low high low 16.0 db low low high 0 db (reference) low high high determined by d0 to d5 high dont care dont care 1 the pupx pins must always be kept at a valid logic level (v ih or v il ) and not be left floating. serin clk p/s le x x msb [first in] t cs t ch t sck t les t ckn t lew t ln d5 d4 d3 d2 d1 d0 x d[5:0] next word x msb [first in] 13719-029 le d5 t o d0 p/s x x x t lew t ph t ps d[5:0] p aralle l contro l 13719-030
HMC1122 data sheet rev. 0 | page 12 of 15 applications informa tion evaluation printed circuit board the schematic of the HMC1122 evaluation board is shown in figure 28 . the HMC1122 evaluation board is constructed of a 4 - layer material with a copper thickness of 0.7 mil on each layer. every copper layer is separated with a dielectric material. the top dielectric material is 10 mil ro4350. the middle and bottom dielectric materials are fr - 4 , used for mechanical strength and overall board th ickn ess of approximately 62 mil, which allows sma connectors to be slipped in at the board edges. all rf and dc traces are routed on the top copper layer . the rf transmission lines are designed using a coplanar waveguide (cpwg) model , with a width of 18 mil , s pacing of 1 3 mil, and dielectric thickness of 10 mil , to have a characteristic imped - ance of 50 ?. the inner and bottom layers are grounded planes to provide a solid ground for the rf transmission lines. for optimal electrical and thermal performance, as m any vias as possible are arranged around transmission lines and under the package exposed pad . the evaluation board layout shown in figure 29 serves as a recommendation for optimal and stable perfor mance , as well as for improvement of thermal efficiency. the evaluation board is grounded from the dc test p oint , tp1. the dc supply must be connected to the dc test point , tp2, o f the evaluation board. three decoupling capacitors are populated on the supply trace to filter high frequency noise . the rf input and output ports ( attin and attout ) are connected through 50 transmission lines to the sma connect - ors, j1 and j2 , respectively. the attin and attout ports are ac - coupled with capacitors of an appropriate value to ensure broadband performance. a thru calibration line connects j4 and j5; t h is transmission line is used to estimate the loss of the pcb over the environmental conditions being evaluated. all the digital control pins are connected through digital signal traces to the 2 9 - pin header, j3. on the digital signal traces, provisions for an rc filter are made to clean any potential coupled noise. in normal operation, series res istors are 0 and shunt capacitors are open. the HMC1122 evaluation board also uses two dual inline package ( dip ) , four - position single - pole dual - throw ( spdt ) switches for the manual control of the device in direct parallel mode .
data sheet HMC1122 rev. 0 | page 13 of 15 evaluation board sch ematic and artwork figure 28 . evaluation board schematic 13719-025
HMC1122 data sheet rev. 0 | page 14 of 15 figure 29 . evaluation board layout top view table 8 . evaluation board components component default value description j1, j2 not applicable sma connector j3 not applicable 2 9 -pi n header j4, j5 do not insert sma connector tp1, tp2 not applicable through hole mount test point c1, c2 100 pf capacitor, 0402 package c3 100 pf capacitor, 0402 package c4 10 f capacitor, 0603 package c7 1 nf capacitor, 0402 package c5, c6 do not insert capacitor, 0402 package c8 to c20 do not insert capacitor, 0402 package sw1, sw2 not applicable spdt four - position dip switch r1 to r13 0 resistor, 0402 package r14 to r25 100 k resistor, 0402 package u1 HMC1122 HMC1122 digital attenuator, analog devices, inc. pcb ev2HMC1122lp4m 600 - 01281 -00 -1 evaluation pcb, analog devices 13719-026
data sheet HMC1122 rev. 0 | page 15 of 15 outline dimensions figure 30. 24-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body and 0.90 mm package height (cp-24-16) dimensions shown in millimeters ordering guide model 1 temperature range msl rating 2 package description package option branding 3 HMC1122lp4me ?40c to +85c msl3 24-lead lead frame chip scale package [lfcsp] cp-24-16 xxxx 1122h HMC1122lp4metr ?40c to +85c msl3 24-lead lead frame chip scale package [lfcsp] cp-24-16 xxxx 1122h ev2HMC1122lp4m evaluation board 1 HMC1122lp4me and HMC1122lp4metr are rohs compliant parts. 2 see the absolute maximum ratings section. 3 xxxx is the 4-digit lot number. 0.50 bsc 0.50 0.40 0.30 compliant to jedec standards mo-220-vggd-8. bottom view top view 4.10 4.00 sq 3.90 seating plane 1.00 0.90 0.80 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 pin 1 indicator 1 24 7 12 13 18 19 6 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-13-2015-a 0.30 0.25 0.18 p i n 1 i n d i c a t o r 0.20 min 2.85 2.70 sq 2.55 exposed pad pkg-000000 ?2016 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d13719-0-4/16(0)

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